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BQ25790

SLUSDF9 –JUNE 2020

BQ25790 I²C Controlled, 1-4 Cell, 5-A Buck-Boost Battery Charger with Dual-Input

Selector and USB PD 3.0 OTG Output

1 Features

•

Package

56-Pin 2.9mm × 3.3mm WCSP

–

1

•

High efficient synchronous Switch Mode buck-

boost charger for 1-4 cell battery

2 Applications

–

750-kHz and 1.5-MHz Programmable

switching frequencies

•

Smartphone, Tablet, Drone

Wireless speaker, Digital Camera

Mobile printer, Electronic point of sales (EPOS)

–

Efficiency optimized for charging 2s battery,

96.5% efficiency with 9-V input and 94.5%

efficiency with 15-V input at 3-A ICHG

3 Description

–

Charging current up to 5 A with 10-mA

resolution

The BQ25790 is a fully integrated switch-mode buck-

boost charger for 1-4 cell Li-ion battery and Li-

polymer battery. The integration includes 4 switching

MOSFETs (Q₁, Q₂, Q₃, Q₄), input and charging

current sensing circuits, the battery FET (Q_BAT) and

all the loop compensation of the buck-boost

converter. It provides high power density and design

flexibility to charge batteries across the full input

voltage range for USB Type-C™ and USB power

delivery (USB-PD) applications such as smart phone,

tablet and other portable devices.

•

Support wide range of input sources

–

3.6-V to 24-V Wide input operating voltage

range with 30-V absolute maximum rating

Maximum power tracking with VINDPM up to

22 V and IINDPM up to 3.3 A

Detect USB BC1.2, SDP, CDP, DCP, HVDCP

and non-standard adapters

•

Dual-input power mux controller for source

selection

Device Information⁽¹⁾

High level integration

PART NUMBER

PACKAGE

BODY SIZE (NOM)

2.90 x 3.30 mm²

–

Four switching MOSFETs and BATFET

Input current and charging current sensing

BQ25790

DSBGA (56)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Narrow-VDC (NVDC) Power Path management

Power USB port from battery (USB OTG)

–

2.8-V to 22-V OTG output voltage with 10-mV

resolution to support USB-PD PPS

Simplified Schematic

VBUS

SW1

PMID

–

OTG Output current regulation up to 3.32 A

with 40-mA resolution

USB

•

Flexible autonomous and I²C mode for optimal

system performance

Integrated 16-bit ADC for voltage, current and

temperature monitor

SYSTEM LOAD

SYS

Low battery quiescent current

SW2

–

Typical 21-µA at battery only operation

BAT

Typical 600 nA in Charger Shutdown Mode

•

High accuracy

I2C Bus

BATP

BATN

–

±0.5% Charge voltage regulation for 2s battery

±5% Charge current regulation

BQ25790

Host

1s~4s

Battery

Host

Control

±5% Input current regulation

GND

Safety

–

Thermal regulation and thermal shutdown

Input/battery OVP and OCP

Converter MOSFETs OCP

Charging safety timer

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

BQ25790

SLUSDF9 –JUNE 2020

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 45

8.5 Register Map........................................................... 46

Application and Implementation ...................... 115

9.1 Application Information.......................................... 115

9.2 Typical Application ................................................ 116

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (continued)......................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements.............................................. 16

7.7 Typical Characteristics............................................ 17

Detailed Description ............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram ....................................... 20

8.3 Feature Description................................................. 21

9

10 Power Supply Recommendations ................... 123

11 Layout................................................................. 124

11.1 Layout Guidelines ............................................... 124

12 Device and Documentation Support ............... 125

12.1 Device Support .................................................. 125

12.2 Documentation Support ...................................... 125

12.3 Receiving Notification of Documentation

Updates.................................................................. 125

12.4 Support Resources ............................................. 125

12.5 Trademarks......................................................... 125

12.6 Electrostatic Discharge Caution.......................... 125

12.7 Glossary.............................................................. 125

8

13 Mechanical, Packaging, and Orderable

Information ......................................................... 126

4 Revision History

DATE

REVISION

NOTES

June

*

Initial release.

2

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5 Description (continued)

The charger supports the narrow VDC power path management, in which the system is regulated at a voltage

slightly higher than the battery voltage, but not drop below the minimum system voltage. The system keeps

operating even when the battery is completely discharged or removed. When load power exceeds input source

rating, the battery gets into supplement mode and prevents the input source from being overloaded and the

system from crashing.

The device charges a battery from a wide range of the input sources including legacy USB adapter to high

voltage USB PD adapter and traditional barrel adapter. The charger automatically sets converter to be buck,

boost or buck-boost configurations based on input voltage and battery voltage without the host control. The dual

input source selector manages the power flowing from two different input sources. The inputs selection is

controlled by the host through I²C with default source #1 (VAC1) as the primary input and the source #2 (VAC2)

as the secondary input.

To support fast charging using adjustable high voltage adapter, the device provides D+/D- handshake. The

device is compliant with USB 2.0 and USB 3.0 power delivery specification with input current and voltage

regulation. In addition, the Input Current Optimizer (ICO) allows the detection of maximum power point of an

unknown input source.

Besides the I²C host controlled charging mode, this charger also supports autonomous charging mode. After

power up, the charging is enabled with default register settings. The device can complete a charging cycle

without any software engagements. It detects battery voltage and charges the battery in different phases: trickle

charging, pre-charging, constant current (CC) charging and constant voltage (CV) charging. At the end of the

charging cycle, the charger automatically terminates when the charge current is below a pre-set limit (termination

current) in the constant voltage phase. When the full battery falls below the recharge threshold, the charger will

automatically start another charging cycle.

In the absence of input sources, this device supports USB On-the-Go (OTG) function, discharging battery to

generate an adjustable 2.8V~22V voltage on VBUS with 10mV step size, which is compliant to the USB PD 3.0

specification defined programmable power supply (PPS) feature.

The charger provides various safety features for battery charging and system operations, including battery

temperature negative thermistor monitoring, trickle charge, pre-charge and fast charge timers and over-

voltage/over-current protections on battery and input. The thermal regulation reduces charge current when the

junction temperature exceeds a programmable threshold. The STAT output of the device reports the charging

status and any fault conditions. The PG output indicates if a good power source is present. The INT pin

immediately notifies host when fault occurs.

The device also provides a 16-bit analog-to-digital converter (ADC) for monitoring charge current and

input/battery/system (VAC, VBUS, BAT, SYS, TS) voltages.

It is available in a 56-pin 2.9mm × 3.3mm WCSP package.

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6 Pin Configuration and Functions

YBG Package

56-Pin DSBGA

Top View

1

2

3

4

5

6

7

VBUS

PMID

SW1

D-

GND

ILIM_HIZ

CE

SW2

SYS

BAT

A

B

C

D

E

F

VBUS

BTST1

REGN

STAT

VAC2

VAC1

PMID

SW2

PROG

INT

SYS

BAT

PMID

SYS

BAT

PMID

SYS

BAT

PMID

SYS

BAT

D+

SDRV

BATN

IBAT

BTST2

BATP

TS

G

H

ACDRV2

QON

ACDRV1

PG

SCL

SDA

Top View = Xray through a soldered down part with A1 starting in upper left corner

Pin Functions

I/O

DESCRIPTION

NAME

NO.

A1

B1

C1

A2

B2

C2

D2

E2

A3

B3

C3

D3

E3

Charger Input Voltage – The power input terminal of the charger. An input current sensing circuit is

connected between VBUS and PMID. The recommended capacitor at VBUS is one piece of 10μF

ceramic capacitor.

VBUS

P

Q1 MOSFET Drain Connection – An internal N-channel high side MOSFET (Q1) is connected

between PMID and SW1 with drain on PMID and source on SW1. Place a 0.1μF ceramic capacitor

from PMID to power GND as close as possible to the charger IC. The recommended capacitors at

PMID are 3 piece of 10μF and one piece of 0.1μF ceramic capacitors.

PMID

SW1

P

Buck Side Half Bridge Switching Node

4

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

A4

B4

C4

D4

E4

A5

B5

C5

D5

E5

A6

B6

C6

D6

E6

A7

B7

C7

D7

E7

GND

P

Ground Return

SW2

SYS

BAT

P

Boost Side Half Bridge Switching Node

The Charger Output Voltage to System – The internal N-channel high side MOSFET (Q4) is

connected between SYS and SW2 with drain on SYS and source on SW2. Place a 0.1μF ceramic

capacitor from SYS to power GND as close as possible to the charger IC. The recommended

capacitors at SYS are 5 piece of 10μF and one piece of 0.1μF ceramic capacitors.

The Battery Charging Power Connection – Connect to the positive terminal of the battery pack. The

internal charging current sensing circuit is connected between SYS and BAT. The recommended

capacitors at BAT are 2 piece of 10μF ceramic capacitors.

Input High Side Power MOSFET Gate Driver Power Supply – Connect a 10V or higher rating, 47nF

ceramic capacitor between SW1 and BTST1 as the bootstrap capacitor for driving high side switching

MOSFET (Q1).

BTST1

REGN

BTST2

D1

E1

F7

P

The Charger Internal Linear Regulator Output – It is supplied from either VBUS or BAT dependent

on which voltage is higher. Connect a 10V, 4.7μF ceramic capacitor from REGN to power ground. The

REGN LDO output is used for the internal MOSFETs gate driving voltage and the voltage bias for TS

pin resistor divider.

Output High Side Power MOSFET Gate Driver Power Supply – Connect a 10V or higher rating,

47nF ceramic capacitor between SW2 and BTST2 as the bootstrap capacitor for driving high side

switching MOSFET (Q4).

Input FETs Driver Pin 1 – The charge pump output to drive the port #1 input N-channel MOSFET

(ACFET1) and the reverse blocking N-channel MOSFET (RBFET1). The charger turns on the back-to-

back MOSFETs by increasing the ACDRV1 voltage 5V above the common drain connection of the

ACFET1 and RBFET1 when the turn-on condition is met. Tie ACDRV1 to GND if no ACFET1 and

RBFET1 installed.

ACDRV1

VAC1

H2

H1

G2

P

VAC1 Input Detection – When a voltage between 3.6V and 24V apply on VAC1, it represents a valid

input is plugged in port 1. Connect to VBUS if the ACFET1 and RBFET1 are not installed.

Input FETs Driver Pin 2 – The charge pump output to drive the port #2 input N-channel MOSFET

(ACFET2) and the reverse blocking N-channel MOSFET (RBFET2). The charger turns on the back-to-

back MOSFETs by increasing the ACDRV2 voltage 5V above the common drain connection of the

ACFET2 and RBFET2 when the turn-on condition is met. Tie ACDRV2 to GND if no ACFET2 and

RBFET2 installed.

ACDRV2

VAC2 Input Detection – When a voltage between 3.6V and 24V is applied on VAC2, it represents a

valid input being plugged in port #2. Connect to VBUS if the ACFET2 and RBFET2 are not present.

VAC2

STAT

G1

F1

P

Open Drain Charge Status Output – It indicates various charger operations. Connect to the pull up

rail via 10kΩ resistor. LOW indicates charging in progress. HIGH indicates charging completed or

charging disabled. When any fault condition occurs, STAT pin blinks at 1Hz. The STAT pin function

can be disabled when DIS_STAT bit is set to 1.

DO

Open Drain Active Low Power Good Indicator – Connected to the pull up rail via 10kΩ resistor.

LOW indicates a good input source if the VBUS voltage is above 3.6V and below 24V.

PG

D+

H3

F2

Positive Line of the USB Data Line Pair – D+/D- based USB host/charging port detection. The

AIO detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and the

adjustable high voltage adapter.

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Negative Line of the USB Data Line Pair – D+/D- based USB host/charging port detection. The

D-

F3

AIO detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and the

adjustable high voltage adapter.

External N-channel Ship FET (SFET) Gate Driver Output – The driver pin of the external ship FET.

The ship FET is always turned on when the ship mode is disabled, and it keeps off when the charger is

in ship mode or shutdown mode. Connect a 0402 / 50V / 1nF ceramic capacitor from SDRV to GND

when the ship FET is not used.

SDRV

QON

F6

P

Ship FET Enable or System Power Reset Control Input – When the device is in ship mode or in the

shutdown mode, the SDRV turns off the external ship FET to minimize the battery leakage current. A

logic low on this pin with t_{SM_EXIT}duration turns on ship FET to force the device exit the ship mode. A

logic low on this pin with t_RSTduration resets system power by turning off the ship FET for t_{RST_SFET}

(also set the charger in HIZ mode when VBUS is high) and then turning on ship FET (also disable the

charger HIZ mode) to provide full system power reset. During t_{RST_SFET}when the ship FET is off, the

charger applies a 30mA discharging current on SYS to discharge system voltage. The pin contains an

internal pull-up to maintain default high logic.

G3

F5

DI

Charger POR Default Settings Program – At power up, the charger detects the resistance tied to

PROG pin to determine the default switching frequency and the default battery charging profile. The

surface mount resistor with ±1% or ±2% tolerance is recommended. Please refer to more details in the

PROG

DI

section of PROG Pin Configuration.

SCL

SDA

H4

H5

DI I²C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.

DIO I²C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.

Open Drain Interrupt Output. – Connect the INT pin to a logic rail via a 10kΩ resistor. The INT pin

sends an active low, 256μs pulse to the host to report the charger device status and faults.

INT

G5

DO

Input Current Limit Setting and HIZ Mode Control Pin – Program ILIM_HIZ voltage by connecting a

resistor divider from pull up rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V_{(ILIM_HIZ)}

=

1V + 800mΩ × IINDPM, in which IINDPM is the target input current. The input current limit used by the

charger is the lower setting of ILIM_HIZ pin and the IINDPM register. When the pin voltage is below

0.75V, the buck-boost converter enters non-switching mode with REGN on. When the pin voltage is

above 1V, the converter resumes switching.

ILIM_HIZ

F4

AI

Charging Current Sensing Output – A current source output pin with the output current value as a

ratio of charging current. The typical ratio is 25μA output current when the charging current is 1A. The

IBAT

H6

AO recommended application case is connecting this pin to GND through a 10kΩ resistor, in order to

achieve a 250 mV/A voltage to charging current gain. The maximum voltage at this pin is clamped at

3.3V.

Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is

LOW. CE pin must be pulled HIGH or LOW, do not leave floating.

CE

G4

G7

G6

DI

Positive Input for Battery Voltage Sensing – Connect to the positive terminal of battery pack. Place

100Ω series resistance between this pin and the battery positive terminal.

BATP

BATN

P

Negative Input for Battery Voltage Sensing – Connect to the negative terminal of battery pack.

Place 100Ω series resistance between this pin and the battery negative terminal.

AI

Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor.

AI Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends

when TS pin voltage is out of range. Recommend a 103AT-2 10kΩ thermistor.

TS

H7

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-2

MAX

30

32

23

20

29

26

30

23

UNIT

V

VAC1, VAC2

VBUS (converter not switching)

PMID (converter not switching)

ACDRV1, ACDRV2, BTST1

SYS (converter not switching)

-2

V

-0.3

V

-0.3

V

-0.3

V

Voltage range (with

respect to GND)

BATP, BAT

BTST2

SDRV

-0.3

V

-0.3

V

-0.3

V

SW1

-2 (50ns)

V

SW2

V

PG, QON, D+, D-, CE, STAT, SCL, SDA, INT, ILIM_HIZ,

PROG, TS, REGN, IBAT, BATN

-0.3

6

V

Output Sink Current

Differential Voltage

INT, STAT

6

mA

V

BTST1-SW1, BTST2-SW2

PMID-VBUS

-0.3

-40

6

V

SYS-BAT

16

6

V

SDRV-BAT

V

T_J

Junction temperature

Storage temperature

150

°C

T_stg

-55

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

24

18.8

3.3

5

UNIT

V

V_VBUS

V_BAT

I_VBUS

I_SW

Input voltage

3.6

Battery voltage

V

Input current

A

Output current (SW)

A

Fast charging current

RMS discharge current (continuously)

Peak discharge current (up to 1 sec)

Ambient temperature

5

A

I_BAT

6

A

10

85

125

A

T_A

-40

°C

µF

T_J

Junction temperature

C_VBUS

C_PMID

C_SYS

Effective VBUS capacitance

Effective PMID capacitance

Effective SYS capacitance

2

4

6

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Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

C_BAT

Effective BAT capacitance

3

µF

7.4 Thermal Information

BQ25790

THERMAL METRIC⁽¹⁾

YBG (DSBGA)

UNIT

56-BALL

46.1

0.2

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

9.5

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

Ψ_JB

9.3

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

QUIESCENT CURRENTS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Quiescent battery current (BATP,

BAT, SYS) when the charger is in

the battery only mode, battery

FET is enabled, ADC is disabled

VBAT = 8V, No VBUS, BATFET is

enabled, I2C enabled, ADC disabled,

system is powered by battery.

I_{Q_BAT_ON}

21

24 µA

Quiescent battery current (BATP) VBAT = 8V, No VBUS, I2C enabled, ADC

when the charger is in ship mode. disabled, in ship mode.

I_{Q_BAT_OFF}

12

16 µA

0.7 µA

Shutdown battery current (BATP)

VBAT = 8V, No VBUS, I2C disabled,

when charger is in shut down

ADC disabled, in shut down mode.

mode.

I_{SD_BAT}

0.6

VBUS = 15V, VBAT = 8V, charge

disabled, converter switching, ISYS = 0A,

3

mA

OOA disabled

I_{Q_VBUS}

I_{SD_VBUS}

I_{Q_OTG}

Quiescent input current (VBUS)

VBUS = 15V, VBAT = 8V, charge

disabled, converter switching, ISYS = 0A,

OOA enabled

5

354

3

mA

µA

Shutdown input current (VBUS) in VBUS = 5V, HIZ mode, no battery, ADC

HIZ

disabled, ACDRV disabled

VBAT = 8V, VBUS = 5V, OTG mode

enabled, converter switching, I_VBUS= 0A,

OOA disabled

mA

Quiescent battery current (BATP,

BAT, SYS) in OTG

VBAT = 8V, VBUS = 5V, OTG mode

enabled, converter switching, I_VBUS= 0A,

OOA enabled

5

mA

VBUS / VBAT SUPPLY

VAC present rising threshold to

3.4

3.2

3.5

V

turnon the ACFET-RBFET

V_{VAC_PRESENT}

For both VAC1 and VAC2

VAC present falling threshold to

turnoff the ACFET-RBFET

3.1

8

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VAC overvoltage rising threshold,

when VAC_OVP[1:0]=00

25.2

26

26.8

V

VAC overvoltage falling

threshold, when

VAC_OVP[1:0]=00

24.4

21.1

20.6

11.6

11.2

6.7

25.2

21.7

21.2

12

26.0

V

VAC overvoltage rising

threshold, when

VAC_OVP[1:0]=01

22.3

21.8

12.4

12.0

7.3

V

VAC overvoltage falling

threshold, when

VAC_OVP[1:0]=01

V_{VAC_OVP}

For both VAC1 and VAC2

VAC overvoltage rising

threshold, when

VAC_OVP[1:0]=10

VAC overvoltage falling

threshold, when

VAC_OVP[1:0]=10

11.6

7

VAC overvoltage rising

threshold, when

VAC_OVP[1:0]=11

VAC overvoltage falling

threshold, when

6.5

6.8

7.1

VAC_OVP[1:0]=11

V_{VBUS_OP}

VBUS operating range

3.6

24

V

VBUS rising for active I2C, no

battery

V_{VBUS_UVLOZ}

VBUS rising

VBUS falling

3.25

3.4

3.2

3.55

VBUS falling to turnoff I2C, no

battery

V_{VBUS_UVLO}

3.05

3.35

V

V_{VBUS_PRESENT}

V_{VBUS_PRESENTZ}

V_{VBUS_OVP}

VBUS to start switching

VBUS to stop switching

VBUS rising

VBUS falling

3.3

3.1

3.4

3.2

3.5

3.3

V

VBUS overvoltage rising threshold VBUS rising

25.2

25.7

26.2

VBUS overvoltage falling

VBUS falling

V_{VBUS_OVPZ}

24.0

24.4

24.8

V

threshold

I_{BUS_OCP}

IBUS over-current rising threshold

IBUS over-current falling threshold

7.0

6.5

8.0

7.5

9.0

8.5

A

I_{BUS_OCPZ}

VBAT rising, when the charger is in ship

mode

3.25

2.50

3.05

2.30

2.7

3.40

2.60

3.20

2.40

2.8

3.55

2.71

3.31

2.50

2.9

V

BAT voltage for active I2C and

turning on BATFET, no VBUS, no

VAC

V_{BAT_UVLOZ}

VBAT rising, when the charger is in

normal mode

VBAT falling, when the charger is in ship

mode

BAT voltage to turn off I2C and

BATFET, no VBUS, no VAC

V_{BAT_UVLO}

VBAT falling, when the charger is in

normal mode

BAT voltage rising threshold to

enable OTG mode

V_{BAT_OTG}

VBAT rising

BAT voltage falling threshold to

disable OTG mode

V_{BAT_OTGZ}

V_POORSRC

VBAT falling

2.4

3.3

2.5

3.4

2.6

3.5

V

Bad adapter detection threshold

VBUS falling

Bad adapter detection threshold

hysteresis

VBUS rising above V_POORSRC

150

200

250 mV

mA

Bad adapter detection current

source

I_POORSRC

30

POWER-PATH MANAGEMENT

System voltage regulation range,

measured on SYS

V_{SYSMAX_REG_RNG}

3.2

19

V

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MAX UNIT

Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_BAT= 16.8V (4s default)

MIN

16.82

12.62

8.44

TYP

17.00

12.80

8.60

17.25

13.04

8.77

V

System voltage regulation

accuracy (when V_BAT>V_SYSMIN,

charging disabled, PFM disabled)

V_BAT= 12.6V (3s default)

V_BAT= 8.4V (2s default)

V_BAT= 4.2V (1s default)

V_{SYSMAX_REG_ACC}

4.268

4.40

4.550

V_SYSMINregulation range,

measured on SYS

V_{SYSMIN_REG_RNG}

2.5

16

V

V_{SYSMIN_REG_STEP}V_SYSMINregulation step size

250

12.2

9.2

mV

V

4s battery

3s battery

2s battery

1s battery

11.9

9.0

12.5

9.4

V

System voltage regulation

V_{SYSMIN_REG_ACC}

accuracy (when V_BAT<V_SYSMIN

)

7.12

3.5

7.2

7.32

3.9

V

3.7

V

As a percentage of the system regulation

voltage, to turnoff the converter.

VSYS overvoltage rising threshold

VSYS overvoltage falling threshold

105.5

95.5

2.1

110.0

100

112.3

102

%

V

V_{SYS_OVP}

As a percentage of the system regulation

voltage, to re-enable the converter.

VSYS short voltage falling

threshold

V_{SYS_SHORT}

2.2

2.3

BATTERY CHARGER

Typical charge voltage regulation

V_{REG_RANGE}

V_{REG_STEP}

3

18.8

V

range

Typical charge voltage step

10

mV

%

V_REG= 16.8V

V_REG= 12.6V

V_REG= 8.4V

V_REG= 4.2V

-0.8

-1.0

-0.4

-0.6

0.4

0.5

0.8

%

Charge voltage accuracy, T_J=

–40°C - 85°C

V_{REG_ACC}

%

Typical charge current regulation

range

I_{CHG_RANGE}

I_{CHG_STEP}

0.05

5

A

Typical charge current regulation

step

10

mA

ICHG = 2A; VBAT=8V

-2

8

%

Typical boost mode PWM charge

I_{CHG_ACC}

current accuracy, VBUS < VBAT, ICHG = 1A; VBAT=8V

T_J= –40°C - 85°C

ICHG = 0.5A; VBAT=8V

-7.5

-5.5

-5

7.5

2.5

5

ICHG = 4A; VBAT=8V

Typical buck mode PWM charge

I_{CHG_ACC}

current accuracy, VBUS > VBAT, ICHG = 1A; VBAT=8V

T_J= –40°C - 85°C

ICHG = 0.5A; VBAT=8V

-7.5

40

7.5

I_{PRECHG_RANGE}

I_{PRECHG_STEP}

Typical pre-charge current range

2000 mA

mA

Typical pre-charge current step

40

Typical LDO mode charge current IPRECHG = 480mA, VBAT = 6.5V

-8

-20

-35

-4.5

-20

-30

-5

8

20

35

3.5

20

30

5

%

accuracy when V_BATP-V_BATN

IPRECHG = 200mA, VBAT = 6.5V

below V_SYSMIN, VBUS < VBAT, T_J

I_{PRECHG_ACC}

IPRECHG = 120mA, VBAT = 6.5V

= –40°C - 85°C

Typical LDO mode charge current IPRECHG = 1000mA, VBAT = 6.5V

accuracy when V_BATP-V_BATN

IPRECHG = 200mA, VBAT = 6.5V

below V_SYSMIN, VBUS > VBAT, T_J

I_{PRECHG_ACC}

IPRECHG = 120mA, VBAT = 6.5V

= –40°C - 85°C

IBAT pin current sensing accuracy IBAT = 4A, VBAT = 8V

with 25µA/A gain. The accuracy is

applied to forward charging mode

IBAT = 1A, VBAT = 8V

-10

10

I_{BAT_ACC}

for charging current sensing, T_J=

IBAT = 0.5A, VBAT = 8V

–40°C - 85°C

-20

40

20

%

I_{TERM_RANGE}

Typical termination current range

1000 mA

10

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_{TERM_STEP}

I_{TERM_ACC}

Typical termination current step

40

mA

ITERM = 120mA

-20

-14

20

14

%

Termination current accuracy, T_J=

–40°C - 85°C

ITERM = 480mA

Battery short voltage rising

threshold to start pre-charge

V_{BAT_SHORTZ}

VBAT rising

2.25

V

Battery short voltage falling

threshold to stop pre-charge

V_{BAT_SHORT}

I_{BAT_SHORT}

VBAT falling

2.06

100

15

V

mA

%

Battery trickle charging current

VBAT < V_{BAT_SHORTZ}

VBAT_LOWV=15%VREG,

VBAT_LOWV_1:0=00

13

61.5

67.0

71.0

17

64.5

69.0

74.0

VBAT_LOWV=62.2%VREG,

VBAT_LOWV_1:0=01

63.0

68.0

72.5

1.4

%

Battery voltage rising threshold to

start fast-charge, as percentage of

V_REG

V_{BAT_LOWV_RISE}

VBAT_LOWV=66.7%VREG,

VBAT_LOWV_1:0=10

VBAT_LOWV=71.4%VREG,

VBAT_LOWV_1:0=11

%

Battery voltage threshold to stop

fast-charge hysteresis

VBAT falling, as percentage of

VREG, VBAT_LOWV_1:0=11

V_{BAT_LOWV_HYS}

%

VBAT falling, VRECHG=0011,

VREG=8.4V

200

400

mV

V_RECHG

Battery recharge threshold

VBAT falling, VRECHG=0111,

VREG=16.8V

BATFET

MOSFET on resistance from SYS

to BAT

R_BATFET

T_j= -40°C-85°C

8

9.69 mΩ

BATTERY PROTECTIONS

VBAT rising, as percentage of VREG

VBAT falling, as percentage of VREG

103

101

104

102

105

103

%

Battery over-voltage threshold,

when battery connected.

V_{BAT_OVP}

VBAT falling, to clamp the charging

current as trickle charging current.

2.06

2.25

11.4

V

A

V_{BAT_SHORT}

Battery short voltage

VBAT rising, to release the trickle

charging current clamp

Battery discharging over-current

rising threshold

I_{BAT_OCP}

9.3

3.6

INPUT VOLTAGE / CURRENT REGULATION

Typical input voltage regulation

range

V_{INDPM_RANGE}

V_{INDPM_STEP}

22

V

Typical input voltage regulation

step

100

mV

VINDPM=18.6V

VINDPM=4.3V

-2

-3

-5

2

3

5

%

V_{INDPM_ACC}

Input voltage regulation accuracy VINDPM=10.6V

Typical input current regulation

range

I_{INDPM_RANGE}

I_{INDPM_STEP}

0.1

3.3

A

Typical input current regulation

step

10

mA

IINDPM = 500mA, VBUS=9V

IINDPM = 1000mA, VBUS=9V

IINDPM = 2000mA, VBUS=9V

IINDPM = 3000mA, VBUS=9V

415

880

460

940

500 mA

1000 mA

1960 mA

2920 mA

I_{INDPM_ACC}

Input current regulation accuracy

1800

2720

1880

2820

Voltage range for input current

regultion at ILIM_HIZ pin

V_{ILIM_REG_RNG}

1

4

V

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_{ILIM_HIZ}= 4V

MIN

TYP

MAX UNIT

I_{LEAK_ILIM}

ILIM_HIZ pin leakage current

-1.5

1.5 µA

D+ / D- DETECTION

V_{D+ _600MVSRC}

I_{D+_10UASRC}

D+ voltage source (600 mV)

D+ current source (10 µA)

D+ current sink (100 µA)

500

7

600

10

700 mV

14 µA

V_D+= 200 mV,

V_D+= 500 mV,

I_{D+_100UASNK}

50

90

150 µA

D+ comparator threshold for

Secondary Detection

V_{D+_0P325}

V_{D+_0P8}

D+ pin rising

250

775

400 mV

925 mV

D+ comparator threshold for Data

Contact Detection

D+ pin rising

850

I_{D+_LKG}

Leakage current into D+

D- voltage source (600 mV)

D- current sink (100 µA)

D+ pin is in HiZ mode

-1

500

50

1

µA

V_{D-_600MVSRC}

I_{D-_100UASNK}

600

90

700 mV

150 µA

V_D-= 500 mV,

D- comparator threshold for

Primary Detection

V_{D-_0P325}

I_{D-_LKG}

D- pin rising

250

-1

400 mV

Leakage current into D-

HiZ mode

1

µA

V

D+ comparator threshold for non-

standard adapter

V_{D+ _2p8}

(combined V_{D+_2p8_hi}and V_{D+_2p8_lo}

)

2.55

2.85

D- comparator threshold for non-

standard adapter

V_{D- _2p8}

V_{D+ _2p0}

V_{D- _2p0}

V_{D+ _1p2}

V_{D- _1p2}

(combined VD-_2p8_hi and VD-_2p8_lo)

2.55

1.85

1.05

2.85

2.15

1.35

V

D+ comparator threshold for non-

standard adapter

(combined V_{D+_2p0_hi}and V_{D+_2p0_lo}

(combined V_{D-_2p0_hi}and V_{D-_2p0_lo}

(combined V_{D+_1p2_hi}and V_{D+_1p2_lo}

)

D- comparator threshold for non-

standard adapter

)

D+ comparator threshold for non-

standard adapter

)

D- comparator threshold for non-

standard adapter

(combined V_{D-_1p2_hi}and V_{D-_1p2_lo}

)

THERMAL REGULATION AND THERMAL SHUTDOWN

TREG = 120°C

TREG = 100°C

TREG = 80°C

TREG = 60°C

120

100

80

°C

Junction temperature regulation

accuracy

T_REG

60

Temperature Increasing (TSHUT[1:0]=00)

Temperature Increasing (TSHUT[1:0]=01)

Temperature Increasing (TSHUT[1:0]=10)

Temperature Increasing (TSHUT[1:0]=11)

130

110

100

65

150

130

120

85

170 °C

150 °C

140 °C

105 °C

Thermal Shutdown Rising

Threshold

T_SHUT

Thermal Shutdown Falling

T_{SHUT_HYS}

Hysteresis

Temperature Decreasing by T_{SHUT_HYS}

30

°C

JEITA THERMISTOR COMPARATOR (CHARGE MODE)

T1 comparator rising threshold,

V_{T1_RISE}

charge suspended above this

voltage.

As Percentage to V_REGN(0°C w/ 103AT)

As Percentage to V_REGN(3°C w/ 103AT)

72.4

71.5

73.3

72

74.2

72.5

%

T1 comparator falling threshold.

charge re-enabled below this

voltage.

V_{T1_FALL}

12

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

As Percentage to V_REGN, JEITA_T2=5°C

w/ 103AT

70.6

71.1

71.6

68.9

66.0

62.9

70.3

67.6

64.7

61.6

50.2

46.6

43.0

39.5

48.9

45.3

41.7

38.2

%

As Percentage to V_REGN

,

67.9

65.0

61.9

69.3

66.6

63.7

60.6

49.2

45.6

42.0

38.5

47.9

44.3

40.7

37.2

68.4

65.5

62.4

69.8

67.1

64.2

61.1

49.7

46.1

42.5

39

JEITA_T2=10°C w/ 103AT

V_{T2_RISE}

V_{T2_FALL}

V_{T3_RISE}

V_{T3_FALL}

T2 comparator rising threshold.

As Percentage to V_REGN

,

JEITA_T2=15°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T2=20°C w/ 103AT

As Percentage to V_REGN, JEITA_T2=5°C

w/ 103AT

As Percentage to V_REGN

,

JEITA_T2=10°C w/ 103AT

T2 comparator falling threshold.

T3 comparator rising threshold.

T3 comparator falling threshold.

As Percentage to V_REGN

,

JEITA_T2=15°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T2=20°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=40°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=45°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=50°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=55°C w/ 103AT

As Percentage to V_REGN

,

48.4

44.8

41.2

37.7

JEITA_T3=40°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=45°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=50°C w/ 103AT

As Percentage to V_REGN

,

JEITA_T3=55°C w/ 103AT

T5 comparator falling threshold,

charge suspended below this

voltage.

As Percentage to V_REGN(60°C w/

103AT)

V_{T5_FALL}

33.7

35

34.2

35.5

34.7

36

%

T5 comparator rising threshold.

charge is re-enabled above this

voltage.

As Percentage to V_REGN(58°C w/

103AT)

V_{T5_RISE}

COLD / HOT THERMISTOR COMPARATOR (OTG MODE)

As Percentage to V_REGN(–20°C w/

79.5

76.6

78.2

75.3

37.2

33.9

30.8

80.0

77.1

78.7

75.8

37.7

34.4

31.3

80.5

77.6

79.2

76.3

38.2

34.9

31.8

%

103AT)

TCOLD comparator rising

threshold.

V_{BCOLD_RISE}

As Percentage to V_REGN(–10°C w/

103AT)

As Percentage to V_REGN(–20°C w/

103AT)

TCOLD comparator falling

threshold.

V_{BCOLD_FALL}

As Percentage to V_REGN(–10°C w/

103AT)

As Percentage to V_REGN, (55°C w/

103AT)

THOT comparator falling

threshold.

As Percentage to V_REGN, (60°C w/

103AT)

V_{BHOT_FALL}

As Percentage to V_REGN, (65°C w/

103AT)

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MAX UNIT

Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

As Percentage to V_REGN, (55°C w/

103AT)

38.8

39.3

39.8

36.2

33.0

%

As Percentage to V_REGN, (60°C w/

103AT)

V_{BHOT_RISE}

THOT comparator rising threshold.

35.2

32.0

35.7

32.5

As Percentage to V_REGN, (65°C w/

103AT)

SWITCHING CONVERTER

1.3

1.5

1.7 MHz

850 kHz

F_SW

PWM switching frequency

650

750

SENSE RESISTANCE and MOSFET Rdson

VBUS to PMID input sensing

resistance

R_SNS

T_j= -40°C-85°C

6

mΩ

Buck high-side switching MOSFET

turnon resistance between PMID

and SW1

R_{Q1_ON}

R_{Q2_ON}

R_{Q3_ON}

R_{Q4_ON}

20

Buck low-side switching MOSFET

turnon resistance between SW1

and PGND

T_j= -40°C-85°C

30

22

13

mΩ

Boost low-side switching MOSFET

turnon resistance between SW2

and PGND

Boost high-side switching

MOSFET turnon resistance

between SW2 and SYS

OTG MODE CONVERTER

Typical OTG mode voltage

regulation range

V_{OTG_RANGE}

V_{OTG_STEP}

V_{OTG_ACC}

I_{OTG_RANGE}

I_{OTG_STEP}

2.8

22

V

mV

%

Typical OTG mode voltage

regulation step

10

40

OTG mode voltage regulation

accuracy

I_BUS= 0A, V_OTG= 5V, 12V, 20V

-3

3

Typical OTG mode current

regulation range

0.12

3.32

A

Typical OTG mode current

regulation step

mA

IOTG = 3.0A

IOTG = 1.52A

IOTG = 0.52A

-2.2

-5

2.2

3

%

OTG mode current regulation

accuracy

I_{OTG_ACC}

-15

8

OTG mode under voltage falling

threshold

V_{OTG_UVP}

2.1

104

90

2.2

113

98

3

2.3

120

104

3.2

V

%

A

OTG mode overvoltage rising

threshold

As percentage of VOTG regulation, OTG

mode OOA disabled.

V_{OTG_OVP}

OTG mode overvoltage falling

threshold

As percentage of VOTG regulation

IBAT_REG_1:0 = 00, VBAT=8V,

VOTG=9V

2.8

3.8

4.8

Battery current regulation in OTG IBAT_REG_1:0 = 01, VBAT=8V,

mode

I_{OTG_BAT}

4

4.2

A

VOTG=9V

IBAT_REG_1:0 = 10, VBAT=8V,

VOTG=9V

5

5.3

A

REGN LDO

V_VBUS= 5V, I_REGN= 20mA

V_VBUS= 15V, I_REGN= 20mA

4.6

4.8

5

V

V_REGN

REGN LDO output voltage

5.2

14

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Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_REGN

REGN LDO current limit

V_VBUS= 5V, V_REGN= 4.5V

30

mA

I2C INTERFACE (SCL, SDA)

V_{IH_SDA}

V_{IL_SDA}

V_{OL_SDA}

I_{BIAS_SDA}

V_{IH_SCL}

V_{IL_SCL}

Input high threshold level, SDA

Pull up rail 1.8V

Sink current = 5mA

Pull up rail 1.8V

Sink current = 5mA

Pull up rail 1.8V

1.3

V

Input low threshold level

Output low threshold level

High-level leakage current

Input high threshold level, SDA

Input low threshold level

Output low threshold level

High-level leakage current

0.4

1

V

µA

V

0.4

1

V

V_{OL_SCL}

I_{BIAS_SCL}

LOGIC I PIN (CE, ILIM_HIZ, QON)

V_{IH_CE}Input high threshold level, CE

V_{IL_CE}

V

µA

1.3

V

Input low threshold level, CE

High-level leakage current, CE

Input high threshold level, QON

Input low threshold level, QON

Internal QON pull up

0.4

1

I_{IN_BIAS_CE}

V_{IH_QON}

V_{IL_QON}

V_QON

Pull up rail 1.8V

µA

V

0.4

V

QON is pulled up internally

3.2

V

R_QON

Internal QON pull up resistance

200

kΩ

Input high threshold level,

ILIM_HIZ

V_{IH_ILIM_HIZ}

V_{IL_ILIM_HIZ}

1

V

Input low threshold level,

ILIM_HIZ

0.75

LOGIC O PIN (INT, PG, STAT)

V_{OL_INT}

Output low threshold level, INT pin Sink current = 5mA

0.4

1

V

High-level leakage current, INT

I_{OUT_BIAS_INT}

Pull up rail 1.8V

µA

V_{OL_PG}

Output low threshold level, PG pin Sink current = 5mA

High-level leakage current, PG pin Pull up rail 1.8V

0.4

1

V

I_{OUT_BIAS_PG}

µA

Output low threshold level, STAT

V_{OL_STAT}

Sink current = 5mA

0.4

1

V

High-level leakage current, STAT

I_{OUT_BIAS_STAT}

Pull up rail 1.8V

µA

ADC MEASUREMENT ACCURACY AND PERFORMANCE

ADC_SAMPLE[1:0] = 00

24

12

6

ms

bits

ADC_SAMPLE[1:0] = 01

ADC_SAMPLE[1:0] = 10

ADC_SAMPLE[1:0] = 11

ADC_SAMPLE[1:0] = 00

ADC_SAMPLE[1:0] = 01

ADC_SAMPLE[1:0] = 10

ADC_SAMPLE[1:0] = 11

Conversion-time, Each

Measurement

t_{ADC_CONV}

3

14

13

12

10

15

14

13

11

ADC_RES

Effective Resolution

ADC MEASUREMENT RANGE AND LSB

Range

LSB

0

5

30

A

mA

V

ADC Bus Current Reading (both

forward and OTG)

IBUS_ADC

VBUS_ADC

VAC_ADC

1

Range

LSB

ADC Bus Voltage Reading

mV

V

Range

LSB

ADC VAC Voltage Reading

mV

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MAX UNIT

Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_{VBUS_OVP}, T_J= -40°C to +125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

Range

LSB

0

20

V

mV

V

VBAT_ADC

VSYS_ADC

IBAT_ADC

TS_ADC

ADC BAT Voltage Reading

1

Range

LSB

0

24

ADC SYS Voltage Reading

ADC BAT Current Reading

ADC TS Voltage Reading

ADC Die Temperature Reading

1

mV

A

Range

LSB

8

1

mA

%

Range

LSB

0

99.9

0.098

0.5

%

Range

LSB

-40

150 °C

°C

TDIE_ADC

7.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

BATTERY CHARGER

12

24

36

15

30

45

18 min

36 min

54 min

t_{TOP_OFF}

Typical top-off timer accuracy

Charge safety timer in trickle

charge

t_{SAFETY_TRKCHG}

t_{SAFETY_PRECHG}

0.9

1.8

1

2

1.1 hr

2.2 hr

5.5 hr

8.8 hr

13.2 hr

26.4 hr

Charge safety timer in pre-

charge, PRECHG_TMR = 1hr

Charge safety timer accuracy,

CHG_TMR = 5hr

4.5

5

Charge safety timer accuracy,

CHG_TMR = 8hr

7.2

8

t_SAFETY

Charge safety timer accuracy,

CHG_TMR = 12hr

10.8

21.6

12

24

Charge safety timer accuracy,

CHG_TMR = 24hr

THERMAL SHUTDOWN

I2C INTERFACE

f_SCL

SCL clock frequency

1000 kHZ

WATCHDOG TIMER

Watchdog Reset time (EN_HIZ =

1, WATCHDOG = 160s)

t_{LP_WDT}

t_WDT

100

136

160

s

Watchdog Reset time (EN_HIZ =

0, WATCHDOG = 160s)

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7.7 Typical Characteristics

C_VBUS= 2*10µF, C_PMID= 3*10µF, C_SYS= 5*10µF, C_BAT= 2*10µF, L1 = 1µH (SPM6530T-1R0M120) and L2 = 2.2µH (WE-

LHMI-74437346022)

100

95

90

85

80

75

70

100

95

90

85

80

75

70

VBUS = 5V

VBUS = 9V

VBUS = 15V

VBUS = 20V

VBUS = 5V

VBUS = 9V

VBUS = 15V

VBUS = 20V

0

0.5

1

1.5

Charging Current (A)

VBAT = 8V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

2

2.5

3

3.5

4

0

0.5

1

1.5

Charging Current (A)

VBAT = 12V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

2

2.5

3

3.5

4

Figure 1. 2s Battery Charge Efficiency vs. Charge Current

Figure 2. 3s Battery Charge Efficiency vs. Charge Current

100

95

90

85

95

90

85

80

VOTG = 5V

VOTG = 9V

VBUS = 5V

VBUS = 9V

75

VOTG = 15V

VOTG = 20V

VBUS = 15V

VBUS = 20V

70

0

0.5

1

1.5

Charging Current (A)

VBAT = 16V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

2

2.5

3

3.5

4

0

0.5

1

1.5

OTG Output Current (A)

VBAT = 8.4V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

2

2.5 3

Figure 3. 4s Battery Charge Efficiency vs. Charge Current

Figure 4. 2s Battery OTG Efficiency vs. OTG Current

100

95

90

85

95

90

85

80

75

70

80

VOTG = 5V

VOTG = 9V

VOTG = 15V

VOTG = 20V

VOTG = 9V

VOTG = 15V

VOTG = 20V

75

70

0

0.5

1

OTG Output Current (A)

1.5

2

2.5

3

0

0.5

1

OTG Output Current (A)

1.5

2

2.5

3

VBAT = 12.6V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

VBAT = 16.8V, Fsw = 1.5MHz with L1 = 1µH, PFM disabled

Figure 5. 3s Battery OTG Efficiency vs. OTG Current

Figure 6. 4s Battery OTG Efficiency vs. OTG Current

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Typical Characteristics (continued)

C_VBUS= 2*10µF, C_PMID= 3*10µF, C_SYS= 5*10µF, C_BAT= 2*10µF, L1 = 1µH (SPM6530T-1R0M120) and L2 = 2.2µH (WE-

LHMI-74437346022)

100

95

90

85

80

75

70

100

95

90

85

80

75

70

VOTG = 5V

VOTG = 9V

VOTG = 15V

VOTG = 20V

VBUS = 5V

VBUS = 9V

VBUS = 15V

0

0.5

1

1.5

Charging Current (A)

VBAT = 8V, Fsw = 750kHz with L2 = 2.2µH, PFM disabled

2

2.5

3

3.5

4

0

0.5

1

OTG Output Current (A)

1.5

2

2.5

3

VBAT = 8.4V, Fsw = 750kHz with L2 = 2.2µH, PFM disabled

Figure 7. 2s Battery Charge Efficiency vs. Charge Current

Figure 8. 2s Battery OTG Efficiency vs. OTG Current

0

3

-3

-6

2

1

-9

0

-12

-1

-2

-3

VBUS = 5V

VBUS = 9V

VBUS = 15V

-15

-18

0

0.5

1

1.5

IINDPM Register Setting (A)

VBAT = 8V, Fsw = 1.5MHz with L1 = 1µH

2

2.5

3

3.5

2

4

6

8

10

12

14

16

VINDPM Register Setting (V)

18

20

22

VBAT = 8V, Fsw = 1.5MHz with L1 = 1µH

Figure 9. Input Current Regulation (IINDPM) Accuracy

Figure 10. Input Voltage Regulation (VINDPM) Accuracy

0.8

3

PFM enabled

PFM disabled

2

1

0.6

0.4

0.2

0

-1

-2

-3

2

4

6

8

VOTG Register Setting (V)

10

12

14

16

18

20

22

2

4

6

8

10 12

VBAT (V)

14

16

18

20

VBAT = 8.4V, Fsw = 1.5MHz with L1 = 1µH

VBUS = 9V, Fsw = 1.5MHz with L1 = 1µH,

ISYS = 0A, Charge Disabled

Figure 12. Offset Voltage of SYS Regulation above VBAT

Figure 11. OTG Voltage Regulation (VOTG) Accuracy

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8 Detailed Description

8.1 Overview

The BQ25790 is a fully integrated switch-mode buck-boost charger for 1 cell ~ 4 cell Li-ion battery and Li-

polymer battery. For compact design and minimum components count, the charger integrates the 4 switching

MOSFETs (Q₁, Q₂, Q₃, Q₄), input and charging current sensing circuits, the battery FET (BATFET) and all the

loop compensation of the buck-boost converter. It provides high power density and design flexibility to charge

batteries across the full input voltage range for USB Type-C™ and USB-PD applications such as smart phone,

tablet and other portable devices.

The charger supports narrow VDC (NVDC) power path management, in which the system is regulated at a

voltage slightly higher than the battery voltage, but not drop below the minimum system voltage. The system

keeps operating even when the battery is completely discharged or removed. When load power exceeds the

input source rating, the battery gets into supplement mode and prevents the input source from being overloaded

and the system from crashing.

The device charges a battery from a wide range of the input sources including legacy USB adapter to high

voltage USB-PD adapter and traditional barrel adapter. The charger seamlessly transits among buck, boost or

buck-boost configurations based on input voltage and battery voltage without the host control. The optional dual-

input source selector manages the power flowing from two different input sources. The host controls the input

source selection through I²C with prioritizing the first available input source.

To support fast charging using adjustable high voltage adapter (HVDCP), the device provides D+/D- handshake.

The device is compliant with USB 2.0 and USB 3.0 power delivery specification with input current and voltage

regulation. In addition, the Input Current Optimizer (ICO) allows the detection of maximum power point of an

unknown input source.

Besides the I²C host controlled charging mode, BQ25790 also supports autonomous charging mode. After power

up, the charging is defaulted enabled with all the registers default settings. The device can complete a charging

cycle without any software engagements. It detects battery voltage and charges the battery in different phases:

trickle charging, pre-charging, constant current (CC) charging and constant voltage (CV) charging. At the end of

the charging cycle, the charger automatically terminates when the charge current is below a pre-set limit

(termination current) in the constant voltage phase. When the full battery falls below the recharge threshold, the

charger will automatically start another charging cycle.

In the absence of input sources, BQ25790 supports USB On-the-Go (OTG) function, discharging the battery to

generate an adjustable 2.8V~22V voltage on VBUS with 10mV step size. This is compliant with the USB PD 3.0

specification defined PPS feature.

The charger provides various safety features for battery charging and system operations, including battery

temperature negative thermistor (NTC) monitoring, trickle charge, pre-charge and fast charge timers and over-

voltage/over-current protections on the battery and the charger power input pin. The thermal regulation reduces

charge current when the die temperature exceeds a programmable threshold. The STAT output of the device

reports the charging status and any fault conditions. The PG output indicates if a good power source is present.

The INT pin immediately notifies host when fault occurs.

The device also provides a 16-bit analog-to-digital converter (ADC) for monitoring charge current and

input/battery/system voltages, the TS pin voltage and the die temperature. It is available in a WCSP 2.9mm x

3.3mm 56 pin package.

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8.2 Functional Block Diagram

SW2

BTST2

PMID

SW1

BTST1

REGN

VBUS

V_{VBUS_UVLOZ}

+

UVLO

SYS

PMID

Q1

+

REGN

Q4

REGN

LDO

V_{VBUS_OV}

EN_HIZ

VBUS_OVP

V_OTG

V_O,REF

V_VBUS

+

V_VBUS

SYS

V_SYSMIN

+

Q2

Q3

REGN

V_INDPM

+

I_IN

BATSNS

V_{BAT_REG}

+

I_INDPM

GND

IC_T_J

T_REG

ICHG

I_{CHG_REG}

EN_CHARGE

EN_OTG

I_Q1

Q1_OCP

+

I_{Q1_OCP}

GND

EN_HIZ

I_Q2

Q2_OCP

Q3_OCP

I_{Q2_OCP}

I_Q3

DC-DC

CONTROL

I_{Q3_OCP}

V_VBUS

OTG_OVP

+

V_{OTG_OVP}

I_Q4

Q4_OCP

CONVERTER

CONTROL

STATE

I_{Q4_OCP}

V_POORSRC

V_{OTG_UVP}

V_VBUS

+

POORSRC

TSHUT

OTG_UVP

IBUS_OCP

REF DAC

V_VBUS

MACHINE

ILIM_HIZ

PROG

V_VBUS

IC_T_J

T_SHUT

I_BUS

VBUS_OVP

+

V_{VBUS_OVP}

I_{BUS_OCP}

IBUS

ICHG

VBUS

VAC1

VAC2

VBAT

VSYS

VTS

BATSNS

V_{BAT_OVP}

VBAT_OVP

V_SYS

SYS_OVP

V_{SYS_OVP}

D+

V_{SYS_SHORT}

V_SYS

SYS_SHORT

ADC

USB

DETECTION

V_BTST2-V_SW2

V_BTST1-V_SW1

Dœ

REFRESH2

REFRESH1

+

V_{BTST2_REFRESH}

V_{BTST1_REFRESH}

TDIE

VD+

VD-

TS

VTS

/PG

BATTERY

SENSING

THERMISTOR

SYS

TS_SUSPEND

RECHRG

IBAT

V_REG- V_RECHG

ICHG

+

BATSNS

BATFET

ICHG

I_TERM

STAT

TERMINATION

SYSMIN_REG

BATUVLO

V_{BAT_REG}

I_{CHG_REG}

BATFET

CONTROL

CHARGE

CONTROL

STATE

V_SYSMIN

BATSNS

BAT

BQ25790

Block Diagram

MACHINE

V_{BAT_UVLOZ}

BATSNS

BATP

/INT

V_{BAT_SHORT}

BATSNS

BAT_SHORT

BATSNS

AMP

SFET

CONTROL

BATN

SDRV

I2C

INTERFACE

CHARGE

PUMP

SCL

SDA

MUX

CONTROL

INPUT SELECTOR

BAT

VAC1 VAC2

ACDRV1 ACDRV2

/CE

/QON

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8.3 Feature Description

8.3.1 Device Power-On-Reset

The internal bias circuits are powered from the higher voltage, whichever V_VBUSor V_BATthrough an integrated

power selector. The valid voltage to power up the device has to be greater than either V_{VBUS_UVLOZ}or V_{BAT_UVLOZ}

thresholds. When V_VBUS< V_{VBUS_UVLOZ}, V_BAT< V_{BAT_UVLOZ}and a voltage higher than V_{AC_PRESENT}is present at

either VAC1 or VAC2, the device will be powered from V_AC1or V_AC2, depending on which comes first.

Typically 5 ms after a valid voltage is first present at either V_BAT, V_BUSor V_AC1/ V_AC2, the charger wakes up,

starts the ACFET-RBFET detection, reading the resistance at PROG pin, then configures the charger power on

reset (POR) register setting accordingly. Approximately 20ms after input voltage presence, the I²C registers

become accessible to the host.

8.3.2 PROG Pin Configuration

At POR, the charger detect the PROG pin pull down resistance, then sets the charger default POR switching

frequency and the battery cell count. Please follow the resistance list in the table below to set the desired POR

switching frequency and battery cell count. The surface mount resistor with ±1% or ±2% tolerance is

recommended.

Table 1. PROG Pin Resistance to Set Default Switching Frequency and Battery Cell Count

SWITCHING FREQUENCY

1.5 MHz

CELL COUNT

TYPICAL RESISTANCE AT PROG PIN

1s

2s

3s

4s

3.0 kΩ

4.7 kΩ

750 kHz

1.5 MHz

6.04 kΩ

8.2 kΩ

750 kHz

1.5 MHz

10.5 kΩ

13.7 kΩ

17.4 kΩ

27.0 kΩ

750 kHz

1.5 MHz

750 kHz

Some of the charging parameters default values are determined by the battery cell count identified by PROG pin

configuration, which are summarized in the table below.

Table 2. Charging Parameters Dependent on Battery Cell Count

CELL (REG0x0A[7:6])

ICHG (REG0x03/04)

VSYSMIN (REG0x00[5:0])

VREG (REG0x01/02)

VREG Range

1s

2 A

2s

2 A

3s

1 A

4s

1 A

3.5 V

7 V

9 V

12 V

4.2 V

8.4 V

12.6 V

16.8 V

14 V - 18.8 V

3 V - 4.99 V

5 V - 9.99 V

10 V - 13.99 V

After POR, the host can program the ICHG and VSYSMIN registers to any values within the ranges defined in

the register tables. However, when programming the battery charging voltage (VREG), the host must ensure the

VREG value falling into the right range associated with the CELL register (REG0x0A[7:6]) setting defined in the

table above. When the CELL register is changed, the ICHG, VSYSMIN and VREG registers are reset to the POR

default values associated with the CELL setting.

For example, if the PROG pin resistance is a 2s battery configuration, the default POR CELL, ICHG, VSYSMIN

and VREG settings will be 2s, 2 A, 7 V and 8.4 V respectively. After POR, the host can change ICHG and

VSYSMIN to any other values, and change VREG to any other values between 5V and 9.99V. With the CELL

bits stay at 2s battery configuration, when REG_RST bit or watchdog timer expired, the registers are reset to

default values with ICGH, VSYSMIN and VREG automatically return to 2A, 7V, 8.4V respectively.

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When the CELL register is 2s battery configuration, any write out of the range of VREG (5 V - 9.99 V) is ignored

by the charger. If VREG needs to be programmed out of the 5 V - 9.9 V range, like 11 V, the CELL bits have to

be changed to 3s setting. The ICHG, VSYSMIN and VREG registers are reset to the 3s POR default values first,

which are 1 A, 9 V and 12.6 V. After that, the host can program VREG in the range of 10 V - 13.99 V. In addition,

when the CELL setting is changed to 3s, ICHG, VSYSMIN and VREG return to 1 A, 9 V and 12.6 V, when the

registers are reset to the default values by REG_RST bit or the watchdog timer expiration.

8.3.3 Dual-Input Power Mux

The BQ25790 has two ACDRV drivers to control two optional sets of back-to-back power N-FETs, selecting and

managing the power from two different input sources. In the POR sequence, the charger detects whether the

ACFETs-RBFETs are present, then updates the ACRB1_STAT or ACRB2_STAT status bits accordingly. The

ACFET1-RBFET1 or ACFET2-RBFET2 can be controlled by setting the register bit EN_ACDRV1 or

EN_ACDRV2. If the external ACFET-RBFET is not present, then tie VAC1 / VAC2 to VBUS and connect

ACDRV1 / ACDRV2 to GND. The power MUX drivers support three different application cases, which are

elaborated in detail below.

8.3.3.1 VBUS Input Only

In this scenario, only single input is connected to VBUS directly, no back-to-back power MOSFETs are required.

VAC1 and VAC2 are recommended to be shorted to VBUS. Both ACDRV1 and ACDRV2 need to be pulled down

to GND, as shown in the figure below.

ACDRV2

VAC2

VBUS

PMID

VBUS

ACDRV1

VAC1

Figure 13. Single Input Connected to VBUS Directly Without ACFET-RBFET

•

At POR, the charger detects no ACFETs-RBFETs are present by sensing that the ACDRV1 and ACDRV2

pins both shorted to GND.

The charger updates the status bits ACRB1_STAT and ACRB2_STAT to 0, and locks EN_ACDRV1 = 0 and

EN_ACDRV2 = 0.

VAC1 and VAC2 are connected to VBUS directly. The ACDRV1 and ACDRV2 pins always stay low.

8.3.3.2 One ACFET-RBFET

In this configuration, only ACFET1-RBFET1 is present, ACFET2-RBFET2 is not. VAC1 is tied to the drain of

ACFET1, ACDRV1 is connected to the gate of ACFET1. VAC2 is shorted to VBUS, ACDRV2 is pulled down to

GND. This structure is illustrated in the figure below, which is able to support either single input (one from VAC1

to VBUS through ACFET1-RBFET1, or one to VBUS directly) or dual-input (one from VAC1 to VBUS through

ACFET1-RBFET1, the other one connected to VBUS directly) applications.

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VRX

Wireless Charging

ACDRV2

VAC2

PMID

VBUS

VIN1

ACFET1

RBFET1

ACDRV1

VAC1

Figure 14. One ACFET-RBFET Structure Supporting One Input at VAC1 and/or One Input at VBUS

•

At POR, the charger detects only ACFET1-RBFET1 presented, updates ACRB1_STAT to 1 and keeps

ACRB2_STAT as 0.

•

The charger locks the register bit EN_ACDRV2 at 0, and the ACDRV2 pin will always stay low.

When a valid input is presented at VAC1, the charger will set EN_ACDRV1 = 1 and turn ACFET1-RBFET1

on.

•

To swap from the input at VAC1 to the input at VBUS, the host has to turn off the ACFET1-RBFET1 first by

setting DIS_ACDRV=1 (forcing EN_ACDRV1 = 0), then enable the other input source which is connected to

VBUS directly.

In contrast, to swap from the input at VBUS to the input at VAC1, the host has to disable the input source

connected to VBUS first, then turn on the ACFET1-RBFET1 by setting DIS_ACDRV = 0.

8.3.3.3 Two ACFETs-RBFETs

In this scenario, both ACFET1-RBFET1 and ACFET2-RBFET2 are present. VAC1 / VAC2 is tied to the drain of

ACFET1 / ACFET2, ACDRV1 / ACDRV2 is connected to the gate of ACFET1 / ACFET2. This structure is

developed to support dual-input connected at VA1 and VAC2.

RBFET2

ACFET2

VIN2

VIN1

ACDRV2

VAC2

PMID

VBUS

ACFET1

RBFET1

ACDRV1

VAC1

Figure 15. Two ACFETs-RBFETs Structure Supporting One Input at VAC1 and One Input at VAC2

•

At POR, the charger detects both ACFET1-RBFET1 and ACFET2-RBFET2 presented, then updates

ACRB1_STAT and ACRB2_STAT to 1.

•

EN_ACDRV1 and EN_ACDRV2 are programmable in this case.

The ACDRV turns on the ACFET-RBFET of the port with a valid input presented first. The other ACFET-

RBFET stays off, even if there is an adapter being plugged in later.

•

Programming EN_ACDRV1 = 1, EN_ACDRV2 = 1 at the same time to turn on both ACFET1-RBFET1 and

ACFET2-RBFET2 is not allowed, which will be ignored by the charger.

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•

Assuming two valid voltages are presented at VAC1 and VAC2, ACFET1-RBFET1 turns on, connecting the

input source at VAC1 to VBUS. If the voltage at VAC1 becomes invalid because of VAC_UVLO, VAC_OV or

IBUS_OC, the charger swaps the input from VAC1 to VAC2, by turning off ACFET1-RBFET1 and then turning

on ACFET2-RBFET2, without any host engagement. Swapping the input from VAC1 to VAC2 also can be

controlled by the host. For example, to swap VAC1 to VAC2, the host can program REG0x13[7:6]

(EN_ACDRV2, EN_ACDRV1) from 01b to 10b. The same control logic is applied to the input swapping from

VAC2 to VAC1.

The waveforms below show the charger input transition from VAC1 to VAC2 when VAC1 is disconnected. At the

beginning, VAC1 = 8V and VAC2 = 5V are both present. When VAC1 = 8V is gone, the charger accomplishes

the input source auto transition from VAC1 to VAC2 without host control.

Powered by VAC1

Powered by VAC2

SW1

Figure 16. Input Source Auto Transition from VAC1 to VAC2 when VAC1 is Gone

When VAC2 has been connected, even if VAC1 is re-plugged in again later, the charger still stays connecting

VAC2 as the input source, which is illustrated as the waveforms below. The host has to be involved to swap the

input source from VAC2 back to VAC1 if necessary.

SW1

Powered by VAC2

Figure 17. VAC1 Re-Plugged in When VAC2 Connected as the Charger Input

Some other critical notes for the application of this dual input power MUX are list below:

•

The register bits, EN_ACDRV1 and EN_ACDRV2, are not only to control the turning on / off of ACFETs-

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RBFETs but also to indicate the on / off status of the FETs.

•

The charger also provides the fault protection by turning ACFETs-RBFETs off, such as VAC_OVP and

IBUS_OCP.

With only one valid input presented at either VAC1 or VAC2, the ACFET1-RBFET1 and ACFET2-RBFET2

can not be both turned off by setting REG0x13[7:6] = 00b, because the charger is always trying to connect

the only one input voltage available to power the charger. At this condition, the host has to set DIS_ACDRV =

1 to force both two ACFETs-RBFETs off. With two input sources presented at both VAC1 and VAC2, the host

can turn of the two ACFETs-RBFETs by setting either REG0x13[7:6] = 00 or DIS_ACDRV = 1.

•

In the transition from one input to the other one, after one ACFET-RBFET is turned off, the other one turns on

until the VBUS voltage drops lower than V_{BUS_PRESENT}. The converter stops switching for a short time period.

When no battery presented or battery depleted, the system output would fall. The user has to be aware of this

and avoid the input source swap when the battery voltage is too low.

8.3.4 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above UVLO threshold (V_{BAT_UVLOZ}), the BATFET turns on and

connects the battery to the system through the internal BATFET. The REGN LDO stays off to minimize the

quiescent current. The low R_DS(ON)of BATFET and the low quiescent current on BAT minimize the conduction

loss and maximize the battery run time. The device always monitors discharge current through the BATFET.

8.3.5 Device Power Up from Input Source

When an input source is present at VBUS, the device checks the input source voltage to turn on REGN LDO and

all the bias circuits. It detects and sets the input current limit before the buck-boost converter is started. The

power up sequence from input source is as listed below:

1. Power Up REGN LDO

2. Poor Source Qualification

3. Set the Input Current Limit based on ILIM_HIZ pin voltage, and set the POR default VINDPM according to

the VBUS open circuit voltage.

4. Input Source Type Detection based on D+/D- to set default Input Current Limit (IINDPM) register and input

source type

5. Converter Power-up

8.3.5.1 Power Up REGN LDO

When the device is powered up from VBUS, the LDO is turned on when V_{VBUS_PRESENT}< VBUS < V_{VBUS_OVP}

.

When the device is powered up from battery only condition, the LDO is turned on at either one of the condition

list below:

•

The charger is operated in the OTG mode

VBAT is higher than 3.2V, and ADC TS channel is on (ADC_EN = 1 and TS_ADC_DIS = 0)

The REGN LDO supplies internal bias circuits and the MOSFETs gate drivers. The pull-up rails of ILIM_HIZ, TS,

and STAT can be connected to REGN. The INT pin pull-up rail is recommended to be an external 1.8V or 3.3V

voltage source, rather than REGN, because at battery only condition, the REGN might not be available. Except

the charger related pull up rails, the REGN is not recommended to source any other external circuit. The REGN

has to power the internal MOSFETs gate drivers, which is very critical for the charger normal operation.

8.3.5.2 Poor Source Qualification

After the REGN LDO powers up, the device checks the current capability of the input source. The input source

has to meet the following requirements in order to move forward to the next power on steps.

1. VBUS voltage below V_{VBUS_OVP}

2. VBUS voltage above V_POORSRCwhen pulling I_POORSRC(typical 30 mA)

Once the conditions are met, the status register bit PG_STAT is set high and the INT pin is pulsed to signal the

host. The PG pin goes LOW.

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If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage

fault goes away. If a poor source is detected (when pulling I_POORSRC, the VBUS voltage drops below V_POORSRC),

the device repeats poor source qualification routine every 2 seconds. After 7 consecutive failures, the device sets

EN_HIZ = 1 and goes to HIZ mode. The battery must have enough charge to power the system while the device

is in HIZ. Adapter re-plugin or EN_HIZ bit toggle is required when the input source can be used to power the

device. The EN_HIZ bit is cleared automatically when the adapter is plugged in. Whenever the VBUS voltage

does not meet either condition 1 or condition 2, it means the input source is not qualified anymore, the PG pin

goes HIGH and the PG_STAT bit goes low, at the same time, an INT pulse will be asserted and PG_FLAG will

be set to 1, if PG_MASK = 0.

8.3.5.3 Input Source Type Detection

After the input source is qualified, the charger device runs Input Source Type Detection if AUTO_INDET_EN bit

is set (default enabled).

The charger follows the USB Battery Charging Specification 1.2 (BC1.2) to detect SDP/CDP/DCP/HVDC input

sources and the non-standard adapters through the USB D+/D- lines. After BC1.2 detection is completed, the

BC1.2_DONE_STAT bit is set to 1, an INT pulse and BC1.2_DONE_FLAG are asserted if BC1.2_DONE_MASK

= 0. In addition, when USB DCP is detected, the charger initiates adjustable high voltage adapter handshake on

D+/D- if HVDCP detection is enabled by the host. The input type might be changed after HVDCP detection is

completed.

After input source type detection, the following registers are changed:

1. Input Current Limit (IINDPM) register is changed to set current limit

2. VBUS_STAT bits change to reflect the detected source

After detection is completed, the host can over-write IINDPM registers to change the input current limit if

necessary. The charger input current is limited by the lower of IINDPM register or ILIM_HIZ pin (when

EN_EXTILIM = 1) regardless of Input Current Optimizer (ICO) setting. When AUTO_INDET_EN is disabled, the

Input Source Type Detection is bypassed, and the Input Current Limit (IINDPM) register remains unchanged from

its previous value.

8.3.5.3.1 D+/D– Detection Sets Input Current Limit

The device contains a D+/D- based input source detection to set the input current limit. The D+/D- detection has

four major steps: Data Contact Detect (DCD), Primary Detection, Secondary Detection and High Voltage

(HVDCP) detection.

The D+/D- Primary Detection includes standard USB BC1.2 and non-standard adapters. When an input source is

plugged in, the device starts standard USB BC1.2 detection first. The USB BC1.2 is capable of identifying

Standard Downstream Port (SDP), Charging Downstream Port (CDP) and Dedicated Charging Port (DCP). The

non-standard detection is used to distinguish vendor specific adapters based on their unique dividers on the

D+/D- pins. The secondary detection is used to distinguish two types of charging ports, CDP and DCP.

A CDP usually requires the portable device (such as smart phone, tablet) to send back an enumeration within 2.5

seconds of CDP plug-in. Otherwise, the port will power cycle back to SDP even the D+/D- detection indicates

CDP.

Divider 1: 2.1A

Non-Standard

Adapter

Divider 2: 3A

Divider 3: 1A

Divider 4: 2.4A

DCP

(3.25A)

Adapter Plug-in

or

FORCE_INDET

Data Detection

Contact

DCP/CDP

Primary Detection

(PD)

Secondary

Detection

HVDCP

Detection

VBUS Detection

(DCD)

USB BC1.2 Standard

SDP

(500mA)

CDP

(1.5A)

HVDCP

(1.5A)

Figure 18. D+/D– Detection Flow

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Table 3. Non-Standard Adapter Detection

NON-STANDARD

D+ THRESHOLD

D– THRESHOLD

INPUT CURRENT LIMIT

ADAPTER

Divider 1

Divider 3

Divider 4

Unknown

V_D+within V_{2P8_VTH}

V_D+within V_{2P0_VTH}

V_D+within V_{2P8_VTH}

VD+ = 1 MΩ to 0 V

V_D–within V_{2P0_VTH}

V_D–within V_{2P8_VTH}

VD- = 3.3 V

2.1 A

1 A

2.4 A

3.0 A

When a Dedicated Charging Port (DCP) is detected, the charger initiates two high voltage adapter (HVDCP)

handshakes to enable the corresponding adapter to output a higher voltage for fast charging. The HVDCP

detection can be enabled by setting EN_HVDCP=1 and then setting either EN_9V=1 to increase the input

voltage to 9V or EN_12V=1 to increase the input voltage to 12V. When EN_12V and EN_9V are both set to 1,

the charger starts 12V first.

After the Input Source Type Detection is done, the DPDM_STAT bit is set to 0, an INT pulse and

DPDM_DONE_FLAG are asserted if DPDM_DONE_MASK = 0. In addition, the Input Current Limit register

(IINDPM), and VBUS_STAT registars are updated as below:

Table 4. Input Current Limit Setting from D+/D– Detection

D+/D– DETECTION

USB SDP

INPUT CURRENT LIMIT (IINDPM)

VBUS_STAT_3:0

0001

500 mA

1.5 A

3.25 A

1.5A

USB CDP

0010

USB DCP

0011

Adjustable High Voltage DCP (HVDCP)

Unknown Adapter

0100

3 A

0101

Non-Standard Adapter, Divider 3

Non-Standard Adapter, Divider 1

Non-Standard Adapter, Divider 4

1 A

0110

2.1 A

2.4 A

0110

8.3.5.3.2 Force Input Current Limit Detection

In host mode, the host can force the device to run Input Current Limit Detection by setting FORCE_INDET bit to

1. After the detection is completed, FORCE_INDET bit automatically returns to 0 and Input Source Result is

updated. After the detection is completed, the input current limit (IINDPM), and the VBUS_STAT bits may be

changed by the device according to the detection result.

8.3.5.3.3 Connector Fault Detection

The host can apply different status on D+ pin including HIZ, 0V, 0.6V, 1.2V, 2.0V, 2.7V, 3.3V or "short to D-", and

different status on D- pin including HIZ, 0.6V, 1.2V, 2.0V, 2.7V or 3.3V. The device also provides ADC readings

of the D+ and D- pin voltages. The host can use the information to determine if connector is normal or in any

faults. The voltage values are set using the DPLUS_DAC and DMINUS_DAC register. The D+/D- pins are only

applied at the VAC1 input source. If the DPLUS_DAC or DMINUS_DAC are programmed when the adapter is

plugged in and the D+/D- detection is in process, the device will ignore the register programming.

8.3.5.4 Input Current Optimizer (ICO)

The device provides Input Current Optimizer (ICO) to identify maximum power point in order to avoid overloading

the input source. The algorithm automatically identifies maximum input current limit of an unknown power source

and sets the charger IINDPM register properly, in order to prevent from entering the charger input voltage

(VINDPM) regulation. This feature is disabled by default at POR (EN_ICO = 0) and only activates when EN_ICO

bit is set to 1.

After DCP type input source is detected based on the procedures describe above (Input Source Type Detection),

the algorithm runs automatically if EN_ICO bit is set. The algorithm can also be forced to execute by setting

FORCE_ICO bit regardless of input source type detected. Please note that EN_ICO = 1 is required for

FORCE_ICO to work.

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The actual input current limit used by the Dynamic Power Management is reported in the ICO_ILIM register

whether set by ICO if enabled or IINDPM register if not. In addition, the current limit is clamped by ILIM pin

unless EN_EXT_ILIM bit is 0 to disable ILIM_HIZ pin function.

When the algorithm is enabled, it runs one time and then waits for the system load plus battery charge current to

pull enough input current to force the charger into VINDPM. The algorithm adjusts the actual input current limit as

shown in the ICO_ILIM until the ICO_STAT[1:0] and ICO_FLAG bits are set (the ICO_FLAG bit indicates any

change in ICO_STAT[1:0] bits). The algorithm operates depending on battery voltage:

1. When the battery voltage is below VSYSMIN, the algorithm starts ICO_ILIM register with IINDPM which is

the maximum input current limit allowed by system

2. When the battery voltage is above VSYSMIN, the algorithm starts ICO_ILIM register with 500 mA which is

the minimum input current limit to minimize adapter overload

Once the optimal input current is identified, the ICO_STAT[1:0] and ICO_FLAG bits are set. The actual input

current is reported in the ICO_ILIM register and does change unless the algorithm is triggered again by the

following events :

1. A new input source is plugged-in, or EN_HIZ bit is toggled

2. IINDPM register is changed

3. VINDPM register is changed

4. FORCE_ICO bit is set to 1

5. VBUS_OVP event

These events also reset the ICO_STAT[1:0] bits to 01

8.3.5.5 Default VINDPM Setting

In the POR sequence, right after the D+/D- detection, the charger initiates ADC reading on the VBUS pin voltage

without any load current (VBUS at no load condition, VBUS0) before the converter starts switching. The default

VINDPM threshold is set to be VBUS0 - 1.4 V (VBUS0 >= 7 V) or VBUS0 - 0.7V (VBUS0 < 7 V).

If the converter already starts switching, the VBUS0 measurement can be performed by setting the register bit

FORCE_VINDPM_DET=1. The force VINDPM detection only can be done when VSYS_STAT = 0 (VBAT >

VSYSMIN). To measure the VBUS0 when the converter is running, the charger suspends charging (if enabled)

and the converter stops switching. Then the ADC measures the VBUS voltage without any input load current and

update the VINDPM register bit. After the VINDPM register bit is reset, the FORCE_VINDPM_DET bit returns to

0 automatically. If VSYS_STAT = 1 (VBAT < VSYSMIN), VBUS0 measurement does not start, the

FORCE_WINDPM_DET bit resets to 0 and the VINDPM register retains its current value. The host must ensure

there is a battery presence prior to force VINDPM detection by setting FORCE_VINDPDM_DET bit to allow

system to be supported by the battery during detection.

When the measured VBUS0 is too low, for example 3.6V, or too high, for example 25V, the calculated VINDPM

based on the equation list above is out of the VINDPM register range, and then the changer sets the VINDPM

register to be the minimal value (3.6V) or maximum (22V) value.

8.3.5.6 Device HIZ State

The charger enters HIZ mode when EN_HIZ bit is set to 1. The HIZ mode refers to a charger state, in which the

REGN LDO is off, and the converter stops switching even if the adapter is present. Similar to the battery only

condition, the charger is in a low quiescent current mode, turns off the ADC and turns on the BATFET to support

the system load.

Some of the faults like VBUS_OVP, VSYS_OVP, VBAT_OVP and OTG_OVP, force only the converter to stop

switching but keep the REGN on. While some of the faults like VSYS_SHORT and IBUS_OCP, force the charger

into HIZ mode by setting EN_HIZ=1. More details could be found in the fault protection section.

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8.3.5.7 ILIM_HIZ Pin

At POR, before the charger converter starts switching, the charger ADC reads the ILIM_HIZ pin voltage, and

calculates the input current limit (ILIM) set by this ILIM_HIZ pin, according to the equation V_{ILIM_HIZ}= 1V + 800

mΩ × ILIM. The ILIM_HIZ pin sets a high clamp for the IINDPM register. If the IINDPM setting from the D+/D-

detection or the POR default 3A IINDPM setting is higher than the ILIM clamp, the IINDPM register stays at this

ILIM clamp. In addition, the host cannot program the IINDPM register to any values higher than this ILIM clamp

after POR, unless the register bit EN_EXTILIM is set to 0.

The ILIM_HIZ pin can be biased from an resistor voltage divider that can be tied to either the REGN or the other

external voltage source. For both the forward charging mode and the OTG mode, when the ILIM_HIZ pin is

pulled lower than 0.75V, the charger stops switching and REGN stays on. The charger resumes switching if the

ILIM_HIZ pin voltage becomes higher than 1V.

If the ADC reads the ILIM_HIZ pin voltage is lower than 1.08V (1V + 800 mΩ × 100 mA), the charger considers

the ILIM clamp to be 100mA, which is the minimal setting of the IINDPM register.

8.3.5.8 IBAT Pin for Battery Current Sensing

BQ25790 provides a high-accuracy battery charging / discharging current sensing pin, IBAT. It outputs a 25 µA

current when the battery charging / discharging current is 1 A. The IBAT pin output is valid when either VBUS or

VBAT voltage is higher than its own ULVO voltage, and EN_IBAT register bit is set to 1. The IBAT pin only

provides the battery charging current in forward charging mode and the battery discharging current at battery

only condition or OTG mode. When the charger is operated in forward charging mode, the output of the IBAT pin

becomes zero when the battery is turning into the supplement mode.

8.3.5.9 Buck-Boost Converter Operation

The charger employs a synchronous buck-boost converter that allows charging the 1s to 4s battery from a legacy

5V USB input source, HVDCP and USB-PD power sources. The charger operates in buck, buck-boost or boost

mode based on different input voltage and output voltage combinations. The converter can operate

uninterruptedly and continuously across the Buck, Buck-boost and Boost three different operating states.

8.3.5.9.1 Pulse Frequency Modulation (PFM)

In order to improve converter light-load efficiency, the device switches to PFM control at light load condition. The

effective switching frequency decreases accordingly as load current decreases. The PFM operation can be

disabled by setting PFM_FWD_DIS = 1, the converter stays at the PWM mode switching frequency and go to

DCM operation at light load condition. The minimum effective switching frequency in PFM can be limited to 25

kHz to eliminate the audible noise concern if the out of audio (OOA) feature is enabled by setting

DIS_FWD_OOA = 0. The host can disable the OOA by setting DIS_FWD_OOA = 1, which may result in the

converter effective switching frequency dropping below 25 kHz at extremely light load.

8.3.6 USB On-The-Go (OTG)

8.3.6.1 OTG Mode to Power External Devices

The device supports the OTG operation to deliver power from the battery to other external devices through the

USB ports. The OTG voltage regulation is set in VOTG[10:0] register bits. The OTG current regulation is set in

IOTG[6:0] register bits. To enable the OTG operation, the following conditions have to be valid:

•

The battery voltage is higher than V_{BAT_OTG}rising threshold, and not trigger the VBAT_OVP protection.

The VBUS is below V_{VBUS_UVLO}

The voltage at TS pin is within the range configured by BHOT and BCOLD register bits

.

If the ACFET1-RBFET1 and the ACFET2-RBFET2 are not detected (ACRB1_STAT = 0 and ACRB2_STAT = 0)

at POR, the converter starts up with typical 5ms delay after the EN_OTG bit is set to 1, then the VBUS voltage

ramps up to the VOTG register setting.

The following cases explain the charger OTG mode behaviors when the ACFET1-RBFET1 or/and ACFET2-

RBFET2 are present.

•

If only ACRB1_STAT=1 OR only ACRB2_STAT = 1, which means only one input ACFET-RBFET is present,

the converter stays in the non-switching mode after the EN_OTG bit is set, until the host writes EN_ACDRV1

= 1 (when only ACRB1_STAT = 1) or EN_ACDRV2 = 1 (when only ACRB2_STAT = 1). The converter starts

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up with 5ms delay after the EN_ACDRV1 or EN_ACDRV2 bit is set to 1, then VBUS voltage ramps up to the

VOTG register setting.

•

If both ACRB1_STAT = 1 AND ACRB2_STAT = 1, which means two input ACFET-RBFET are present, the

converter stays in the non-switching mode after the EN_OTG bit is set, until the host writes either

EN_ACDRV1 = 1 or EN_ACDRV2 = 1. The converter starts up with 5ms delay after the EN_ACDRV1 or

EN_ACDRV2 bit is set to 1, then VBUS voltage ramps up to the VOTG register setting.

•

Regardless of ACRB1_STAT and ACRB2_STAT, if DIS_ACDRV = 1, the ACDRV is disabled. The converter

starts up with 5ms delay after the EN_OTG bit is set to 1, then VBUS voltage ramps up to the VOTG register

setting. The operation is the same as that when ACFET1-RBFET1 and ACFET2-RBFET2 are not detected.

For swapping the OTG output from port 1 to port 2, assuming EN_ACDRV2 is already 0, the host has to set

EN_ACDRV1 = 0 to turn off ACFET1_RBFET1 first, which causes the converter to stop switching and VBUS

to drop below V_{BUS_PRESENT}. The host sets EN_ACDRV2 = 1, the converter starts switching again and

ACDRV2 turns on ACFET2-RBFET2, which allows VBUS to ramp up. The similar procedure can be applied

to the case of swapping the OTG output from port 2 to port 1.

In OTG mode, the converter PFM operation can be disabled by setting PFM_OTG_DIS = 1 and the OOA can be

disabled by setting DIS_OTG_OOA = 1.

USB2

ACFET2

ACFET1

RBFET2

RBFET1

VBUS

SW1

PMID

SYS

BAT

USB1

SW2

I2C Bus

BATP

BATN

Host

Battery

Host

Control

GND

Figure 19. The Simplified Application Diagram for the OTG Mode Operation

The simplified application diagram for the OTG mode operation is shown as the figure above, in which the power

flow is illustrated by the blue arrows.

The charger is also monitoring the battery discharging current in OTG mode. When IBAT rises higher than the

IBAT_REG[1:0] register setting, the charger reduces the OTG output current and prioritizes the system load

current if there is any. The IBAT_REG_STAT bit is set to 1 and an INT pulse is asserted and the

IBAT_REG_FLAG is set to 1, if IBAT_REG_MASK = 0. If the OTG output current is decreased to zero and the

system load pulls even more current, the charger can no longer limit the battery discharging current.

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8.3.7 Power Path Management

The device accommodates a wide range of input voltage range from 3.6V to 24V covering the legacy 5V USB

input, HVDCP, USB-PD input and the wall adapter. The device provides automatic power path selection to

supply the system (SYS) from input source (VBUS), battery (BAT) or both.

8.3.7.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by VSYSMIN bits. Even with a fully depleted battery, the system is regulated

above the minimum system voltages. The default minimum system voltage at POR is determined according to

different battery cell settings.

The NVDC architecture also provides the charging termination when the battery is fully charged. By turning off

the BATFET, the adapter power is prioritized to support the system, which avoid the battery being continuously

charged and discharged by the system load even if the adapter is present. This is very important to keep the

battery in a healthy condition and extend the battery life time.

When the battery voltage is below the minimum system voltage setting, the BATFET operates in linear mode

(LDO mode), and the system is regulated at around 200 mV above the minimum system voltage setting. As the

battery voltage rises above the minimum system voltage, the BATFET is fully on and the voltage difference

between the system and battery is the Rdson of BATFET multiplied by the charging current. When battery

charging is disabled and VBAT is above the minimum system voltage setting or charging is terminated, the

system is always regulated at typically 200mV (PFM disabled) or typical 600mV (PFM enabled) above battery

voltage. The status register VSYS_STAT bit goes high when the system is in minimum system voltage

regulation.

9.0

8.6

Charge Enabled

8.2

7.8

Charge Disabled

7.4

7.0

Minimum System Voltage

6.6

6.2

5.4 5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6

BAT (V)

Figure 20. Typical System Voltage vs Battery Voltage for a 2S Battery Configuration

8.3.7.2 Dynamic Power Management

To meet the maximum current limit in USB spec and avoid over loading the adapter, the device features

Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When the

input power at the VBUS pin is too low to support the load from SYS pin and the battery charge current from BAT

pin, the charger engages either IINDPM to limit its current or VINDPM to prevent further reduction in VBUS pin

voltage.

When the system voltage is regulated at VSYSMIN, the charger could be in trickle charge, pre-charge or fast

charge stages, the SYS voltage drops lower than VSYSMIN, the VSYSMIN loop takes over and reduces the

trickle charge, pre-charge or fast charge current, so that the SYS voltage remains at the VSYSMIN level.

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If the charge current falls to zero, but the input source is still overloaded, the SYS voltage will drop. Once the

SYS voltage falls below the battery voltage, the device automatically enters Supplement Mode in which the

BATFET turns on. The battery starts discharging so that the system is supported from both the input source and

battery. In supplement mode, the battery FET is operated in ideal diode mode in which the charger regulates the

battery FET gate voltage to keep the BATFET minimum V_DSto approximately 25 mV when the current is low.

This prevents SYS voltage oscillations from entering and exiting the supplement mode. As the discharge current

increases, the charger regulates the BATFET gate to a higher voltage, in order to reduce the battery FET R_DSON

until the MOSFET is in full turn-on stage. At this point onwards, the V_DSof the battery FET linearly increase with

the discharge current. The figure below shows the V-I curve of the BATFET gate regulation operation. The

BATFET turns off to exit Supplement Mode when the battery is below battery depletion threshold.

45

40

35

30

25

20

1

1.5

2

2.5

3

IBAT (A)

3.5

4

4.5

5

Figure 21. BATFET I-V Curve

During DPM mode, the status register bits VINDPM_STAT (VINDPM) and/or IINDPM_STAT (IINDPM) go high.

The figure below shows the DPM response with 5V/3A adapter, 6.4V battery, 1.5A charge current and 6.8V

minimum system voltage setting.

V_SYS

7.0V

6.8V

V_BAT

6.4V

6.0V

V_BUS

5.0V

4.0V

3A

I_BUS

2A

I_BAT

1A

I_SYS

0A

-1A

DPM

CC

DPM

CC

Supplement

Figure 22. DPM Response

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8.3.8 Battery Charging Management

BQ25790 charges 1S~4S Li-Ion batteries with up to 5A charge current for high capacity cells. The battery

charging in different stages is controlled by the integrated BATFET. The low R_DS(ON)BATFET improves charging

efficiency and minimizes the voltage drop during discharging.

8.3.8.1 Autonomous Charging Cycle

When battery charging is enabled (EN_CHG bit =1 and CE pin is LOW), the device autonomously completes a

charging cycle without host involvement. The device default charging parameters are listed in the table below.

The host can always control the charging operation and optimize the charging parameters by writing to the

corresponding registers through I²C.

Table 5. Charging Parameter Default Settings

DEFAULT MODE

Charging voltage

BQ25790

4.2 V (1S), 8.4 V (2S), 12.6 V (3S), 16.8 V (4S)

Recharging voltage threshold

Fast charge current

200 mV

2 A (1S and 2S), 1 A (3S and 4S)

Pre-charge current

120 mA

100 mA

200 mA

JEITA

Trickle charge current

Termination current

Temperature profile

Fast charge safety timer

Pre charge safety Timer

Trickle charge safety Timer

12 hours

2 hours

1 hour

A new charge cycle starts when the following conditions are valid:

•

Converter starts up

Battery charging is enabled by setting register bit EN_CHG = 1 and keeping CE pin LOW

No thermistor fault on TS pin

No safety timer fault

The charger automatically terminates the charging cycle when the charging current is below termination

threshold, charge voltage is above recharge threshold, and the device is not in DPM mode or thermal regulation.

When a fully charged battery voltage is discharged below recharge threshold (threshold selectable via

VRECHG[1:0] bits), the device automatically starts a new charging cycle. After the charging terminates, toggling

either CE pin or EN_CHG bit initiates a new charging cycle.

The STAT output indicates the charging status of: charging (LOW), charging complete or charging disabled

(HIGH) or charging fault (Blinking). The STAT output can be disabled by setting DIS_STAT = 1. In addition, the

status register (CHG_STAT) indicates the different charging phases as:

•

000 – Not Charging

001 – Trickle Charge (VBAT < V_{BAT_SHORTZ}

)

010 – Pre-charge (V_{BAT_SHORTZ}< VBAT < V_{BAT_LOWV}

011 – Fast Charge (CC mode)

100 – Taper Charge (CV mode)

101 – Reserved

110 – Top-off Timer Active Charging

111 – Charge Termination Done

)

When the charger transitions to any of these states, including when the charge cycle completes, an INT is

asserted to notify the host.

8.3.8.2 Battery Charging Profile

The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and

top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and

regulates current/voltage accordingly.

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Table 6. Default Charging Current Setting

VBAT

CHARGING CURRENT

I_{BAT_SHORT}

REGISTER DEFAULT SETTING

CHRG_STAT

< V_{BAT_SHORT}

V_{BAT_SHORTZ}to V_{BAT_LOWV}

100 mA

120 mA

001

010

I_PRECHG

2 A (1S and 2S)

1 A (3S and 4S)

> V_{BAT_LOWV}

ICHG

011

If the charger is in DPM regulation or thermal regulation during charging, the actual charging current is less than

the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted

at half the clock rate, as explained in Charging Safety Timer.

The BATFET LDO operation can be disabled by setting DIS_LDO = 1. At this condition, the pre-charge current

and fast charge current are both regulated by the buck-boost converter PWM current regulation loop. The SYS is

not regulated at VSYSMIN any more when the LDO mode is disabled at the low battery voltage condition. When

in trickle charge, setting DIS_LDO = 1 does not affect I_{BAT_SHORT}or VSYSMIN operation.

V_{BAT_LOWV}is the battery voltage threshold for the transition from pre-charge to fast charge. It is defined as a ratio

of battery voltage regulation limit (VREG). The V_{BAT_SHORTZ}is the battery voltage threshold for the transition from

trickle charge to pre-charge, which is fixed value 2.2V.

Regulation Voltage

VREG[10:0]

Battery Voltage

Charge Current

ICHG[8:0]

Charge Current

V_SYSMIN

V_{BAT_LOWV}

V_{BAT_SHORTZ}

IPRECHG[5:0]

ITERM[4:0]

Trickle Charge

001

Pre-charge

010

Fast-Charge

CC

Taper-Charge

CV

Top-off Timer

(optional)

CHG_STAT[2:0]

011

110

111

100

Safety Timer

CHG_TMR[1:0]

Pre-charge

Timer

(2hrs or 0.5hr)

Trickle charge

Timer

(1hr fixed)

Figure 23. Battery Charging Profile

8.3.8.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above the recharge threshold, the converter is

operated in the battery constant voltage regulation loop and the current is below the termination current. After the

charging cycle is completed, the BATFET turns off. The converter keeps running to power the system and the

BATFET can turn on again if the supplement mode is triggered.

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When termination is done, the status register CHG_STAT is set to 111 and an INT pulse is asserted to the host.

Termination is temporarily disabled when the charger device is in input current (IINDPM), input voltage

(VINDPM) or thermal (TREG) regulation. Termination can be permanently disabled by writing 0 to EN_TERM bit

prior to charging termination. Writing 0 to EN_TERM when the termination already occurred or in the top-off

charging stage does not disable termination, until the next charging cycle has been restarted. If termination is

reenabled by setting EN_TERM = 1 during the current charge cycle, the change is applied immediately to the

current charging cycle.

At low termination currents (like 40mA to 160mA), due to the comparator offset, the actual termination current

may be up to 20%~40% higher than the termination target. In order to compensate for the comparator offset, a

programmable top-off timer (default disabled) can be activated after termination is detected. Whlie the top-off

timer is running, the device continues to charge the battery in constant voltage mode (BATFET stays on) until the

top-off time expires. The top-off timer follows safety timer constraints, such that if the safety timer is suspended,

so is the top-off timer. And if the safety timer is doubled, so is the top-off timer. CHG_STAT reports whether the

top off timer is active via the 110 code. Once the top-off timer expires, the CHG_STAT register is set to 111 and

an INT pulse is asserted to the host.

The top-off timer gets reset (set to 0 and counting resumes when appropriate) for any of the following conditions:

1. Charge disable to enable

2. Termination status low to high

3. REG_RST register bit is set (disables top-off timer)

Once the charger detects termination, the charger reads the top-off timer (TOPOFF_TMR) settings.

Programming the top-off timer value after termination has no effect unless a recharge cycle is initiated. The top-

off timer only starts to count when the charger's termination criteria are met. If EN_TERM = 0, the charger never

terminates charging, so the top-off timer does not start counting, even if it is enabled. An INT is asserted to the

host when the top-off timer starts counting as well as when the top-off timer expires. All charge cycle related INT

pulses (including top-off timer INT pulse) can be masked by CHG_MASK bit.

8.3.8.4 Charging Safety Timer

The device has a built-in safety timer to prevent an extended charging cycle due to abnormal battery conditions.

The user can program the fast charge safety timer through I²C (CHG_TMR bits). When the fast charge safety

timer expires, the fault register CHG_TMR_STAT bit is set to 1, and an INT pulse is asserted to the host. The

trickle charge timer is fixed 1 hour. The pre-charge safety timer is adjustable 2 hours (POR default) or 0.5 hour.

The fast charging timer POR default setting is 12 hours.

The trickle charge, pre-charge and fast charge safety timers can be disabled by setting EN_TRICHG_TMR,

EN_PRECHG_TMR or EN_CHG_TMR bit to 0. Each charging safety timer can be enabled anytime regardless of

the current charging state. Each timer restarts counting when it is enabled. As soon as each charging stage is

initiated, the associated safety timer starts to count, which is illustrated in the battery charging profile chart shown

in the section Battery Charging Profile.

During input voltage, current or thermal regulation, the safety timer counts at half-clock rate as the actual charge

current is likely to be below the register setting. For example, if the charger is in input current regulation

(IINDPM_STAT = 1) throughout the whole charging cycle, and the safety timer is set to 5 hours, then the timer

will expire in 10 hours. This half-clock rate feature can be disabled by setting TMR2X_EN = 0. If the host

disables the half-clock rate while the charger is already running at half-clock rate, the charger keeps running at

the half-clock rate and the half-clock rate is not disabled until the charger exit the voltage, current or thermal

regulation.

During faults which disable charging, or supplement mode, the timer is suspended. Since the timer is not

counting in this state, the TMR2X_EN bit has no effect. Once the fault goes away, the safety timer resumes. If

the charging cycle is stopped and started, the timer resets. The pre-charge safety timer and the trickle charge

safety timer follow the same rules as the fast charge safety timer in terms of getting suspended, reset and

counting at half-rate when TMR2X_EN is set.

The fast charge timer is reset at the following events:

1. Charging cycle stop and restart (toggle CE pin, EN_CHG bit, or charged battery falls below recharge

threshold after termination)

2. BAT voltage changes from pre-charge to fast-charge or vice versa (in host-mode or default mode)

3. A change of the value of CHG_TMR[1:0] register bits

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The pre-charge timer is reset at the following events:

1. Charging cycle stop and restart (toggle CE pin, EN_CHG bit, or charged battery falls below recharge

threshold)

2. BAT voltage changes from trickle charge to pre-charge or vice versa, pre-charge to fast charge or vice versa

(in host-mode or default mode)

3. A change of the value of PRECHG_TMR register bit.

The trickle charge timer is reset at the following events:

1. Charging cycle stop and restart (toggle CE pin, EN_CHG bit, or charged battery falls below recharge

threshold)

2. BAT voltage changes from trickle charge to pre-charge or vice versa (in host-mode or default mode)

8.3.8.5 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitoring.

8.3.8.5.1 JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, the JEITA guideline was released on April 20, 2007. The

guideline emphasized the importance of avoiding a high charge current and high charge voltage at certain low

and high temperature ranges.

To initiate a charge cycle, the voltage on the TS pin must be within the VT1 to VT5 thresholds. If TS voltage

exceeds the VT1-VT5 range, the controller suspends charging and waits until the battery temperature is within

the T1 to T5 range. At cool temperature T1-T2, JEITA recommends to reduce the charge current to be lower

than half of the charge current at normal temperature T2-T3. The charger register bits JEITA_ISETC[1:0] provide

the charge current programmability at T1-T2, to be 20%, 40% or 100% of the charge current in the T2-T3

temperature range or charge suspend. At warm temperature T3-T5, JEITA recommends charge voltage less than

4.1V / cell. The charger register bits JEITA_VSET[2:0] provide the charge voltage programmability at T3-T5, to

be with a voltage offset less than charge voltage in the T2-T3 temperature range or charge suspend.

Charging termination is still enabled (when EN_TERM = 1) at cool temperature T1-T2 and warm temperature T3-

T5. The termination current remains the same in all different temperature ranges. In normal operation, battery

charging terminates when the charge current is lower than the termination current, the battery voltage is higher

than the battery recharge voltage and the charger is in the battery voltage CV regulation loop. When the

temperature enters the T1-T2 or T3-T5 ranges, the charge current may reduce to 20% or 40% of that in the T2-

T3 range, which might be lower than the termination current setting. If at this moment, the battery voltage is

already higher than the battery recharge voltage and the charger is in the battery voltage CV regulation loop, the

charger terminates charge.

In warm T3-T5 temperature range, the battery voltage regulation value become lower than that in the T2-T3

temperature range. If the battery voltage is already very close to the T2-T3 regulation value, the JEITA warm

automatic regulation voltage reduction might cause a battery over-voltage (VBAT_OVP) fault.

In cool T1-T2 temperature range or warm T3-T5 temperature range, the charge current is different from that at

the normal T2-T3 temperature range , the safety timer must be adjusted accordingly. The safety timer is

suspended when the charge is suspended, and runs at half of the clock rate when the charge current is reduced

to 20% or 40%, but stays the same when the charge current is unchanged.

One typical JEITA charging values are shown as the figure below, in which the blue real line is the default setting

and the red dash line is the programmable options.

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programmable

VREG - offset

programmable

100%

V_REG

offset = 0mV, 100mV, 200mV,

300mV, 400mV, 600mV or 800mV

80%

60%

40%

20%

T1

T2

T3

T5

T1

T2

T3

T5

TS Temperature

Figure 24. TS Charging Values

The NTC monitoring on the battery temperature can be ignored by the charger if TS_IGNORE = 1. When the TS

pin feedback is ignored, the charger considers the TS is always good for charging and OTG modes. The

TS_STAT including TS_COLD_STAT, TS_COOL_STAT, TS_WARM_STAT and TS_HOT_STAT, always report

000 with TS_IGNORE = 1.

When TS_IGNORE = 0, the charger adjusts the charging profile based on the TS pin feedback information.

When the battery temperature jumps from one temperature range to the other one, the associated TS status bits

are updated accordingly. The TS flag bits are set for the temperature range for which the TS voltage is reporting,

and an INT pulse is asserted to alert the host if TS_MASK is low. The FLAG and INT pulse can be individually

masked by properly setting the associated mask bit, to prevent the INT pulse from alerting the host of battery

temperature range changes.

The typical TS resistor network is illustrated in the figure below.

REGN

10 kꢀ

TS

BQ2579x

Figure 25. TS Resistor Network

Assuming a 103AT NTC thermistor on the battery pack as shown above, the value of TSR1 and TSR2 can be

determined by:

(1)

(2)

The BQ25790 provides the comparators with fixed thresholds for VT1 and VT5, and the comparators with

programmable thresholds for VT2 and VT3. The thresholds for VT2 and VT3 are controlled by TS_COOL[1:0]

and TS_WARM[1:0]. This programmability gives more flexibility for the configuration of the JEITA profile. Select

T1=0°C and T5=60°C for Li-ion or Li-polymer battery, the RT1 and RT2 are calculated to be 5.24KΩ and

30.31KΩ respectively.

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8.3.8.5.2 Cold/Hot Temperature Window in OTG Mode

For battery protection during OTG mode, the device monitors the battery temperature to be within the VBCOLD

to VBHOT thresholds. When RT1 is 5.24 KΩ and RT2 is 31.31 KΩ, TBCOLD default is -10°C and TBHOT default

is 60°C. When the temperature is outside of this range, OTG mode is suspended, the converter stops switching.

The charger waits in OTG mode (EN_OTG = 1). In addition, the VBUS_STAT bits are set to 000 and the

corresponding TS_COLD_STAT or TS_HOT_STAT is reported. Once temperature returns to the normal

temperature range, OTG mode is recovered and TS stauts bit is cleared. During TS fault, REGN still stays on.

Temperature Range for OTG Mode

VREGN

OTG suspended

V_BCOLDx

(œ10°C / œ20°C)

OTG is ongoing

V_BHOTx

(55°C / 60°C / 65°C)

OTG suspended

GND

Figure 26. TS Pin Thermistor Sense Threshold in OTG Mode

8.3.9 Integrated 16-Bit ADC for Monitoring

The integrated 16-bit ADC in the device allows the user to get critical system information for optimizing the

behavior of the charger. The ADC control is through the ADC Control register. The ADC_EN bit provides the

ability to enable and disable the ADC in order to conserve power dissipation. The ADC_RATE bit allows

continuous conversion or one-shot behavior. After a 1-shot conversion finishes, the ADC_EN bit is cleared, and

must be re-asserted to start a new conversion. The ADC_AVG bit enables or disables (default) averaging.

ADC_AVG_INIT starts average using the existing (default) or using a new ADC value.

To enable the ADC, the ADC_EN bit must be set to 1. The ADC is allowed to operate if either the VAC > 3.4 V or

VBUS > 3.4 V or VBAT > 2.9 V is valid. If ADC_EN is set to 1 before VAC1/VAC2, VBUS or VBAT reaches its

valid threshold, then the ADC conversion is postponed until one of the power supplies reaches the threshold. If

the charger is in HIZ mode, the ADC still can be enabled by setting ADC_EN = 1. At battery only condition, if the

TS_ADC channel is enable, the ADC only works when battery voltage is higher than 3.2V, otherwise, the ADC

works when the battery voltage is higher than 2.9V.

The ADC_SAMPLE bits control the ADC sample speed, with conversion times of t_{ADC_CONV}. If the host changes

the sample speed in the middle of an ADC conversion, the ADC conversion stops the channel being converted,

and that channel is reconverted at the new rate. At that point, some of the ADC register values might have been

converted with one sample rate and others with a different sample rate.

By default, all ADC channels are enabled with 1-shot or continuous conversion mode unless the channel is

disabled in the ADC_Function_Disable_0 or ADC_Function_Disable_1 register. If an ADC channel is disabled by

setting the corresponding register bit, then the value in that register is from the last valid ADC conversion or the

default POR value (all zeros if no conversions have been taken place). If an ADC channel is disabled in the

middle of an ADC measurement cycle, the device finishes the conversion of that channel, but not convert the

channel at the next conversion cycle. Even though no conversion takes place when all ADC channels are

disabled, the ADC circuitry is active and ready to begin conversion as soon as one of the bits in the

ADC_Function_Disable_0 or ADC_Function_Disable_1 register is set to 0.

The ADC_DONE_STAT and ADC_DONE_FLAG bits are set when a conversion is complete in 1-shot mode only.

This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous

conversion mode, the ADC_DONE_STAT and ADC_DONE_FLAG bits have no meaning and remain 0.

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ADC conversion operates independently of the faults present in the device. ADC conversion continues even after

a fault has occurred (such as one that causes the power stage to be disabled) and the host must set ADC_EN =

0 to disable the ADC. ADC conversion is interrupted upon adapter plug-in and resumes after Input Source Type

Detection default VINDPM setting are complete. ADC readings are only valid for DC states and not for transients.

Enabling ADC does not require to bring up REGN, however, when the ADC TS channel is enabled, the charger

will turn on the REGN to bias the TS pin. For the ICHG channel, the ADC is able to read the battery pre-charge

and fast charge current in forward charging mode when the adapter is present. It also can read the battery

discharging current in battery only mode, OTG mode. When the charger is in trickle charge, supplement mode or

charge disabled, the ICHG ADC reading is zero. In battery only mode, the battery current sensing amplifier

(CSA) default turns off to minimize the quiescent current. Setting EN_IBAT = 1 is necessary to enable the CSA

so that the ADC can read back the battery current information.

If the host wants to exit the ADC more gracefully, it is possible to do either of the following:

1. Write ADC_RATE to one-shot in order to force the ADC to stop at the end of a complete cycle of conversions

2. Disable all ADC conversion channels so that the ADC stops at the end of the current measurement.

8.3.10 Status Outputs (PG, STAT, and INT)

8.3.10.1 Power Good Indicator (PG)

The PG pin goes low and the power good status register is set to 1 once a good input source is qualified. The

PG_STAT and PG_FLAG change to 1 to indicate a good input source. An INT is asserted low to alert the host

unless masked by PG_MASK when the following conditions are met:

1. VBUS above V_{VBUS_UVLOZ}

2. VBUS below V_{VBUS_OVP}threshold

3. VBUS above V_POORSRC(typical 3.4 V) when I_POORSRC(typical 30 mA) current is applied (not a poor source)

8.3.10.2 Charging Status Indicator (STAT Pin)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED. The STAT pin

function can be disabled via the DIS_STAT bit.

Table 7. STAT Pin State

CHARGING STATE

STAT INDICATOR

Charging in progress (including recharge and charging in top-off

timer)

LOW

Charging complete

HIZ mode, charge disable

HIGH

Battery only mode and OTG mode

HIGH

Charge suspend (A fault condition which disable charging)

Blinking at 1 Hz

8.3.10.3 Interrupt to Host (INT)

In some applications, the host does not always monitor charger operation. The INT pin notifies the system host

on the device operation. By default, the following events generate an active-low, 256µs INT pulse.

1. Good input source detected

–

V_VBUS< V_{VBUS_OVP}threshold

V_VBUS> V_POORSRC(typical 3.4 V) when I_POORSRC(typical 30 mA) current is applied (not a poor source)

2. VBUS_STAT changes state (VBUS_STAT any bit change)

3. Good input source removed

4. Entering IINDPM regulation

5. Entering VINDPM regulation

6. Entering IC junction temperature regulation (TREG)

7. I²C Watchdog timer expired

–

At initial power up, this INT gets asserted to signal I²C is ready for communication

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8. Charger status changes state (CHRG_STAT value change), including Charge Complete

9. TS_STAT changes state (TS_STAT any bit change)

10. VBUS over-voltage detected (VBUS_OVP)

11. VAC over-voltage detected (VAC_OVP for VAC1 or VAC2)

12. Junction temperature shutdown (TSHUT)

13. Battery over-voltage detected (BATOVP)

14. System over-voltage detected (VSYS_OVP)

15. IBUS over-current detected (IBUS_OCP)

16. IBAT over-current detected (IBAT_OCP)

17. Charge safety timer expired, including trickle charge and pre-charge and fast charge safety timer expired

18. A rising edge on any of the other *_STAT bits

Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.

Three bits exist for each one of these events:

•

The STAT bit holds the current status of each INT source

The FLAG bit holds information on which source produced an INT, regardless of the current status

The MASK bit is used to prevent the device from sending out INT for each particular event

When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT

pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are

automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the

FLAG.

IINDPM_STAT

IINDPM_FLAG

TREG_STAT

TREG_FLAG

INT

I2C Flag Read

Figure 27. INT Generation Behavior Example

8.3.11 Ship FET Control

The charger provides an N-FET driving pin (SDRV) to control an external ship FET. When this ship FET is off, it

removes leakage current from the battery to the system. The ship FET is controlled by the SDRV_CTRL[1:0]

register bits, to support the shutdown mode, ship mode and the system power reset.

•

IDLE Mode when SDRV_CTRL[1:0] = 00, POR default. The external ship FET is fully on, I²C is enabled. The

internal BATFET status is determined by the charging status. This mode could be for adapter present forward

mode, OTG mode or battery only condition.

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•

Shutdown Mode when SDRV_CTRL[1:0] = 01. The ship FET and the internal BATFET are both off. The I²C

is disabled. The charger is totally shutdown and can only be woken up by an adapter plug-in. This mode is

only for the battery only condition.

Ship Mode when SDRV_CTRL[1:0] = 10. The ship FET and the internal BATFET are both off. The I²C is still

enabled. The charger can be woken up by setting SDRV_CTRL[1:0] back to 00, or pulling the QON pin low,

or an adapter plug-in. This mode is only for the battery only condition.

System Power Reset when SDRV_CTRL[1:0] = 11. The ship FET is turned off for typical 350ms to reset the

system power (converter goes to HIZ mode if VBUS is high), then the ship FET is fully turned on again. The

BATFET keeps the status unchanged during the system power reset. After the reset is done,

SDRV_CTRL[1:0] goes back to 00.

When the host changes SDRV_CTRL[1:0] from 00 to the other values, the charger turns off the ship FET

immediately or delays by t_{SM_DLY}as configured by SDRV_DLY bit. The application diagram when the battery is

connected to the charger through an external ship FET is illustrated in the figure below.

Q4

SYS

SYSTEM LOAD

SW2

Q3

BTST2

STAT

BATFET

REGN

BAT

Ship FET

SDRV

CE

100ꢀ

BQ25790

PG

BATP

TS

REGN

SDA

SCL

INT

Host

QON

IBAT

BATN

100ꢀ

Figure 28. The Application Diagram for the External Ship FET

8.3.11.1 Shutdown Mode

To further reduce battery leakage current, the host can shut down the charger by setting the register bits

SDRV_CTRL[1:0] to 01. In this mode, the I²C is disabled and the charger is totally shut down. The device can

only be woken up by plugging in an adapter.

After the SDRV_CTRL[1:0] is set to 01, the external ship FET turns off either immediately or after waiting for 10s

as configured by SDRV_DLY register bit. When VBUS is high because of an adapter being present or the OTG

mode being enable, SDRV_CTRL[1:0] will be reset to 00 if the host writes it to 01.

When the device exits shutdown mode, the SDRV_CTRL bits are reset to the POR default values (00).

8.3.11.2 Ship Mode

To extend battery life and minimize the system power loss when system is powered off during idle, shipping or

storage, the device can turn off BATFET and external ship FET to minimize the battery leakage current. The ship

mode is enabled when the host sets SDRV_CTRL[1:0] to 10. The I²C is still enabled, but the charger system

clock slows down to minimize the device quiescent current.

After the SDRV_CTRL[1:0] is set to 10, the external ship FET is turned off either immediately or after waiting 10

seconds as configured by SDRV_DLY register bit. When VBUS is high because of an adapter being present or

OTG mode being enabled, SDRV_CTRL[1:0] automatically resets to 00 if the host writes it to 10.

The ship mode is disabled by one of the following events. The charger turns on ship FET and internal BATFET to

reconnect the battery to the system, SDRV_CTRL bits are reset to the POR default values (00).

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•

Plug in an adapter

Set SDRV_CTRL[1:0] = 00

Set REG_RST = 1, to reset all the registers including SDRV_CTRL bits back to default (00)

A logic low of t_{SM_EXIT}(typical 1s or 15ms programmed by WKUP_DLY bit) duration on QON pin

8.3.11.3 System Power Reset

The host can reset the system power by:

•

Set the register bits SDRV_CTRL[1:0] to 11

A logic low of t_RST(typical 10s) duration on QON pin

When the system power reset is enabled, the device turns off the ship FET and also sets the charger in HIZ

mode if VBUS is high for t_{RST_SFET}(typical 350ms), then turns on the ship FET and also disable the charger HIZ

mode to provide full system power reset. When the SFET is off for t_{RST_SFET}, the charger applies a typical 30mA

sink current on SYS to discharge system voltage down.

No matter the charger is at battery only condition or in the forward charging mode with adapter present, the

charger resets the system power when the SDRV_CTRL[1:0] bits are set to 11 or the QON pin is pulled low for

t_RSTduration.

8.3.12 Protections

8.3.12.1 Voltage and Current Monitoring

The device closely monitors the input, system and battery voltage and current, as well as internal FET currents

for safe converter operation. The charger provides the faults protection list below:

•

VAC Over-voltage Protection (VAC_OVP)

VBUS Over-voltage Protection (VBUS_OVP)

VBUS Under-voltage Protection (POORSRC)

System Over-voltage Protection (VSYS_OVP)

System Short Protection (VSYS_SHORT)

Battery Over-voltage Protection (VBAT_OVP)

Battery Over-current Protection (IBAT_OCP)

Input Over-current Protection (IBUS_OCP)

OTG Over-voltage Protection (OTG_OVP)

OTG Under-voltage Protection (OTG_UVP)

8.3.12.2 Thermal Regulation and Thermal Shutdown

The device monitors its internal junction temperature (T_J) to avoid overheating and to limit the IC surface

temperature. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits), the

device reduces the charge current or OTG output current to maintain the junction temperature at the thermal

regulation limit. A wide thermal regulation range from 60°C to 120°C allows optimization of the system thermal

performance. During thermal regulation, the actual charging current is usually below the programmed value in

the ICHG registers. Therefore, termination is disabled, the fast charging safety timer runs at half the clock rate,

the status register TREG_STAT bit goes high, TREG_FLAG bit is set to 1, and an INT is asserted to alert host

unless TREG_MASK is set to 1.

Additionally, the device has thermal shutdown to turn off the converter when the IC junction temperature exceeds

the TSHUT threshold. The fault register bits TSHUT_STAT and TSHUT_FLAG are set and an INT pulse is

asserted to the host, unless TSHUT_MASK is set to 1. The BATFET and the converter resumes normal

operation when the IC die temperature decreases lower than TSHUT threshold by T_{SHUT_HYS}

.

8.3.13 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial

data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing

data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to

permit that transfer. At that time, any device addressed is considered a slave.

42

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The device operates as a slave device with address 0x6B, receiving control inputs from the master device like

micro-controller or digital signal processor through REG00 – REG25. Register read beyond REG25 (0x25),

returns 0xFF. The I²C interface supports both standard mode (up to 100 kbits/s), and fast mode (up to 400

kbits/s). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be

connected to the positive supply voltage via a current source or pull-up resistor.

8.3.13.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data

bit transferred.

SDA

SCL

Data line stable;

Data valid

Change of

data allowed

Figure 29. Bit Transfers on the I²C Bus

8.3.13.2 START and STOP Conditions

All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

Figure 30. START and STOP Conditions on the I²C Bus

START (S)

8.3.13.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most

Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has

performed some other function, it can hold the SCL line low to force the master into a wait state (clock

stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL

line.

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Acknowledgeme

nt signal from

receiver

Acknowledgement

signal from slave

MSB

1

SDA

2

7

8

9

1

2

8

9

SCL S or Sr

P or Sr

ACK

START or

Repeated

START

STOP or

Repeate

d START

Figure 31. Data Transfer on the I²C Bus

8.3.13.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte

was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9^thclock

pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this 9^thclock pulse.

A NACK is signaled when the SDA line remains HIGH during the 9^thclock pulse. The master can then generate

either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.13.5 Slave Address and Data Direction Bit

After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

The device 7-bit address is defined as 1101 011' (0x6B) by default. The address bit arrangement is shown

below.

Slave Address

1

0

1

0

1

R/W

Figure 32. 7-Bit Addressing (0x6B)

SDA

SCL

S

8

9

8

9

8

9

P

1-7

DATA

START

ADDRESS

R/W ACK

DATA

ACK

STOP

Figure 33. Complete Data Transfer on the I²C Bus

8.3.13.6 Single Write and Read

Figure 34. Single Write

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Figure 35. Single Read

If the register address is not defined, the charger IC sends back NACK and returns to the idle state.

8.3.13.7 Multi-Write and Multi-Read

The charger device supports multi-read and multi-write of all registers.

Figure 36. Multi-Write

Figure 37. Multi-Read

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default

mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the

charger is in default mode, WD_STAT bit becomes HIGH, WD_FLAG is set to 1, and an INT is asserted low to

alert the host (unless masked by WD_MASK). The WD_FLAG bit would read as 1 upon the first read and then 0

upon subsequent reads. When the charger is in host mode, WD_STAT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the

registers are in the default settings.

In default mode, the device keeps charging the battery with default 1-hour trickle charging safety timer, 2-hour

pre-charging safety timer and the 12-hour fast charging safety timer. At the end of the 1-hour or 2-hour or 12-

hour timer expired, the charging is stopped and the buck-boost converter continues to operate to supply system

load.

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Device Functional Modes (continued)

A write to any I²C register transitions the charger from default mode to host mode, and initiates the watchdog

timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has

to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set),

or disable watchdog timer by setting WATCHDOG bits = 00.

When the watchdog timer is expired, the device returns to default mode and all registers are reset to default

values except the ones described as detailed in the Register Map section. The Watchdog timer will be reset on

any write if the watchdog timer has expired. When watchdog timer expires, WD_STAT and WD_FLAG is set to 1,

and an INT is asserted low to alert the host (unless masked by WD_MASK).

Reset

Selective

Registers

Default Mode

WD_STAT=1

POR

I2C Write

Reset

Watchdog

Timer

Yes

Host Mode

WD_STAT=0

I2C Write to

WD_RST

No

Watchdog Timer Expired?

Yes

No

Figure 38. Watchdog Timer Flow Chart

8.4.2 Register Bit Reset

Beside the register reset by the watchdog timer in the default mode, the register and the timer could be reset to

the default value by writing the REG_RST bit to 1. The register bits, which can be reset by the REG_RST bit, are

noted in the Register Map section. After the register reset, the REG_RST bit will go back from 1 to 0

automatically.

The register reset by the REG_RST bit will not initiate the ACFET-RBFET detection, which is only done at the

charger first time POR. It will not repeat the open-circuit adapter measurements for the default VINDPM setting,

which in only done when an adapter is plugged in. In addition, if the charger is in the process of forced ICO, the

forced open-circuit adapter measurements or the forced D+/D- detection, set the REG_RST to 1 will terminate all

of these processes, because reset the register to default values will set FORCE_ICO, FORCE_INDET and

FORCE_VINDPM_DET bits to 0.

8.5 Register Map

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Register Map (continued)

8.5.1 I2C Registers

Table 8 lists the I2C registers. All register offset addresses not listed in Table 8 should be considered as

reserved locations and the register contents should not be modified.

Table 8. I2C Registers

Offset

Acronym

Register Name

Section

0h

REG00_Minimal_System_Voltage Minimal System Voltage

REG00_Minimal_System_Voltage

Register (Offset = 0h) [reset = X]

1h

3h

REG01_Charge_Voltage_Limit

REG03_Charge_Current_Limit

REG05_Input_Voltage_Limit

REG06_Input_Current_Limit

REG08_Precharge_Control

REG09_Termination_Control

REG0A_Re-charge_Control

REG0B_VOTG_regulation

REG0D_IOTG_regulation

REG0E_Timer_Control

Charge Voltage Limit

Charge Current Limit

Input Voltage Limit

Input Current Limit

Precharge Control

Termination Control

Re-charge Control

VOTG regulation

IOTG regulation

Timer Control

REG01_Charge_Voltage_Limit Register

(Offset = 1h) [reset = X]

REG03_Charge_Current_Limit Register

(Offset = 3h) [reset = X]

5h

REG05_Input_Voltage_Limit Register

(Offset = 5h) [reset = 24h]

6h

REG06_Input_Current_Limit Register

(Offset = 6h) [reset = 12Ch]

8h

REG08_Precharge_Control Register

(Offset = 8h) [reset = C3h]

9h

REG09_Termination_Control Register

(Offset = 9h) [reset = 5h]

Ah

REG0A_Re-charge_Control Register

(Offset = Ah) [reset = X]

Bh

REG0B_VOTG_regulation Register

(Offset = Bh) [reset = DCh]

Dh

REG0D_IOTG_regulation Register

(Offset = Dh) [reset = 4Bh]

Eh

REG0E_Timer_Control Register (Offset

= Eh) [reset = 3Dh]

Fh

REG0F_Charger_Control_0

REG10_Charger_Control_1

REG11_Charger_Control_2

REG12_Charger_Control_3

REG13_Charger_Control_4

REG14_Charger_Control_5

REG15_Reserved

Charger Control 0

Charger Control 1

Charger Control 2

Charger Control 3

Charger Control 4

Charger Control 5

Reserved

REG0F_Charger_Control_0 Register

(Offset = Fh) [reset = A2h]

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Bh

1Ch

1Dh

REG10_Charger_Control_1 Register

(Offset = 10h) [reset = 85h]

REG11_Charger_Control_2 Register

(Offset = 11h) [reset = 40h]

REG12_Charger_Control_3 Register

(Offset = 12h) [reset = 0h]

REG13_Charger_Control_4 Register

(Offset = 13h) [reset = X]

REG14_Charger_Control_5 Register

(Offset = 14h) [reset = 16h]

REG15_Reserved Register (Offset =

15h) [reset = 00h]

REG16_Temperature_Control

REG17_NTC_Control_0

Temperature Control

NTC Control 0

REG16_Temperature_Control Register

(Offset = 16h) [reset = C0h]

REG17_NTC_Control_0 Register (Offset

= 17h) [reset = 7Ah]

REG18_NTC_Control_1

NTC Control 1

REG18_NTC_Control_1 Register (Offset

= 18h) [reset = 54h]

REG19_ICO_Current_Limit

REG1B_Charger_Status_0

REG1C_Charger_Status_1

REG1D_Charger_Status_2

ICO Current Limit

Charger Status 0

Charger Status 1

Charger Status 2

REG19_ICO_Current_Limit Register

(Offset = 19h) [reset = 0h]

REG1B_Charger_Status_0 Register

(Offset = 1Bh) [reset = 0h]

REG1C_Charger_Status_1 Register

(Offset = 1Ch) [reset = 0h]

REG1D_Charger_Status_2 Register

(Offset = 1Dh) [reset = 0h]

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Table 8. I2C Registers (continued)

Offset

Acronym

Register Name

Section

1Eh

REG1E_Charger_Status_3

REG1F_Charger_Status_4

REG20_FAULT_Status_0

REG21_FAULT_Status_1

REG22_Charger_Flag_0

REG23_Charger_Flag_1

REG24_Charger_Flag_2

REG25_Charger_Flag_3

REG26_FAULT_Flag_0

REG27_FAULT_Flag_1

REG28_Charger_Mask_0

REG29_Charger_Mask_1

REG2A_Charger_Mask_2

REG2B_Charger_Mask_3

REG2C_FAULT_Mask_0

REG2D_FAULT_Mask_1

REG2E_ADC_Control

Charger Status 3

REG1E_Charger_Status_3 Register

(Offset = 1Eh) [reset = 0h]

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

33h

35h

37h

39h

3Bh

3Dh

3Fh

41h

Charger Status 4

FAULT Status 0

FAULT Status 1

Charger Flag 0

Charger Flag 1

Charger Flag 2

Charger Flag 3

FAULT Flag 0

FAULT Flag 1

Charger Mask 0

Charger Mask 1

Charger Mask 2

Charger Mask 3

FAULT Mask 0

FAULT Mask 1

ADC Control

REG1F_Charger_Status_4 Register

(Offset = 1Fh) [reset = 0h]

REG20_FAULT_Status_0 Register

(Offset = 20h) [reset = 0h]

REG21_FAULT_Status_1 Register

(Offset = 21h) [reset = 0h]

REG22_Charger_Flag_0 Register

(Offset = 22h) [reset = 0h]

REG23_Charger_Flag_1 Register

(Offset = 23h) [reset = 0h]

REG24_Charger_Flag_2 Register

(Offset = 24h) [reset = 0h]

REG25_Charger_Flag_3 Register

(Offset = 25h) [reset = 0h]

REG26_FAULT_Flag_0 Register (Offset

= 26h) [reset = 0h]

REG27_FAULT_Flag_1 Register (Offset

= 27h) [reset = 0h]

REG28_Charger_Mask_0 Register

(Offset = 28h) [reset = 0h]

REG29_Charger_Mask_1 Register

(Offset = 29h) [reset = 0h]

REG2A_Charger_Mask_2 Register

(Offset = 2Ah) [reset = 0h]

REG2B_Charger_Mask_3 Register

(Offset = 2Bh) [reset = 0h]

REG2C_FAULT_Mask_0 Register

(Offset = 2Ch) [reset = 0h]

REG2D_FAULT_Mask_1 Register

(Offset = 2Dh) [reset = 0h]

REG2E_ADC_Control Register (Offset =

2Eh) [reset = 30h]

REG2F_ADC_Function_Disable_0 ADC Function Disable 0

REG30_ADC_Function_Disable_1 ADC Function Disable 1

REG2F_ADC_Function_Disable_0

Register (Offset = 2Fh) [reset = 0h]

REG30_ADC_Function_Disable_1

Register (Offset = 30h) [reset = 0h]

REG31_IBUS_ADC

REG33_IBAT_ADC

REG35_VBUS_ADC

REG37_VAC1_ADC

REG39_VAC2_ADC

REG3B_VBAT_ADC

REG3D_VSYS_ADC

REG3F_TS_ADC

IBUS ADC

IBAT ADC

VBUS ADC

VAC1 ADC

VAC2 ADC

VBAT ADC

VSYS ADC

TS ADC

REG31_IBUS_ADC Register (Offset =

31h) [reset = 0h]

REG33_IBAT_ADC Register (Offset =

33h) [reset = 0h]

REG35_VBUS_ADC Register (Offset =

35h) [reset = 0h]

REG37_VAC1_ADC Register (Offset =

37h) [reset = 0h]

REG39_VAC2_ADC Register (Offset =

39h) [reset = 0h]

REG3B_VBAT_ADC Register (Offset =

3Bh) [reset = 0h]

REG3D_VSYS_ADC Register (Offset =

3Dh) [reset = 0h]

REG3F_TS_ADC Register (Offset =

3Fh) [reset = 0h]

REG41_TDIE_ADC

TDIE_ADC

REG41_TDIE_ADC Register (Offset =

41h) [reset = 0h]

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Table 8. I2C Registers (continued)

Offset

Acronym

Register Name

Section

43h

REG43_D+_ADC

D+ ADC

REG43_D+_ADC Register (Offset =

43h) [reset = 0h]

45h

47h

48h

REG45_D-_ADC

D- ADC

REG45_D-_ADC Register (Offset = 45h)

[reset = 0h]

REG47_DPDM_Driver

REG48_Part_Information

DPDM Driver

Part Information

REG47_DPDM_Driver Register (Offset

= 47h) [reset = 0h]

REG48_Part_Information Register

(Offset = 48h) [reset = 0h]

Complex bit access types are encoded to fit into small table cells. Table 9 shows the codes that are used for

access types in this section.

Table 9. I2C Access Type Codes

Access Type Code

Read Type

Description

R

Read

Write Type

W

Write

Others

Range

The register bits are only valid in this

defined range.

Clamped Low

Clamped High

Any write on the register lower than the

minimal value of the valid range, will be

ignored by the charger

Any write on the register higher than the

maximum value of the valid range, will be

ignored by the charger

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8.5.1.1 REG00_Minimal_System_Voltage Register (Offset = 0h) [reset = X]

REG00_Minimal_System_Voltage is shown in Figure 39 and described in Table 10.

Return to the Summary Table.

Minimal System Voltage

Figure 39. REG00_Minimal_System_Voltage Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

VSYSMIN_5:0

R/W-X

Table 10. REG00_Minimal_System_Voltage Register Field Descriptions

Bit

7-6

5-0

Field

Type

R/W

Reset

0h

Notes

Description

RESERVED

VSYSMIN_5:0

RESERVED

X

Reset by:

Minimal System Voltage:

REG_RST

During POR, the device reads the resistance tie to

PROG pin, to identify the default battery cell count and

determine the default power on VSYSMIN list below:

1s: 3.5V

2s: 7V

3s: 9V

4s: 12V

Type : RW

Range : 2500mV-16000mV

Fixed Offset : 2500mV

Bit Step Size : 250mV

Clamped High

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8.5.1.2 REG01_Charge_Voltage_Limit Register (Offset = 1h) [reset = X]

REG01_Charge_Voltage_Limit is shown in Figure 40 and described in Table 11.

Return to the Summary Table.

Charge Voltage Limit

Figure 40. REG01_Charge_Voltage_Limit Register

15

7

14

6

13

12

11

10

9

8

0

RESERVED

R-0h

VREG_10:0

R/W-X

5

4

3

2

1

VREG_10:0

R/W-X

Table 11. REG01_Charge_Voltage_Limit Register Field Descriptions

Bit

Field

Type

R

Reset

0h

Notes

Description

15-11

10-0

RESERVED

VREG_10:0

RESERVED

R/W

X

Reset by:

Battery Voltage Limit:

REG_RST

During POR, the device reads the resistance tie to

PROG pin, to identify the default battery cell count and

determine the default power-on battery voltage

regulation limit:

1s: 4.2V

2s: 8.4V

3s: 12.6V

4s: 16.8V

Type : RW

Range : 3000mV-18800mV

Fixed Offset : 0mV

Bit Step Size : 10mV

Clamped Low

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8.5.1.3 REG03_Charge_Current_Limit Register (Offset = 3h) [reset = X]

REG03_Charge_Current_Limit is shown in Figure 41 and described in Table 12.

Return to the Summary Table.

Charge Current Limit

Figure 41. REG03_Charge_Current_Limit Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

R-0h

ICHG_8:0

R/W-X

5

4

3

2

0

ICHG_8:0

R/W-X

Table 12. REG03_Charge_Current_Limit Register Field Descriptions

Bit

Field

Type

R

Reset

0h

Notes

Description

15-9

8-0

RESERVED

ICHG_8:0

RESERVED

R/W

X

Reset by:

Charge Current Limit

WATCHDOG

REG_RST

During POR, the device reads the resistance tie to

PROG pin, to identify the default battery cell count and

determine the default power-on battery charging

current:

1s and 2s: 2A

3s and 4s: 1A

Type : RW

Range : 50mA-5000mA

Fixed Offset : 0mA

Bit Step Size : 10mA

Clamped Low

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8.5.1.4 REG05_Input_Voltage_Limit Register (Offset = 5h) [reset = 24h]

REG05_Input_Voltage_Limit is shown in Figure 42 and described in Table 13.

Return to the Summary Table.

Input Voltage Limit

Figure 42. REG05_Input_Voltage_Limit Register

7

6

5

4

3

2

1

0

VINDPM_7:0

R/W-24h

Table 13. REG05_Input_Voltage_Limit Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

VINDPM_7:0

R/W

24h

Absolute VINDPM Threshold

VINDPM register is reset to 3600mV upon adapter unplugged and it

is set to the value based on the VBUS measurement when the

adapter plugs in. It is not reset by the REG_RST and the

WATCHDOG

Type : RW

POR: 3600mV (24h)

Range : 3600mV-22000mV

Fixed Offset : 0mV

Bit Step Size : 100mV

Clamped Low

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8.5.1.5 REG06_Input_Current_Limit Register (Offset = 6h) [reset = 12Ch]

REG06_Input_Current_Limit is shown in Figure 43 and described in Table 14.

Return to the Summary Table.

Input Current Limit

Figure 43. REG06_Input_Current_Limit Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

R-0h

IINDPM_8:0

R/W-12Ch

5

4

3

2

0

IINDPM_8:0

R/W-12Ch

Table 14. REG06_Input_Current_Limit Register Field Descriptions

Bit

Field

Type

R

Reset

0h

Notes

Description

15-9

8-0

RESERVED

IINDPM_8:0

RESERVED

R/W

12Ch

Reset by:

REG_RST

Based on D+/D- detection results:

USB SDP = 500mA

USB CDP = 1.5A

USB DCP = 3.25A

Adjustable High Voltage DCP = 1.5A

Unknown Adapter = 3A

Non-Standard Adapter = 1A/2A/2.1A/2.4A

Type : RW

POR: 3000mA (12Ch)

Range : 100mA-3300mA

Fixed Offset : 0mA

Bit Step Size : 10mA

Clamped Low

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8.5.1.6 REG08_Precharge_Control Register (Offset = 8h) [reset = C3h]

REG08_Precharge_Control is shown in Figure 44 and described in Table 15.

Return to the Summary Table.

Precharge Control

Figure 44. REG08_Precharge_Control Register

7

6

5

4

3

2

1

0

VBAT_LOWV_1:0

R/W-3h

IPRECHG_5:0

R/W-3h

Table 15. REG08_Precharge_Control Register Field Descriptions

Bit

Field

VBAT_LOWV_1:0

Type

Reset

Notes

Description

7-6

R/W

3h

Reset by:

REG_RST

Battery voltage thresholds for the transition from

precharge to fast charge, which is defined as a ratio of

battery regulation limit (VREG)

Type : RW

POR: 11b

0h = 15%*VREG

1h = 62.2%*VREG

2h = 66.7%*VREG

3h = 71.4%*VREG

5-0

IPRECHG_5:0

R/W

3h

Reset by:

WATCHDOG

REG_RST

Precharge current limit

Type : RW

POR: 120mA (3h)

Range : 40mA-2000mA

Fixed Offset : 0mA

Bit Step Size : 40mA

Clamped Low

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8.5.1.7 REG09_Termination_Control Register (Offset = 9h) [reset = 5h]

REG09_Termination_Control is shown in Figure 45 and described in Table 16.

Return to the Summary Table.

Termination Control

Figure 45. REG09_Termination_Control Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

REG_RST

R/W-0h

RESERVED

R/W-0h

ITERM_4:0

R/W-5h

Table 16. REG09_Termination_Control Register Field Descriptions

Bit

7

Field

Type

R

Reset

0h

Notes

Description

RESERVED

REG_RST

RESERVED

6

R/W

0h

Reset registers to default values and reset timer

Type : RW

POR: 0b

0h = Not reset

1h = Reset

5

RESERVED

ITERM_4:0

R/W

0h

5h

RESERVED

4-0

Reset by:

WATCHDOG

REG_RST

Termination current

Type : RW

POR: 200mA (5h)

Range : 40mA-1000mA

Fixed Offset : 0mA

Bit Step Size : 40mA

Clamped Low

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8.5.1.8 REG0A_Re-charge_Control Register (Offset = Ah) [reset = X]

REG0A_Re-charge_Control is shown in Figure 46 and described in Table 17.

Return to the Summary Table.

Re-charge Control

Figure 46. REG0A_Re-charge_Control Register

7

6

5

4

3

2

1

0

CELL_1:0

R/W-X

TRECHG_1:0

R/W-2h

VRECHG_3:0

R/W-3h

Table 17. REG0A_Re-charge_Control Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-6

CELL_1:0

R/W

X

At POR, the charger reads the PROG pin resistance to

determine the battery cell count and update this CELL

bits accordingly.

Type : RW

0h = 1s

1h = 2s

2h = 3s

3h = 4s

5-4

TRECHG_1:0

R/W

2h

Reset by:

WATCHDOG

REG_RST

Battery recharge deglich time

Type : RW

POR: 10b

0h = 64ms

1h = 256ms

2h = 1024ms (default)

3h = 2048ms

3-0

VRECHG_3:0

R/W

3h

Reset by:

WATCHDOG

REG_RST

Battery Recharge Threshold Offset (Below VREG)

Type : RW

POR: 200mV (3h)

Range : 50mV-800mV

Fixed Offset : 50mV

Bit Step Size : 50mV

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8.5.1.9 REG0B_VOTG_regulation Register (Offset = Bh) [reset = DCh]

REG0B_VOTG_regulation is shown in Figure 47 and described in Table 18.

Return to the Summary Table.

VOTG regulation

Figure 47. REG0B_VOTG_regulation Register

15

7

14

6

13

12

11

10

9

8

0

RESERVED

R-0h

VOTG_10:0

R/W-DCh

5

4

3

2

1

VOTG_10:0

R/W-DCh

Table 18. REG0B_VOTG_regulation Register Field Descriptions

Bit

Field

Type

R

Reset

0h

Notes

Description

15-11

10-0

RESERVED

VOTG_10:0

RESERVED

R/W

DCh

Reset by:

WATCHDOG

REG_RST

OTG mode regulation voltage

Type : RW

POR: 5000mV (DCh)

Range : 2800mV-22000mV

Fixed Offset : 2800mV

Bit Step Size : 10mV

Clamped High

58

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8.5.1.10 REG0D_IOTG_regulation Register (Offset = Dh) [reset = 4Bh]

REG0D_IOTG_regulation is shown in Figure 48 and described in Table 19.

Return to the Summary Table.

IOTG regulation

Figure 48. REG0D_IOTG_regulation Register

7

6

5

4

3

2

1

0

PRECHG_TMR

R/W-0h

IOTG_6:0

R/W-4Bh

Table 19. REG0D_IOTG_regulation Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

PRECHG_TMR

R/W

0h

Reset by:

WATCHDOG

REG_RST

Pre-charge safety timer setting

Type : RW

POR: 0b

0h = 2 hrs (default)

1h = 0.5 hrs

6-0

IOTG_6:0

R/W

4Bh

Reset by:

WATCHDOG

REG_RST

OTG current limit

Type : RW

POR: 3000mA (4Bh)

Range : 120mA-3320mA

Fixed Offset : 0mA

Bit Step Size : 40mA

Clamped Low

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8.5.1.11 REG0E_Timer_Control Register (Offset = Eh) [reset = 3Dh]

REG0E_Timer_Control is shown in Figure 49 and described in Table 20.

Return to the Summary Table.

Timer Control

Figure 49. REG0E_Timer_Control Register

7

6

5

4

3

2

1

0

TOPOFF_TMR_1:0

EN_TRICHG_T EN_PRECHG_ EN_CHG_TMR

CHG_TMR_1:0

R/W-2h

TMR2X_EN

MR

TMR

R/W-0h

R/W-1h

Table 20. REG0E_Timer_Control Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-6

TOPOFF_TMR_1:0 R/W

0h

Reset by:

WATCHDOG

REG_RST

Top-off timer control

Type : RW

POR: 00b

0h = Disabled (default)

1h = 15 mins

2h = 30 mins

3h = 45 mins

5

4

EN_TRICHG_TMR

R/W

1h

2h

Reset by:

WATCHDOG

REG_RST

Enable trickle charge timer (fixed as 1hr)

Type : RW

POR: 1b

0h = Disabled

1h = Enabled (default)

EN_PRECHG_TMR R/W

Reset by:

WATCHDOG

REG_RST

Enable pre-charge timer

Type : RW

POR: 1b

0h = Disabled

1h = Enabled (default)

3

EN_CHG_TMR

CHG_TMR_1:0

R/W

Reset by:

WATCHDOG

REG_RST

Enable fast charge timer

Type : RW

POR: 1b

0h = Disabled

1h = Enabled (default)

2-1

Reset by:

WATCHDOG

REG_RST

Fast charge timer setting

Type : RW

POR: 10b

0h = 5 hrs

1h = 8 hrs

2h = 12 hrs (default)

3h = 24 hrs

0

TMR2X_EN

R/W

1h

Reset by:

WATCHDOG

REG_RST

TMR2X_EN

Type : RW

POR: 1b

0h = Trickle charge, pre-charge and fast charge timer

NOT slowed by 2X during input DPM or thermal

regulation.

1h = Trickle charge, pre-charge and fast charge timer

slowed by 2X during input DPM or thermal regulation

(default)

60

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8.5.1.12 REG0F_Charger_Control_0 Register (Offset = Fh) [reset = A2h]

REG0F_Charger_Control_0 is shown in Figure 50 and described in Table 21.

Return to the Summary Table.

Charger Control 0

Figure 50. REG0F_Charger_Control_0 Register

7

6

5

4

3

2

1

0

EN_AUTO_IBA FORCE_IBATD

EN_CHG

EN_ICO

FORCE_ICO

EN_HIZ

EN_TERM

RESERVED

TDIS

IS

R/W-1h

R/W-0h

R/W-1h

R/W-0h

R/W-1h

R-0h

Table 21. REG0F_Charger_Control_0 Register Field Descriptions

Bit

7

Field

Type

Reset

Notes

Description

EN_AUTO_IBATDIS R/W

1h

Reset by:

Enable the auto battery discharging during the battery

OVP fault

Type : RW

POR: 1b

REG_RST

0h = The charger will NOT apply a discharging current

on BAT during battery OVP

1h = The charger will apply a discharging current on

BAT during battery OVP

6

FORCE_IBATDIS

R/W

0h

Reset by:

Force a battery discharging current

REG_RST

Type : RW

POR: 0b

0h = IDLE (default)

1h = Force the charger to apply a discharging current

on BAT regardless the battery OVP status

5

4

3

EN_CHG

EN_ICO

R/W

1h

0h

Reset by:

WATCHDOG

REG_RST

Charger Enable Configuration

Type : RW

POR: 1b

0h = Charge Disable

1h = Charge Enable (default)

Reset by:

REG_RST

Input Current Optimizer (ICO) Enable

Type : RW

POR: 0b

0h = Disable ICO (default)

1h = Enable ICO

FORCE_ICO

Reset by:

WATCHDOG

REG_RST

Force start input current optimizer (ICO)

Note: This bit can only be set and returns 0 after ICO

starts. This bit only valid when EN_ICO = 1

Type : RW

POR: 0b

0h = Do NOT force ICO (Default)

1h = Force ICO start

2

1

EN_HIZ

R/W

0h

1h

Reset by:

REG_RST

Enable HIZ mode.

This bit will be also reset to 0, when the adapter is

plugged in at VBUS.

Type : RW

POR: 0b

0h = Disable (default)

1h = Enable

EN_TERM

Reset by:

WATCHDOG

REG_RST

Enable termination

Type : RW

POR: 1b

0h = Disable

1h = Enable (default)

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Table 21. REG0F_Charger_Control_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Notes

Description

0

RESERVED

R

0h

Reserved

62

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8.5.1.13 REG10_Charger_Control_1 Register (Offset = 10h) [reset = 85h]

REG10_Charger_Control_1 is shown in Figure 51 and described in Table 22.

Return to the Summary Table.

Charger Control 1

Figure 51. REG10_Charger_Control_1 Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

VAC_OVP_1:0

R/W-3h

WD_RST

R/W-0h

WATCHDOG_2:0

R/W-5h

Table 22. REG10_Charger_Control_1 Register Field Descriptions

Bit

7-6

5-4

Field

Type

R

Reset

0h

Notes

Description

RESERVED

Reserved

VAC_OVP_1:0

R/W

3h

Reset by:

REG_RST

VAC_OVP thresholds

Type : RW

POR: 11b

0h = 26V

1h = 22V

2h = 12V

3h = 7V (default)

3

WD_RST

R/W

0h

5h

Reset by:

WATCHDOG

REG_RST

I2C watch dog timer reset

Type : RW

POR: 0b

0h = Normal (default)

1h = Reset (this bit goes back to 0 after timer resets)

2-0

WATCHDOG_2:0

Reset by:

REG_RST

Watchdog timer settings

Type : RW

POR: 101b

0h = Disable

1h = 0.5s

2h = 1s

3h = 2s

4h = 20s

5h = 40s (default)

6h = 80s

7h = 160s

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8.5.1.14 REG11_Charger_Control_2 Register (Offset = 11h) [reset = 40h]

REG11_Charger_Control_2 is shown in Figure 52 and described in Table 23.

Return to the Summary Table.

Charger Control 2

Figure 52. REG11_Charger_Control_2 Register

7

6

5

4

3

2

1

0

FORCE_INDET AUTO_INDET_

EN

EN_12V

EN_9V

HVDCP_EN

SDRV_CTRL_1:0

SDRV_DLY

R/W-0h

R/W-1h

R/W-0h

Table 23. REG11_Charger_Control_2 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

6

FORCE_INDET

R/W

0h

Reset by:

WATCHDOG

REG_RST

Force D+/D- detection

Type : RW

POR: 0b

0h = Do NOT force D+/D- detection (default)

1h = Force D+/D- algorithm, when D+/D- detection is

done, this bit will be reset to 0

AUTO_INDET_EN

R/W

1h

Reset by:

Automatic D+/D- Detection Enable

WATCHDOG

REG_RST

Type : RW

POR: 1b

0h = Disable D+/D- detection when VBUS is plugged-

in

1h = Enable D+/D- detection when VBUS is plugged-in

(default)

5

4

EN_12V

R/W

0h

Reset by:

REG_RST

EN_12V HVDC

Type : RW

POR: 0b

0h = Disable 12V mode in HVDCP (default)

1h = Enable 12V mode in HVDCP

EN_9V

Reset by:

REG_RST

EN_9V HVDC

Type : RW

POR: 0b

0h = Disable 9V mode in HVDCP (default)

1h = Enable 9V mode in HVDCP

3

HVDCP_EN

SDRV_CTRL_1:0

Reset by:

REG_RST

High voltage DCP enable.

Type : RW

POR: 0b

0h = Disable HVDCP handshake (default)

1h = Enable HVDCP handshake

2-1

Reset by:

SFET control

REG_RST

The external ship FET control logic to force the device

enter different modes.

Type : RW

POR: 00b

0h = IDLE (default)

1h = Shutdown Mode

2h = Ship Mode

3h = System Power Reset

0

SDRV_DLY

R/W

0h

Reset by:

Delay time added to the taking action in bit [2:1] of the

SFET control

Type : RW

POR: 0b

REG_RST

0h = Add 10s delay time (default)

1h = Do NOT add 10s delay time

64

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8.5.1.15 REG12_Charger_Control_3 Register (Offset = 12h) [reset = 0h]

REG12_Charger_Control_3 is shown in Figure 53 and described in Table 24.

Return to the Summary Table.

Charger Control 3

Figure 53. REG12_Charger_Control_3 Register

7

6

5

4

3

2

1

0

DIS_ACDRV

EN_OTG

PFM_OTG_DIS PFM_FWD_DI

S

WKUP_DLY

DIS_LDO

DIS_OTG_OO DIS_FWD_OO

A

R/W-0h

Table 24. REG12_Charger_Control_3 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

DIS_ACDRV

R/W

0h

When this bit is set, the charger will force both

EN_ACDRV1=0 and EN_ACDRV2=0

Type : RW

POR: 0b

6

5

4

3

EN_OTG

R/W

0h

Reset by:

WATCHDOG

REG_RST

OTG mode control

Type : RW

POR: 0b

0h = OTG Disable (default)

1h = OTG Enable

PFM_OTG_DIS

PFM_FWD_DIS

WKUP_DLY

Reset by:

WATCHDOG

REG_RST

Disable PFM in OTG mode

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

Disable PFM in forward mode

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

When wake up the device from ship mode, how much

time (t_{SM_EXIT}) is required to pull low the QON pin.

REG_RST

Type : RW

POR: 0b

0h = 1s (Default)

1h = 15ms

2

1

0

DIS_LDO

R/W

0h

Reset by:

WATCHDOG

REG_RST

Disable BATFET LDO mode in pre-charge stage.

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

DIS_OTG_OOA

DIS_FWD_OOA

Reset by:

WATCHDOG

REG_RST

Disable OOA in OTG mode

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

Disable OOA in forward mode

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

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8.5.1.16 REG13_Charger_Control_4 Register (Offset = 13h) [reset = X]

REG13_Charger_Control_4 is shown in Figure 54 and described in Table 25.

Return to the Summary Table.

Charger Control 4

Figure 54. REG13_Charger_Control_4 Register

7

6

5

4

3

2

1

0

EN_ACDRV2

EN_ACDRV1

PWM_FREQ

DIS_STAT

DIS_VSYS_SH DIS_VOTG_UV FORCE_VINDP EN_IBUS_OCP

ORT

P

M_DET

R/W-0h

R/W-X

R/W-0h

R/W-1h

Table 25. REG13_Charger_Control_4 Register Field Descriptions

Bit

Field

EN_ACDRV2

Type

Reset

Notes

Description

7

R/W

0h

External ACFET2-RBFET2 gate driver control

At POR, if the charger detects that there is no

ACFET2-RBFET2 populated, this bit will be locked at

0

Type : RW

POR: 0b

0h = turn off (default)

1h = turn on

6

EN_ACDRV1

R/W

0h

External ACFET1-RBFET1 gate driver control

At POR, if the charger detects that there is no

ACFET1-RBFET1 populated, this bit will be locked at

0

Type : RW

POR: 0b

0h = turn off (default)

1h = turn on

5

4

3

2

PWM_FREQ

DIS_STAT

R/W

X

Switching frequency selection, this bit POR default

value is based on the PROG pin strapping.

Type : RW

0h = 1.5 MHz

1h = 750 kHz

0h

Reset by:

WATCHDOG

REG_RST

Disable the STAT pin output

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

DIS_VSYS_SHORT R/W

Reset by:

REG_RST

Disable forward mode VSYS short hiccup protection.

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

DIS_VOTG_UVP

R/W

Reset by:

Disable OTG mode VOTG UVP hiccup protection.

REG_RST

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

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Table 25. REG13_Charger_Control_4 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Notes

Description

1

FORCE_VINDPM_D R/W

ET

0h

Reset by:

REG_RST

Force VINDPM detection

Note: only when VBAT>VSYSMIN, this bit can be set

to 1. Once the VINDPM auto detection is done, this

bits returns to 0.

Type : RW

POR: 0b

0h = Do NOT force VINDPM detection (default)

1h = Force the converter stop switching, and ADC

measures the VBUS voltage without input current,

then the charger updates the VINDPM register

accordingly.

0

EN_IBUS_OCP

R/W

1h

Reset by:

Enable IBUS_OCP in forward mode

REG_RST

Type : RW

POR: 1b

0h = Disable

1h = Enable (default)

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8.5.1.17 REG14_Charger_Control_5 Register (Offset = 14h) [reset = 16h]

REG14_Charger_Control_5 is shown in Figure 55 and described in Table 26.

Return to the Summary Table.

Charger Control 5

Figure 55. REG14_Charger_Control_5 Register

7

6

5

4

3

2

1

0

SFET_PRESE

NT

RESERVED

EN_IBAT

IBAT_REG_1:0

R/W-2h

EN_IINDPM

EN_EXTILIM

EN_BATOC

R/W-0h

R-0h

R/W-0h

R/W-1h

R/W-0h

Table 26. REG14_Charger_Control_5 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

SFET_PRESENT

R/W

0h

The user has to set this bit based on whether a ship

FET is populated or not. The POR default value is 0,

which means the charger does not support all the

features associated with the ship FET. The register

bits list below all are locked at 0.

EN_BATOC=0

FORCE_SFET_OFF=0

SDRV_CTRL=00

When this bit is set to 1, the register bits list above

become programmable, and the charger can support

the features associated with the ship FET

Type : RW

POR: 0b

0h = No ship FET populated

1h = Ship FET populated

Reserved

6

5

RESERVED

EN_IBAT

R

0h

R/W

Reset by:

WATCHDOG

REG_RST

IBAT pin output enable

Type : RW

POR: 0b

0h = IBAT pin output is disabled (default)

1h = IBAT pin output is enable

4-3

IBAT_REG_1:0

R/W

2h

Reset by:

Battery discharging current regulation in OTG mode

WATCHDOG

REG_RST

Type : RW

POR: 10b

0h = 3A

1h = 4A

2h = 5A (default)

3h = Disable

2

1

EN_IINDPM

EN_EXTILIM

R/W

1h

Reset by:

WATCHDOG

REG_RST

Enable the internal IINDPM register input current

regulation

Type : RW

POR: 1b

0h = Disable

1h = Enable (default)

Reset by:

Enable the external ILIM_HIZ pin input current

regulation

Type : RW

POR: 1b

REG_RST

0h = Disable

1h = Enable (default)

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Table 26. REG14_Charger_Control_5 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Notes

Description

0

EN_BATOC

R/W

0h

Reset by:

Enable the battery discharging current OCP

WATCHDOG

REG_RST

Type : RW

POR: 0b

0h = Disable (default)

1h = Enable

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8.5.1.18 REG15_Reserved Register (Offset = 15h) [reset = 00h]

REG15_Reserved is shown in Figure 56 and described in Table 27.

Return to the Summary Table.

Reserved Register

Figure 56. REG15_Reserved Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

Table 27. REG15_Reserved Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-0

RESERVED

R

0h

Reserved

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8.5.1.19 REG16_Temperature_Control Register (Offset = 16h) [reset = C0h]

REG16_Temperature_Control is shown in Figure 57 and described in Table 28.

Return to the Summary Table.

Temperature Control

Figure 57. REG16_Temperature_Control Register

7

6

5

4

3

2

1

0

TREG_1:0

R/W-3h

TSHUT_1:0

R/W-0h

VBUS_PD_EN VAC1_PD_EN VAC2_PD_EN

R/W-0h R/W-0h R/W-0h

RESERVED

R-0h

Table 28. REG16_Temperature_Control Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-6

TREG_1:0

R/W

3h

Reset by:

WATCHDOG

REG_RST

Thermal regulation thresholds.

Type : RW

POR: 11b

0h = 60°C

1h = 80°C

2h = 100°C

3h = 120°C (default)

5-4

TSHUT_1:0

R/W

0h

Reset by:

WATCHDOG

REG_RST

Thermal shutdown thresholds.

Type : RW

POR: 00b

0h = 150°C (default)

1h = 130°C

2h = 120°C

3h = 85°C

3

2

1

0

VBUS_PD_EN

VAC1_PD_EN

VAC2_PD_EN

RESERVED

R/W

R

0h

Reset by:

REG_RST

Enable VBUS pull down resistor (6k Ohm)

Type : RW

POR: 0b

0h = Disable (default)

1h = Enable

Reset by:

REG_RST

Enable VAC1 pull down resistor

Type : RW

POR: 0b

0h = Disable (default)

1h = Enable

Reset by:

REG_RST

Enable VAC2 pull down resistor

Type : RW

POR: 0b

0h = Disable (default)

1h = Enable

Reserved

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8.5.1.20 REG17_NTC_Control_0 Register (Offset = 17h) [reset = 7Ah]

REG17_NTC_Control_0 is shown in Figure 58 and described in Table 29.

Return to the Summary Table.

NTC Control 0

Figure 58. REG17_NTC_Control_0 Register

7

6

5

4

3

2

1

0

JEITA_VSET_2:0

R/W-3h

JEITA_ISETH_1:0

R/W-3h

JEITA_ISETC_1:0

R/W-1h

RESERVED

R-0h

Table 29. REG17_NTC_Control_0 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-5

JEITA_VSET_2:0

R/W

3h

Reset by:

JEITA high temperature range (TWARN – THOT)

charge voltage setting

Type : RW

WATCHDOG

REG_RST

POR: 011b

0h = Charge Suspend

1h = Set VREG to VREG-800mV

2h = Set VREG to VREG-600mV

3h = Set VREG to VREG-400mV (default)

4h = Set VREG to VREG-300mV

5h = Set VREG to VREG-200mV

6h = Set VREG to VREG-100mV

7h = VREG unchanged

4-3

2-1

0

JEITA_ISETH_1:0

JEITA_ISETC_1:0

RESERVED

R/W

R

3h

1h

0h

Reset by:

WATCHDOG

REG_RST

JEITA high temperature range (TWARN – THOT)

charge current setting

Type : RW

POR: 11b

0h = Charge Suspend

1h = Set ICHG to 20%* ICHG

2h = Set ICHG to 40%* ICHG

3h = ICHG unchanged (default)

Reset by:

WATCHDOG

REG_RST

JEITA low temperature range (TCOLD – TCOOL)

charge current setting

Type : RW

POR: 01b

0h = Charge Suspend

1h = Set ICHG to 20%* ICHG (default)

2h = Set ICHG to 40%* ICHG

3h = ICHG unchanged

Reserved

72

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8.5.1.21 REG18_NTC_Control_1 Register (Offset = 18h) [reset = 54h]

REG18_NTC_Control_1 is shown in Figure 59 and described in Table 30.

Return to the Summary Table.

NTC Control 1

Figure 59. REG18_NTC_Control_1 Register

7

6

5

4

3

2

1

0

TS_COOL_1:0

R/W-1h

TS_WARM_1:0

R/W-1h

BHOT_1:0

R/W-1h

BCOLD

R/W-0h

TS_IGNORE

R/W-0h

Table 30. REG18_NTC_Control_1 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7-6

TS_COOL_1:0

TS_WARM_1:0

BHOT_1:0

R/W

1h

Reset by:

WATCHDOG

REG_RST

JEITA VT2 comparator voltage rising thresholds as a

percentage of REGN. The corresponding temperature

in the brackets is achieved when a 103AT NTC

thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

Type : RW

POR: 01b

0h = 71.1% (5°C)

1h = 68.4% (default) (10°C)

2h = 65.5% (15°C)

3h = 62.4% (20°C)

5-4

R/W

1h

Reset by:

WATCHDOG

REG_RST

JEITA VT3 comparator voltage falling thresholds as a

percentage of REGN. The corresponding temperature

in the brackets is achieved when a 103AT NTC

thermistor is used, RT1=5.24kΩ and RT2=30.31kΩ.

Type : RW

POR: 01b

0h = 48.4% (40°C)

1h = 44.8% (default) (45°C)

2h = 41.2% (50°C)

3h = 37.7% (55°C)

3-2

R/W

1h

Reset by:

OTG mode TS HOT temperature threshold

WATCHDOG

REG_RST

Type : RW

POR: 01b

0h = 55°C

1h = 60°C (default)

2h = 65°C

3h = Disable

1

0

BCOLD

R/W

0h

Reset by:

WATCHDOG

REG_RST

OTG mode TS COLD temperature threshold

Type : RW

POR: 0b

0h = -10°C (default)

1h = -20°C

TS_IGNORE

Reset by:

WATCHDOG

REG_RST

Ignore the TS feedback, the charger considers the TS

is always good to allow the charging and OTG modes,

all the four TS status bits always stay at 0000 to report

the normal condition.

Type : RW

POR: 0b

0h = NOT ignore (Default)

1h = Ignore

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8.5.1.22 REG19_ICO_Current_Limit Register (Offset = 19h) [reset = 0h]

REG19_ICO_Current_Limit is shown in Figure 60 and described in Table 31.

Return to the Summary Table.

ICO Current Limit

Figure 60. REG19_ICO_Current_Limit Register

15

7

14

6

13

12

11

10

9

1

8

RESERVED

R-0h

ICO_ILIM_8:0

R-0h

5

4

3

2

0

ICO_ILIM_8:0

R-0h

Table 31. REG19_ICO_Current_Limit Register Field Descriptions

Bit

Field

Type

Reset

Description

15-9

8-0

RESERVED

R

0h

RESERVED

ICO_ILIM_8:0

R

0h

Input Current Limit obtained from ICO or ILIM_HIZ pin setting

Type : R

POR: 0mA (0h)

Range : 100mA-3300mA

Fixed Offset : 0mA

Bit Step Size : 10mA

Clamped Low

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8.5.1.23 REG1B_Charger_Status_0 Register (Offset = 1Bh) [reset = 0h]

REG1B_Charger_Status_0 is shown in Figure 61 and described in Table 32.

Return to the Summary Table.

Charger Status 0

Figure 61. REG1B_Charger_Status_0 Register

7

6

5

4

3

2

1

0

IINDPM_STAT VINDPM_STAT

WD_STAT

POORSRC_ST

AT

PG_STAT

AC2_PRESEN AC1_PRESEN VBUS_PRESE

T_STAT

NT_STAT

R-0h R-0h

R-0h

Table 32. REG1B_Charger_Status_0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

IINDPM_STAT

R

0h

IINDPM status (forward mode) or IOTG status (OTG mode)

Type : R

POR: 0b

0h = Normal

1h = In IINDPM regulation or IOTG regulation

VINDPM_STAT

WD_STAT

R

0h

VINDPM status (forward mode) or VOTG status (OTG mode)

Type : R

POR: 0b

0h = Normal

1h = In VINDPM regulation or VOTG regualtion

I2C watch dog timer status

Type : R

POR: 0b

0h = Normal

1h = WD timer expired

POORSRC_STAT

Poor source detection status

Type : R

POR: 0b

0h = Normal

1h = Weak adaptor detected

PG_STAT

Power Good Status

Type : R

POR: 0b

0h = NOT in power good status

1h = Power good

AC2_PRESENT_STAT

AC1_PRESENT_STAT

VAC2 insert status

Type : R

POR: 0b

0h = VAC2 NOT present

1h = VAC2 present (above present threshold)

VAC1 insert status

Type : R

POR: 0b

0h = VAC1 NOT present

1h = VAC1 present (above present threshold)

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Table 32. REG1B_Charger_Status_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

VBUS_PRESENT_STAT

R

0h

VBUS present status

Type : R

POR: 0b

0h = VBUS NOT present

1h = VBUS present (above present threshold)

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8.5.1.24 REG1C_Charger_Status_1 Register (Offset = 1Ch) [reset = 0h]

REG1C_Charger_Status_1 is shown in Figure 62 and described in Table 33.

Return to the Summary Table.

Charger Status 1

Figure 62. REG1C_Charger_Status_1 Register

7

6

5

4

3

2

1

0

CHG_STAT_2:0

VBUS_STAT_3:0

BC1.2_DONE_

STAT

R-0h

Table 33. REG1C_Charger_Status_1 Register Field Descriptions

Bit

7-5

Field

Type

Reset

Description

CHG_STAT_2:0

R

0h

Charge Status bits

Type : R

POR: 000b

0h = Not Charging

1h = Trickle Charge

2h = Pre-charge

3h = Fast charge (CC mode)

4h = Taper Charge (CV mode)

5h = Reserved

6h = Top-off Timer Active Charging

7h = Charge Termination Done

4-1

VBUS_STAT_3:0

R

0h

VBUS status bits

0h: No Input or BHOT or BCOLD in OTG mode

1h: USB SDP (500mA)

2h: USB CDP (1.5A)

3h: USB DCP (3.25A)

4h: Adjustable High Voltage DCP (HVDCP) (1.5A)

5h: Unknown adaptor (3A)

6h: Non-Standard Adapter (1A/2A/2.1A/2.4A)

7h: In OTG mode

8h: Not qualified adaptor

9h: Reserved

Ah: Reserved

Bh: Device directly powered from VBUS

Ch: Reserved

Dh: Reserved

Eh: Reserved

Fh: Reserved

Type : R

POR: 0h

0

BC1.2_DONE_STAT

R

0h

BC1.2 status bit

Type : R

POR: 0b

0h = BC1.2 or non-standard detection NOT complete

1h = BC1.2 or non-standard detection complete

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8.5.1.25 REG1D_Charger_Status_2 Register (Offset = 1Dh) [reset = 0h]

REG1D_Charger_Status_2 is shown in Figure 63 and described in Table 34.

Return to the Summary Table.

Charger Status 2

Figure 63. REG1D_Charger_Status_2 Register

7

6

5

4

3

2

1

0

ICO_STAT_1:0

R-0h

RESERVED

TREG_STAT

DPDM_STAT

VBAT_PRESE

NT_STAT

R-0h

Table 34. REG1D_Charger_Status_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

ICO_STAT_1:0

R

0h

Input Current Optimizer (ICO) status

Type : R

POR: 00b

0h = ICO disabled

1h = ICO optimization in progress

2h = Maximum input current detected

3h = Reserved

5-3

2

RESERVED

TREG_STAT

R

0h

RESERVED

IC thermal regulation status

Type : R

POR: 0b

0h = Normal

1h = Device in thermal regulation

1

0

DPDM_STAT

R

0h

D+/D- detection status bits

Type : R

POR: 0b

0h = The D+/D- detection is NOT started yet, or the detection is

done

1h = The D+/D- detection is ongoing

VBAT_PRESENT_STAT

Battery present status (V_BAT> V_{BAT_UVLOZ}

)

Type : R

POR: 0b

0h = V_BATNOT present

1h = V_BATpresent

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8.5.1.26 REG1E_Charger_Status_3 Register (Offset = 1Eh) [reset = 0h]

REG1E_Charger_Status_3 is shown in Figure 64 and described in Table 35.

Return to the Summary Table.

Charger Status 3

Figure 64. REG1E_Charger_Status_3 Register

7

6

5

4

3

2

1

0

ACRB2_STAT ACRB1_STAT ADC_DONE_S

TAT

VSYS_STAT

CHG_TMR_ST TRICHG_TMR_ PRECHG_TMR

RESERVED

AT

STAT

_STAT

R-0h

Table 35. REG1E_Charger_Status_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

0

ACRB2_STAT

R

0h

The ACFET2-RBFET2 status

Type : R

POR: 0b

0h = ACFET2-RBFET2 is NOT placed

1h = ACFET2-RBFET2 is placed

ACRB1_STAT

R

0h

The ACFET1-RBFET1 status

Type : R

POR: 0b

0h = ACFET1-RBFET1 is NOT placed

1h = ACFET1-RBFET1 is placed

ADC_DONE_STAT

VSYS_STAT

ADC Conversion Status (in one-shot mode only)

Type : R

POR: 0b

0h = Conversion NOT complete

1h = Conversion complete

VSYS Regulation Status (forward mode)

Type : R

POR: 0b

0h = Not in VSYSMIN regulation (V_BAT> V_SYSMIN

)

1h = In VSYSMIN regulation (V_BAT< V_SYSMIN

)

CHG_TMR_STAT

TRICHG_TMR_STAT

PRECHG_TMR_STAT

RESERVED

Fast charge timer status

Type : R

POR: 0b

0h = Normal

1h = Safety timer expired

Trickle charge timer status

Type : R

POR: 0b

0h = Normal

1h = Safety timer expired

Pre-charge timer status

Type : R

POR: 0b

0h = Normal

1h = Safety timer expired

RESERVED

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8.5.1.27 REG1F_Charger_Status_4 Register (Offset = 1Fh) [reset = 0h]

REG1F_Charger_Status_4 is shown in Figure 65 and described in Table 36.

Return to the Summary Table.

Charger Status 4

Figure 65. REG1F_Charger_Status_4 Register

7

6

5

4

3

2

1

0

RESERVED

VBATOTG_LO TS_COLD_STA TS_COOL_ST TS_WARM_ST TS_HOT_STAT

W_STAT

T

AT

R-0h

Table 36. REG1F_Charger_Status_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

R

0h

RESERVED

VBATOTG_LOW_STAT

R

0h

The battery voltage is too low to enable OTG mode.

Type : R

POR: 0b

0h = The battery voltage is high enough to enable the OTG

operation

1h = The battery volage is too low to enable the OTG operation

3

2

1

0

TS_COLD_STAT

TS_COOL_STAT

TS_WARM_STAT

TS_HOT_STAT

R

0h

The TS temperature is in the cold range, lower than T1.

Type : R

POR: 0b

0h = TS status is NOT in cold range

1h = TS status is in cold range

The TS temperature is in the cool range, between T1 and T2.

Type : R

POR: 0b

0h = TS status is NOT in cool range

1h = TS status is in cool range

The TS temperature is in the warm range, between T3 and T5.

Type : R

POR: 0b

0h = TS status is NOT in warm range

1h = TS status is in warm range

The TS temperature is in the hot range, higher than T5.

Type : R

POR: 0b

0h = TS status is NOT in hot range

1h = TS status is in hot range

80

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8.5.1.28 REG20_FAULT_Status_0 Register (Offset = 20h) [reset = 0h]

REG20_FAULT_Status_0 is shown in Figure 66 and described in Table 37.

Return to the Summary Table.

FAULT Status 0

Figure 66. REG20_FAULT_Status_0 Register

7

6

5

4

3

2

1

0

IBAT_REG_ST VBUS_OVP_S VBAT_OVP_ST IBUS_OCP_ST IBAT_OCP_ST CONV_OCP_S VAC2_OVP_ST VAC1_OVP_ST

AT

TAT

AT

TAT

AT

R-0h

Table 37. REG20_FAULT_Status_0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

IBAT_REG_STAT

VBUS_OVP_STAT

VBAT_OVP_STAT

IBUS_OCP_STAT

IBAT_OCP_STAT

CONV_OCP_STAT

VAC2_OVP_STAT

R

0h

IBAT regulation status

Type : R

POR: 0b

0h = Normal

1h = Device in battery discharging current regulation

R

0h

VBUS over-voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in over voltage protection

VBAT over-voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in over voltage protection

IBUS over-current status

Type : R

POR: 0b

0h = Normal

1h = Device in over current protection

IBAT over-current status

Type : R

POR: 0b

0h = Normal

1h = Device in over current protection

Converter over current status

Type : R

POR: 0b

0h = Normal

1h = Converter in over current protection

VAC2 over-voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in over voltage protection

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Table 37. REG20_FAULT_Status_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

VAC1_OVP_STAT

R

0h

VAC1 over-voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in over voltage protection

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8.5.1.29 REG21_FAULT_Status_1 Register (Offset = 21h) [reset = 0h]

REG21_FAULT_Status_1 is shown in Figure 67 and described in Table 38.

Return to the Summary Table.

FAULT Status 1

Figure 67. REG21_FAULT_Status_1 Register

7

6

5

4

3

2

1

0

VSYS_SHORT VSYS_OVP_S OTG_OVP_ST OTG_UVP_ST

RESERVED

TSHUT_STAT

RESERVED

R-0h

_STAT

TAT

AT

R-0h

Table 38. REG21_FAULT_Status_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VSYS_SHORT_STAT

VSYS_OVP_STAT

OTG_OVP_STAT

OTG_UVP_STAT

R

0h

VSYS short circuit status

Type : R

POR: 0b

0h = Normal

1h = Device in SYS short circuit protection

6

5

4

R

0h

VSYS over-voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in SYS over-voltage protection

OTG over voltage status

Type : R

POR: 0b

0h = Normal

1h = Device in OTG over-voltage

OTG under voltage status.

Type : R

POR: 0b

0h = Normal

1h = Device in OTG under voltage

3

2

RESERVED

R

0h

RESERVED

TSHUT_STAT

IC temperature shutdown status

Type : R

POR: 0b

0h = Normal

1h = Device in thermal shutdown protection

1-0

RESERVED

R

0h

RESERVED

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8.5.1.30 REG22_Charger_Flag_0 Register (Offset = 22h) [reset = 0h]

REG22_Charger_Flag_0 is shown in Figure 68 and described in Table 39.

Return to the Summary Table.

Charger Flag 0

Figure 68. REG22_Charger_Flag_0 Register

7

6

5

4

3

2

1

0

IINDPM_FLAG VINDPM_FLAG

WD_FLAG

POORSRC_FL

AG

PG_FLAG

AC2_PRESEN AC1_PRESEN VBUS_PRESE

T_FLAG

NT_FLAG

R-0h R-0h

R-0h

Table 39. REG22_Charger_Flag_0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

IINDPM_FLAG

VINDPM_FLAG

WD_FLAG

R

0h

IINDPM / IOTG flag

Type : R

POR: 0b

0h = Normal

1h = IINDPM / IOTG signal rising edge detected

R

0h

VINDPM / VOTG Flag

Type : R

POR: 0b

0h = Normal

1h = VINDPM / VOTG regulation signal rising edge detected

I2C watchdog timer flag

Type : R

POR: 0b

0h = Normal

1h = WD timer signal rising edge detected

POORSRC_FLAG

Poor source detection flag

Type : R

POR: 0b

0h = Normal

1h = Poor source status rising edge detected

PG_FLAG

Power good flag

Type : R

POR: 0b

0h = Normal

1h = Any change in PG_STAT even (adapter good qualification

or adapter good going away)

2

1

AC2_PRESENT_FLAG

AC1_PRESENT_FLAG

R

0h

VAC2 present flag

Type : R

POR: 0b

0h = Normal

1h = VAC2 present status changed

VAC1 present flag

Type : R

POR: 0b

0h = Normal

1h = VAC1 present status changed

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Table 39. REG22_Charger_Flag_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

VBUS_PRESENT_FLAG

R

0h

VBUS present flag

Type : R

POR: 0b

0h = Normal

1h = VBUS present status changed

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8.5.1.31 REG23_Charger_Flag_1 Register (Offset = 23h) [reset = 0h]

REG23_Charger_Flag_1 is shown in Figure 69 and described in Table 40.

Return to the Summary Table.

Charger Flag 1

Figure 69. REG23_Charger_Flag_1 Register

7

6

5

4

3

2

1

0

CHG_FLAG

ICO_FLAG

RESERVED

VBUS_FLAG

RESERVED

TREG_FLAG

VBAT_PRESE BC1.2_DONE_

NT_FLAG

FLAG

R-0h

Table 40. REG23_Charger_Flag_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

CHG_FLAG

R

0h

Charge status flag

Type : R

POR: 0b

0h = Normal

1h = Charge status changed

6

ICO_FLAG

R

0h

ICO status flag

Type : R

POR: 0b

0h = Normal

1h = ICO status changed

5

4

RESERVED

VBUS_FLAG

R

0h

RESERVED

VBUS status flag

Type : R

POR: 0b

0h = Normal

1h = VBUS status changed

3

2

RESERVED

TREG_FLAG

R

0h

RESERVED

IC thermal regulation flag

Type : R

POR: 0b

0h = Normal

1h = TREG signal rising threshold detected

1

0

VBAT_PRESENT_FLAG

BC1.2_DONE_FLAG

R

0h

VBAT present flag

Type : R

POR: 0b

0h = Normal

1h = VBAT present status changed

BC1.2 status Flag

Type : R

POR: 0b

0h = Normal

1h = BC1.2 detection status changed

86

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8.5.1.32 REG24_Charger_Flag_2 Register (Offset = 24h) [reset = 0h]

REG24_Charger_Flag_2 is shown in Figure 70 and described in Table 41.

Return to the Summary Table.

Charger Flag 2

Figure 70. REG24_Charger_Flag_2 Register

7

6

5

4

3

2

1

0

RESERVED

DPDM_DONE_ ADC_DONE_F

VSYS_FLAG

CHG_TMR_FL TRICHG_TMR_ PRECHG_TMR TOPOFF_TMR

FLAG

LAG

AG

FLAG

_FLAG

R-0h

Table 41. REG24_Charger_Flag_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R

0h

RESERVED

6

5

4

3

2

1

0

DPDM_DONE_FLAG

R

0h

D+/D- detection is done flag.

Type : R

POR: 0b

0h = D+/D- detection is NOT started or still ongoing

1h = D+/D- detection is completed

ADC_DONE_FLAG

VSYS_FLAG

ADC conversion flag (only in one-shot mode)

Type : R

POR: 0b

0h = Conversion NOT completed

1h = Conversion completed

VSYSMIN regulation flag

Type : R

POR: 0b

0h = Normal

1h = Entered or existed VSYSMIN regulation

CHG_TMR_FLAG

TRICHG_TMR_FLAG

PRECHG_TMR_FLAG

TOPOFF_TMR_FLAG

Fast charge timer flag

Type : R

POR: 0b

0h = Normal

1h = Fast charge timer expired rising edge detected

Trickle charge timer flag

Type : R

POR: 0b

0h = Normal

1h = Trickle charger timer expired rising edge detected

Pre-charge timer flag

Type : R

POR: 0b

0h = Normal

1h = Pre-charge timer expired rising edge detected

Top off timer flag

Type : R

POR: 0b

0h = Normal

1h = Top off timer expired rising edge detected

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8.5.1.33 REG25_Charger_Flag_3 Register (Offset = 25h) [reset = 0h]

REG25_Charger_Flag_3 is shown in Figure 71 and described in Table 42.

Return to the Summary Table.

Charger Flag 3

Figure 71. REG25_Charger_Flag_3 Register

7

6

5

4

3

2

1

0

RESERVED

VBATOTG_LO TS_COLD_FLA TS_COOL_FLA TS_WARM_FL TS_HOT_FLAG

W_FLAG

G

AG

R-0h

Table 42. REG25_Charger_Flag_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

R

0h

RESERVED

VBATOTG_LOW_FLAG

TS_COLD_FLAG

TS_COOL_FLAG

TS_WARM_FLAG

TS_HOT_FLAG

R

0h

VBAT too low to enable OTG flag

Type : R

POR: 0b

0h = Normal

1h = VBAT falls below the threshold to enable the OTG mode

3

2

1

0

TS cold temperature flag

Type : R

POR: 0b

0h = Normal

1h = TS across cold temperature (T1) is detected

TS cool temperature flag

Type : R

POR: 0b

0h = Normal

1h = TS across cool temperature (T2) is detected

TS warm temperature flag

Type : R

POR: 0b

0h = Normal

1h = TS across warm temperature (T3) is detected

TS hot temperature flag

Type : R

POR: 0b

0h = Normal

1h = TS across hot temperature (T5) is detected

88

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8.5.1.34 REG26_FAULT_Flag_0 Register (Offset = 26h) [reset = 0h]

REG26_FAULT_Flag_0 is shown in Figure 72 and described in Table 43.

Return to the Summary Table.

FAULT Flag 0

Figure 72. REG26_FAULT_Flag_0 Register

7

6

5

4

3

2

1

0

IBAT_REG_FL VBUS_OVP_FL VBAT_OVP_FL IBUS_OCP_FL IBAT_OCP_FL CONV_OCP_F VAC2_OVP_FL VAC1_OVP_FL

AG

LAG

AG

R-0h

Table 43. REG26_FAULT_Flag_0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

2

1

IBAT_REG_FLAG

VBUS_OVP_FLAG

VBAT_OVP_FLAG

IBUS_OCP_FLAG

IBAT_OCP_FLAG

CONV_OCP_FLAG

VAC2_OVP_FLAG

R

0h

IBAT regulation flag

Type : R

POR: 0b

0h = Normal

1h = Enter or exit IBAT regulation

R

0h

VBUS over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Enter VBUS OVP

VBAT over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Enter VBAT OVP

IBUS over-current flag

Type : R

POR: 0b

0h = Normal

1h = Enter IBUS OCP

IBAT over-current flag

Type : R

POR: 0b

0h = Normal

1h = Enter discharged OCP

Converter over-current flag

Type : R

POR: 0b

0h = Normal

1h = Enter converter OCP

VAC2 over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Enter VAC2 OVP

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Table 43. REG26_FAULT_Flag_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

VAC1_OVP_FLAG

R

0h

VAC1 over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Enter VAC1 OVP

90

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8.5.1.35 REG27_FAULT_Flag_1 Register (Offset = 27h) [reset = 0h]

REG27_FAULT_Flag_1 is shown in Figure 73 and described in Table 44.

Return to the Summary Table.

FAULT Flag 1

Figure 73. REG27_FAULT_Flag_1 Register

7

6

5

4

3

2

1

0

VSYS_SHORT VSYS_OVP_FL OTG_OVP_FL OTG_UVP_FL

RESERVED

TSHUT_FLAG

RESERVED

R-0h

_FLAG

AG

R-0h

Table 44. REG27_FAULT_Flag_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

VSYS_SHORT_FLAG

VSYS_OVP_FLAG

OTG_OVP_FLAG

OTG_UVP_FLAG

R

0h

VSYS short circuit flag

Type : R

POR: 0b

0h = Normal

1h = Stop switching due to system short

6

5

4

R

0h

VSYS over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Stop switching due to system over-voltage

OTG over-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Stop OTG due to VBUS over voltage

OTG under-voltage flag

Type : R

POR: 0b

0h = Normal

1h = Stop OTG due to VBUS under-voltage

3

2

RESERVED

R

0h

RESERVED

TSHUT_FLAG

IC thermal shutdown flag

Type : R

POR: 0b

0h = Normal

1h = TS shutdown signal rising threshold detected

1-0

RESERVED

R

0h

RESERVED

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8.5.1.36 REG28_Charger_Mask_0 Register (Offset = 28h) [reset = 0h]

REG28_Charger_Mask_0 is shown in Figure 74 and described in Table 45.

Return to the Summary Table.

Charger Mask 0

Figure 74. REG28_Charger_Mask_0 Register

7

6

5

4

3

2

1

0

IINDPM_MASK VINDPM_MAS

K

WD_MASK

POORSRC_MA

SK

PG_MASK

AC2_PRESEN AC1_PRESEN VBUS_PRESE

T_MASK

NT_MASK

R/W-0h

Table 45. REG28_Charger_Mask_0 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

6

5

IINDPM_MASK

VINDPM_MASK

WD_MASK

R/W

0h

Reset by:

REG_RST

IINDPM / IOTG mask flag

Type : RW

POR: 0b

0h = Enter IINDPM / IOTG does produce INT pulse

1h = Enter IINDPM / IOTG does NOT produce INT

pulse

R/W

0h

Reset by:

REG_RST

VINDPM / VOTG mask flag

Type : RW

POR: 0b

0h = Enter VINDPM / VOTG does produce INT pulse

1h = Enter VINDPM / VOTG does NOT produce INT

pulse

Reset by:

REG_RST

I2C watch dog timer mask flag

Type : RW

POR: 0b

0h = I2C watch dog timer expired does produce INT

pulse

1h = I2C watch dog timer expired does NOT produce

INT pulse

4

3

2

POORSRC_MASK

PG_MASK

R/W

0h

Reset by:

REG_RST

Poor source detection mask flag

Type : RW

POR: 0b

0h = Poor source detected does produce INT

1h = Poor source detected does NOT produce INT

Reset by:

REG_RST

Power Good mask flag

Type : RW

POR: 0b

0h = PG toggle does produce INT

1h = PG toggle does NOT produce INT

AC2_PRESENT_MA R/W

SK

Reset by:

REG_RST

VAC2 present mask flag

Type : RW

POR: 0b

0h = VAC2 present status change does produce INT

1h = VAC2 present status change does NOT produce

INT

1

AC1_PRESENT_MA R/W

SK

0h

Reset by:

REG_RST

VAC1 present mask flag

Type : RW

POR: 0b

0h = VAC1 present status change does produce INT

1h = VAC1 present status change does NOT produce

INT

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Table 45. REG28_Charger_Mask_0 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Notes

Description

0

VBUS_PRESENT_

MASK

R/W

0h

Reset by:

REG_RST

VBUS present mask flag

Type : RW

POR: 0b

0h = VBUS present status change does produce INT

1h = VBUS present status change does NOT produce

INT

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8.5.1.37 REG29_Charger_Mask_1 Register (Offset = 29h) [reset = 0h]

REG29_Charger_Mask_1 is shown in Figure 75 and described in Table 46.

Return to the Summary Table.

Charger Mask 1

Figure 75. REG29_Charger_Mask_1 Register

7

6

5

4

3

2

1

0

CHG_MASK

ICO_MASK

RESERVED

VBUS_MASK

RESERVED

TREG_MASK

VBAT_PRESE BC1.2_DONE_

NT_MASK

MASK

R/W-0h

R-0h

R/W-0h

R-0h

R/W-0h

Table 46. REG29_Charger_Mask_1 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

CHG_MASK

ICO_MASK

R/W

0h

Reset by:

REG_RST

Charge status mask flag

Type : RW

POR: 0b

0h = Charging status change does produce INT

1h = Charging status change does NOT produce INT

6

R/W

0h

Reset by:

REG_RST

ICO status mask flag

Type : RW

POR: 0b

0h = ICO status change does produce INT

1h = ICO status change does NOT produce INT

RESERVED

5

4

RESERVED

R

0h

VBUS_MASK

R/W

Reset by:

REG_RST

VBUS status mask flag

Type : RW

POR: 0b

0h = VBUS status change does produce INT

1h = VBUS status change does NOT produce INT

RESERVED

3

2

RESERVED

R

0h

TREG_MASK

R/W

Reset by:

REG_RST

IC thermal regulation mask flag

Type : RW

POR: 0b

0h = entering TREG does produce INT

1h = entering TREG does NOT produce INT

1

0

VBAT_PRESENT_M R/W

ASK

0h

Reset by:

REG_RST

VBAT present mask flag

Type : RW

POR: 0b

0h = VBAT present status change does produce INT

1h = VBAT present status change does NOT produce

INT

BC1.2_DONE_MAS R/W

K

Reset by:

REG_RST

BC1.2 status mask flag

Type : RW

POR: 0b

0h = BC1.2 status change does produce INT

1h = BC1.2 status change does NOT produce INT

94

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8.5.1.38 REG2A_Charger_Mask_2 Register (Offset = 2Ah) [reset = 0h]

REG2A_Charger_Mask_2 is shown in Figure 76 and described in Table 47.

Return to the Summary Table.

Charger Mask 2

Figure 76. REG2A_Charger_Mask_2 Register

7

6

5

4

3

2

1

0

RESERVED

DPDM_DONE_ ADC_DONE_M VSYS_MASK CHG_TMR_MA TRICHG_TMR_ PRECHG_TMR TOPOFF_TMR

MASK

ASK

SK

MASK

_MASK

R-0h

R/W-0h

Table 47. REG2A_Charger_Mask_2 Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

0h

Notes

Description

R

RESERVED

6

DPDM_DONE_MAS R/W

K

0h

Reset by:

REG_RST

D+/D- detection is done mask flag

Type : RW

POR: 0b

0h = D+/D- detection done does produce INT pulse

1h = D+/D- detection done does NOT produce INT

pulse

5

4

ADC_DONE_MASK R/W

0h

Reset by:

REG_RST

ADC conversion mask flag (only in one-shot mode)

Type : RW

POR: 0b

0h = ADC conversion done does produce INT pulse

1h = ADC conversion done does NOT produce INT

pulse

VSYS_MASK

R/W

Reset by:

REG_RST

VSYS min regulation mask flag

Type : RW

POR: 0b

0h = enter or exit VSYSMIN regulation does produce

INT pulse

1h = enter or exit VSYSMIN regulation does NOT

produce INT pulse

3

2

CHG_TMR_MASK

0h

Reset by:

REG_RST

Fast charge timer mask flag

Type : RW

POR: 0b

0h = Fast charge timer expire does produce INT

1h = Fast charge timer expire does NOT produce INT

TRICHG_TMR_MAS R/W

K

Reset by:

REG_RST

Trickle charge timer mask flag

Type : RW

POR: 0b

0h = Trickle charge timer expire does produce INT

1h = Trickle charge timer expire does NOT produce

INT

1

0

PRECHG_TMR_MA R/W

SK

0h

Reset by:

REG_RST

Pre-charge timer mask flag

Type : RW

POR: 0b

0h = Pre-charge timer expire does produce INT

1h = Pre-charge timer expire does NOT produce INT

TOPOFF_TMR_MA R/W

SK

Reset by:

REG_RST

Top off timer mask flag

Type : RW

POR: 0b

0h = Top off timer expire does produce INT

1h = Top off timer expire does NOT produce INT

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8.5.1.39 REG2B_Charger_Mask_3 Register (Offset = 2Bh) [reset = 0h]

REG2B_Charger_Mask_3 is shown in Figure 77 and described in Table 48.

Return to the Summary Table.

Charger Mask 3

Figure 77. REG2B_Charger_Mask_3 Register

7

6

5

4

3

2

1

0

RESERVED

VBATOTG_LO TS_COLD_MA TS_COOL_MA TS_WARM_MA TS_HOT_MAS

W_MASK

SK

K

R-0h

R/W-0h

Table 48. REG2B_Charger_Mask_3 Register Field Descriptions

Bit

7-5

4

Field

Type

Reset

0h

Notes

Description

RESERVED

R

RESERVED

VBATOTG_LOW_M R/W

ASK

0h

Reset by:

WATCHDOG

REG_RST

VBAT too low to enable OTG mask

Type : RW

POR: 0b

0h = VBAT falling below the threshold to enable the

OTG mode, does produce INT

1h = VBAT falling below the threshold to enable the

OTG mode, does NOT produce INT

3

2

1

0

TS_COLD_MASK

TS_COOL_MASK

TS_WARM_MASK

TS_HOT_MASK

R/W

0h

Reset by:

WATCHDOG

REG_RST

TS cold temperature interrupt mask

Type : RW

POR: 0b

0h = TS across cold temperature (T1) does produce

INT

1h = TS across cold temperature (T1) does NOT

produce INT

Reset by:

WATCHDOG

REG_RST

TS cool temperature interrupt mask

Type : RW

POR: 0b

0h = TS across cool temperature (T2) does produce

INT

1h = TS across cool temperature (T2) does NOT

produce INT

Reset by:

WATCHDOG

REG_RST

TS warm temperature interrupt mask

Type : RW

POR: 0b

0h = TS across warm temperature (T3) does produce

INT

1h = TS across warm temperature (T3) does NOT

produce INT

Reset by:

TS hot temperature interrupt mask

WATCHDOG

REG_RST

Type : RW

POR: 0b

0h = TS across hot temperature (T5) does produce

INT

1h = TS across hot temperature (T5) does NOT

produce INT

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8.5.1.40 REG2C_FAULT_Mask_0 Register (Offset = 2Ch) [reset = 0h]

REG2C_FAULT_Mask_0 is shown in Figure 78 and described in Table 49.

Return to the Summary Table.

FAULT Mask 0

Figure 78. REG2C_FAULT_Mask_0 Register

7

6

5

4

3

2

1

0

IBAT_REG_MA VBUS_OVP_M VBAT_OVP_M IBUS_OCP_MA IBAT_OCP_MA CONV_OCP_M VAC2_OVP_M VAC1_OVP_M

SK

ASK

SK

ASK

R/W-0h

Table 49. REG2C_FAULT_Mask_0 Register Field Descriptions

Bit

Field

IBAT_REG_MASK

Type

Reset

Notes

Description

7

R/W

0h

Reset by:

REG_RST

IBAT regulation mask flag

Type : RW

POR: 0b

0h = enter or exit IBAT regulation does produce INT

1h = enter or exit IBAT regulation does NOT produce

INT

6

5

4

3

2

1

0

VBUS_OVP_MASK R/W

VBAT_OVP_MASK R/W

0h

Reset by:

REG_RST

VBUS over-voltage mask flag

Type : RW

POR: 0b

0h = entering VBUS OVP does produce INT

1h = entering VBUS OVP does NOT produce INT

Reset by:

REG_RST

VBAT over-voltage mask flag

Type : RW

POR: 0b

0h = entering VBAT OVP does produce INT

1h = entering VBAT OVP does NOT produce INT

IBUS_OCP_MASK

IBAT_OCP_MASK

R/W

Reset by:

REG_RST

IBUS over-current mask flag

Type : RW

POR: 0b

0h = IBUS OCP fault does produce INT

1h = IBUS OCP fault does NOT produce INT

Reset by:

REG_RST

IBAT over-current mask flag

Type : RW

POR: 0b

0h = IBAT OCP fault does produce INT

1h = IBAT OCP fault does NOT produce INT

CONV_OCP_MASK R/W

VAC2_OVP_MASK R/W

VAC1_OVP_MASK R/W

Reset by:

REG_RST

Converter over-current mask flag

Type : RW

POR: 0b

0h = Converter OCP fault does produce INT

1h = Converter OCP fault does NOT produce INT

Reset by:

REG_RST

VAC2 over-voltage mask flag

Type : RW

POR: 0b

0h = entering VAC2 OVP does produce INT

1h = entering VAC2 OVP does NOT produce INT

Reset by:

REG_RST

VAC1 over-voltage mask flag

Type : RW

POR: 0b

0h = entering VAC1 OVP does produce INT

1h = entering VAC1 OVP does NOT produce INT

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8.5.1.41 REG2D_FAULT_Mask_1 Register (Offset = 2Dh) [reset = 0h]

REG2D_FAULT_Mask_1 is shown in Figure 79 and described in Table 50.

Return to the Summary Table.

FAULT Mask 1

Figure 79. REG2D_FAULT_Mask_1 Register

7

6

5

4

3

2

1

0

VSYS_SHORT VSYS_OVP_M OTG_OVP_MA OTG_UVP_MA

RESERVED

TSHUT_MASK

RESERVED

R-0h

_MASK

ASK

SK

R/W-0h

Table 50. REG2D_FAULT_Mask_1 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

6

5

VSYS_SHORT_MA R/W

SK

0h

Reset by:

REG_RST

VSYS short circuit mask flag

Type : RW

POR: 0b

0h = System short fault does produce INT

1h = System short fault does NOT produce INT

VSYS_OVP_MASK R/W

0h

Reset by:

REG_RST

VSYS over-voltage mask flag

Type : RW

POR: 0b

0h = System over-voltage fault does produce INT

1h = System over-voltage fault does NOT produce INT

OTG_OVP_MASK

OTG_UVP_MASK

R/W

Reset by:

REG_RST

OTG over-voltage mask flag

Type : RW

POR: 0b

0h = OTG VBUS over-voltage fault does produce INT

1h = OTG VBUS over-voltage fault does NOT produce

INT

4

0h

Reset by:

REG_RST

OTG under-voltage mask flag

Type : RW

POR: 0b

0h = OTG VBUS under voltage fault does produce INT

1h

= OTG VBUS under voltage fault does NOT

produce INT

3

2

RESERVED

R/W

0h

RESERVED

TSHUT_MASK

Reset by:

REG_RST

IC thermal shutdown mask flag

Type : RW

POR: 0b

0h = TSHUT does produce INT

1h = TSHUT does NOT produce INT

RESERVED

1-0

RESERVED

R

0h

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8.5.1.42 REG2E_ADC_Control Register (Offset = 2Eh) [reset = 30h]

REG2E_ADC_Control is shown in Figure 80 and described in Table 51.

Return to the Summary Table.

ADC Control

Figure 80. REG2E_ADC_Control Register

7

6

5

4

3

2

1

0

ADC_EN

ADC_RATE

ADC_SAMPLE_1:0

ADC_AVG

ADC_AVG_INI

T

RESERVED

R/W-0h

R/W-3h

R/W-0h

Table 51. REG2E_ADC_Control Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

ADC_EN

R/W

0h

Reset by:

WATCHDOG

REG_RST

ADC Control

Type : RW

POR: 0b

0h = Disable

1h = Enable

6

ADC_RATE

R/W

0h

3h

Reset by:

REG_RST

ADC conversion rate control

Type : RW

POR: 0b

0h = Continuous conversion

1h = One shot conversion

5-4

ADC_SAMPLE_1:0 R/W

Reset by:

REG_RST

ADC sample speed

Type : RW

POR: 11b

0h = 15 bit effective resolution

1h = 14 bit effective resolution

2h = 13 bit effective resolution

3h = 12 bit effective resolution

3

2

ADC_AVG

R/W

0h

Reset by:

REG_RST

ADC average control

Type : RW

POR: 0b

0h = Single value

1h = Running average

ADC_AVG_INIT

RESERVED

Reset by:

REG_RST

ADC average initial value control

Type : RW

POR: 0b

0h = Start average using the existing register value

1h = Start average using a new ADC conversion

RESERVED

1-0

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8.5.1.43 REG2F_ADC_Function_Disable_0 Register (Offset = 2Fh) [reset = 0h]

REG2F_ADC_Function_Disable_0 is shown in Figure 81 and described in Table 52.

Return to the Summary Table.

ADC Function Disable 0

Figure 81. REG2F_ADC_Function_Disable_0 Register

7

6

5

4

3

2

1

0

IBUS_ADC_DI IBAT_ADC_DIS VBUS_ADC_DI VBAT_ADC_DI VSYS_ADC_DI TS_ADC_DIS

TDIE_ADC_DI

S

RESERVED

S

R/W-0h

R-0h

Table 52. REG2F_ADC_Function_Disable_0 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

6

5

4

3

2

1

0

IBUS_ADC_DIS

IBAT_ADC_DIS

VBUS_ADC_DIS

VBAT_ADC_DIS

VSYS_ADC_DIS

TS_ADC_DIS

R/W

0h

Reset by:

REG_RST

IBUS ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

R/W

R

0h

Reset by:

REG_RST

IBAT ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

VBUS ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

VBAT ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

VSYS ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

TS ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

TDIE_ADC_DIS

RESERVED

Reset by:

REG_RST

TDIE ADC control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

RESERVED

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8.5.1.44 REG30_ADC_Function_Disable_1 Register (Offset = 30h) [reset = 0h]

REG30_ADC_Function_Disable_1 is shown in Figure 82 and described in Table 53.

Return to the Summary Table.

ADC Function Disable 1

Figure 82. REG30_ADC_Function_Disable_1 Register

7

6

5

4

3

2

1

0

DP_ADC_DIS

DM_ADC_DIS VAC2_ADC_DI VAC1_ADC_DI

RESERVED

R-0h

S

R/W-0h

Table 53. REG30_ADC_Function_Disable_1 Register Field Descriptions

Bit

Field

Type

Reset

Notes

Description

7

DP_ADC_DIS

DM_ADC_DIS

VAC2_ADC_DIS

VAC1_ADC_DIS

RESERVED

R/W

0h

Reset by:

REG_RST

D+ ADC Control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

6

5

R/W

R

0h

Reset by:

REG_RST

D- ADC Control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

Reset by:

REG_RST

VAC2 ADC Control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

4

Reset by:

REG_RST

VAC1 ADC Control

Type : RW

POR: 0b

0h = Enable (Default)

1h = Disable

3-0

RESERVED

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8.5.1.45 REG31_IBUS_ADC Register (Offset = 31h) [reset = 0h]

REG31_IBUS_ADC is shown in Figure 83 and described in Table 54.

Return to the Summary Table.

IBUS ADC

Figure 83. REG31_IBUS_ADC Register

15

7

14

6

13

12

IBUS_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

IBUS_ADC_15:0

R-0h

Table 54. REG31_IBUS_ADC Register Field Descriptions

Bit

15-0

Field

IBUS_ADC_15:0

Type

Reset

Description

R

0h

IBUS ADC reading

Reported in 2 's Complement.

When the current is flowing from VBUS to PMID, IBUS ADC reports

positive value, and when the current is flowing from PMID to VBUS,

IBUS ADC reports negative value.

Type : R

POR: 0mA (0h)

Range : 0mA-5000mA

Fixed Offset : 0mA

Bit Step Size : 1mA

102

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8.5.1.46 REG33_IBAT_ADC Register (Offset = 33h) [reset = 0h]

REG33_IBAT_ADC is shown in Figure 84 and described in Table 55.

Return to the Summary Table.

IBAT ADC

Figure 84. REG33_IBAT_ADC Register

15

7

14

6

13

12

IBAT_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

IBAT_ADC_15:0

R-0h

Table 55. REG33_IBAT_ADC Register Field Descriptions

Bit

15-0

Field

IBAT_ADC_15:0

Type

Reset

Description

R

0h

IBAT ADC reading

Reported in 2 's Complement.

The IBAT ADC reports positive value for the battery charging

current, and negative value for the battery discharging current.

Type : R

POR: 0mA (0h)

Range : 0mA-8000mA

Fixed Offset : 0mA

Bit Step Size : 1mA

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8.5.1.47 REG35_VBUS_ADC Register (Offset = 35h) [reset = 0h]

REG35_VBUS_ADC is shown in Figure 85 and described in Table 56.

Return to the Summary Table.

VBUS ADC

Figure 85. REG35_VBUS_ADC Register

15

7

14

6

13

12

VBUS_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

VBUS_ADC_15:0

R-0h

Table 56. REG35_VBUS_ADC Register Field Descriptions

Bit

15-0

Field

VBUS_ADC_15:0

Type

Reset

Description

R

0h

VBUS ADC reading

Reported in 2 's Complement.

Type : R

POR: 0mV (0h)

Range : 0mV-30000mV

Fixed Offset : 0mV

Bit Step Size : 1mV

104

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8.5.1.48 REG37_VAC1_ADC Register (Offset = 37h) [reset = 0h]

REG37_VAC1_ADC is shown in Figure 86 and described in Table 57.

Return to the Summary Table.

VAC1 ADC

Figure 86. REG37_VAC1_ADC Register

15

7

14

6

13

12

VAC1_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

VAC1_ADC_15:0

R-0h

Table 57. REG37_VAC1_ADC Register Field Descriptions

Bit

15-0

Field

VAC1_ADC_15:0

Type

Reset

Description

R

0h

VAC1 ADC reading

Reported in 2 's Complement.

Type : R

POR: 0mV (0h)

Range : 0mV-30000mV

Fixed Offset : 0mV

Bit Step Size : 1mV

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8.5.1.49 REG39_VAC2_ADC Register (Offset = 39h) [reset = 0h]

REG39_VAC2_ADC is shown in Figure 87 and described in Table 58.

Return to the Summary Table.

VAC2 ADC

Figure 87. REG39_VAC2_ADC Register

15

7

14

6

13

12

VAC2_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

VAC2_ADC_15:0

R-0h

Table 58. REG39_VAC2_ADC Register Field Descriptions

Bit

15-0

Field

VAC2_ADC_15:0

Type

Reset

Description

R

0h

VAC2 ADC reading

Reported in 2 's Complement.

Type : R

POR: 0mV (0h)

Range : 0mV-30000mV

Fixed Offset : 0mV

Bit Step Size : 1mV

106

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8.5.1.50 REG3B_VBAT_ADC Register (Offset = 3Bh) [reset = 0h]

REG3B_VBAT_ADC is shown in Figure 88 and described in Table 59.

Return to the Summary Table.

VBAT ADC

Figure 88. REG3B_VBAT_ADC Register

15

7

14

6

13

12

VBAT_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

VBAT_ADC_15:0

R-0h

Table 59. REG3B_VBAT_ADC Register Field Descriptions

Bit

15-0

Field

VBAT_ADC_15:0

Type

Reset

Description

R

0h

The battery differential sensing voltage (VBATP - VBATN) ADC

reading

Reported in 2 's Complement.

Type : R

POR: 0mV (0h)

Range : 0mV-20000mV

Fixed Offset : 0mV

Bit Step Size : 1mV

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8.5.1.51 REG3D_VSYS_ADC Register (Offset = 3Dh) [reset = 0h]

REG3D_VSYS_ADC is shown in Figure 89 and described in Table 60.

Return to the Summary Table.

VSYS ADC

Figure 89. REG3D_VSYS_ADC Register

15

7

14

6

13

12

VSYS_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

VSYS_ADC_15:0

R-0h

Table 60. REG3D_VSYS_ADC Register Field Descriptions

Bit

15-0

Field

VSYS_ADC_15:0

Type

Reset

Description

R

0h

VSYS ADC reading

Reported in 2 's Complement.

Type : R

POR: 0mV (0h)

Range : 0mV-24000mV

Fixed Offset : 0mV

Bit Step Size : 1mV

108

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8.5.1.52 REG3F_TS_ADC Register (Offset = 3Fh) [reset = 0h]

REG3F_TS_ADC is shown in Figure 90 and described in Table 61.

Return to the Summary Table.

TS ADC

Figure 90. REG3F_TS_ADC Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

TS_ADC_15:0

R-0h

4

3

TS_ADC_15:0

R-0h

Table 61. REG3F_TS_ADC Register Field Descriptions

Bit

15-0

Field

TS_ADC_15:0

Type

Reset

Description

R

0h

TS ADC reading

Type : R

POR: 0% (0h)

Range : 0%-99.9023%

Fixed Offset : 0%

Bit Step Size : 0.0976563%

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8.5.1.53 REG41_TDIE_ADC Register (Offset = 41h) [reset = 0h]

REG41_TDIE_ADC is shown in Figure 91 and described in Table 62.

Return to the Summary Table.

TDIE_ADC

Figure 91. REG41_TDIE_ADC Register

15

7

14

6

13

12

TDIE_ADC_15:0

R-0h

11

10

9

1

8

0

5

4

3

2

TDIE_ADC_15:0

R-0h

Table 62. REG41_TDIE_ADC Register Field Descriptions

Bit

15-0

Field

TDIE_ADC_15:0

Type

Reset

Description

R

0h

TDIE ADC reading

Reported in 2 's Complement.

Type : R

POR: 0°C (0h)

Range : -40°C-150°C

Fixed Offset : 0°C

Bit Step Size : 0.5°C

110

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8.5.1.54 REG43_D+_ADC Register (Offset = 43h) [reset = 0h]

REG43_D+_ADC is shown in Figure 92 and described in Table 63.

Return to the Summary Table.

D+ ADC

Figure 92. REG43_D+_ADC Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

D+_ADC_15:0

R-0h

4

3

D+_ADC_15:0

R-0h

Table 63. REG43_D+_ADC Register Field Descriptions

Bit

15-0

Field

D+_ADC_15:0

Type

Reset

Description

R

0h

D+ ADC reading

Type : R

POR: 0mV (0h)

Range : 0mV-3600mV

Fixed Offset : 0mV

Bit Step Size : 1mV

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8.5.1.55 REG45_D-_ADC Register (Offset = 45h) [reset = 0h]

REG45_D-_ADC is shown in Figure 93 and described in Table 64.

Return to the Summary Table.

D- ADC

Figure 93. REG45_D-_ADC Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

D-_ADC_15:0

R-0h

4

3

D-_ADC_15:0

R-0h

Table 64. REG45_D-_ADC Register Field Descriptions

Bit

15-0

Field

D-_ADC_15:0

Type

Reset

Description

R

0h

D- ADC reading

Type : R

POR: 0mV (0h)

Range : 0mV-3600mV

Fixed Offset : 0mV

Bit Step Size : 1mV

112

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8.5.1.56 REG47_DPDM_Driver Register (Offset = 47h) [reset = 0h]

REG47_DPDM_Driver is shown in Figure 94 and described in Table 65.

Return to the Summary Table.

DPDM Driver

Figure 94. REG47_DPDM_Driver Register

7

6

5

4

3

2

1

0

DPLUS_DAC_2:0

R/W-0h

DMINUS_DAC_2:0

R/W-0h

RESERVED

R/W-0h

Table 65. REG47_DPDM_Driver Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-2

1-0

DPLUS_DAC_2:0

R/W

0h

D+ Output Driver

Type : RW

POR: 000b

0h = HIZ

1h = 0

2h = 0.6V

3h = 1.2V

4h = 2.0V

5h = 2.7V

6h = 3.3V

7h = D+/D- Short

DMINUS_DAC_2:0

R/W

0h

D- Output Driver

Type : RW

POR: 000b

0h = HIZ

1h = 0

2h = 0.6V

3h = 1.2V

4h = 2.0V

5h = 2.7V

6h = 3.3V

7h = reserved

RESERVED

R/W

0h

RESERVED

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8.5.1.57 REG48_Part_Information Register (Offset = 48h) [reset = 0h]

REG48_Part_Information is shown in Figure 95 and described in Table 66.

Return to the Summary Table.

Part Information

Figure 95. REG48_Part_Information Register

7

6

5

4

3

2

1

0

RESERVED

R-0h

PN_2:0

R-0h

DEV_REV_2:0

R-0h

Table 66. REG48_Part_Information Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-3

RESERVED

PN_2:0

R

0h

RESERVED

R

0h

Device Part number

0h = BQ25790.

All the other options are reserved

Type : R

POR: 000b

2-0

DEV_REV_2:0

R

0h

Device Revision

Type : R

POR: 001b

114

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

A typical application consists of the device configured as an I²C controlled power path management device and a

multi-cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other

portable devices. It integrates all the four switching MOSFETs (Q₁to Q₄) for the buck-boost converter, and the

battery FET (BATFET) between system and battery. The device also integrates the input current sensing and

charging current sensing circuitries, the bootstrap diode for the high-side gate driving and the dual-input power

mux for the power sources selection.

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9.2 Typical Application

Optional

VIN2

2 × 10 µF

0.1 µF

ACDRV2

VAC2

PMID

VBUS

VIN1

1 × 0.1 µF and 3 × 10 µF

0.1 µF

ACDRV1

VAC1

REGN

6.04 kꢀ

PROG

ILIM_HIZ

GND

127 kꢀ

D+

D-

USB

100 kꢀ

BTST1

47 nF

Q1

SW1

REGN

1.0 µH

Q2

4.7 µF

SYSTEM

LOAD

Q4

SYS

2.5V to 19.4V

SW2

47 nF

1 × 0.1 µF and 5 × 10 µF

Q3

BTST2

STAT

BATFET

REGN

Optional

BAT

2.2 kꢀ

SDRV

CE

100ꢀ

2 × 10 µF

BQ25790

PG

BATP

TS

REGN

SDA

SCL

INT

5.24 kꢀ

10 kꢀ

Host

30.31 kꢀ

QON

IBAT

BATN

100ꢀ

Figure 96. BQ25790 Application Diagram with Two Input Sources and Ship FET

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Typical Application (continued)

ACDRV2

VAC2

2 × 10 µF

PMID

VBUS

VIN1

1 × 0.1 µF and 3 × 10 µF

0.1 µF

ACDRV1

VAC1

REGN

6.04 kꢀ

PROG

ILIM_HIZ

GND

127 kꢀ

100 kꢀ

D+

D-

USB

BTST1

47 nF

Q1

SW1

REGN

1.0 µH

4.7 µF

47 nF

Q2

SYSTEM

LOAD

Q4

SYS

2.5V to 19.4V

SW2

1 × 0.1 µF and 5 × 10 µF

Q3

BTST2

STAT

BATFET

REGN

BAT

SDRV

2.2 kꢀ

1 nF

CE

100ꢀ

2 × 10 µF

PG

BATP

TS

BQ25790

REGN

SDA

SCL

INT

5.24 kꢀ

Host

10 kꢀ

30.31 kꢀ

QON

IBAT

BATN

100ꢀ

Figure 97. BQ25790 Application Diagram with Single Input Source and No Ship FET

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Typical Application (continued)

9.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

Table 67. Design Parameters

PARAMETER

VALUE

5 V to 20 V

3.0 A

VBUS voltage range

Input current limit (IINDPM[8:0])

Fast charge current limit (ICHG[8:0])

Minimum system voltage (VSYS_MIN[5:0])

Battery regulation voltage (VREG[10:0])

3.0 A

7.0 V

8.4 V

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor (1µH) and capacitor values. It

also provide the 750kHz switching frequency to achieve higher efficiency for the applications which have enough

design space to accommodate the larger inductor (2.2 µH) and capacitors. Please note that the 1.5 MHz

switching frequency only works with the 1µH inductor and the 750 kHz switching frequency only works with the

2.2µH inductor.

Because the converter might be either operated in the buck mode or the boost mode, so the inductor current is

equal to either the charging current or the input current. The inductor saturation current should be higher than the

larger value of the input current (I_IN) or the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

(3)

The inductor ripple current (I_RIPPLE) depends on the input voltage (V_BUS), the output voltage (V_SYS), the switching

frequency (F_SW) and the inductance (L). The inductor current ripples for buck mode and boost mode are

calculated with equations (4) and (5), respectively:

(4)

(5)

The inductor current ripple in the buck mode is usually larger than that in the boost mode, since the voltage-

second applied on the inductor is larger. The maximum inductor current ripple in the buck mode happens in the

vicinity of D = V_SYS/ V_BUS= 0.5. The SYS voltage is approximately 8V for the 2s battery configuration, so the

worst case for the inductor ripples is with the 15V or 20V input voltage.

9.2.2.2 Input (VBUS / PMID) Capacitor

In the buck mode operation, the input current is discontinuous, which dominates the input RMS ripple current and

input voltage ripple. The input capacitors should have enough ripple current rating to absorb the input AC current

and have large enough capacitance to maintain the small input voltage ripple. For the buck mode operation, the

input RMS ripple current is calculated by the equation (6) and the input voltage ripple is calculated by the

equation (7), where D = V_SYS/ V_BUS

.

(6)

(7)

118

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The worst case input RMS ripple current and input voltage ripple both occur at 0.5 duty cycle condition. The SYS

voltage is approximately 8V for the 2s battery configuration, so the worst case is when 15V to 20V VBUS

condition. Low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and

should be placed close to the PMID and GND pins of the IC. The voltage rating of the capacitor must be higher

than the normal input voltage level. The capacitor with 25V or higher voltage rating is preferred for up to 20V

input voltage. 1*0.1 μF + 3*10 μF capacitors are suggested for up to 3.3-A input current limit.

9.2.2.3 Output (VSYS) Capacitor

In the boost mode operation, the output current is discontinuous, which dominates the output RMS ripple current

and output voltage ripple. The output capacitors should have enough ripple current rating to absorb the output

AC current and have large enough capacitance to maintain the small output voltage ripple. For the boost mode

operation, the output RMS ripple current is calculated by the equation (8) and the output voltage ripple is

calculated by the equation (9), where D = (1 - V_BUS/ V_SYS).

(8)

(9)

The worst case output RMS ripple current and output voltage ripple both occur at the lowest VBUS input voltage.

The SYS voltage is approximately 8V for the 2s battery configuration, so the worst case is 5V VBUS condition.

Low ESR ceramic capacitor such as X7R or X5R is preferred for the output decoupling capacitor and should be

placed close to the SYS and GND pins of the IC. The voltage rating of the capacitor must be higher than the

normal input voltage level. The capacitor with 16V or higher voltage rating is preferred for the 2s battery

configuration. 1*0.1 μF + 5*10 μF capacitors are suggested for up to 5A charging current.

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9.2.3 Application Curves

C_VBUS= 2*10µF, C_PMID= 3*10µF, C_SYS= 5*10µF, C_BAT= 2*10µF, L1 = 1µH (SPM6530T-1R0M120), Fsw = 1.5MHz.

VAC1 = VBUS = 5V

VBAT = 8V

VAC1 = VBUS = 5V

VBAT = 8V

Figure 98. ACFET1-RBFET1 Turns on at Power Up

Figure 99. Power Up from VAC1 with Charge Enabled

VBUS = 5V

VBAT = 8V

ICHG = 1A

VBUS = 5V

VBAT = 8V

ICHG = 1A

Figure 100. Charge Enable

Figure 101. Charge Disable

VBUS = 5V

VBAT = 8V

ICHG = 1A

VBUS = 8V

VBAT = 8V

ICHG = 1A

Figure 102. Boost Charging Mode PWM Operation

Figure 103. Buck-Boost Charging Mode PWM Operation

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C_VBUS= 2*10µF, C_PMID= 3*10µF, C_SYS= 5*10µF, C_BAT= 2*10µF, L1 = 1µH (SPM6530T-1R0M120), Fsw = 1.5MHz.

VBUS = 15V

VBAT = 8V

ICHG = 0A

VBUS = 15V

VBAT = 8V

ICHG = 1.5A

Figure 105. Buck Mode PFM with OOA

Figure 104. Buck Charging Mode PWM Operation

VBUS = 15V

VBAT = 8V

ICHG = 0A

VBAT = 8V

VOTG = 5V

IBUS = 0A

Figure 106. Buck Mode PFM without OOA

Figure 107. OTG Startup at No Load

VBUS = 15V

VBAT = 8V

Charge disabled

VBAT = 8V

VOTG = 5V

IBUS = 500mA

Figure 109. VSYS Load Transient Response

Figure 108. OTG Startup at 500-mA Load

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C_VBUS= 2*10µF, C_PMID= 3*10µF, C_SYS= 5*10µF, C_BAT= 2*10µF, L1 = 1µH (SPM6530T-1R0M120), Fsw = 1.5MHz.

VBAT = 8V

VOTG = 5V

VBUS = 5V

VBAT = 8V

Charge enabled

Figure 111. VOTG Load Transient Response

Figure 110. IINDPM Transient Response

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10 Power Supply Recommendations

In order to provide an output voltage on SYS, the device requires a power supply between 3.6 V and 24 V input

with recommended >500mA current rating connected to VBUS or a 1s to 4s Li-Ion battery with voltage higher

than V_{BAT_UVLO}connected to BAT. The source current rating needs to be at least 3A for the buck-boost converter

of the charger to provide maximum output power to SYS.

The charger does not support the testing condition when the battery connection is floating. The BAT pin has to

be connected to a real battery or some devices which can emulate the battery, like the battery emulator or bulk

capacitors. When the BAT pin is floating, please disable charge by setting EN_CHG to 0 or pulling low the EC

pin. Otherwise, the voltage overshoot at SYS might trigger the SYSOVP protection periodically.

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11 Layout

11.1 Layout Guidelines

The switching nodes rising and falling times should be minimized for minimum switching loss. Proper layout of

the components to minimize the high frequency current path loops (shown in the figure below) is important to

prevent the electrical and magnetic field radiation and the high frequency resonant problems. Here is a PCB

layout priority list for proper layout. Layout PCB according to this specific order is essential.

1. Place the SYS output capacitors as close to SYS and GND bumps as possible. Place a 0.1 µF small size

(such as 0402 or 0201) capacitor closer than the other 10 µF capacitors. Ground connections need to be tied

to the IC ground with a short copper trace connection or GND plane.

2. Place the PMID input capacitors as close to PMID and GND bumps as possible. Place a 0.1 µF small size

(such as 0402 or 0201) capacitor closer than the other 10 µF capacitors. Ground connections need to be tied

to the IC ground with a short copper trace connection or GND plane.

3. The connection from SYS/PMID to the 0.1 µF has to be routed on the top layer of the PCB, the returning

back to GND also has to be in the top layer. Keep the whole routing loop as small as possible.

4. Place the inductor input terminal to SW1 bumps and the inductor output terminal to SW2 bumps as close as

possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the

trace wide enough to carry the inductor current. Minimize parasitic capacitance from this area to any other

trace or plane.

5. Place the BAT capacitors close to BAT and GND bumps, place the VBUS capacitors close to VBUS and

GND bumps

6. The REGN decoupling capacitor and the bootstrap capacitors should be placed next to the IC and make

trace connection as short as possible.

7. Ensure that there are sufficient thermal vias directly under bumps of the power MOSFETs, connecting to

copper on other layers.

8. Via size and number should be enough for a given current path.

9. Route BATP and BATN away from switching nodes such as SW1 and SW2.

Refer to the EVM design and more information in the BQ25790EVM (BMS027) Evaluation Module User's

Guide for the recommended component placement with trace and via locations.

+

œ

Figure 112. Buck-Boost Converter High Frequency Current Path

124

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

12.1.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•

BQ25790EVM (BMS027) Evaluation Module User's Guide

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

126

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PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jun-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25790YBGR

DSBGA

YBG

56

3000

330.0

12.4

3.08

3.5

0.7

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jun-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YBG 56

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

BQ25790YBGR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

YBG0056-C01

DSBGA - 0.5 mm max height

SCALE 4.000

DIE SIZE BALL GRID ARRAY

2.917

2.877

A

B

BALL A1

CORNER

3.337

3.297

C

0.5 MAX

SEATING PLANE

0.05 C

0.20

0.14

BALL TYP

2.4 TYP

SYMM

H

G

F

E

D

C

2.8

TYP

SYMM

B

A

0.4 TYP

0.27

1

3

4

5

6

7

2

56X

0.23

0.015

C A B

0.4 TYP

4226147/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YBG0056-C01

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

56X ( 0.23)

1

4

5

6

7

2

A

(0.4) TYP

B

C

D

E

F

SYMM

G

H

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 25X

0.05 MIN

0.05 MAX

METAL UNDER

SOLDER MASK

(

0.23)

METAL

(

0.23)

EXPOSED

METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4226147/A 08/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YBG0056-C01

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

(R0.05) TYP

56X ( 0.25)

1

4

5

6

7

2

A

(0.4) TYP

B

C

METAL

TYP

D

E

F

SYMM

G

H

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 25X

4226147/A 08/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25790YBGR
厂家：	TEXAS INSTRUMENTS
描述：	集成式、NVDC、5A、1 至 4 节开关模式降压/升压电池充电器 \| YBG \| 56 \| -40 to 85 电池开关
文件：	总133页 (文件大小：2116K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25790YBGR [TI]

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