BQ25882 [TI]
采用 WCSP 封装、具有电源路径且适用于 USB 输入的 I2C 2 节 2A 升压电池充电器;
| 型号： | BQ25882 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 WCSP 封装、具有电源路径且适用于 USB 输入的 I2C 2 节 2A 升压电池充电器 电池 |
| 文件： | 总86页 (文件大小：1746K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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BQ25882
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
适用于 USB 输入的 BQ25882 I2C 控制型 2 节 2A 升压模式电池充电器
1 特性
•
•
高集成度包括所有 MOSFET、电流检测和环路补偿
高精度
1
•
高效的 2A、1.5MHz 开关模式升压充电器
–
–
–
±0.4% 充电电压调节
±7.5% 充电电流调节
±7.5% 输入电流调节
–
–
–
在 7.6V 电池、充电电流为 1A 的情况下，充电
效率为 92.5%
针对 USB 输入和 2 节锂离子电池输出进行了优
化
•
安全
用于轻负载运行的可选低功耗 PFM 模式（具有
无声选项）
–
–
在充电和 OTG 降压模式下的电池温度检测
热调节和热关断
•
USB On-the-Go (OTG)，可调输出电压范围为
4.5V 至 5.5V
2 应用
–
–
–
–
–
具有高达 2A 输出的降压转换器
在 5V、1A 输出的情况下，效率为 94.5%
精确的恒定电流 (CC) 限制
输出短路保护
•
•
•
•
•
•
无线扬声器
数码相机（DSC、DVC）
移动打印机
平板电脑
用于轻负载运行的可选低功耗 PFM 模式（具有
无声选项）
电子销售终端 (ePOS)
便携式电子设备
•
单输入，支持 USB 输入适配器
–
–
–
–
支持 3.9V 至 6.2V 的输入电压范围，绝对最大
输入电压额定值为 20V
3 说明
BQ25882 是高度集成的 2A 开关模式电池充电管理和
系统电源路径管理器件，适用于两节锂离子电池和锂聚
合物电池。具有充电和系统设置的 I2C 串行接口使得此
器件成为真正的灵活解决方案。
输入电流限制（500mA 至 3.3A，精度为 100-
mA），支持 USB2.0、USB3.0 标准适配器
通过高达 5.5V 的输入电压限制进行最大功率跟
踪
器件信息(1)
自动检测 USB SDP、CDP、DCP 以及非标准
适配器
器件型号
BQ25882
封装
封装尺寸（标称值）
2.10 x 2.10 mm2
•
•
•
输入电流优化器 (ICO)，无需过载适配器即可最大
限度地提高输入功率
DSBGA (25)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
采用 15mΩ 电池放电 MOSFET，具有较高的电池
放电效率
简化原理图
集成 ADC，用于系统监视（总线电压和电流、电池
电压、充电电流、系统电压以及 NTC 和裸片温
度）
BQ25882
SYSTEM
USB
VBUS
PMID
SYS
BAT
•
•
窄 VDC (NVDC) 电源路径管理
–
无需电池或深度放电的电池即可瞬时启动
–
电池充电模式下实现理想的二极管运行
灵活的自主和 I2C 模式，可实现最优系统性能
SW
BATP
BATN
I2C Bus
Host
Host
Control
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSE40
BQ25882
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 34
8.5 Register Maps ........................................................ 35
Application and Implementation ........................ 68
9.1 Application Information............................................ 68
9.2 Typical Application .................................................. 68
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements.............................................. 11
7.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
9
10 Power Supply Recommendations ..................... 74
11 Layout................................................................... 75
11.1 Layout Guidelines ................................................. 75
11.2 Layout Example .................................................... 76
12 器件和文档支持 ..................................................... 77
12.1 器件支持 ............................................................... 77
12.2 文档支持................................................................ 77
12.3 接收文档更新通知 ................................................. 77
12.4 社区资源................................................................ 77
12.5 商标....................................................................... 77
12.6 静电放电警告......................................................... 77
12.7 Glossary................................................................ 77
13 机械、封装和可订购信息....................................... 78
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (December 2018) to Revision C
Page
•
Added Device Comparison Table section .............................................................................................................................. 3
Changes from Revision A (August 2018) to Revision B
Page
•
•
已删除 bq25880 references from Functional Block Diagram .............................................................................................. 17
已添加 ADC is enabled to list of conditions to enable buck operation in Buck Mode Operation from Battery (OTG)
section .................................................................................................................................................................................. 20
Changes from Original (February 2018) to Revision A
Page
•
已更改 将“预告信息”更改为“生产数据”.................................................................................................................................... 1
2
版权 © 2018–2019, Texas Instruments Incorporated
BQ25882
www.ti.com.cn
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
5 Device Comparison Table
Table 1. Device Comparison
PRT NUMBER
VBUS Operating Range
USB Detection
Power Path
BQ25882
BQ25883
3.9 to 6.2 V
D+/D-
BQ25886
4.3 to 6.2 V
D+/D-
BQ25887
3.9 to 6.2 V
PSEL
3.9 to 6.2 V
D+/D-
Yes
Yes
Yes
No
Cell Balancing
OTG
No
Up to 2 A
Yes
No
No
Yes
Up to 2 A
Yes
Up to 2 A
No
No OTG
Yes
16 bit ADC
Control Interface
Status Pin
I2C
I2C
Standalone
STAS, /PG
4x4 QFN-24
I2C
/PG
STAT, /PG
4x4 QFN-24
STAT, /PG
4x4 QFN-24
Package
2.1x2.1 WCSP-25
Copyright © 2018–2019, Texas Instruments Incorporated
3
BQ25882
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6 Pin Configuration and Functions
YFF (I2C controlled)
25-Pin DSBGA
Top View
1
2
3
4
5
A
B
C
D
E
VBUS
VBUS
D+
PMID
GND
SW
SW
PMID
GND
INT
ILIM
TS
SYS
BAT
SYS
BAT
PG
Dœ
SCL
SDA
REGN
BATN
BTST
BATP
CE
Top View = Xray through a soldered down part with A1 starting in upper left corner
Pin Functions
PIN
I/O DESCRIPTION
NO.
NAME
C4
C5
E4
E5
Battery Power Connection – The internal BATFET is connected between SYS and BAT. Connect a
10µF ceramic capacitor closely to the BAT pin and GND.
BAT
P
BATN
BATP
AI Negative Battery Sense Terminal – Kelvin connect as close as possible to negative battery terminal
AI Positive Battery Sense Terminal – Kelvin connect as close as possible to positive battery terminal
PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap diode.
Connect a 0.047µF bootstrap capacitor from SW to BTST.
BTST
CE
D5
E1
C1
D1
P
Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is
LOW. CE pin must be pulled HIGH or LOW, do not leave floating.
DI
Positive USB data line – D+/D– based USB host/charging port detection. The detection includes data
contact detection (DCD) and secondary detection in BC1.2.
D+
AIO
Negative USB data line – D+/D– based USB host/charging port detection. The detection includes
data contact detection (DCD) and secondary detection in BC1.2.
D–
AIO
A3
B3
GND
—
Ground Return
Input Current Limit – ILIM pin sets the maximum input current and can be used to monitor input
current. IINDPM loop regulates ILIM pin voltage at 0.8 V. When ILIM pin is less than 0.8 V, the input
current limit can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8 V). A resistor connected from ILIM
pin to ground sets the current limit as IINMAX = KILIM / RILIM. The actual input current limit is the lower
limit set by ILIM pin (when EN_ILIM bit is HIGH) or IINDPM register bits. Input current limit less than
500mA is not supported on ILIM pin. The ILIM pin function can be disabled when EN_ILIM bit is 0.
ILIM
D3
AI
Open Drain Active Low Interrupt Output – Connect /INT to the logic rail via a 10-kΩ resistor. The
INT pin sends active low, 256-µs pulse to the host to report charger device status and fault.
INT
PG
C3
C2
DO
Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW
DO indicates a good input source if the input voltage is within VVBUS_OP, and can provide more than
IPOORSRC.
A2
B2
Blocking MOSFET Connection – Given the total input capacitance, place 1µF on VBUS, and the rest
on PMID, as close to the IC as possible. Typical value: 10µF ceramic capacitor
PMID
P
4
Copyright © 2018–2019, Texas Instruments Incorporated
BQ25882
www.ti.com.cn
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Pin Functions (continued)
PIN
I/O DESCRIPTION
NAME
NO.
Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a
4.7µF ceramic capacitor.
REGN
D4
P
SCL
SDA
D2
E2
A4
A5
B4
DI I2C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
DIO I2C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
SW
P
P
Inductor Connection – Connect to the switched side of the external inductor.
System Connection – The internal BATFET is connected between SYS and BAT. When the battery
falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum
system voltage. Connect a 44µF ceramic capacitor closely to the SYS pin and GND.
SYS
B5
Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor. Program
TS
E3
AI temperature window with a resistor divider from REGN to TS to GND. Charge suspends when TS pin
is out of range. Recommend 103AT-2 thermistor.
A1
B1
Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1µF
ceramic capacitor, placed as close to the IC as possible.
VBUS
P
Copyright © 2018–2019, Texas Instruments Incorporated
5
BQ25882
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
20
UNIT
V
VBUS (converter not switching)
PMID (converter not switching)
BAT, SYS (converter not switching)
SW
–0.3
8.5
12
V
–0.3
–0.6(2)
V
13
V
BTST
–0.3
19
V
Voltage Range (with respect to GND unless
otherwise specified)
BATP
–0.3
12
V
BATN, REGN, SDA, SCL, INT, CE, TS, D+,
D–, PG
–0.3
6
V
ILIM
–0.3
–0.3
–0.3
5
6
V
V
BTST to SW
SYS to BAT
8.5
6
V
Output Sink Current
INT, PG
mA
°C
°C
Junction Temperature, TJ
Storage temperature, Tstg
–40
–40
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) –2V for 50ns
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
±250
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6.2
3.3
2.2
9.2(1)
4
UNIT
V
VVBUS
IVBUS
IBAT
Input voltage
3.9
Average input current (VBUS)
Average charge current (BAT)
Battery voltage (BATP - BATN)
RMS discharging current with internal MOSFET
Peak discharging current with internal MOSFET
Operating free-air temperature
A
A
VBAT
V
IBAT_RMS
IBAT_PK
TA
A
8
A
–40
85
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on SW pins. A tight layout minimizes
switching noise.
6
Copyright © 2018–2019, Texas Instruments Incorporated
BQ25882
www.ti.com.cn
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
BQ25882
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
25-BALL
24
RΘJA
Junction-to-ambient thermal resistance (EVM(2)
)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1)
RΘJA
Junction-to-ambient thermal resistance (JEDEC
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
64.4
0.4
RΘJC(top)
RΘJB
14.8
0.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
14.9
N/A
RΘJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured on 35µm thick copper, 4-layer board.
7.5 Electrical Characteristics
VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
QUIESCENT CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, ADC Disabled, TJ = 25℃
11.5
11.5
30
14 µA
20 µA
35 µA
40 µA
Battery discharge current (BATP,
BAT, SYS)
IBAT
VBAT = 9 V, No VBUS, SCL, SDA = 0 V
or 1.8 V, ADC Disabled, TJ < 85℃
VBUS = 5 V, High-Z Mode, no battery,
ADC Disabled, TJ = 25℃
IVBUS_HIZ
Input supply current (VBUS) in HIZ
Input supply current (VBUS)
VBUS = 5 V, High-Z Mode, no battery,
ADC Disabled, TJ < 85℃
30
VBUS = 5 V, VBAT = 7.6 V, converter not
switching
1.5
3
3
mA
mA
mA
IVBUS
VBUS = 5 V, VBAT = 7.6 V, converter
switching, ISYS = 0A
VBAT = 8.4 V, OTG Buck Mode,
IVBUS = 0A, converter switching
Battery discharge current in OTG
mode
IBAT_OTG
3
VBUS/VBAT POWER UP
VVBUS_OP
VBUS operating range
VBUS rising for active I2C, no battery VBUS rising
3.9
6.2
3.6
V
V
VVBUS_UVLOZ
VVBUS_PRESENT
3.3
VBUS rising
VBUS rising
VBUS falling
VBAT rising
3.65
3.9
V
VBUS over-voltage rising threshold
VBUS over-voltage falling threshold
Battery for active I2C
6.2
5.9
3.7
6.6
V
VVBUS_OV
6.4
V
VBAT_UVLOZ
VPOORSRC
4.0
3.7
15
4.335
V
Bad adapter detection threshold
Bad adapter detection current source
V
IPOORSRC
mA
POWER-PATH
ISYS = 0A, VBAT = 8.80 V >
VSYS
Typical System Regulation Voltage
SYS_MIN[3:0], Charge Disabled (EN_CHG
= 0). Offset above VBAT
100
mV
ISYS = 0A, VBAT < SYS_MIN[3:0],
Charge Disabled (EN_CHG = 0). Offset
above SYS_MIN
VSYS
Typical System Regulation Voltage
System Regulation Voltage
200
7.2
mV
V
VBAT < SYS_MIN[3:0] = 1010, Charge
Disabled (EN_CHG = 0)
VSYS_MIN
7
TJ = 25°C
25
25
36 mΩ
52 mΩ
Blocking MOSFET on-resistance
between VBUS and PMID (QB)
RON_QBLK (Q1)
TJ = – 40°C - 125°C
Copyright © 2018–2019, Texas Instruments Incorporated
7
BQ25882
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-side switching MOSFET on-
resistance between SW and SYS
(Q2)
TJ = 25°C
30
40 mΩ
RON_QHS (Q2)
TJ = – 40°C - 125°C
TJ = 25°C
30
40
40
55 mΩ
59 mΩ
80 mΩ
Low-side switching MOSFET on-
resistance between SW and GND
(Q3)
RON_QLS (Q3)
TJ = – 40°C - 125°C
BATTERY CHARGER
Typical charge voltage regulation
VREG_RANGE
VREG_STEP
6.8
9.2
V
range
Typical charge voltage step
10
mV
V
VREG = 8.40 V, TJ = – 40°C - 85°C
VREG = 8.70 V, TJ = – 40°C - 85°C
VREG = 8.80 V, TJ = – 40°C - 85°C
8.3664
8.6652
8.7648
0
8.4 8.4336
8.7 8.7348
8.8 8.8352
VREG_ACC
Charge voltage accuracy
V
V
ICHG_RANGE
ICHG_STEP
Charge current regulation range
Charge current regulation step
2200 mA
mA
50
ICHG = 250 mA, VBAT = 6.2 V or 7.6 V,
TJ = – 20°C - 85°C
-25
-10
25
10
%
%
%
Fast Charge current regulation
accuracy
ICHG = 500 mA, VBAT = 6.2 V or 7.6 V,
TJ = – 20°C - 85°C
ICHG_ACC
ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V,
TJ = – 20°C - 85°C
-7.5
50
7.5
IPRECHG_RANGE
IPRECHG_STEP
Precharge current range
800 mA
mA
Typical precharge current step
50
50
VBAT = 5.2 V, IPRECHG = 200 mA,
TJ = – 20°C - 85°C
IPRECHG_ACC
Precharge current accuracy
-20
50
20
%
ITERM_RANGE
ITERM_STEP
Termination current range
800 mA
mA
Typical termination current step
ICHG = 1.5A, ITERM = 50 mA,
TJ = – 40°C - 85°C
-40
40
%
ITERM_ACC
Termination current accuracy
ICHG = 1.5A, ITERM = 150 mA,
TJ = – 40°C - 85°C
-20
4.1
20
%
V
VBAT_SHORT
Short Battery Voltage rising threshold VBAT rising
to start pre-charging
4.4
4.0
4.7
VBAT_SHORT_HYS
Short Battery Voltage falling
threshold to stop pre-charging
VBAT falling
3.7
4.3
V
Short Battery Voltage trickle charging
current
IBAT_SHORT
VBAT < 4.4 V
100
6
mA
V
VBAT LOWV Rising threshold to
start fast-charging
VBAT rising, VBATLOW = 6.0 V
VBAT falling, VBATLOW = 6.0 V
5.7
5.3
6.3
5.9
VBAT_LOWV
VBAT LOWV Falling threshold to
stop fast-charging
5.6
V
VBAT falling, VRECHG[1:0] = 01
VBAT falling, VRECHG[1:0] = 10
TJ = 25°C
200
300
15
mV
mV
VRECHG
Recharge threshold below VREG
18 mΩ
26 mΩ
MOSFET on-resistance between
SYS and BAT (Q4)
RON_QBAT (Q4)
TJ = – 40°C - 125°C
15
VBAT = 8 V, VBUS = 5 V, EN_HIZ = 1,
ADC Disabled
RBATP
RBATN
BATP Input resistance
BATN Input resistance
2.7
2.7
MΩ
MΩ
VBAT = 8 V, VBUS = 5 V, EN_HIZ = 1,
ADC Disabled
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Input voltage regulation range
3.9
5.5
V
8
Copyright © 2018–2019, Texas Instruments Incorporated
BQ25882
www.ti.com.cn
ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
100
3.9
MAX UNIT
VINDPM_STEP
VINDPM
Input voltage regulation step
mV
VINDPM = 3.9 V
3.783
4.268
500
4.017
4.532
V
V
Input voltage limit
VINDPM = 4.4 V
4.4
IINDPM_RANGE
IINDPM_STEP
Input current regulation range
Input current regulation step
3300 mA
mA
100
470
IINDPM = 500 mA
IINDPM = 900 mA
IINDPM = 2500 mA
IINDPM = 3000 mA
445
765
500 mA
900 mA
2500 mA
3000 mA
832.5
IINDPM_ACC
Input current regulation limit
2125 2312.5
2550
2775
IINMAX = KILIM/RILIM, Input Current
regulation by ILIM pin = 1.5A
A x
Ω
KILIM
1000
1085
1170
D+/D- DETECTION
VD+D-_600MVSRC
ID+_10UASRC
D+/D- Voltage Source (600 mV)
D+ Current Source (10 µA)
D+/D- Current Sink (100 µA)
500
7
600
10
700 mV
14 µA
ID+D-_100UASNK
50
100
150 µA
D+/D- Comparator Threshold for
Secondary Detection
VD+D-_0P325
250
400 mV
D+Comparator Threshold for Data
Contact Detection
VD+_0P8
RD-_19K
800 mV
D- Resistor to Ground (19 kΩ)
14.25
1.05
24.8 kΩ
D+/D- Threshold for Non-standard
adapter
VD+D-_1P2
1.35
2.15
V
V
D+/D- Threshold for Non-standard
adapter
VD+D-_2P0
1.85
D+/D- Threshold for Non-standard
adapter
VD+D-_2P8
ID+D-_LKG
2.55
-1
2.85
1
V
D+/D- Leakage Current
HiZ
µA
BATTERY OVER-VOLTAGE PROTECTION
Battery over-voltage rising threshold VBAT rising, as percentage of VREG
Battery over-voltage falling threshold VBAT falling, as percentage of VREG
103
101
104
102
105
103
%
%
VBAT_OVP
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction temperature regulation
accuracy
TREG
TREG = 120°C
120
°C
Thermal Shutdown Rising threshold
TSHUT
Temperature Increasing
150
120
°C
°C
Thermal Shutdown Falling threshold Temperature Decreasing
JEITA THERMISTOR COMPARATOR (BOOST MODE)
T1 (0°C) threshold, Charge
suspended below this temperature.
VT1
As Percentage to REGN
As Percentage to REGN
72.75
67.75
73.25
1.3
73.75
68.75
%
%
Charge re-enabled to ICHG/2 and
VREG above this temperature
VT1_HYS
T2 (10°C) threshold, Charge back to
ICHG/2 and VREG below this
temperature
VT2
As Percentage to REGN
As Percentage to REGN
As Percentage to REGN
As Percentage to REGN
68.25
1.3
%
%
%
%
Charge back to ICHG and VREG
above this temperature
VT2_HYS
T3 (45°C) threshold, Charge back to
ICHG and 8.1 V above this
temperature.
VT3
44.25
44.75
1
45.25
Charge back to ICHG and VREG
below this temperature
VT3_HYS
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MAX UNIT
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
As Percentage to REGN
As Percentage to REGN
MIN
TYP
T5 (60°C) threshold, charge
suspended above this temperature.
VT5
33.875 34.375 34.875
1.3
%
%
Charge back to ICHG and 8.1 V
below this temperature
VT5_HYS
COLD/HOT THERMISTOR COMPARATOR (OTG BUCK MODE)
Cold Temperature Threshold 0, TS
pin Voltage Rising Threshold
As Percentage to REGN, BCOLD = 0
(Approx. – 10°C w/ 103AT)
VBCOLD0
76.5
79.5
77
77.5
80.5
%
%
%
%
%
%
%
%
%
%
Cold Temperature Threshold 0, TS
pin Voltage Falling Threshold
VBCOLD0_HYS
VBCOLD1
VBCOLD1_HYS
VBHOT0
VBHOT0_HYS
VBHOT1
VBHOT1_HYS
VBHOT2
As Percentage to REGN
1
80
Cold Temperature Threshold 1, TS
pin Voltage Rising Threshold
As Percentage to REGN, BCOLD = 1
(Approx. – 20°C w/ 103AT)
Cold Temperature Threshold 1, TS
pin Voltage Falling Threshold
As Percentage to REGN
1
Hot Temperature Threshold 0, TS pin As Percentage to REGN, BHOT[1:0] = 01
Voltage Falling Threshold
37.25
37.75
3
38.25
(Approx. 55°C w/ 103AT)
Hot Temperature Threshold 0, TS pin
Voltage Rising Threshold
As Percentage to REGN
Hot Temperature Threshold 1, TS pin As Percentage to REGN, BHOT[1:0] = 00
Voltage falling Threshold
33.875 34.375 34.875
3
(Approx. 60°C w/ 103AT)
Hot Temperature Threshold 1, TS pin
Voltage rising Threshold
As Percentage to REGN
Hot Temperature Threshold 2, TS pin As Percentage to REGN, BHOT[1:0] = 10
Voltage falling Threshold
30.75
31.25
3
31.75
(Approx. 65°C w/ 103AT)
Hot Temperature Threshold 2, TS pin
Voltage rising Threshold
VBHOT1_HY2
As Percentage to REGN
BOOST MODE CONVERTER
FSW
PWM switching frequency
Oscillator frequency
BAT falling
1.35
1.5
6
1.65 MHz
OTG BUCK MODE CONVERTER
VOTG_BAT
Battery voltage exiting OTG mode
5.85
4.5
6.15
5.5
V
V
Typical OTG Buck mode voltage
regulation range
VOTG_RANGE
Typical OTG Buck mode voltage
regulation step
VOTG_STEP
VOTG_ACC
IOTG_RANGE
IOTG_STEP
IOTG_ACC
100
mV
%
OTG Buck mode voltage regulation
accuracy
IVBUS = 0A, OTG_VLIM = 5 V
-3
3
2
Typical OTG Buck mode current
regulation range
0.5
A
Typical OTG Buck mode current
regulation step
100
-7.5
6
mA
%
OTG Buck mode current regulation
accuracy
OTG_ILIM = 1A
-15
5.8
0.05
OTG Buck mode over-voltage
threshold
VOTG_OVP
V
REGN LDO
VREGN
REGN LDO output voltage
REGN LDO current limit
VVBUS = 5 V, IREGN = 20 mA
VVBUS = 5 V, VREGN = 3.8 V
4.7
50
4.8
V
IREGN
mA
Analog-to-Digital Converter (ADC)
ADC_SAMPLE[1:0] = 00
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
24
12
6
ms
ms
ms
ms
tADC_CONV
Conversion time, each measurement
3
10
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Electrical Characteristics (continued)
VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC_SAMPLE[1:0] = 00
MIN
14
TYP
15
MAX UNIT
bits
bits
bits
bits
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
13
14
ADCRES
Effective resolution
12
13
10
11
ADC MEASUREMENT RANGES AND LSB
IBUS_ADC_RANGE
IBUS_ADC_LSB
IBAT_ADC_RANGE
IBAT_ADC_LSB
ADC BUS current range
ADC BUS current LSB
ADC BAT current range
ADC BAT current LSB
ADC BUS voltage range
ADC BUS voltage LSB
ADC SYS voltage range
ADC SYS voltage LSB
ADC BAT voltage range
ADC BAT voltage LSB
ADC TS voltage range
ADC TS voltage LSB
0
0
4
4
A
mA
A
1
1
mA
V
VBUS_ADC_RANGE
VBUS_ADC_LSB
VSYS_ADC_RANGE
VSYS_ADC_LSB
VBAT_ADC_RANGE
VBAT_ADC_LSB
VTS_ADC_RANGE
VTS_ADC_LSB
0
6.5
10
10
80
1
mV
V
0
1
1
mV
V
0
mV
%
20
0
0.098
1
%
VTDIE_ADC_RANGE
VTDIE_ADC_LSB
ADC Die temperature range
ADC Die temperature LSB
150 °C
°C
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA and
SCL
VIH
Pull-up rail 1.8 V
1.3
1.3
V
VIL
Input low threshold level
Output low threshold level
High level leakage current
Pull-up rail 1.8 V
Sink current = 5 mA
Pull-up rail 1.8 V
0.4
0.4
1
V
V
VOL
IBIAS
µA
LOGIC I/O PIN (/CE, PSEL)
VIH
Input high threshold level
V
V
VIL
Input low threshold level
High level leakage current
0.4
1
IIN_BIAS
Pull-up rail 1.8 V
µA
LOGIC O PIN (/INT, /PG, STAT)
VOL
Output low threshold level
High level leakage current
Sink current = 5 mA
Pull-up rail 1.8 V
0.4
1
V
IOUT_BIAS
µA
7.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
VBUS/BAT POWER UP
VBUS rising above VBUS_OV threshold to
converter turn off
tVBUS_OV
VBUS OVP reaction time
Bad adapter detection duration
200
30
ns
tPOORSRC
BATTERY CHARGER
ms
tTERM_DGL
Deglitch time for charge termination
Charge current falling below ITERM
250
250
ms
ms
BAT voltage falling below VRECHG = 100
mV
tRECGH_DGL
Deglitch time for recharge threshold
Deglitch time for battery over-voltage
to disable charge
tBAT_OVP_DGL
1
µs
tTOP_OFF
tSAFETY
Typical Top-Off Timer Accuracy
Charge Safety Timer Accuracy
TOP_OFF_TIMER[1:0] = 30 min
CHG_TIMER[1:0] = 12 hours
24
30
12
36 min
10.8
13.2 hr
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Timing Requirements (continued)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
I2C INTERFACE
fSCL
SCL clock frequency
1000 kHZ
DIGITAL CLOCK AND WATCHDOG TIMER
fLPDIG
fDIG
Digital low power clock
Digital clock
REGN LDO disabled
18
30
45 kHZ
REGN LDO enabled
1.35
1.5
1.65 MHz
WATCHDOG[1:0] = 160 s, REGN LDO
disabled
tWDT
tWDT
Watchdog Reset time
Watchdog Reset time
100
136
160
160
sec
sec
WATCHDOG[1:0] = 160 s, REGN LDO
enabled
12
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
7.7 Typical Characteristics
CVBUS = 1µF, CPMID= 10µF, CSYS = 44µF, CBAT = 10µF, L = 1uH (DFE252012F-1R0) (unless otherwise specified)
95
94
93
92
91
90
89
88
87
86
85
95
94
93
92
91
90
89
88
87
86
85
VBAT = 7.6V
VBAT = 8.0V
VBAT = 7.6V
VBAT = 8.0V
0
0.2 0.4 0.6 0.8
1
Charge Current (A)
1.2 1.4 1.6 1.8
2
2
1
0
0.2 0.4 0.6 0.8
1
Charge Current (A)
1.2 1.4 1.6 1.8
2
VBUS = 5V
图 1. Charge Efficiency vs. Charge Current
VBUS = 5V
L = 1µH (IHLP2525CZ-01)
图 2. Charge Efficiency vs. Charge Current
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
55
PFM En, OOA En
PFM En, OOA Dis
PFM Dis
PFM En, OOA En
PFM En, OOA Dis
PFM Dis
0.01
0.020.03 0.05
0.1
0.2 0.3 0.5 0.7
IBUS (A)
1
0.01
0.020.03 0.05
0.1
0.2 0.3 0.5 0.7
IBUS (A)
1
2
VBUS = 5.0V
VBAT = 7.6V
VBUS = 5.0V
VBAT = 7.6V L = 1µH (IHLP2525CZ-01)
图 3. OTG Efficiency vs. VBUS Output Current
图 4. OTG Efficiency vs. VBUS Output Current
95
90
85
80
75
70
65
60
55
15
12.5
10
VBAT = 6.6V
VBAT = 7.6V
7.5
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
PFM En, OOA En
PFM En, OOA Dis
PFM Dis
0.01
0.02 0.03 0.050.07 0.1
0.2 0.3
0.5 0.7
0
0.2 0.4 0.6 0.8 1
ICHG Setting (A)
1.2 1.4 1.6 1.8
2
System Current (A)
VBUS = 5V
VBAT = 8.4V
VBUS = 5V
图 5. System Efficiency vs. System Current
图 6. Charge Current Accuracy vs. ICHG Setting
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Typical Characteristics (接下页)
CVBUS = 1µF, CPMID= 10µF, CSYS = 44µF, CBAT = 10µF, L = 1uH (DFE252012F-1R0) (unless otherwise specified)
0.4
250
225
200
175
150
125
100
75
-40èC
0èC
25èC
85èC
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
50
25
0
6.75 7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75 9.00 9.25
VREG Setting (V)
1
1.2
1.4 1.6
System Current (A)
1.8
2
VBUS = 5V
VBUS = 5V
VBAT = 6V,
SYSMIN = 7V
EN_CHG = 0
图 8. SYSMIN Load Regulation
图 7. Battery Voltage Accuracy vs. VREG Setting
8.50
3.0
2.5
-40èC
0èC
25èC
85èC
8.49
8.48
8.47
8.46
8.45
8.44
8.43
8.42
8.41
8.40
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0.3
0.4
0.5
0.6 0.7
System Current (A)
0.8
0.9
1
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
OTG_VLIM Setting(V)
VBUS = 5V
VBAT = 8.4V
EN_CHG = 0
VBAT = 8.0V
图 9. System Load Regulation After Charge Done
图 10. OTG VBUS Regulation vs. OTG_VLIM Setting
0
-1
3.0
-40èC
25èC
85èC
-40èC
0èC
25èC
85èC
2.5
2.0
-2
-3
1.5
-4
-5
1.0
-6
-7
0.5
0.0
-8
-9
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-10
-11
-12
-13
-14
-15
0.4
VBAT = 8.0V
图 11. OTG IBUS Limit vs. OTG_ILIM Setting
0.6
0.8
1
1.2
1.4
1.6
1.8
2
6.0
6.3
6.6
6.9
7.2
VBAT Voltage (V)
7.5
7.8
8.1
8.4
8.7
OTG_ILIM Setting (A)
VBUS = 5.1V
IBUS = 1A
图 12. OTG Voltage Regulation vs. VBAT Voltage
14
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
Typical Characteristics (接下页)
CVBUS = 1µF, CPMID= 10µF, CSYS = 44µF, CBAT = 10µF, L = 1uH (DFE252012F-1R0) (unless otherwise specified)
0
-1
3.0
Temp = -40èC
Temp = -20èC
Temp = 25èC
Temp = 85èC
Temp = -40èC
Temp = 0èC
Temp = 25èC
Temp = 85èC
2.5
-2
-3
2.0
1.5
-4
-5
1.0
-6
-7
0.5
0.0
-8
-9
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-10
-11
-12
-13
-14
-15
0.6
0.8
1.0
1.2 1.4
VBUS Current (A)
1.6
1.8
2.0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
IINDPM Setting (A)
VBUS = 5.1V
VBAT = 8.0V
VBUS = 5.0V
VBAT = 7.6V
图 13. OTG Voltage Regulation vs. OTG BUS Current
图 14. Input Current Limit Accuracy vs. IINDPM Setting
0.2
3.0
2.5
TREG = 60èC
TREG = 80èC
TREG = 100èC
TREG = 120èC
VBAT = 6.6V
VBAT = 7.6V
2.0
0.15
0.1
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0.05
0
-0.05
3.8
4.0
4.2
4.4
4.6
VINDPM Setting (V)
4.8
5.0
5.2
5.4
5.6
40
60
80
100
120
140
160
180
Die Temperature (èC)
VBAT = 7.6V
VBUS = 5V
VBAT = 7.6V
ICHG = 150mA
图 15. Input Voltage Limit Accuracy vs. VINDPM Setting
图 16. TREG Profiles
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
ICHG = 0.5A
ICHG = 1.0A
ICHG = 1.8A
90 95 100 105 110 115 120 125 130 135 140 145 150
Die Temperature (èC)
VBUS = 5V
VBAT = 7.6V
ICHG = 1A, 1.5A, 2.2A
图 17. Max Current Temperature Profile
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8 Detailed Description
8.1 Overview
The device is a highly integrated 2-A switch-mode battery charger for dual cell Li-Ion and Li-polymer battery. It
integrates the input blocking FET (Q1, QBLK), high-side switching FET (Q2, QHS), low-side switching FET (Q3,
QLS), and battery FET (Q4, QBAT). The device also integrates the boot-strap diode for high-side gate drive.
8.2 Functional Block Diagram
VBUS
PMID
VVBUS_UVLOZ
QBLK
(Q1)
+
UVLO
QBLK
CONTROL
REGN
BTST
REGN
REGN
LDO
EN_HIZ
+
VBUS_OVP
VVBUS_OV
VO,REF
SYS
VVBUS
OTG_OVP
VOTG
VVBUS
+
VOTG_OVP
QHS
(Q2)
+
OTG_Q2_OCP
+
IQ2
VVBUS
SYS
+
+
+
IHSOCP
VMIN_SYS
VINDPM
+
SW
BAT_OVP
BATSNS
VBAT_OVP
IIN
BATSNS
VBAT_REG
+
+
+
QLS
(Q3)
REGN
DC-DC
CONTROL
IINDPM
IC_TJ
TREG
ICHG
GND
ICHG_REG
EN_CHARGE
IQ3
+
+
Q3_OCP
GND
EN_HIZ
ILSOCP
EN_OTG
VBTST œ VSW
REFRESH
VBTST_REFRESH
VPOORSRC
CONVERTER
CONTROL
STATE
+
+
POORSRC
TSHUT
VVBUS
REF
DAC
IC_TJ
TSHUT
MACHINE
SYS
ILIM
D+
IBUS
ICHG
VBUS
VBAT
VSYS
VTS
ICHG
QBAT
(Q4)
ADC
VBAT_REG
ICHG_REG
USB
DETECTION
QBAT
CONTROL
Dœ
/PG
/INT
TDIE
VREG - VRECHG
BATSNS
RECHRG
+
+
BAT
ICHG
ITERM
BATP
TERMINATION
BATLOWV
BATSNS
BATSNS
AMP
CHARGE
CONTROL
STATE
VBAT_LOWV
BATSNS
+
+
MACHINE
BATN
TS
BQ25882
VBAT_UVLOZ
BATSNS
BATUVLO
BATTERY
SENSING
THERMISTOR
VTS
I2C
INTERFACE
TS_SUSPEND
/CE
SCL
SDA
16
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8.3 Feature Description
8.3.1 Device Power-On-Reset
The internal bias circuits are powered from either VBAT or VBUS. When VBUS rises above VVBUS_UVLOZ or BAT
rises above VBAT_UVLOZ, the BATFET driver is active. I2C interface is ready for communication and all the
registers are reset to default value. The host can access all the registers after POR.
8.3.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above UVLO threshold (VBAT_UVLOZ), the BATFET turns on and
connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of
BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors discharge current through BATFET (Supplement Mode).
8.3.3 Device Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the boost converter is started. The power up
sequence from input source is as listed:
1. Poor Source Qualification
2. Input Source Type Detection based on D+/D– to set default Input Current Limit (IINDPM) register and input
source type
3. Power Up REGN LDO
4. Converter Power-up
8.3.3.1 Poor Source Qualification
After valid VBUS is plugged in, the device checks the current capability of the input source. The input source has
to meet the following requirements in order to start the boost converter.
1. VBUS voltage below VVBUS_OVP
2. VBUS voltage above VPOORSRC when pulling IPOORSRC
If VBUS_OVP is detected (condition 1 above), the device automatically retries detection once the over-voltage
fault goes away . If a poor source is detected (condition 2 above), the device repeats poor source qualification
routine every 2 seconds. After 7 consecutive failures, the device sets EN_HIZ = 1, and goes to HIZ mode. The
battery powers up the system when the device is in HIZ. Adapter re-plugin and/or EN_HIZ bit toggle is required
to restart device operation. The EN_HIZ bit is cleared automatically when the adapter is plugged in.
8.3.3.2 Input Source Type Detection
After the input source is qualified, the charger device runs Input Source Type Detection when AUTO_INDET_EN
bit is set.
The BQ25882 follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source
(SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. After input source type detection, the
following registers and pins are changed:
1. Input Current Limit (IINDPM) register is changed to set current limit
2. Input Voltage Limit (VINDPM) register is changed to set default limit (if EN_VINDPM_RST = 1, otherwise
VINDPM value remains unchanged)
3. VBUS_STAT bits change to reflect the detected source
4. INT pin pulses to notify the host
5. PG pin is pulled LOW, and PG_STAT bit is set to '1'
After detection is completed, the host can over-write IINDPM or VINDPM registers to change the input current, or
input voltage limit if needed. The charger input current is always limited by the lower of IINDPM register or ILIM
pin at all-times regardless of Input Current Optimizer (ICO) setting.
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Feature Description (接下页)
When AUTO_INDET_EN is disabled, the Input Source Type Detection is bypassed, and the Input Current Limit
(IINDPM) register remains unchanged from previous value. When EN_VINDPM_RST is disabled, the Input
Voltage Limit (VINDPM) register remains unchanged from previous value.
8.3.3.2.1 D+/D– Detection Sets Input Current Limit
The BQ25882 contains a D+/D- based input source detection to program the input current limit. The D+/D-
detection has three major steps: Data Contact Detect (DCD), Primary Detection, and Secondary Detection.
Unknown/1000mA
Unknown/500mA or ILIM
Divider 1/2.1A
Divider 3/1.0A
Divider 4/2.4A
Non-Standard
Adapter
Data Detection
Contact
(DCD)
Adapter Plug-in
or
FORCE_INDET
Secondary
Detection
VBUS
Detection
Primary
Detection
DCP
(3000mA)
USB BC1.2 Standard
CDP
(1500mA)
SDP
(500mA)
图 18. D+/D– Detection Flow
表 2. Non-Standard Adapter Detection
NON-STANDARD
D+ THRESHOLD
D– THRESHOLD
INPUT CURRENT LIMIT
ADAPTER
Divider 1
VD+ within VD+D-_2P8
VD+ within VD+D-_2P0
VD+ within VD+D-_2P8
VD+ = 1 MΩ to 0 V
VD– within VD+D-_2P0
VD– within VD+D-_2P8
VD– within VD+D-_2P8
VD- = 3.3 V
2.1 A
1 A
Divider 3
Divider 4
2.4 A
1.0 A
Unknown 2
After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following
registers including Input Current Limit register (IINDPM), and VBUS_STAT are updated as below:
表 3. Input Current Limit Setting from D+/D– Detection
D+/D– DETECTION
USB SDP (USB500)
USB CDP
INPUT CURRENT LIMIT (IINDPM)
VBUS_STAT
001
500 mA
1.5 A
010
USB DCP
3.0 A
011
Divider 3
1 A
110
Divider 1
2.1 A
110
Divider 4
2.4 A
110
Unknown 5-V Adapter (1)
Unknown 5-V Adapter (2)
500 mA
1000 mA
101
101
8.3.3.2.2 Force Input Current Limit Detection
In host mode, the host can force the device to run Input Current Limit Detection by setting FORCE_INDET bit.
After the detection is completed, FORCE_INDET bit returns to 0 by itself and Input Result is updated. After the
detection is completed, the input current limit (IINDPM), and the VBUS_STAT bits may be changed by the device
due to the detection result.
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8.3.3.3 Power up REGN Regulator (LDO)
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also
provides bias rail to TS external resistors. The pull-up rail of /PG can be connected to REGN as well. The REGN
is enabled when all the below conditions are valid.
1. VBUS above VVBUS_UVLOZ in boost mode or VBUS below VVBUS_UVLOZ in buck mode
2. Poor Source Qualification detects a valid input source
3. Input Source Type Detection completes and sets appropriate input current limit
4. After 220 ms delay is complete
If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The
device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the
device is in HIZ.
8.3.3.4 Converter Power Up
After the input current limit is set, the PG pin is pulled LOW, the PG_STAT and VBUS_STAT bits are changed,
and the converter is enabled, allowing the HSFET and LSFET to start switching. If battery charging is disabled,
BATFET turns off. Otherwise, BATFET stays on to charge the battery. The device provides soft-start when
system rail is ramped up.
Before charging begins, the battery discharge source (IBAT_DISCHG) is enabled automatically to detect the
presence of battery. The host can enable IBAT_DISCHG via the EN_BAT_DISCHG bit at any point during
operation, including in Battery Only or HIZ modes.
As a battery charger, the device deploys a highly efficient 1.5-MHz step-up switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying filter design.
In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below
minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is
set by the ratio of SYS and VBUS. PFM operation may be disabled by the host using the PFM_DIS bit. PFM
operation also includes an out-of-audio (OOA) feature to prevent the converter from switching within the audible
range (< 20 kHz) at no load conditions. This feature may be disabled by the host using the PFM_OOA_DIS bit.
8.3.4 Input Current Optimizer (ICO)
The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without
overloading the input source. The algorithm automatically identifies maximum input current limit of a power
source without staying in VINDPM to avoid input source overload.
This feature is enabled by default (EN_ICO=1) and can be disabled by setting EN_ICO bit to 0. After DCP type
input source is detected based on the procedures describe above (Input Source Type Detection), the algorithm
runs automatically when EN_ICO bit is set. The algorithm can also be forced to execute by setting FORCE_ICO
bit regardless of input source type detected (EN_ICO = 1 is required for FORCE_ICO to work).
表 4. Input Current Optimizer Automatic Operation
AUTOMATIC START ICO
ALGORITHM WHEN EN_ICO = 1
DEVICE
INPUT SOURCE
INPUT CURRENT LIMIT (IINDPM)
USB SDP (USB500)
USB CDP
500mA
1.5A
Disable
Disable
Enable
Disable
Disable
Disable
Disable
Disable
USB DCP
3.0A
Divider 3
1A
BQ25882 (D+/D–)
Divider 1
2.1A
Divider 4
2.4A
Unknown 5V Adapter (1)
Unknown 5V Adapter (2)
500mA
1000mA
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The actual input current limit used by the Dynamic Power Management is reported in ICO_ILIM register while
Input Current Optimizer is enabled (EN_ICO = 1) or set by IINDPM register when the algorithm is disabled
(EN_ICO = 0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin
function.
When the algorithm is enabled, it runs continuously to adjust input current limit of Dynamic Power Management
(IINDPM) using ICO_ILIM register until ICO_STAT[1:0] and ICO_FLAG bits are set (the ICO_FLAG bit indicates
any change in ICO_STAT[1:0] bits). The algorithm operates depending on battery voltage:
1. When battery voltage is below SYS_MIN, the algorithm starts ICO_ILIM register with IINDPM which is the
maximum input current limit allowed by system
2. When battery voltage is above SYS_MIN, the algorithm starts ICO_ILIM register with 500 mA which is the
minimum input current limit to minimize adapter overload
When optimal input current is identified, the ICO_STAT[1:0] and ICO_FLAG bits are set to indicate input current
limit in ICO_ILIM register would not be changed until the algorithm is forced to run by the following event (these
events also reset the ICO_STAT[1:0] bits to '01'):
1. A new input source is plugged-in, or EN_HIZ bit is toggled
2. IINDPM register is changed
3. VINDPM register is changed
4. FORCE_ICO bit is set to 1
5. VBUS_OVP event
8.3.5 Buck Mode Operation from Battery (OTG)
The device supports buck converter operation to deliver power from the battery to other portable devices through
USB port. The buck mode output current rating meets the USB On-The-Go 500-mA (OTG_ILIM bits = 000)
output requirement. The maximum output current is up to 2.0 A. The buck operation can be enabled if the
following conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than VVBUS_PRESENT
3. ADC is enabled
4. Buck mode operation is enabled (EN_OTG = 1)
5. Voltage at TS (thermistor) pin is within range configured by Buck Mode Temperature Monitor as configured
by BHOT and BCOLD register bits
In buck mode, the device employs 1.5-MHz step-down switching regulator based on system requirements.
During buck mode, the status register VBUS_STAT bits are set to 111, the VBUS output is 5.1 V by default
(selectable via OTG_VLIM register bits) and the output current can reach up to 2.0 A, selected via I2C
(OTG_ILIM bits). The buck output is maintained when BAT is above VOTG_BAT threshold, and VBUS is above
VVBUS_PRESENT threshold.
In order to improve light-load efficiency, the device switches to PFM control at light load. During the PFM
operation, the switching duty cycle is set by the ratio of SYS and VBUS. PFM operation may be disabled by the
host using the PFM_DIS bit. PFM operation also includes an out-of-audio (OOA) feature to prevent the converter
from switching within the audible range (< 20 kHz) at no load conditions. This feature may be disabled by the
host using the PFM_OOA_DIS bit.
8.3.6 Power Path Management
The device accommodates a wide range of input sources from USB, to wall adapter, to power bank. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
8.3.6.1 Narrow VDC Architecture
The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The
minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated
above the minimum system voltage (default 7.0 V).
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When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),
and the system is typically 200 mV above the minimum system voltage setting. As the battery voltage rises
above the minimum system voltage, BATFET is fully on and the voltage difference between the system and
battery is the VDS of BATFET.
When the battery charging is disabled and VBAT is above minimum system voltage setting or charging is
terminated, the system is always regulated at typically 100 mV above battery voltage. The status register
VSYS_STAT bit goes high when the system is in minimum system voltage regulation.
9.0
8.6
Charge Enabled
8.2
7.8
Charge Disabled
7.4
7.0
Minimum System Voltage
6.6
6.2
5.4
5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6
BAT (V)
图 19. System Voltage vs. Battery Voltage
8.3.6.2 Dynamic Power Management
To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic
Power Management (DPM), which continuously monitors the input current and input voltage. When input source
is over-loaded, either the current exceeds the input current limit (IINDPM or ICO_ILIM or ILIM pin setting) or the
voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the input
current falls below the input current limit and the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement
Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the
input source and battery.
During DPM mode, the status register bits VINDPM_STAT (VINDPM) and/or IINDPM_STAT (IINDPM) go high.
The figure shows the DPM response with 5-V/3-A adapter, 6.4-V battery, 1.5-A charge current and 6.8-V
minimum system voltage setting.
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VSYS
7.0V
6.8V
VBAT
6.4V
6.0V
VBUS
5.0V
4.0V
3A
IBUS
2A
IBAT
1A
ISYS
0A
-1A
DPM
CC
DPM
CC
Supplement
图 20. DPM Response
8.3.6.3 Supplement Mode
When the voltage falls below the battery voltage, the BATFET turns on.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the
BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current.
The figure shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit Supplement
Mode when the battery is below battery depletion threshold (VBAT_DPL).
75
70
65
60
55
50
45
40
35
30
25
0
0.5
1
1.5
2
2.5
IBAT (A)
3
3.5
4
4.5
5
D001
图 21. BATFET I-V Curve
8.3.7 Battery Charging Management
The device charges 2-cell Li-Ion battery with up to 2.2-A charge current for high capacity battery. The low RDS(ON)
BATFET improves charging efficiency and minimize the voltage drop during discharging.
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8.3.7.1 Autonomous Charging Cycle
When battery charging is enabled (EN_CHG bit =1 and /CE pin is LOW), the device autonomously completes a
charging cycle without host involvement. The device default charging parameters are listed in the table below.
The host can always control the charging operation and optimize the charging parameters by writing to the
corresponding registers through I2C.
表 5. Charging Parameter Default Settings
DEFAULT MODE
Charging Voltage
Charging Current
Pre-Charge Current
Termination Current
Temperature Profile
Safety Timer
BQ25882
8.4 V
1.00 A
150 mA
150 mA
JEITA
12 hours
A new charge cycle starts when the following conditions are valid:
•
•
Converter starts
Battery charging is enabled by I2C register bit (EN_CHG = 1 and CE pin is LOW and ICHG register is not 0
mA)
•
•
No thermistor fault on TS
No safety timer fault
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, charge voltage is above recharge threshold, and device is not in DPM mode or thermal regulation.
When a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG[1:0] bits),
the device automatically starts a new charging cycle. After the charge is done, toggle either CE pin or EN_CHG
bit can initiate a new charging cycle.
The status register (CHRG_STAT) indicates the different charging phases as:
•
•
•
•
•
•
•
000 – Not Charging
001 – Trickle Charge (VBAT < VBAT_SHORT
010 – Pre-charge (VBAT_SHORT < VBAT < VBAT_LOWV
011 – Fast-charge (CC mode)
100 – Taper Charge (CV mode)
101 – Top-off Timer Active Charging
110 – Charge Termination Done
)
)
When the charger transitions to any of these states, including when charge cycle is completed, an INT is
asserted to notify the host.
8.3.7.2 Battery Charging Profile
The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and
top-off trickle charging (optional). At the beginning of a charging cycle, the device checks the battery voltage and
regulates current/voltage accordingly.
表 6. Default Charging Current Setting
VBAT
< VBAT_SHORT
CHARGING CURRENT
IBAT_SHORT
REGISTER DEFAULT SETTING
CHRG_STAT
100 mA
150 mA
1500 mA
001
010
011
VBAT_SHORT to VBAT_LOWV
> VBAT_LOWV
IPRECHG
ICHG
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If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will
be less than the programmed value. In this case, termination is temporarily disabled and the charging safety
timer is counted at half the clock rate, as explained in the Charging Safety Timer section.
Regulation Voltage
VREG[7:0]
Battery Voltage
Charge Current
ICHG[5:0]
Charge Current
VBATLOWV
VBAT_SHORT
IPRECHG[3:0]
ITERM[3:0]
IBAT_SHORT
Trickle Charge
001
Pre-charge
010
Fast-Charge
CC
Taper-Charge
CV
Top-off Timer
(optional)
CHRG_STAT[2:0]
011
101
110
100
Precharge Timer
(2hrs)
Safety Timer
CHG_TIMER[1:0]
图 22. Battery Charging Profile
8.3.7.3 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
When termination occurs, the status register CHRG_STAT is set to 110, and an INT pulse is asserted to the
host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal
regulation. Termination can be permanently disabled by writing 0 to EN_TERM bit prior to charge termination.
At low termination currents (50 mA to100 mA), due to the comparator offset, the actual termination current may
be up to 40% higher than the termination target. In order to compensate for comparator offset, a programmable
top-off timer (default disabled) can be applied after termination is detected. The top-off timer will follow safety
timer constraints, such that if safety timer is suspended, so will the top-off timer. Similarly, if safety timer is
doubled, so will the top-off timer. CHRG_STAT reports whether the top off timer is active via the 101 code. Once
the Top-Off timer expires, the CHRG_STAT register is set to 110 and an INT pulse is asserted to the host.
Top-off timer gets reset (set to 0 and counting resumes when appropriate) for any of the following conditions:
1. Charge disable to enable
2. Termination status low to high
3. REG_RST register bit is set (disables top-off timer)
The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer
value after termination will have no effect until a new charge cycle is initiated. An INT is asserted to the host
when entering top-off timer segment as well as when top-off timer expires. All charge cycle related INT pulses
(including top-off timer INT pulses) can be masked by CHRG_MASK bit.
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8.3.7.4 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
8.3.7.4.1 JEITA Guideline Compliance in Charge Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range. At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge
current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1 V / cell.
The charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at
warm temperature (T3-T5) can be VREG, 8.0 V, 8.3 V, or charge suspend (configured by JEITA_VSET [1:0]).
The fast charge current setting at warm temperature (T3-T5) can be 100%, or 40% of fast charge current, ICHG
(configured by JEITA_ISETH). The fast charge current setting at cool temperature (T1-T2) can be 100%, 40%, or
20% of fast charge current, ICHG, or charge suspend (configured by JEITA_ISETC[1:0]). Whenever the charger
detects "warm" or "cool" temperature, TERMINATION is automatically disabled regardless of JEITA_VSET,
JEITA_ISETH and JEITA_ISETC register bit settings.
REGN
TS
BQ2588x
图 23. TS Resistor Network
ISETC=11
VSET =11
ISETH=1
100%
VREG
80%
60%
40%
20%
VSET =10
VSET = 01
8.3V
8.0V
ISETC=10
ISETC=01
ISETC=00
ISETH=0
VSET = 00
T1
0°C
T2
10°C
T3
45°C
T5
60°C
T1
0°C
T2
10°C
T3
45°C
T5
60°C
TS Temperature
TS Temperature
图 24. TS Charging Values
Assuming a 103AT NTC thermistor on the battery pack as shown above, the value of RT1 and RT2 can be
determined by:
1
1
≈
’
VREGN ì RTHCOLD ì RTHHOT
ì
-
∆
«
÷
◊
VT1 VT5
RT2 =
V
V
≈
≈
’
’
REGN
REGN
RTHHOT
ì
-1 - RTHCOLD
ì
-1
∆
«
÷
∆
÷
◊
VT5
VT1
◊
«
(1)
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VREGN
-1
VT1
RT1=
1
1
+
RT2 RTHCOLD
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
RTHT1 = 27.28 kΩ
RTHT5 = 3.02 kΩ
RT1 = 5.24 kΩ
RT2 = 30.31 kΩ
8.3.7.4.2 Cold/Hot Temperature Window in OTG Buck Mode
For battery protection during OTG buck mode, the device monitors the battery temperature to be within the
VBCOLD to VBHOT thresholds. When temperature is outside of the temperature thresholds, the OTG mode is
suspended. In addition, VBUS_STAT bits are set to 000 and corresponding TS_STAT is reported. Once
temperature returns within thresholds, the OTG mode is recovered and TS_STAT is cleared.
Temperature Range for OTG Buck Mode
VREGN
Buck Disable
VBCOLDx
(œ10°C / œ20°C)
Buck Enable
VBHOTx
(55°C / 60°C / 65°C)
Buck Disable
GND
图 25. TS Pin Thermistor Sense Threshold in OTG Buck Mode
8.3.7.5 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault
register TMR_STAT bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can be
disabled by clearing EN_TIMER bit.
During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge
current is likely to be below the register setting. For example, if the charger is in input current regulation
(IINDPM_STAT=1) throughout the whole charging cycle, and the safety timer is set to 5 hours, then the timer will
expire in 10 hours. This half clock rate feature can be disabled by setting TMR2X_EN = 0. Changing the
TMR2X_EN bit while the device is running has no effect on the safety timer count, other than forcing the timer to
count at half the rate under the conditions dictated above.
During faults which disable charging, or supplement mode, timer is suspended. Since the timer is not counting in
this state, the TMR2X_EN bit has no effect. Once the fault goes away, safety timer resumes. If the charging
cycle is stopped and started again, the timer gets reset (toggle CE pin or EN_CHG bit restarts the timer).
The safety timer is reset for the following events:
1. Charging cycle stop and restart (toggle CE pin, EN_CHG bit, or charged battery falls below recharge
threshold)
2. BAT voltage changes from pre-charge to fast-charge or vice versa (in host-mode or default mode)
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The precharge safety timer (fixed 2hr counter that runs when VBAT < VBAT_SHORT), follows the same rules as the
fast-charge safety timer in terms of getting suspended, reset, and counting at half-rate when TMR2X_EN is set.
8.3.8 Integrated 16-Bit ADC for Monitoring
The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of
operation. The control of the ADC is done through the ADC Control Register (Address = 15h) [reset = 30h]
register. The ADC_EN bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE
bit allows continuous conversion or one-shot behavior. After a 1-shot conversion finishes, the ADC_EN bit is
cleared, and must be re-asserted to start a new conversion.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the
VVBUS>VVBUS_UVLOZ or VBAT>VBAT_UVLOZ is valid. If no adapter is present, and the VBAT is less than VBAT_UVLOZ
,
the device will not perform an ADC measurement, nor update the ADC read-back values in REG17 through
REG24. Additionally, the device will immediately reset ADC_EN bit without sending any interrupt. The same will
happen if the ADC is enabled when all ADC channels are disabled. It is recommended to read back ADC_EN
after setting it to '1' to ensure ADC is running a conversion. If the charger changes mode (for example, if adapter
is connected, EN_HIZ goes to '1', or EN_OTG goes to '1') while an ADC conversion is running, the conversion is
interrupted. Once the mode change is complete, the ADC resumes conversion, starting with the channel where it
was interrupted.
The ADC_SAMPLE bits control the sample speed of the ADC, with conversion time of tADC_CONV. The integrated
ADC has two rate conversion options: a 1-shot mode and a continuous conversion mode set by the ADC_RATE
bit. By default, all ADC parameters will be converted in 1-shot or continuous conversion mode unless disabled in
the ADC Function Disable Register (Address = 16h) [reset = 00h]. If an ADC parameter is disabled by setting the
corresponding bit in REG16, then the read-back value in the corresponding register will be from the last valid
ADC conversion or the default POR value (all zeros if no conversions have taken place). If an ADC parameter is
disabled in the middle of an ADC measurement cycle, the device will finish the conversion of that parameter, but
will not convert the parameter starting the next conversion cycle. Even though no conversion takes place when
all ADC measurement parameters are disabled, the ADC circuitry is active and ready to begin conversion as
soon as one of the bits in the ADC Function Disable register is set to ‘0’. If all channels are disabled in 1-shot
conversion mode, the ADC_EN bit is cleared.
The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is complete in 1-shot mode only.
This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous
conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will
remain unchanged in continuous conversion mode.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set
ADC_EN = ‘0’ to disable the ADC. ADC conversion is interrupted upon adapter plug-in, and will only resume until
after Input Source Type Detection is complete. ADC readings are only valid for DC states and not for transients.
When host writes ADC_EN = 0, the ADC stops immediately, and ADC measurement values correspond to last
valid ADC reading.
If the host wants to exit ADC more gracefully, it is possible to do either of the following:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Disable all ADC conversion channels, and the ADC will stop at the end of the current measurement.
8.3.9 Status Outputs (PG, and INT)
8.3.9.1 Power Good Indicator (PG)
The PG_STAT bit goes HIGH and the PG pin goes LOW to indicate a good input source when:
1. VBUS above VVBUS_UVLOZ
2. VBUS below VVBUS_OV threshold
3. VBUS above VPOORSRC when IPOORSRC current is applied (not a poor source)
4. Input Source Type Detection is completed
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8.3.9.2 Interrupt to Host (INT)
In some applications, the host does not always monitor the charger operation. The INT pin notifies the system
host on the device operation. By default, the following events will generate an active-low, 256-µs INT pulse.
1. Good input source detected
–
–
VVBUS < VVBUS_OV threshold
VVBUS > VPOORSRC when IPOORSRC current is applied (not a poor source)
2. VBUS_STAT changes state (VBUS_STAT any bit change)
3. Good input source removed
4. Entering IINDPM regulation
5. Entering VINDPM regulation
6. Entering IC junction temperature regulation (TREG)
7. I2C Watchdog timer expired
–
At initial power up, this INT gets asserted to signal I2C is ready for communication
8. Charger status changes state (CHRG_STAT value change), including Charge Complete
9. TS_STAT changes state (TS_STAT any bit change)
10. VBUS overvoltage detected (VBUS_OVP)
11. Junction temperature shutdown (TSHUT)
12. Battery overvoltage detected (BATOVP)
13. Charge safety timer expired
14. A rising edge on any of the *_STAT bits
Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.
Three bits exist for each one of these events:
•
•
•
The STAT bit holds the current status of each INT source
The FLAG bit holds information on which source produced an INT, regardless of the current status
The MASK bit is used to prevent the device from sending out INT for each particular event
When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT
pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are
automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the
FLAG.
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IINDPM_STAT
IINDPM_FLAG
TREG_STAT
TREG_FLAG
INT
I2C Flag Read
图 26. INT Generation Behavior Example
8.3.10 Input Current Limit on ILIM Pin
For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current. The
maximum input current is set by a resistor from ILIM pin to ground as:
KILIM
=
I
INMAX
RILIM
(3)
The actual input current limit is the lower value between ILIM pin setting and register setting (IINDPM). For
example, if the register setting is 3.3 A (0x1C), and ILIM has a 820-Ω resistor to ground, the input current limit is
1.43 A (KILIM = 1170 max). ILIM pin can be used to set the input current limit rather than the register settings
when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters
input current regulation (refer to Dynamic Power Management section). Entering IINDPM through ILIM pin sets
the IINDPM_STAT and FLAG bits, and produces an interrupt to host. The interrupt can be masked via the
IINDPM_MASK bit.
The ILIM pin can also be used to monitor input current when EN_ILIM is set and the device is not in ILIM
regulation. The voltage on ILIM pin is proportional to the input current. ILIM can be used to monitor input current
with the following relationship:
K
ìV
ì0.8V
ILIM
ILIM
I
=
IN
R
ILIM
(4)
For example, if ILIM pin is set with 820-Ω resistor, and the ILIM voltage 0.5 V, the actual input current is 0.762 A
to 0.892 A (based on KILIM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage
floats above 0.8 V. If ILIM pin is shorted, the input current limit is set by the register.
The ILIM pin function can be disabled by setting the EN_ILIM bit to 0. When the pin is disabled, both input
current limit function and monitoring function are not available.
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8.3.11 Voltage and Current Monitoring
The device closely monitors the input and system voltage, as well as internal FET currents for safe boost and
buck mode operation.
8.3.11.1 Voltage and Current Monitoring in Boost Mode
8.3.11.1.1 Input Over-voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage exceeds VVBUS_OV, the
device stops switching immediately to protect the power FETs. During input over-voltage, an INT pulse is
asserted to signal the host, and the VBUS_OVP_STAT and VBUS_OVP_FLAG fault registers get set. The
device automatically starts switching again when the over-voltage condition goes away.
8.3.11.1.2 Input Under-Voltage Protection
The valid input voltage range for boost mode operation is VVBUS_OP. If VBUS voltage falls below VPOORSRC during
operation, the device stops switching. During input under-voltage, an INT pulse is asserted to signal the host,
and the PG_STAT bit gets cleared. The PG_FLAG bit will get set to signal this event. The device automatically
attempts to restart switching when the under-voltage condition goes away.
8.3.11.1.3 System Over-Voltage Protection
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above system regulation voltage.
Upon SYSOVP, converter stops immediately to clamp the overshoot.
8.3.11.1.4 System Over-Current Protection
The charger device continually monitors and compares VBUS to VSYS to protect against a system short-circuit
event. In the event that VSYS drops to within 250 mV of VBUS during operation, and the input current exceeds
IINDPM threshold, a short circuit event is flagged and the converter stops switching. The SYS_SHORT_FLAG bit
is set and an INT pulse is asserted to the host. The device attempts to recover from this condition automatically.
8.3.11.2 Voltage and Current Monitoring in OTG Buck Mode
The device closely monitors the VBUS voltage, as well as RBFET (Q1, QBLK) and LSFET (Q3, QLS) current to
ensure safe buck mode operation.
8.3.11.2.1 VBUS Over-Voltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device enters over-voltage
protection which stops switching, clears the EN_OTG bit and exits buck mode. During the over-voltage duration,
the OTG_STAT and OTG_FLAG bits are set high to indicate a fault in buck mode operation. An INT is also
asserted to the host.
8.3.11.2.2 VBUS Over-Current Protection
The device monitors output current to provide output short protection. The OTG buck mode has built-in constant
current regulation to allow OTG to adapt to various types of loads. If short circuit is detected on VBUS, the OTG
turns off and OTG is disabled with EN_OTG bit cleared. In addition OTG_STAT and OTG_FLAG bits are set high
to indicate the fault, and an INT is asserted to the host.
8.3.12 Thermal Regulation and Thermal Shutdown
8.3.12.1 Thermal Protection in Boost Mode
The device monitors internal junction temperature, TJ, to avoid overheating and limits the IC surface temperature
in boost mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits),
the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows optimization for
the system thermal performance.
During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers.
Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit
goes high, and an INT is asserted to the host.
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Additionally, the device has thermal shutdown to turn off the converter when IC surface temperature exceeds
TSHUT. The fault register bits TSHUT_STAT and TSHUT_FLAG are set and an INT pulse is asserted to the host.
The converter turns back on when IC temperature is below TSHUT_HYS
.
8.3.12.2 Thermal Protection in OTG Buck Mode
The device monitors the internal junction temperature to provide thermal shutdown during OTG buck mode.
When IC surface temperature exceeds TSHUT, the buck mode is disabled (converter is turned off) by setting
EN_OTG bit low. The fault register bits TSHUT_STAT and TSHUT_FLAG are set and an INT pulse is asserted
to the host. When IC surface temperature is below TSHUT_HYS (typ. 30°C), the host can set EN_OTG bit to '1' to
recover.
8.3.13 Battery Protection
8.3.13.1 Battery Overvoltage Protection (BATOVP)
The battery over-voltage limit is clamped at 4% above the battery regulation voltage while charging. When
battery overvoltage occurs, the charger device immediately disables charge. The fault register BATOVP_STAT
bit goes high and an INT pulse is asserted to signal the host.
8.3.13.2 Battery Over-Discharge Protection
When the battery is discharged below VBAT_UVLOZ, the BATFET is turned off to protect battery from over-
discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is
plugged in, the BATFET turns on. The battery is charged with IBAT_SHORT current when the VBAT < VBAT_SHORT, or
pre-charge current as set in IPRECHG registers when the battery voltage is between VBAT_SHORT and VBAT_LOWV
.
8.3.14 Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 0x6B, receiving control inputs from the master device like
micro-controller or digital signal processor through REG00 – REG25. Register read beyond REG25 (0x25),
returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits/s), and fast mode (up to 400
kbits/s). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be
connected to the positive supply voltage via a current source or pull-up resistor.
8.3.14.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data
bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of
data allowed
图 27. Bit Transfers on the I2C bus
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8.3.14.2 START and STOP Conditions
All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SCL
SDA
SCL
STOP (P)
图 28. START and STOP Conditions on the I2C Bus
START (S)
8.3.14.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most
Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, it can hold the SCL line low to force the master into a wait state (clock
stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL
line.
Acknowledgeme
nt signal from
Acknowledgement
signal from slave
receiver
MSB
SDA
1
2
7
8
9
1
2
8
9
SCL S or Sr
START or
P or Sr
ACK
ACK
STOP or
Repeate
d START
Repeated
START
图 29. Data Transfer on the I2C Bus
8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte
was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock
pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this 9th clock pulse.
A NACK is signaled when the SDA line remains HIGH during the 9th clock pulse. The master can then generate
either a STOP to abort the transfer or a repeated START to start a new transfer.
8.3.14.5 Slave Address and Data Direction Bit
After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
The device 7-bit address is defined as 1101 011' (0x6B) by default. The address bit arrangement is shown
below.
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Slave Address
1
1
0
1
0
1
1
R/W
图 30. 7-Bit Addressing (0x6B)
SDA
SCL
S
8
9
8
9
8
9
P
1-7
1-7
1-7
DATA
START
ADDRESS
R/W ACK
DATA
ACK
ACK
STOP
图 31. Complete Data Transfer on the I2C Bus
8.3.14.6 Single Write and Read
图 32. Single Write
图 33. Single Read
If the register address is not defined, the charger IC sends back NACK and returns to the idle state.
8.3.14.7 Multi-Write and Multi-Read
The charger device supports multi-read and multi-write of all registers.
图 34. Multi-Write
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图 35. Multi-Read
8.4 Device Functional Modes
8.4.1 Host Mode and Default Mode
The device is a host controlled charger, but it can operate in default mode without host management. In default
mode, the device can be used as an autonomous charger with no host or while host is in sleep mode. When the
charger is in default mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is LOW.
After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the
registers are in the default settings.
In default mode, the device keeps charging the battery with default 10-hour fast charging safety timer. At the end
of the 10-hour, the charging is stopped and the boost converter continues to operate to supply system load.
A write to any I2C register transitions the charger from default mode to host mode, and initiates the watchdog
timer. All the device parameters can be programmed by the host. To keep the device in host mode, the host has
to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set),
or disable watchdog timer by setting WATCHDOG bits = 00.
When the watchdog timer (WD_STAT bit = 1) is expired, the device returns to default mode and all registers are
reset to default values except as detailed in the Register Maps section.
POR
watchdog timer expired
Reset registers
I2C interface enabled
Host Mode
Start watchdog timer
Host programs registers
Y
I2C Write?
N
Default Mode
Reset watchdog timer
Reset selective registers
Y
N
WD_RST bit = 1?
N
N
Y
Y
I2C Write?
Watchdog Timer
Expired?
图 36. Watchdog Timer Flow Chart
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8.5 Register Maps
Default I2C Slave Address: 0x6B (1101 011B + R/W)
表 7. I2C Registers
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
Access Type
Acronym
REG00
REG01
REG02
REG03
REG04
REG05
REG06
REG07
REG08
REG09
REG0A
REG0h
REG0C
REG0D
REG0E
REG0F
REG10
REG11
REG12
REG13
REG14
REG15
REG16
REG17
REG18
REG19
REG1A
REG1B
REG1C
REG1D
REG1E
REG1F
REG20
REG21
REG22
REG23
REG24
REG25
Register Name
Section
Go
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Battery Voltage Limit
Charge Current Limit
Input Voltage Limit
Input Current Limit
Go
Go
Go
Precharge and Termination Control
Charger Control 1
Charger Control 2
Charger Control 3
Charger Control 4
OTG Control
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
ICO Current Limit
Charger Status 1
Charger Status 2
NTC Status
R
R
R
R
FAULT Status
Charger Flag 1
Charger Flag 2
Fault Flag
R
R
R
R/W
R/W
R/W
R/W
R/W
R
Charger Mask 1
Charger Mask 2
Fault Mask
ADC Control
ADC Function Disable
IBUS ADC1
R
IBUS ADC0
R
ICHG ADC1
R
ICHG ADC0
R
VBUS ADC1
R
VBUS ADC0
R
VBAT ADC1
R
VBAT ADC0
R
VSYS ADC1
R
VSYS ADC0
R
TS ADC1
R
TS ADC0
R
TDIE ADC1
R
TDIE ADC0
R/W
Part Information
Complex bit access types are encoded to fit into small table cells. 表 8 shows the codes that are used for access
types in this section.
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表 8. I2C Access Type Codes
ACCESS TYPE CODE
Read Type
DESCRIPTION
R
R
Read
Write Type
W
W
Write
Reset Value
-n
Value after reset
Undefined value
-X
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8.5.1 Battery Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
REG00 is shown in 图 37 and described in 表 9.
Return to Summary Table.
图 37. REG00 Register
Bit
7
1
6
0
5
1
4
0
3
0
2
0
1
0
0
0
Reset
Field
VREG[7:0]
表 9. REG00 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VREG[7]
VREG[6]
VREG[5]
VREG[4]
VREG[3]
VREG[2]
VREG[1]
VREG[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1280 mV
640 mV
320 mV
160 mV
80 mV
Charge voltage limit
Offset: 6.80 V
Range: 6.80 V to 9.20 V
Default 8.40 V
Yes
Yes
Yes
Yes
Yes
40 mV
Yes
20 mV
Yes
10 mV
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8.5.2 Charger Current Limit Register (Address = 01h) [reset = 54h]
REG01 is shown in 图 38 and described in 表 10.
Return to Summary Table.
图 38. REG01 Register
Bit
7
0
6
1
5
0
4
1
3
0
2
1
1
0
0
0
Reset
Field
EN_HIZ
EN_ILIM
ICHG[5:0]
表 10. REG01 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_HIZ
R/W
Yes
Yes
Enable HIZ Mode:
0 – Disable (default)
1 – Enable
6
EN_ILIM
R/W
Yes
Yes
Enable ILIM Pin Function:
0 – Disable
1 – Enable (default)
5
4
3
2
1
0
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
ICHG[1]
ICHG[0]
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1600 mA
800 mA
400 mA
200 mA
100 mA
50 mA
Fast Charge Current Limit
Offset: 0 mA
Range: 100 mA – 2200 mA
Default: 1000 mA
Note: ICHG > 2.2 A (2Ch) clamped to 2.2 A. ICHG < 100 mA (01h)
clamped at 100 mA
38
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8.5.3 Input Voltage Limit Register (Address = 02h) [reset = 85h]
REG02 is shown in 图 39 and described in 表 11.
Return to Summary Table.
图 39. REG02 Register
Bit
7
1
6
0
5
4
0
3
0
2
1
0
0
1
Reset
Field
0
1
EN_VINDPM_
RST
EN_BAT_
DISCHG
PFM_OOA_DIS
VINDPM[4:0]
表 11. REG02 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_VINDPM_RST
R/W
Yes
Yes
Enable VINDPM automatic reset upon adapter plugin:
0 – Disable VINDPM reset when adapter is plugged in
1 – Enable VINDPM reset when adapter is plugged in (VINDPM resets to default
value after Input Source Type Detection)
6
5
EN_BAT_DISCHG
PFM_OOA_DIS
R/W
R/W
Yes
Yes
Yes
No
Enable BAT pin discharge load (IBAT_DISCHG):
0 – Disable load (Default)
1 – Enable BAT discharge load
PFM Out-of-Audio (OOA) Mode Disable:
0 – Out-of-audio mode enabled while in converter is in PFM (Default)
1 – Out-of-audio mode disabled while in converter is in PFM
4
3
2
1
0
VINDPM[4]
VINDPM[3]
VINDPM[2]
VINDPM[1]
VINDPM[0]
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
1600 mV
800 mV
400 mV
200 mV
100 mV
Absolute Input Voltage Limit:
Offset: 3.9 V
Range: 3.9 V – 5.5 V
Default: 4.4 V
Note: VINDPM > 5.5 V (10h) clamped to 5.5 V. VINDPM register is
reset upon adapter plug-in if EN_VINDPM_RST = 1.
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8.5.4 Input Current Limit Register (Address = 03h) [reset = 39h]
REG03 is shown in 图 40 and described in 表 12.
Return to Summary Table.
图 40. REG03 Register
Bit
7
6
5
1
4
1
3
1
2
1
0
0
1
Reset
Field
0
0
0
FORCE_ICO
FORCE_INDET
EN_ICO
IINDPM[4:0]
表 12. REG03 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
FORCE_ICO
R/W
Yes
Yes
Force Start Input Current Optimizer (ICO):
0 – Do not force ICO (default)
1 – Force ICO start
Note: This bit can only be set and always returns 0 after ICO starts. This bit only
valid when EN_ICO = 1
6
5
FORCE_INDET
EN_ICO
R/W
R/W
Yes
Yes
Yes
No
Force D+/D– Detection:
0 – Not in D+/D– detection (default)
1 – Force D+/D– detection
Input Current Optimization (ICO) Algorithm Control:
0 – Disable ICO
1 – Enable ICO (default)
4
3
2
1
0
IINDPM[4]
IINDPM[3]
IINDPM[2]
IINDPM[1]
IINDPM[0]
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
1600 mA
800 mA
400 mA
200 mA
100 mA
Input Current Limit:
Offset: 500 mA
Range: 500 mA – 3300 mA
Default: 3000 mA
Note: IINDPM > 3300 mA (1Ch) clamped to 3300 mA. Actual input
current limit is lower of I2C or ILIM pin.
40
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8.5.5 Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
REG04 is shown in 图 41 and described in 表 13.
Return to Summary Table.
图 41. REG04 Register
Bit
7
0
6
0
5
1
4
0
3
0
2
0
1
1
0
0
Reset
Field
IPRECHG[3:0]
ITERM[3:0]
表 13. REG04 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IPRECHG[3]
IPRECHG[2]
IPRECHG[1]
IPRECHG[0]
ITERM[3]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
400 mA
200 mA
100 mA
50 mA
Precharge Current Limit:
Offset: 50 mA
Range: 50 mA – 800 mA
Default: 150 mA
Yes
Yes
Yes
Yes
400 mA
200 mA
100 mA
50 mA
Termination Current Limit:
Offset: 50 mA
Range: 50 mA – 800 mA
Default: 150 mA
ITERM[2]
Yes
ITERM[1]
Yes
ITERM[0]
Yes
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8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Dh]
REG05 is shown in 图 42 and described in 表 14.
Return to Summary Table.
图 42. REG05 Register
Bit
7
1
6
5
0
4
1
3
2
1
1
0
0
Reset
Field
0
1
1
EN_TERM
RESERVED
WATCHDOG[1:0]
EN_TIMER
CHG_TIMER[1:0]
TMR2X_EN
表 14. REG05 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_TERM
R/W
Yes
Yes
Termination Control:
0 – Disable termination
1 – Enable termination (default)
6
5
4
RESERVED
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Reserved bit always reads 0
WATCHDOG[1]
WATCHDOG[0]
I2C Watchdog Timer Settings:
00 – Disable WD Timer
01 – 40s (default)
10 – 80s
11 – 160s
3
EN_TIMER
R/W
Yes
Yes
Charging Safety Timer Enable
0 – Disable
1 – Enable (Default)
2
1
CHG_TIMER[1]
CHG_TIMER[0]
R/W
R/W
Yes
Yes
Yes
Yes
Fast Charge Timer Setting
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (Default)
11 – 20 hrs
0
TMR2X_EN
R/W
Yes
Yes
Safety Timer during DPM or TREG
0 – Safety timer always count normally
1 – Safety timer slowed by 2X during input DPM or TREG (Default)
System Note: When the WATCHDOG bits are changed (writing the same value does not change WATCHDOG
bit), the internal counter is reset. The same applies for the CHG_TIMER bits. Only changing the value in the
register will reset the CHG_TIMER
42
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8.5.7 Charger Control 2 Register (Address = 06h) [reset = 7Dh]
REG06 is shown in 图 43 and described in 表 15.
Return to Summary Table.
图 43. REG06 Register
Bit
7
0
6
1
5
1
4
1
3
1
2
1
1
0
0
1
Reset
Field
EN_OTG
AUTO_INDET_
EN
TREG[1:0]
EN_CHG
BATLOWV
VRECHG[1:0]
表 15. REG06 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
EN_OTG
R/W
Yes
Yes
Buck (OTG) Mode control:
0 – Disable OTG (default)
1 – Enable OTG
Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority
6
AUTO_INDET_EN
R/W
Yes
Yes
Automatic Input Source Detection Enable:
0 – Disable D+/D– detection when VBUS plugs in
1 – Enable D+/D– detection when VBUS plugs in (default)
5
4
TREG[1]
TREG[0]
R/W
R/W
Yes
Yes
Yes
Yes
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (Default)
3
2
EN_CHG
R/W
R/W
Yes
Yes
Yes
Yes
Charger Enable Configuration
0 – Charge Disable
1 – Charge Enable (default)
Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority
BATLOWV
Battery precharge to fast-charge threshold:
0 – 5.6 V
1 – 6.0 V (default)
1
0
VRECHG[1]
VRECHG[0]
R/W
R/W
Yes
Yes
No
No
200 mV
100 mV
Battery Recharge Threshold Offset (below VREG):
Offset: 100 mV
Range: 100 mV – 400 mV
Default: 200 mV
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8.5.8 Charger Control 3 Register (Address = 07h) [reset = 0Ah]
REG07 is shown in 图 44 and described in 表 16.
Return to Summary Table.
图 44. REG07 Register
Bit
7
0
6
0
5
0
4
0
3
1
2
0
1
1
0
0
Reset
Field
PFM_DIS
WD_RST
TOPOFF_TIMER[1:0]
SYS_MIN[3:0]
表 16. REG07 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PFM_DIS
R/W
Yes
No
PFM Mode Disable control:
0 – Enable PFM operation (default)
1 – Disable PFM operation
6
WD_RST
R/W
Yes
Yes
I2C Watchdog Timer Reset:
0 – Normal
1 – Reset (Bit goes back to 0 after timer reset)
5
4
TOPOFF_TIMER[1]
TOPOFF_TIMER[0]
R/W
R/W
Yes
Yes
Yes
Yes
Top-off Timer Control :
00 – Disabled (default)
01 – 15 mins
10 – 30 mins
11 – 45 mins
3
2
1
0
SYS_MIN[3]
SYS_MIN[2]
SYS_MIN[2]
SYS_MIN[0]
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
No
No
No
No
800 mV
400 mV
200 mV
100 mV
Minimum System Voltage Limit
Offset: 6.0 V
Range: 6.0 V – 7.5 V
Default: 7.0 V
44
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8.5.9 Charger Control 4 Register (Address = 08h) [reset = 0Dh]
REG08 is shown in 图 45 and described in 表 17.
Return to Summary Table.
图 45. REG08 Register
Bit
7
0
6
0
5
0
4
0
3
1
2
1
0
0
1
Reset
Field
1
BHOT[1:0]
BCOLD
JEITA_VSET[1:0]
JEITA_ISETH
JEITA_ISETC[1:0]
表 17. REG08 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
BHOT[1]
BHOT[0]
R/W
R/W
Yes
Yes
Yes
OTG Mode TS HOT Temperature Threshold:
00 – VBHOT1 threshold (34.75%) (default)
01 – VBHOT0 threshold (37.75%)
Yes
10 – VBHOT2 threshold (31.25%)
11 – Disable OTG mode thermal protection
5
BCOLD
R/W
Yes
Yes
OTG Mode TS COLD Temperature Threshold:
0 – VBCOLD0 threshold (77%) (default)
1 – VBCOLD1 threshold (80%)
4
3
JEITA_VSET[1]
JEITA_VSET[0]
R/W
R/W
Yes
Yes
Yes
Yes
JEITA High Temp. (45°C – 60°C) Voltage Setting:
00 – Charge Suspend
01 – Set VREG to 8.0 V (default)
10 – Set VREG to 8.3 V
11 – VREG unchanged
2
JEITA_ISETH
R/W
Yes
Yes
JEITA High Temp. (45°C – 60°C) Current Setting (percentage with respect to
ICHG REG01[5:0]):
0 – 40% of ICHG
1 – 100% of ICHG (default)
1
0
JEITA_ISETC[1]
JEITA_ISETC[0]
R/W
R/W
Yes
Yes
Yes
Yes
JEITA Low Temp. (0°C – 10°C) Current Setting (percentage with respect to
ICHG REG01[5:0]):
00 – Charge Suspend
01 – 20% of ICHG (default)
10 – 40% of ICHG
11 – 100% of ICHG
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8.5.10 OTG Control Register (Address = 09h) [reset = F6h]
REG09 is shown in 图 46 and described in 表 18.
Return to Summary Table.
图 46. REG09 Register
Bit
7
1
6
1
5
1
4
1
3
0
2
1
1
1
0
0
Reset
Field
OTG_ILIM[3:0]
OTG_VLIM[3:0]
表 18. REG09 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
OTG_ILIM[3]
OTG_ILIM[2]
OTG_ILIM[1]
OTG_ILIM[0]
OTG_VLIM[3]
OTG_VLIM[2]
OTG_VLIM[1]
OTG_VLIM[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
800 mA
400 mA
200 mA
100 mA
800 mV
400 mV
200 mV
100 mV
Buck (OTG) Mode Current Limit:
Offset: 0.5 A
Range: 0.5 A – 2.0 A
Default: 2 A
Yes
Yes
Yes
Yes
Buck (OTG) Mode Regulation Voltage:
Offset: 4.5 V
Range: 4.5 V – 5.5 V
Default: 5.1 V
Yes
Yes
Note: Values above 5.5 V (Ah) will be clamped to 5.5 V
Yes
46
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8.5.11 ICO Current Limit Register (Address = 0Ah) [reset = XXh]
REG0A is shown in 图 47 and described in 表 19.
Return to Summary Table.
图 47. REG0A Register
Bit
7
6
5
4
3
2
1
0
Reset
Field
0
0
0
X
X
X
X
X
RESERVED
RESERVED
RESERVED
ICO_ILIM[4:0]
表 19. REG0A Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
ICO_ILIM[4]
ICO_ILIM[3]
ICO_ILIM[2]
ICO_ILIM[1]
ICO_ILIM[0]
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
No
No
No
No
No
No
No
1600 mA
800 mA
400 mA
200 mA
100 mA
Input Current Limit when ICO is enabled:
Offset: 500 mA
Range: 500 mA – 3300 mA
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8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
REG0B is shown in 图 48 and described in 表 20.
Return to Summary Table.
图 48. REG0B Register
Bit
7
6
5
4
3
X
2
1
0
Reset
Field
X
X
X
X
X
X
X
ADC_DONE_
STAT
IINDPM_STAT VINDPM_STAT
TREG_STAT
WD_STAT
CHRG_STAT[2:0]
表 20. REG0B Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
ADC_DONE_STAT
R
No
No
ADC Conversion Status (in one-shot mode only):
0 – Conversion not complete
1 – Conversion complete
Note: Always reads 0 in continuous mode
6
5
4
3
IINDPM_STAT
VINDPM_STAT
TREG_STAT
WD_STAT
R
R
R
R
No
No
No
No
No
No
No
No
IINDPM Status:
0 – Normal
1 – In IINDPM Regulation (ILIM pin or IINDPM register)
VINDPM Status:
0 – Normal
1 – In VINDPM Regulation
IC Thermal regulation Status:
0 – Normal
1 – In Thermal Regulation
I2C Watchdog Timer Status bit:
0 – Normal
1 – WD Timer expired
2
1
0
CHRG_STAT[2]
CHRG_STAT[1]
CHRG_STAT[0]
R
R
R
No
No
No
No
No
No
Charge Status bits:
000 – Not Charging
001 – Trickle Charge (VBAT < VBAT_SHORT)
010 – Pre-charge (VBAT_SHORT < VBAT < VBAT_LOWV)
011 – Fast-charge (CC mode)
100 – Taper Charge (CV mode)
101 – Top-off Timer Charging
110 – Charge Termination Done
111 – Reserved
48
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8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
REG0C is shown in 图 49 and described in 表 21.
Return to Summary Table.
图 49. REG0C Register
Bit
7
X
6
5
4
3
2
1
0
Reset
Field
X
X
X
0
X
X
X
PG_STAT
VBUS_STAT[2:0]
RESERVED
ICO_STAT[1]
ICO_STAT[0]
VSYS_STAT
表 21. REG0C Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_STAT
R
No
No
Power Good Status:
0 – Not Power Good
1 – Power Good
6
5
4
VBUS_STAT[2]
VBUS_STAT[1]
VBUS_STAT[0]
R
R
R
No
No
No
No
No
No
VBUS Detection Status
000 – No Input
001 – USB Host SDP
010 – USB CDP (1.5 A)
011 – USB DCP (3.0 A)
100 – POORSRC detected 7 consecutive times
101 – Unknown Adapter (500 mA)
110 – Non-standard Adapter (1 A/2 A/2.1 A/2.4 A)
111 – OTG
3
2
1
RESERVED
ICO_STAT[1]
ICO_STAT[0]
R
R
R
No
No
No
No
No
No
Reserved bit always reads 0
Input Current Optimizer (ICO) Status:
00 – ICO Disabled
01 – ICO Optimization is in progress
10 – Maximum input current detected
11 – Reserved
0
VSYS_STAT
R
No
No
VSYS Regulation Status:
0 – Not in SYS_MIN regulation (BAT > VSYS_MIN)
1 – In SYS_MIN regulation (BAT < VSYS_MIN)
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8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
REG0D is shown in 图 50 and described in 表 22.
Return to Summary Table.
图 50. REG0D Register
Bit
7
6
5
4
3
2
1
0
Reset
Field
0
0
0
0
0
X
X
X
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TS_STAT[2:0]
表 22. REG0D Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TS_STAT[2]
TS_STAT[1]
TS_STAT[0]
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
No
No
No
No
No
No
No
NTC (TS) Status:
000 – Normal
010 – TS Warm
011 – TS Cool
101 – TS Cold
110 – TS Hot
50
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8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
REG0E is shown in 图 51 and described in 表 23.
Return to Summary Table.
图 51. REG0E Register
Bit
7
6
5
4
X
3
2
1
0
Reset
Field
X
X
X
0
0
0
0
VBUS_OVP_
STAT
TSHUT_STAT BATOVP_STAT
TMR_STAT
RESERVED
RESERVED
RESERVED
RESERVED
表 23. REG0E Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_STAT
TSHUT_STAT
BATOVP_STAT
TMR_STAT
R
No
No
No
No
No
Input overvoltage Status:
0 – Normal
1 – Device in overvoltage protection
6
5
4
R
R
R
No
No
No
IC Temperature shutdown Status:
0 – Normal
1 – Device in thermal shutdown protection
Battery over-voltage Status:
0 – Normal
1 – BATOVP (VBAT > VBATOVP)
Charge Safety timer Status:
0 – Normal
1 – Charge Safety timer expired
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R
R
R
R
No
No
No
No
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
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8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
REG0F is shown in 图 52 and described in 表 24.
Return to Summary Table.
图 52. REG0F Register
Bit
7
0
6
0
5
0
4
3
0
2
1
0
Reset
Field
0
0
0
0
ADC_DONE_
FLAG
IINDPM_FLAG VINDPM_FLAG
TREG_FLAG
WD_FLAG
RESERVED
RESERVED
CHRG_FLAG
表 24. REG0F Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
ADC_DONE_FLAG
R
Yes
No
ADC Conversion Flag (only 1-shot mode):
0 – Conversion not complete
1 – Conversion complete
Note: Always reads 0 in continuos mode
6
5
4
3
IINDPM_FLAG
VINDPM_FLAG
TREG_FLAG
WD_FLAG
R
R
R
R
Yes
Yes
Yes
Yes
No
No
No
No
IINDPM Regulation INT Flag:
0 – Normal
1 – IINDPM signal rising edge detected
VINDPM regulation INT Flag:
0 – Normal
1 – VINDPM signal rising edge detected
IC Temperature Regulation INT Flag:
0 – Normal
1 – TREG signal rising edge detected
I2C Watchdog INT Flag:
0 – Normal
1 – WD_STAT signal rising edge detected
2
1
0
RESERVED
RESERVED
CHRG_FLAG
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Charge Status INT Flag:
0 – Normal
1 – CHRG_STAT[2:0] bits changed (transition to any state)
52
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8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
REG10 is shown in 图 53 and described in 表 25.
Return to Summary Table.
图 53. REG10 Register
Bit
7
0
6
5
4
3
2
0
1
0
Reset
Field
0
0
0
0
0
0
PG_FLAG
RESERVED
RESERVED
VBUS_FLAG
RESERVED
TS_FLAG
ICO_FLAG
VSYS_FLAG
表 25. REG10 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_FLAG
R
Yes
No
Power Good INT Flag:
0 – Normal
1 – PG signal toggle detected
6
5
4
RESERVED
RESERVED
VBUS_FLAG
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
VBUS Status INT Flag:
0 – Normal
1 – VBUS_STAT[2:0] bits changed (transition to any state)
3
2
RESERVED
TS_FLAG
R
R
Yes
Yes
No
No
Reserved bit always reads 0
TS Status INT Flag:
0 – Normal
1 – TS_STAT[2:0] bits changed (transition to any state)
1
0
ICO_FLAG
R
R
Yes
Yes
No
No
Input Current Optimizer (ICO) INT Flag:
0 – Normal
1 – ICO_STAT[1:0] changed (transition to any state)
VSYS_FLAG
VSYS Regulation INT Flag:
0 – Normal
1 – Entered or exited SYS_MIN regulation
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8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
REG11 is shown in 图 54 and described in 表 26.
Return to Summary Table.
图 54. REG11 Register
Bit
7
0
6
0
5
0
4
3
0
2
1
0
Reset
Field
0
0
0
0
VBUS_OVP_
FLAG
TSHUT_FLAG BATOVP_FLAG
TMR_FLAG
SYS_SHORT_
FLAG
RESERVED
RESERVED
OTG_FLAG
表 26. REG11 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_FLAG
R
Yes
No
No
No
No
No
Input over-voltage INT Flag:
0 – Normal
1 – Entered VBUS_OVP Fault
6
5
4
3
TSHUT_FLAG
R
R
R
R
Yes
Yes
Yes
Yes
IC Temperature shutdown INT Flag:
0 – Normal
1 – Entered TSHUT Fault
BATOVP_FLAG
TMR_FLAG
Battery over-voltage INT Flag:
0 – Normal
1 – Entered BATOVP Fault
Charge Safety timer Fault INT Flag:
0 – Normal
1 – Charge Safety timer expired rising edge detected
SYS_SHORT_FLAG
System Short INT Flag:
0 – Normal
1 – Stopped switching due to boost converter overload
2
1
0
RESERVED
RESERVED
OTG_FLAG
R
R
R
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
OTG Buck Mode Fault INT Flag:
0 – Normal
1 – VBUS overloaded in OTG, or VBUS OVP, or battery below VOTG_BAT
54
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8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
REG12 is shown in 图 55 and described in 表 27.
Return to Summary Table.
图 55. REG12 Register
Bit
7
0
6
0
5
0
4
0
3
2
1
0
Reset
Field
0
0
0
0
ADC_DONE_
MASK
IINDPM_MASK VINDPM_MASK TREG_MASK
WD_MASK
RESERVED
RESERVED
CHRG_MASK
表 27. REG12 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
ADC_DONE_MASK
IINDPM_MASK
VINDPM_MASK
TREG_MASK
R/W
Yes
No
No
No
No
No
ADC Conversion INT Mask Flag (only 1-shot mode)
0 – ADC_DONE does produce INT pulse
1 – ADC_DONE does produce not INT pulse
6
5
4
3
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
IINDPM Regulation INT Mask
0 – IINDPM entry produces INT pulse
1 – IINDPM entry does not produce INT pulse
VINDPM Regulation INT Mask
0 – VINDPM entry produces INT pulse
1 – VINDPM entry not produce INT pulse
IC Temperature Regulation INT Mask
0 – TREG entry produces INT pulse
1 – TREG entry produce INT pulse
WD_MASK
I2C Watchdog Timer INT Mask
0 – WD_STAT rising edge produces INT pulse
1 – WD_STAT rising edge does not produce INT
2
1
0
RESERVED
RESERVED
CHRG_MASK
R/W
R/W
R/W
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Charge Status INT Mask
0 – CHRG_STAT[2:0] bit change produces INT
1 – CHRG_STAT[2:0] bit change does not produce INT pulse
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8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
REG13 is shown in 图 56 and described in 表 28.
Return to Summary Table.
图 56. REG13 Register
Bit
7
0
6
5
4
3
2
0
1
0
Reset
Field
0
0
0
0
0
0
PG_MASK
RESERVED
RESERVED
VBUS_MASK
RESERVED
TS_MASK
ICO_MASK
VSYS_MASK
表 28. REG13 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
PG_MASK
R/W
Yes
No
Power Good INT Mask:
0 – PG toggle produces INT pulse
1 – PG toggle does not produce INT pulse
6
5
4
RESERVED
RESERVED
VBUS_MASK
R/W
R/W
R/W
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
VBUS Status INT Mask:
0 – VBUS_STAT[2:0] bit change produces INT
1 – VBUS_STAT[2:0] bit change does not produces INT
3
2
RESERVED
TS_MASK
R/W
R/W
Yes
Yes
No
No
Reserved bit always reads 0
TS Status INT Mask:
0 – TS_STAT[2:0] bit change produces INT
1 – TS_STAT[2:0] bit change does not produces INT pulse
1
0
ICO_MASK
R/W
R/W
Yes
Yes
No
No
Input Current Optimizer (ICO) INT Mask:
0 – ICO_STAT rising edge produces INT
1 – ICO_STAT rising edge does not produce INT
VSYS_MASK
VSYS Regulation INT Mask:
0 – Entering or exiting SYS_MIN produces INT
1 – Entering or exiting SYS_MIN does not produce INT
56
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8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
REG14 is shown in 图 57 and described in 表 29.
Return to Summary Table.
图 57. REG14 Register
Bit
7
0
6
0
5
0
4
3
0
2
1
0
Reset
Field
0
0
0
0
VBUS_OVP_
MASK
TSHUT_MASK BATOVP_MAS
K
TMR_MASK
SYS_SHORT_
MASK
RESERVED
RESERVED
OTG_MASK
表 29. REG14 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
VBUS_OVP_MASK
R/W
Yes
No
No
No
No
No
Input over-voltage INT Mask:
0 – VBUS_OVP rising edge produces INT pulse
1 – VBUS_OVP rising edge does not produce INT pulse
6
5
4
3
TSHUT_MASK
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Thermal Shutdown INT Mask:
0 – TSHUT rising edge produces INT pulse
1 – TSHUT rising edge does not produce INT pulse
BATOVP_MASK
TMR_MASK
Battery overvoltage INT Mask:
0 – BATOVP rising edge produces INT pulse
1 – BATOVP rising edge does not produce INT pulse
Charge Safety Timer Fault INT Mask:
0 – Timer expired rising edge produces INT pulse
1 – Timer expired rising edge does not produce INT pulse
SYS_SHORT_MASK
System Short Fault INT Mask:
0 – System short rising edge produces INT pulse
1 – System short rising edge does not produce INT pulse
2
1
0
RESERVED
RESERVED
OTG_MASK
R/W
R/W
R/W
Yes
Yes
Yes
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
OTG Buck Mode Fault INT Mask:
0 – OTG_STAT event produces INT
1 – OTG_STAT event does not produce INT
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8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
REG15 is shown in 图 58 and described in 表 30.
Return to Summary Table.
图 58. REG15 Register
Bit
7
0
6
5
1
4
1
3
2
1
0
Reset
Field
0
0
0
0
0
ADC_EN
ADC_RATE
ADC_SAMPLE[1:0]
RESERVED
RESERVED
RESERVED
RESERVED
表 30. REG15 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
ADC_EN
R/W
Yes
Yes
ADC Control:
0 – Disable ADC (default)
1 – Enable ADC
6
ADC_RATE
R/W
Yes
No
0 – Continuous conversion (default)
1 – One-shot conversion
5
4
ADC_SAMPLE[1]
ADC_SAMPLE[0]
R/W
R/W
Yes
Yes
No
No
Sample Speed of ADC:
00 – 15-bit effective resolution
01 – 14-bit effective resolution
10 – 13-bit effective resolution
11 – 12-bit effective resolution (default)
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
No
No
No
No
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
Reserved bit always reads 0
58
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8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
REG16 is shown in 图 59 and described in 表 31.
Return to Summary Table.
图 59. REG16 Register
Bit
7
6
0
5
0
4
0
3
0
2
1
0
Reset
Field
0
0
0
0
IBUS_ADC_DIS
ICHG_ADC_
DIS
VBUS_ADC_
DIS
VBAT_ADC_
DIS
VSYS_ADC_
DIS
TS_ADC_DIS
RESERVED
TDIE_ADC_DIS
表 31. REG16 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
IBUS_ADC_DIS
ICHG_ADC_DIS
VBUS_ADC_DIS
VBAT_ADC_DIS
VSYS_ADC_DIS
TS_ADC_DIS
R/W
R/W
R/W
R/W
R/W
R/W
Yes
No
No
No
No
No
No
0 – Enable conversion
1 – Disable conversion
Yes
Yes
Yes
Yes
Yes
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
0 – Enable conversion
1 – Disable conversion
1
0
RESERVED
R/W
R/W
Yes
Yes
No
No
Reserved bit always reads 0
TDIE_ADC_DIS
0 – Enable conversion
1 – Disable conversion
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8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
REG17 is shown in 图 60 and described in 表 32.
Return to Summary Table.
图 60. REG17 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
IBUS_ADC[15:8]
表 32. REG17 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IBUS_ADC[15]
IBUS_ADC[14]
IBUS_ADC[13]
IBUS_ADC[12]
IBUS_ADC[11]
IBUS_ADC[10]
IBUS_ADC[9]
IBUS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
Yes
16384 mA
8192 mA
4096 mA
Yes
Yes
Yes
2048 mA
1024 mA
512 mA
256 mA
VBUS Current Reading (positive current flows into VBUS pin,
negative current flows out ot VBUS pin):
Range: 0 A – 4 A
Yes
Yes
Yes
8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
REG18 is shown in 图 61 and described in 表 33.
Return to Summary Table.
图 61. REG18 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
IBUS_ADC[7:0]
表 33. REG18 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
IBUS_ADC[7]
IBUS_ADC[6]
IBUS_ADC[5]
IBUS_ADC[4]
IBUS_ADC[3]
IBUS_ADC[2]
IBUS_ADC[1]
IBUS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mA
64 mA
32 mA
16 mA
8 mA
VBUS Current Reading (positive current flows into VBUS pin,
negative current flows out ot VBUS pin):
Range: 0 A – 4 A
Yes
Yes
Yes
Yes
Yes
4 mA
Yes
2 mA
Yes
1 mA
60
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8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
REG19 is shown in 图 62 and described in 表 34.
Return to Summary Table.
图 62. REG19 Register
Bit
7
6
0
5
0
4
0
3
2
0
1
0
0
0
Reset
Field
0
0
RESERVED
ICHG_ADC[14:8]
表 34. REG19 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Reserved register always reads 0.
ICHG_ADC[14]
ICHG_ADC[13]
ICHG_ADC[12]
ICHG_ADC[11]
ICHG_ADC[10]
ICHG_ADC[9]
ICHG_ADC[8]
Yes
16384 mA
8192 mA
4096 mA
Yes
Yes
Yes
2048 mA
1024 mA
512 mA
256 mA
Charge Current Reading:
Range: 0 A – 4 A
Yes
Yes
Yes
8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
REG1A is shown in 图 63 and described in 表 35.
Return to Summary Table.
图 63. REG1A Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
ICHG_ADC[7:0]
表 35. REG1A Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
ICHG_ADC[7]
ICHG_ADC[6]
ICHG_ADC[5]
ICHG_ADC[4]
ICHG_ADC[3]
ICHG_ADC[2]
ICHG_ADC[1]
ICHG_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mA
64 mA
32 mA
16 mA
8 mA
Charge Current Reading:
Range: 0 A – 4 A
Yes
Yes
Yes
Yes
Yes
4 mA
Yes
2 mA
Yes
1 mA
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8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
REG1B is shown in 图 64 and described in 表 36.
Return to Summary Table.
图 64. REG1B Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBUS_ADC[15:8]
表 36. REG1B Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBUS_ADC[15]
VBUS_ADC[14]
VBUS_ADC[13]
VBUS_ADC[12]
VBUS_ADC[11]
VBUS_ADC[10]
VBUS_ADC[9]
VBUS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
VBUS Voltage reading
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
REG1C is shown in 图 65 and described in 表 37.
Return to Summary Table.
图 65. REG1C Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBUS_ADC[7:0]
表 37. REG1C Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBUS_ADC[7]
VBUS_ADC[6]
VBUS_ADC[5]
VBUS_ADC[4]
VBUS_ADC[3]
VBUS_ADC[2]
VBUS_ADC[1]
VBUS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VBUS Voltage Reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
62
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8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
REG1D is shown in 图 66 and described in 表 38.
Return to Summary Table.
图 66. REG1D Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBAT_ADC[15:8]
表 38. REG1D Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBAT_ADC[15]
VBAT_ADC[14]
VBAT_ADC[13]
VBAT_ADC[12]
VBAT_ADC[11]
VBAT_ADC[10]
VBAT_ADC[9]
VBAT_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
VBAT Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
REG1E is shown in 图 67 and described in 表 39.
Return to Summary Table.
图 67. REG1E Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VBAT_ADC[7:0]
表 39. REG1E Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VBAT_ADC[7]
VBAT_ADC[6]
VBAT_ADC[5]
VBAT_ADC[4]
VBAT_ADC[3]
VBAT_ADC[2]
VBAT_ADC[1]
VBAT_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VBAT Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
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8.5.32 VSYS ADC 1 Register (Address = 1Fh) [reset = 00h]
REG1F is shown in 图 68 and described in 表 40.
Return to Summary Table.
图 68. REG1F Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VSYS_ADC[15:8]
表 40. REG1F Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VSYS_ADC[15]
VSYS_ADC[14]
VSYS_ADC[13]
VSYS_ADC[12]
VSYS_ADC[11]
VSYS_ADC[10]
VSYS_ADC[9]
VSYS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Sign bit: overall results reported in two's complement.
16384 mV
Yes
Yes
8192 mV
4096 mV
2048 mV
1024 mV
512 mV
VSYS Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
256 mV
8.5.33 VSYS ADC 0 Register (Address = 20h) [reset = 00h]
REG20 is shown in 图 69 and described in 表 41.
Return to Summary Table.
图 69. REG20 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
VSYS_ADC[7:0]
表 41. REG20 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
VSYS_ADC[7]
VSYS_ADC[6]
VSYS_ADC[5]
VSYS_ADC[4]
VSYS_ADC[3]
VSYS_ADC[2]
VSYS_ADC[1]
VSYS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
128 mV
64 mV
32 mV
16 mV
8 mV
VSYS Voltage reading:
Range: 0 V – 10 V
Yes
Yes
Yes
Yes
Yes
4 mV
Yes
2 mV
Yes
1 mV
64
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8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
REG21 is shown in 图 70 and described in 表 42.
Return to Summary Table.
图 70. REG21 Register
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Field
TS_ADC[15:8]
表 42. REG21 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
Sign bit: overall results reported in two's complement.
7
6
5
4
3
2
1
0
TS_ADC[15]
TS_ADC[14]
TS_ADC[13]
TS_ADC[12]
TS_ADC[11]
TS_ADC[10]
TS_ADC[9]
TS_ADC[8]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
50.0%
25.0%
TS as percentage of REGN reading:
Range: 0% – 94.9%
Yes
8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
REG22 is shown in 图 71 and described in 表 43.
Return to Summary Table.
图 71. REG22 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
TS_ADC[7:0]
表 43. REG22 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
TS_ADC[7]
TS_ADC[6]
TS_ADC[5]
TS_ADC[4]
TS_ADC[3]
TS_ADC[2]
TS_ADC[1]
TS_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
12.50%
6.25%
TS as percentage of REGN reading:
Range: 0% – 94.9%
Yes
Yes
3.125%
1.563%
0.781%
0.391%
0.195%
0.098%
Yes
Yes
Yes
Yes
Yes
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8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
REG23 is shown in 图 72 and described in 表 44.
Return to Summary Table.
图 72. REG23 Register
Bit
7
6
0
5
0
4
0
3
2
0
1
0
0
0
Reset
Field
0
0
RESERVED
TDIE_ADC[14:8]
表 44. REG23 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
RESERVED
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
Reserved bit always reads 0
TDIE_ADC[14]
TDIE_ADC[13]
TDIE_ADC[12]
TDIE_ADC[11]
TDIE_ADC[10]
TDIE_ADC[9]
TDIE_ADC[8]
Yes
Yes
Yes
Yes
Yes
Yes
Yes
128°C
TDIE (IC Temperature) reading:
Range: 0°C – 128°C
8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
REG24 is shown in 图 73 and described in 表 45.
Return to Summary Table.
图 73. REG24 Register
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
Reset
Field
0
0
TDIE_ADC[7:0]
表 45. REG24 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
6
5
4
3
2
1
0
TDIE_ADC[7]
TDIE_ADC[6]
TDIE_ADC[5]
TDIE_ADC[4]
TDIE_ADC[3]
TDIE_ADC[2]
TDIE_ADC[1]
TDIE_ADC[0]
R
R
R
R
R
R
R
R
Yes
No
No
No
No
No
No
No
No
64°C
32°C
16°C
8°C
TDIE (IC Temperature) reading:
Range: 0°C – 128°C
Yes
Yes
Yes
Yes
4°C
Yes
2°C
Yes
1°C
Yes
0.5°C
66
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
8.5.38 Part Information Register (Address = 25h) [reset = 11h]
REG25 is shown in 图 74 and described in 表 46.
Return to Summary Table.
图 74. REG25 Register
Bit
7
0
6
0
5
0
4
1
3
0
2
0
1
0
1
Reset
Field
0
REG_RST
PN[3:0]
DEV_REV[2:0]
表 46. REG25 Register Field Descriptions
Reset by
REG_RST
Reset by
WATCHDOG
Bit
Field
Type
Description
7
REG_RST
R
Yes
No
Register Reset:
0 – Keep current register settings
1 – Reset to default register value and reset safety timer (bit resets to 0 after
register reset is complete)
6
5
4
3
2
1
0
PN[3]
R
R
R
R
R
R
R
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
0010: BQ25882
PN[2]
PN[1]
PN[0]
DEV_REV[2]
DEV_REV[1]
DEV_REV[0]
Device revision: 001
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled power path management device and a
dual-cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other
portable devices. It integrates an input blocking FET (QBLK, Q1), high-side switching FET (QHS, Q2), low-side
switching FET (QLS, Q3), and battery FET (QBAT, Q4) between system and battery. The device also integrates
a bootstrap diode for the high-side gate drive.
9.2 Typical Application
VBUS
/PG
1 µF
ILIM
360 ꢀ
PMID
SYSTEM
Load
7V to 8.8V
SYS
10 µF
47 nF
4.7 µF
1 µH
2 x 22 µF
SW
BAT
BTST
10 µF
REGN
BATP
REGN
D+
USB
Port
Dœ
VREF
TS
SDA
SCL
/INT
/CE
Host
BATN
GND
BQ25882
图 75. BQ25882 Typical Application Diagram
9.2.1 Design Requirements
For this design example, use the parameters shown in the table below.
68
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Typical Application (接下页)
表 47. Design Parameters
PARAMETER
VALUE
3.9 V to 6.2 V
3.0 A
VBUS voltage range
Input current limit (IINDPM[4:0])
Fast charge current limit (ICHG[5:0])
Minimum system voltage (SYS_MIN[3:0])
Cell regulation voltage (VREG[7:0])
1.5 A
7.0 V
8.7 V
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The device has 1.5-MHz switching frequency to allow the use of small inductor and capacitor values. The
inductor saturation current should be higher than the input current (IIN) plus half the ripple current (IRIPPLE):
I
RIPPLE
ISAT í IIN +
2
(5)
The inductor ripple current (IRIPPLE) depends on input voltage (VVBUS), duty cycle (D = 1 – VBUS/VBAT), switching
frequency (fSW) and inductance (L):
V
BUS ì(VSYS-VBUS
)
IRIPPLE
=
VSYS ì fSW ì L
(6)
The maximum inductor ripple current happens in the vicinity of D = 0.5. Usually inductor ripple is designed in the
range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical
design.
9.2.2.2 Input (VBUS / PMID) Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the
worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated by
I
RIPPLE
IPMID
=
ö 0.29ì IRIPPLE
2ì 3
(7)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed close to the PMID and GND pins of the IC. Voltage rating of the capacitor must be higher than normal
input voltage level. 25-V rating or higher capacitor is preferred for up to 5-V input voltage. 10-μF capacitor is
suggested for up to 3.3-A input current.
9.2.2.3 Output (VSYS) Capacitor
SYS capacitor is the boost converter output capacitor and should also have enough ripple current rating to
absorb output switching ripple current. The output capacitor RMS current ICSYS is given:
D
ICSYS, rms = IOUT ì
1- D
(8)
The output capacitor voltage ripple is a function of the boost output current (IOUT), and can be calculated as
follows:
I
OUT ì D
DVSYS
=
f
SW ìCSYS
(9)
69
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Low ESR ceramic capacitor such as X7R or X5R is preferred for SYS decoupling capacitor and should be placed
close to the SYS and GND pins of the IC. Voltage rating of the capacitor must be higher than normal output
voltage level. 16-V rating or higher capacitor is preferred. 40-μF capacitor is suggested for up to 2.2-A boost
converter output current.
70
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
9.2.3 Application Curves
CVBUS = 1µF, CPMID= 10µF, CBAT = 10µF, CSYS = 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)
VBUS = 5V
VBAT = 6.0V
VBUS = 5V
VBAT = 6.0V
ICHG = 1A
图 76. Adapter Power Up With Charge Enabled
图 77. Adapter Power Up With Charge Enabled
VBUS = 5V
VBAT = 7.4V
ICHG = 1A
VBUS = 5V
VBAT = 7.4V
ICHG = 1A
图 78. Charge Enable
图 79. Charge Disable
VBUS = 5V
VBAT = Open
Charge enabled
VBUS = 5V
VBAT = Open
Charge disabled
图 80. Adapter Plug-in with No Battery
图 81. Adapter Plug-in with No Dead Battery
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CVBUS = 1µF, CPMID= 10µF, CBAT = 10µF, CSYS = 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)
VBAT = 7.6V
VBUS = 5.1V
No IBUS load
VBAT = 7.6V
Adapter removed
with EN_OTG = 1
RBUS = 25Ω
图 83. Buck Mode Startup After Adapter Removal
图 82. Buck Mode (OTG) Startup
VBAT = 7.6V
VBUS = 5.1V
IBUS = 1A
VBAT = 7.6V
VBUS = 5.1V
IBUS = 0mA
图 84. Buck Mode (OTG) PWM Switching
图 85. Buck Mode (OTG) PFM Switching
VBUS = 5V
VBAT = 7.6V
ICHG = 1A
VBUS = 5V
VBAT = 8.4V
Charge disabled
图 86. Boost Mode PWM Switching
图 87. Boost Mode PFM Switching
72
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
CVBUS = 1µF, CPMID= 10µF, CBAT = 10µF, CSYS = 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)
VBUS = 5V
VBAT = 8.7V
Charge disabled
DCP Adapter
VBAT = 8.0V
Charge enabled
图 88. SYSMIN Transient Response
图 89. VINDPM Transient Response
IBUS
DCP Adapter
VBAT = 8.0V
Charge enabled
VBAT = 7.6V
VBUS = 5.1V
图 90. IINDPM Transient Response
图 91. Buck Mode (OTG) Load Transient Response
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10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 6.2 V input
with at least 500-mA current rating connected to VBUS or a dual-cell Li-Ion battery with voltage > VBAT_UVLO
connected to BAT. The source current rating needs to be at least 3.3 A in order for the boost converter of the
charger to provide maximum output power to SYS.
74
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loops is important to prevent electrical and magnetic field
radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB
according to this specific order is essential.
1. Place SYS and BAT output capacitor as close to SYS, BAT and GND bumps as possible. Ground
connections need to be tied to the IC ground with a short copper trace connection or GND plane.
2. Place PMID input capacitor as close as possible to PMID bumps and GND bumps and use shortest copper
trace connection or GND plane.
3. Place inductor input terminal to SW bumps as close as possible. Minimize the copper area of this trace to
lower electrical and magnetic field radiation but make the trace wide enough to carry the input current.
Minimize parasitic capacitance from this area to any other trace or plane.
4. Decoupling capacitors should be placed next to the IC and make trace connection as short as possible.
5. Ensure that there are sufficient thermal vias directly under bumps of the power FETs, connecting to copper
on other layers.
6. Via size and number should be enough for a given current path.
7. Route BATP and BATN away from switching nodes such as SW.
Refer to the EVM design and the Layout Example below for the recommended component placement with
trace and via locations.
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11.2 Layout Example
GND
GND
GND
BTST
PMID
SW
PMID
PMID
/PG
GND
GND
/INT
ILIM
TS
SW
SYS
BAT
SW
SYS
VBUS
VBUS
VBUS
SYS
BAT
D+
D-
BAT
REG
N
SCL
BTST
BATP
/CE
SDA
BATN
GND
REGN
图 92. PCB Layout Example
76
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ZHCSJ56C –FEBRUARY 2018–REVISED SEPTEMBER 2019
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
12.1.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
《BQ2588x 升压电池充电器评估模块用户指南》
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25882YFFR
BQ25882YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
25
25
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25882
BQ25882
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25882YFFR
BQ25882YFFT
DSBGA
DSBGA
YFF
YFF
25
25
3000
250
180.0
180.0
8.4
8.4
2.28
2.28
2.28
2.28
0.73
0.73
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25882YFFR
BQ25882YFFT
DSBGA
DSBGA
YFF
YFF
25
25
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YFF0025
DSBGA - 0.625 mm max height
S
C
A
L
E
6
.
0
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
1.6 TYP
SYMM
E
D
D: Max = 2.135 mm, Min =2.075 mm
E: Max = 2.135 mm, Min =2.075 mm
SYMM
1.6
C
B
A
TYP
0.4 TYP
3
4
5
1
2
0.3
0.2
25X
0.4 TYP
0.015
C A B
4223786/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0025
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
25X ( 0.23)
(0.4) TYP
1
2
4
5
A
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.05 MAX
(
0.23)
0.05 MIN
(
0.23)
METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223786/A 06/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0025
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
25X ( 0.25)
(R0.05) TYP
3
1
2
4
5
A
B
C
(0.4) TYP
METAL
TYP
SYMM
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223786/A 06/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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