BQ25883RGET_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

BQ25883 2-Cell, 2-A Boost-Mode Battery Charger With Power Path, USB On-The-Go Boost

(OTG) For USB Input

1 Features

•

High accuracy

–

±0.5% Charge voltage regulation

±5% Charge current regulation

±7.5% Input current regulation

1

•

High-efficiency 2-A, 1.5MHz switch mode boost

charger

–

93.4% Charge efficiency at 5V adapter, 7.6-V

battery, 1-A charge

•

Safety

Optimized for USB input and 2-cell Li-Ion

battery

–

Battery temperature sensing in charge and

OTG buck mode

Selectable low power PFM mode for light load

operation

–

Thermal regulation and thermal shutdown

•

Single input to support USB input adapters

2 Applications

–

Supports 3.9 V – 6.2 V input voltage range

with 20-V absolute maximum input voltage

rating

•

Bluetooth speaker

EPOS Printer

Portable POS

–

Input current limit (500 mA to 3.3 A with 100-

mA resolution) to support USB2.0, USB3.0

standard adapters

Wireless security camera

3 Description

–

Maximum power tracking by input voltage limit

up-to 5.5 V

The BQ25883 is a highly-integrated 2-A boost switch-

mode battery charge management and system power

path management device for 2-cell (2s) Li-Ion and Li-

polymer battery. The BQ25883 has I²C control with

OTG and power path.

Integrated USB D+/D- auto-detect USB SDP,

CDP, DCP, and non-standard adapters

•

Power path management and I²C control

–

Highest battery discharge efficiency with 17mΩ

battery discharge MOSFET

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

–

Narrow VDC (NVDC) power path management

BQ25883

VQFN (24)

4.00 mm x 4.00 mm

–

Instant-on system on with no battery or

deeply discharged battery

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

Ideal diode operation in battery supplement

mode

Simplified Schematic

•

USB on-the-go (OTG) with adjustable output from

4.5V to 5.5V

VREF

5V @ 3A

STAT

VBUS

ILIM

–

Buck converter with up-to 2 A output

94% Efficiency at 5 V, 1 A output

PMID

SYSTEM

LOAD

6.0V to 8.8V

ICHG=2A

SYS

BAT

SW

Accurate constant current (CC) regulation and

output short protection

BTST

REGN

–

Selectable low power PFM mode for light load

operation with out-of-audio option

VREGN

D+

USB

Host

•

Input current optimizer (ICO) to maximize input

power without overloading adapters

Dœ

VREF

TS

SDA

`

Integrated 16-bit ADC for system monitoring (BUS

voltage and current, each cell voltage, charge

current, SYS voltage, and NTC and die

temperature)

SCL

INT

PG

BQ25883

CE

GND

•

High integration includes all MOSFETs, current

sensing and loop compensation

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 34

8.5 Register Maps ........................................................ 35

Application and Implementation ........................ 68

9.1 Application Information............................................ 68

9.2 Typical Application .................................................. 68

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Timing Requirements.............................................. 11

7.7 Typical Characteristics............................................ 13

Detailed Description ............................................ 16

8.1 Overview ................................................................. 16

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

9

10 Power Supply Recommendations ..................... 74

11 Layout................................................................... 74

11.1 Layout Guidelines ................................................. 74

11.2 Layout Example .................................................... 75

12 Device and Documentation Support ................. 76

12.1 Device Support .................................................... 76

12.2 Documentation Support ........................................ 76

12.3 Receiving Notification of Documentation Updates 76

12.4 Community Resources.......................................... 76

12.5 Trademarks........................................................... 76

12.6 Electrostatic Discharge Caution............................ 76

12.7 Glossary................................................................ 76

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 77

4 Revision History

Changes from Original (February 2019) to Revision A

Page

•

Changed from Advance Information to Production Data ....................................................................................................... 1

2

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

5 Device Comparison Table

Table 1. Device Comparison

PART NUMBER

VBUS Operating Range

USB Detection

Power Path

BQ25882

BQ25883

3.9 to 6.2 V

D+/D-

BQ25886

4.3 to 6.2 V

D+/D-

BQ25887

3.9 to 6.2 V

PSEL

3.9 to 6.2 V

D+/D-

Yes

No

Cell Balancing

OTG

No

Yes

Up to 2 A

Yes

Up to 2 A

Yes

Up to 2 A

No

No OTG

Yes

16 bit ADC

Control Interface

Status Pin

I2C

Standalone

STAT, /PG

4x4 QFN-24

I2C

/PG

STAT, /PG

4x4 QFN-24

STAT, /PG

4x4 QFN-24

Package

2.1x2.1 WCSP-25

Submit Documentation Feedback

3

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

6 Pin Configuration and Functions

RGE Package

24-Pin VQFN

Top View

24

23

22

21

20

19

1

18

17

16

15

14

13

SW

SYS

D-

2

STAT

3

CE

BQ25883

RGE, 4x4

4

SDA

5

BAT

SCL

/INT

6

INT

7

8

9

10

11

12

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Positive USB data line – D+/D– based USB host/charging port detection. The detection includes

data contact detection (DCD) and secondary detection in BC1.2.

D+

24

AIO

Negative USB data line – D+/D– based USB host/charging port detection. The detection includes

data contact detection (DCD) and secondary detection in BC1.2.

D–

1

2

3

Open drain charge status indicator – Connect to the pull-up rail via 10-kΩ resistor. LOW indicates

charge in progress. HIGH indicates charge complete or charge disabled. When any fault occurs, the

STAT pin blinks at 1Hz. The STAT function can be disabled when the STAT_DIS bit is set.

STAT

CE

DO

DI

Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is

LOW. CE pin is internally pulled low with 900k-Ω resistor.

SDA

SCL

4

5

DIO

DI

I2C Interface Data – Connect SDA to the pull up rail through a 10-kΩ resistor.

I2C Interface Clock – Connect SCL to the pull up rail through a 10-kΩ resistor.

Open drain active Interrupt Output – Connect INT to the pull up rail via a 10-kΩ resistor. The INT

pin sends active low, 256-µs pulse to the host to report charger device status and fault.

INT

6

DO

Temperature Qualification Voltage – Connect a negative temperature coefficient thermistor.

Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends

when TS pin is out of range. Recommend 103AT-2 thermistor.

TS

7

AI

4

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Input Current Limit (IINDPM) – ILIM pin sets the maximum input current and can be used to

monitor input current. IINDPM loop regulates ILIM pin voltage at 0.8V. When ILIM pin is less than

0.8V, the input current can be calculated by IIN = KILIM x VILIM / (RILIM x 0.8V). A resistor

connected from ILIM pin to ground sets the input current limit as maximum (IINMAX = KILIM /

RILIM). When ILIM pin is short to GND, the input current limit is set to maximum by ILIM. The actual

input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is HIGH) or IINDPM register

bits. Input current limit less than 500mA is not supported on ILIM pin. The ILIM pin function can be

disabled when EN_ILIM bit is 0. If ILIM pin is not used, pull this pin to GND.Do not float this pin.

ILIM

8

AI

Open drain active low power good indicator – Connect to the pull up rail via 10-kΩ resistor. LOW

indicates a good input source if the input voltage is within VVBUS_OP (3.9 V), and can provide more

than IPOORSRC (30 mA).

PG

9

DO

Gate Drive Supply – Bias supply for internal MOSFETs driver and IC. Bypass REGN to GND with a

4.7-µF ceramic capacitor. REGN current limit is 50 mA.

REGN

BTST

BAT

11

12

P

PWM High-side Driver Supply – Internally, BTST is connected to the cathode of the boot-strap

diode. Connect a 47nF bootstrap capacitor from SW to BTST.

Battery Power Connection – Connect minimum recommended 10-µF capacitance after derating

closely to the BAT pin and GND.

13, 14

System Connection – The internal BATFET is connected between SYS and BAT. When the battery

falls below the minimum system voltage, the switch-mode converter keeps SYS above the minimum

system voltage. Connect a 2x22-µF capacitance after derating closely to the SYS pin and PGND.

SYS

15, 16

P

SW

17, 18

19, 20,

P

Inductor Connection – Connect to the switched side of the external inductor.

GND

–

Ground Return

Blocking MOSFET Connection – The minimum recommended total input low-ESR capacitance on

VBUS and PMID, after applied derating, is 10 uF. At least 1-uF is recommended at VBUS with the

remainder at PMID. Typical value for PMID is 10 uF.

PMID

21, 22

P

Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1-

µF ceramic capacitor, placed as close to the IC as possible.

VBUS

NC

23

10

P

–

No Connect – Leave these pins floating or tie to ground.

Submit Documentation Feedback

5

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

MIN

-0.3

MAX

20

8.5

12

13

19

6

UNIT

V

VBUS (converter not switching)

PMID (converter not switching)

BAT, SYS (converter not switching)

SW

V

Voltage Range (with respect to GND unless otherwise

specified)

BTST

V

REGN, STAT, /PG, TS

ILIM

V

5

V

BTST to SW

6

V

D+, D-, /CE, SDA, SCL, /INT

6

V

Output Sink Current

/INT, STAT, /PG

6

mA

°C

Junction Temperature, T_J

Storage temperature, T_stg

–40

150

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

3.3

2.2

5

UNIT

I_VBUS

Average input current (VBUS)

A

I_BAT

Average charge current (IBAT)

I_{BAT_RMS}

RMS discharging current with internal MOSFET

9 (up to

1us)

I_{BAT_PK}

Peak discharging current with internal MOSFET

A

V_BAT

T_A

Battery Voltage

9.2⁽¹⁾

V

Operating free-air temperature range

-40

85

°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on SW pin. A tight layout minimizes

switching noise.

7.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

BQ25883

THERMAL METRIC⁽¹⁾

RGE (VQFN)

24-PIN

32.4

UNIT

R_ΘJA

R_ΘJC(top)

R_ΘJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

26.7

10.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.4

Ψ_JB

10.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Thermal Information (continued)

over operating free-air temperature range (unless otherwise noted)

BQ25883

THERMAL METRIC⁽¹⁾

RGE (VQFN)

24-PIN

UNIT

R_{Θ JC(bot)}

Junction-to-case (bottom) thermal resistance

3.7

°C/W

7.5 Electrical Characteristics

V_{VBUS_UVLO_RISING}< V_VBUS< V_{VBUS_OV}, T_J= -40°C to+125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

QUIESCENT CURRENTS

TEST CONDITIONS

MIN

TYP

MAX UNIT

VBAT = 9 V, No VBUS, SCL, SDA = 0 V

or 1.8 V, T_J=25C, ADC Disabled

12

30

1.5

3

14 µA

20 µA

38 µA

48 µA

I_BAT

Battery discharge current (BAT)

Input supply current (VBUS) in HIZ

Input supply current (VBUS)

VBAT = 9 V, No VBUS, SCL, SDA = 0 V

or 1.8 V, T_J< 85C, ADC Disabled

VBUS = 5 V, High-Z Mode, no battery,

ADC Disabled, 25℃

I_{VBUS_HIZ}

VBUS = 5 V, High-Z Mode, no battery,

ADC Disabled, <85℃

VBUS = 5 V, V_BAT= 7.6 V, converter not

switching

3

mA

I_VBUS

VBUS = 5 V, V_BAT= 7.6 V, converter

switching, I_SYS= 0A

Battery discharge current in OTG

mode

VBAT = 8.4 V, OTG Buck Mode, I_VBUS

0A, converter switching

=

I_{BAT_OTG}

3

VBUS/VBAT POWER UP

V_{VBUS_OP}VBUS operating range

V_{VBUS_UVLO_RISING}VBUS rising for active I2C, no battery VBUS rising

3.9

6.2

3.68

6.6

V

3.3

VBUS over-voltage rising threshold

VBUS over-voltage falling threshold

Battery for active I2C

VBUS rising

6.2

5.9

3.7

V

V_{VBUS_OV}

VBUS falling

6.4

V

V_{BAT_UVLO_RISING}

VBAT rising

4

3.7

15

4.42

V

V_{POORSRC_FALLING}Bad adapter detection threshold

VBUS falling below V_{POORSRC_FALLING}

V

I_POORSRC

Bad adapter detection current source

mA

POWER-PATH

ISYS = 0A, VBAT = 8.80 V >

SYS_MIN[3:0], Charge Disabled (EN_CHG

= 0)

V_BAT+0.

1

V

V_SYS

Typical System Regulation Voltage

System Regulation Voltage

VSYS_

MIN+0.

2

ISYS = 0A, VBAT < SYS_MIN[3:0],

Charge Disabled (EN_CHG = 0)

V

VBAT < SYS_MIN[3:0] = 0010, Charge

Disabled (EN_CHG = 0)

V_{SYS_MIN}

6.2

6.8

6.4

BATTERY CHARGER

Typical charge voltage regulation

range

V_{REG_RANGE}

9.2

V

V_{REG_STEP}

V_{REG_ACC}

I_{CHG_RANGE}

I_{CHG_STEP}

Typical charge voltage step

Charge voltage

10

mV

V

VREG = 8.40 V, T_J= 0°C to 85°C,

8.35

100

8.4

8.44

Charge current regulation range

Charge current regulation step

2200 mA

mA

50

Fast Charge current regulation

accuracy

ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V,

T_J= 0°C to 85°C

I_{CHG_ACC}

-7.5

-15

7.5

15

%

Fast Charge current regulation

accuracy

ICHG = 500mA, VBAT = 6.2 V or 7.6 V, T_J

= 0°C to 85°C

Submit Documentation Feedback

7

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Electrical Characteristics (continued)

V_{VBUS_UVLO_RISING}< V_VBUS< V_{VBUS_OV}, T_J= -40°C to+125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

-25

50

TYP

MAX UNIT

Fast Charge current regulation

accuracy

ICHG = 250 mA, VBAT = 6.2 V or 7.6 V,

T_J= 0°C to 85°C

I_{CHG_ACC}

25

%

I_{PRECHG_RANGE}

I_{PRECHG_STEP}

Precharge current range

800 mA

mA

Typical precharge current step

50

VBAT = 5.2 V, IPRECHG = 200 mA, T_J=

25°C

170

237 mA

245 mA

I_{PRECHG_ACC}

Precharge current accuracy

VBAT = 5.2 V, IPRECHG = 200 mA, T_J=

0°C to 85°C

150

50

I_{TERM_RANGE}

I_{TERM_STEP}

Termination current range

800 mA

mA

Typical termination current step

50

ICHG = 1.5A, ITERM = 150 mA, T_J= 25°C

143

120

45

157 mA

ICHG = 1.5A, ITERM = 150 mA, T_J= 0°C

to 85°C

180 mA

60 mA

75 mA

I_{TERM_ACC}

Termination current accuracy

ICHG = 1.5A, ITERM = 50 mA, T_J= 25°C

ICHG = 1.5A, ITERM = 50 mA, T_J= 0°C to

85°C

22

Short Battery Voltage rising threshold

to start pre-charging

V_{BAT_SHORT_RISING}

VBAT rising

VBAT falling

VBAT < 4.4 V

4.1

3.7

4.4

4

4.7

4.3

V

Short Battery Voltage falling

threshold to stop pre-charging

V_{BAT_SHORT_FALLIN}

G

Low Battery Voltage trickle charging

current

I_{BAT_SHORT}

100

mA

VBAT rising, VBATLOWV = 6.0 V

VBAT rising, VBATLOW = 5.6 V

VBAT falling, VBATLOW = 5.6 V

VBAT falling, VBATLOWV = 6.0 V

VBAT falling, VRECHG[1:0] = 01

VBAT falling, VRECHG[1:0] = 10

T_J= 25°C

5.7

5.3

4.9

5.3

6

5.6

5.2

5.6

200

300

32

6.3

5.9

5.5

5.9

V

VBAT LOWV Rising threshold to

start fast-charging

V_{BAT_LOWV_RISING}

V

VBAT LOWV Falling threshold to

stop fast-charging

V_{BAT_LOWV_FALLING}

V

mV

V_RECHG

Recharge threshold below V_REG

High-side switching MOSFET on-

resistance between SW and

SYS (Q2)

34.2 mΩ

46.5 mΩ

45.8 mΩ

62.9 mΩ

R_{ON_QHS}(Q2)

T_J= – 40°C to 125°C

T_J= 25°C

32

42

Low-side switching MOSFET on-

resistance between SW and GND

(Q3)

R_{ON_QLS}(Q3)

T_J= – 40°C to 125°C

T_J= 25°C

18

18.8 mΩ

22.5 mΩ

16 mA

MOSFET on-resistance between

SYS and BAT (Q4)

R_{ON_QBAT}(Q4)

I_{BAT_DISCHG}

T_J= – 40°C - 85°C

BAT Discharge current source

VBAT = 8V, EN_BAT_DISCHG = 1

8

11.5

INPUT VOLTAGE / CURRENT REGULATION

V_{INDPM_RANGE}

V_{INDPM_STEP}

Input voltage regulation range

Input voltage regulation step

3.9

5.5

V

mV

V

100

3.9

4.4

VINDPM = 3.9 V

VINDPM = 4.4 V

3.783

4.268

500

4.017

4.532

V_INDPM

Input voltage limit

V

I_{INDPM_RANGE}

I_{INDPM_STEP}

Input current regulation range

Input current regulation step

3300 mA

mA

100

469

IINDPM = 500 mA

IINDPM = 900 mA

IINDPM = 2500 mA

IINDPM = 3000 mA

438

765

500 mA

900 mA

2500 mA

3000 mA

832

I_{INDPM_ACC}

Input current regulation limit

I_INMAX= K_ILIM/R_ILIM

2125

2550

2312

2775

A x

Ω

K_ILIM

Input Current regulation by ILIM pin = 1.5A

1012

1098

1185

8

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Electrical Characteristics (continued)

V_{VBUS_UVLO_RISING}< V_VBUS< V_{VBUS_OV}, T_J= -40°C to+125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

33

MAX UNIT

36.8 mΩ

50.9 mΩ

T_J= 25°C

Blocking MOSFET on-resistance

between VBUS and PMID (QBLK)

R_{ON_QBLK}(Q1)

T_J= – 40°C to 125°C

33

D + /D- DETECTION

V_{D+D-_600MVSRC}

I_{D+_10UASRC}

D+/D- Voltage Source (600 mV)

D+ Current Source (10 µA)

D+/D- Current Sink (100 µA)

500

7

600

10

700 mV

14 µA

VD + = 200 mV,

VD + = 500 mV,

I_{D+D-_100UASNK}

50

100

150 µA

D+/D- Comparator Threshold for

Secondary Detection

V_{D+D-_0P325}

R_{D-_19K}

D + pin Rising

VD- = 500 mV,

D + pin Rising

250

400 mV

24.8 kΩ

800 mV

D- Resistor to Ground (19 kΩ)

14.25

D+ Comparator Threshold for Data

Contact Detection

V_{D+_0P8}

D+/D- Threshold for Non-standard

adapter

V_{D+D-_1P2}

V_{D+D-_2P0}

V_{D+D-_2P8}

I_{D+D-_LKG}

1.05

1.85

1.35

2.15

V

D+/D- Comparator Threshold for

Non-standard adapter

D+/D- Threshold for Non-standard

adapter

2.55

-1

2.85

1

V

D+/D- Leakage Current

HiZ

µA

BATTERY OVER-VOLTAGE PROTECTION

V_{BAT_OVP_RISING}

V_{BAT_OVP_FALLING}

Battery over-voltage rising threshold VBAT rising, as percentage of VREG

Battery over-voltage falling threshold VBAT falling, as percentage of VREG

102.5

101

104

102

105

%

103.3

THERMAL REGULATION AND THERMAL SHUTDOWN

Junction temperature regulation

accuracy

T_REG

TREG = 120°C

120

°C

Thermal Shutdown Rising threshold

T_{SHUT_RISING}

Temperature Increasing

150

120

°C

Thermal Shutdown Falling threshold Temperature Decreasing

JEITA THERMISTOR COMPARATOR (BOOST MODE)

TS pin voltage rising. T1 (0°C)

V_T1

threshold, Charge suspended below As Percentage to REGN

this temperature.

72.75

67.75

44.25

73.25

1.3

73.75

68.75

45.25

%

TS pin voltage falling. Charge re-

enabled to ICHG/2 and VREG above As Percentage to REGN

this temperature

V_{T1_HYS}

TS pin voltage rising. T2 (10°C)

threshold, charge set to ICHG/2 and As Percentage to REGN

VREG below this temperature

V_T2

68.25

1.2

TS pin voltage falling. Charge set to

V_{T2_HYS}

ICHG and VREG above this

temperature

As Percentage to REGN

TS pin voltage falling. T3 (45°C)

threshold, charge set to ICHG and

8.1 V above this temperature.

V_T3

44.75

1

TS pin voltage rising. Charge set to

ICHG and VREG below this

temperature

V_{T3_HYS}

TS pin voltage falling. T5 (60°C)

threshold, charge suspended above As Percentage to REGN

this temperature.

V_T5

33.875 34.375 34.875

1.35

TS pin voltage rising. Charge set to

V_{T5_HYS}

ICHG and 8.1 V below this

temperature

As Percentage to REGN

COLD/HOT THERMISTOR COMPARATOR (OTG BUCK MODE)

Submit Documentation Feedback

9

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Electrical Characteristics (continued)

V_{VBUS_UVLO_RISING}< V_VBUS< V_{VBUS_OV}, T_J= -40°C to+125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Cold Temperature Threshold 0, TS

pin Voltage Rising Threshold

As Percentage to REGN, BCOLD = 0

(Approx. – 10°C w/ 103AT)

V_BCOLD0

76.5

77

77.5

%

Cold Temperature Threshold 0, TS

pin Voltage Falling Threshold

V_{BCOLD0_HYS}

V_BCOLD1

V_{BCOLD1_HYS}

V_BHOT0

V_{BHOT0_HYS}

V_BHOT1

V_{BHOT1_HYS}

V_BHOT2

As Percentage to REGN

1

80

Cold Temperature Threshold 1, TS

pin Voltage Rising Threshold

As Percentage to REGN, BCOLD = 1

(Approx. – 20°C w/ 103AT)

79.5

80.5

Cold Temperature Threshold 1, TS

pin Voltage Falling Threshold

As Percentage to REGN

1

Hot Temperature Threshold 0, TS pin As Percentage to REGN, BHOT[1:0] = 01

Voltage Falling Threshold

37.25

37.75

3

38.25

(Approx. 55°C w/ 103AT)

Hot Temperature Threshold 0, TS pin

Voltage Rising Threshold

As Percentage to REGN

Hot Temperature Threshold 1, TS pin As Percentage to REGN, BHOT[1:0] = 00

Voltage falling Threshold

33.875 34.375 34.875

3

(Approx. 60°C w/ 103AT)

Hot Temperature Threshold 1, TS pin

Voltage rising Threshold

As Percentage to REGN

Hot Temperature Threshold 2, TS pin As Percentage to REGN, BHOT[1:0] = 10

Voltage falling Threshold

30.75

31.25

3

31.75

(Approx. 65°C w/ 103AT)

Hot Temperature Threshold 2, TS pin

Voltage rising Threshold

V_{BHOT2_HY2}

As Percentage to REGN

BOOST MODE CONVERTER

F_SW

PWM switching frequency

Oscillator frequency

VBAT falling

1.35

1.5

6

1.65 MHz

OTG BUCK MODE CONVERTER

V_{OTG_BAT}

Battery voltage exiting OTG mode

5.85

4.5

6.15

5.5

V

Typical OTG Buck mode voltage

regulation range

V_{OTG_RANGE}

Typical OTG Buck mode voltage

regulation step

V_{OTG_STEP}

V_{OTG_ACC}

I_{OTG_RANGE}

I_{OTG_STEP}

I_{OTG_ACC}

100

mV

%

OTG Buck mode voltage regulation

accuracy

IVBUS = 0A, OTG_VLIM = 5.1 V

-3

3

2

Typical OTG Buck mode current

regulation range

0.5

A

Typical OTG Buck mode current

regulation step

100

-7.5

6

mA

%

OTG Buck mode current regulation

accuracy

OTG_ILIM = 1A

-15

5.8

0

OTG Buck mode over-voltage

threshold

V_{OTG_OVP}

V

REGN LDO

V_REGN

REGN LDO output voltage

REGN LDO current limit

V_VBUS= 5 V, I_REGN= 20 mA

V_VBUS= 5 V, V_REGN= 3.8 V

4.7

50

4.8

5.15

V

I_REGN

mA

Analog-to-Digital Converter (ADC)

ADC_SAMPLE[1:0] = 11

ADC_SAMPLE[1:0] = 10

ADC_SAMPLE[1:0] = 01

ADC_SAMPLE[1:0] = 00

ADC_SAMPLE[1:0] = 11

ADC_SAMPLE[1:0] = 10

ADC_SAMPLE[1:0] = 01

ADC_SAMPLE[1:0] = 00

24

12

6

ms

bits

t_{ADC_CONV}

Conversion time, each measurement

3

14

13

12

10

15

14

13

12

ADCRES

Effective resolution

ADC MEASUREMENT RANGES AND LSB

10

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Electrical Characteristics (continued)

V_{VBUS_UVLO_RISING}< V_VBUS< V_{VBUS_OV}, T_J= -40°C to+125°C, and T_J= 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_{BUS_ADC_RANGE}

I_{BUS_ADC_LSB}

I_{BAT_ADC_RANGE}

I_{BAT_ADC_LSB}

ADC BUS current range

ADC BUS current LSB

ADC BAT current range

ADC BAT current LSB

ADC BUS voltage range

ADC BUS voltage LSB

ADC SYS voltage range

ADC SYS voltage LSB

ADC BAT voltage range

ADC BAT voltage LSB

ADC TS voltage range

ADC TS voltage LSB

ADC Die temperature range

ADC Die temperature LSB

0

4

A

mA

A

1

0

4

1

mA

V

V_{BUS_ADC_RANGE}

V_{BUS_ADC_LSB}

V_{SYS_ADC_RANGE}

V_{SYS_ADC_LSB}

V_{BAT_ADC_RANGE}

V_{BAT_ADC_LSB}

V_{TS_ADC_RANGE}

V_{TS_ADC_LSB}

6.5

10

80

mV

V

0

1

mV

V

0

1

mV

%

20

0

0.098

0.5

%

V_{TDIE_ADC_RANGE}

V_{TDIE_ADC_LSB}

I2C INTERFACE (SCL, SDA)

150 °C

°C

Input high threshold level, SDA and

SCL

V_IH

Pull-up rail 1.8 V

1.3

V

V_IL

Input low threshold level

Output low threshold level

High level leakage current

Pull-up rail 1.8 V

Sink current = 5 mA

Pull-up rail 1.8 V

0.4

1

V

V_OL

I_BIAS

uA

LOGIC I/O PIN (/CE)

V_{IH_CEZ}

Input high threshold level, /CE

Input low threshold level, /CE

High level leakage current, /CE

V

V_{IL_CEZ}

0.4

I_{IN_BIAS_CEZ}

Pull-up rail 1.8 V

2.5 uA

LOGIC O PIN (/INT, /PG, STAT)

V_OL

Output low threshold level

High level leakage current

Sink current = 5 mA

Pull-up rail 1.8 V

0.4

1

V

I_{OUT_BIAS}

µA

7.6 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

VBUS/BAT POWER UP

VBUS rising above V_{BUS_OV}threshold to

converter turn off

t_{VBUS_OV}

VBUS OVP reaction time

Bad adapter detection duration

200

30

ns

t_POORSRC

BATTERY CHARGER

ms

t_{TERM_DGL}

Deglitch time for charge termination

Charge current falling below I_TERM

250

ms

BAT voltage falling below VRECHG = 100

mV

t_{RECGH_DGL}

Deglitch time for recharge threshold

Deglitch time for battery over-voltage

to disable charge

t_{BAT_OVP_DGL}

1

µs

t_{TOP_OFF}

t_SAFETY

I2C INTERFACE

f_SCL

Typical Top-Off Timer Accuracy

Charge Safety Timer Accuracy

TOP_OFF_TIMER = 30 min

CHG_TIMER = 12 hours

24

30

12

36 min

10.8

13.2 hr

SCL clock frequency

Data set-up time

1000 kHZ

ns

t_{SU_STA}

t_{HD_DAT}

t_rDA

10

0

Data hold time

70 ns

80 ns

Rise time of SDA signal

10

Submit Documentation Feedback

11

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Timing Requirements (continued)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

t_fDA

Fall time of SDA signal

10

80 ns

DIGITAL CLOCK AND WATCHDOG TIMER

f_LPDIG

f_DIG

Digital low power clock

Digital clock

REGN LDO disabled

18

30

45 kHZ

REGN LDO enabled

1.35

1.5

1.65 MHz

12

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

7.7 Typical Characteristics

C_VBUS= 1µF, C_PMID= 10µF, C_SYS= 44µF, C_BAT= 10µF, L = 1µH ( IHLP2525CZER1R0k01) (unless otherwise specified)

95

94

93

92

91

90

89

88

87

86

85

100

95

90

85

80

75

70

65

60

VBAT = 7.6 V

VBAT = 8 V

PFM En, OOA En

PFM En, OOA Dis

PFM Dis

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0.01

0.02 0.03 0.050.07 0.1

0.2 0.3

0.5 0.7

1

Charge Current (A)

System Current (A)

D021

D022

VBUS = 5 V

VBAT = 8.4 V

Figure 1. Charge Efficiency vs Charge Current

Figure 2. System Efficiency vs System Current

100

95

90

85

80

75

70

65

60

55

50

10

7.5

5

2.5

0

-2.5

-5

PFM En, OOA En

PFM En, OOA Dis

PFM Dis

-7.5

-10

VBAT = 6.6 V

VBAT = 7.6 V

0.01

OTG_VLIM = 5 V

Figure 3. OTG Efficiency vs VBUS Output Current

0.020.03 0.05

0.1

IBUS (A)

0.2 0.3 0.5 0.7

1

2

0.2

VBUS = 5 V

Figure 4. Charge Current Accuracy vs ICHG Setting

0.4

0.6

0.8

1

1.2

1.4

1.6 1.7

ICHG Setting (A)

D023

D034

VBAT = 7.6 V

225

200

175

150

125

100

75

8.58

8.57

8.56

8.55

8.54

8.53

8.52

8.51

8.50

8.49

8.48

8.47

8.46

8.45

50

25

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

System Current (A)

D026

D027

VBUS = 5 V

VBAT = 6 V

SYS_MIN = 7 V

VBUS = 5 V

VBAT = 8.4 V

EN_CHG = 0

Figure 5. SYSMIN Load Regulation

Figure 6. System Load Regulation After Charge Done

Submit Documentation Feedback

13

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Typical Characteristics (continued)

C_VBUS= 1µF, C_PMID= 10µF, C_SYS= 44µF, C_BAT= 10µF, L = 1µH ( IHLP2525CZER1R0k01) (unless otherwise specified)

0

-1

2

1.5

1

-40èC

25èC

85èC

-40èC

25èC

85èC

-2

-3

-4

-5

0.5

0

-6

-7

-8

-0.5

-1

-9

-10

-11

-12

-13

-14

-1.5

-2

4.5 4.6 4.7 4.8 4.9

5

5.1 5.2 5.3 5.4 5.5

0.4

VBAT = 8 V

Figure 8. OTG IBUS Limit vs OTG_ILIM Setting

0.6

0.8

1

1.2

1.4

1.6

1.8

2

OTG_VLIM Setting (V)

OTG_ILIM Setting (A)

D028

D029

VBAT = 7.6 V

Figure 7. OTG VBUS Regulation vs OTG_VLIM Setting

3.0

2.5

-40èC

0èC

25èC

85èC

-40èC

0èC

25èC

85èC

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

6

6.3

6.6

6.9

7.2

7.5

7.8

8.1

8.4

8.7

0.6

0.8

1

1.2

1.4

1.6

1.8

2

VBAT Voltage (V)

VBUS Current (A)

D030

D031

VOTG = 5.1 V

VBAT = 8 V

Figure 9. OTG Voltage Regulation vs VBAT Voltage

Figure 10. OTG Voltage Regulation vs OTG BUS Current

3.0

0

-1

-2

-3

-4

-40èC

-20èC

25èC

85èC

VBAT = 6.6 V

VBAT = 7.6 V

2.5

2.0

1.5

-5

1.0

-6

-7

-8

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-9

-10

-11

-12

-13

-14

-15

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3

IINDPM Setting (A)

3.8

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

VINDPM Setting (V)

D032

D033

VBUS = 5 V

VBAT = 7.6 V

T_A= 25°C

Figure 11. Input Current Limit Accuracy vs IINDPM Setting

Figure 12. Input Voltage Limit Accuracy vs VINDPM Setting

14

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Typical Characteristics (continued)

C_VBUS= 1µF, C_PMID= 10µF, C_SYS= 44µF, C_BAT= 10µF, L = 1µH ( IHLP2525CZER1R0k01) (unless otherwise specified)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.15

ICHG = 0.5A

ICHG = 1.0A

ICHG = 1.4A

TREG = 60°C

TREG = 80°C

TREG = 100°C

TREG = 120°C

0.1

0.05

0

-0.05

50

60

70

80

90 100 110 120 130 140 150

Die Temperature (°C)

90

95

100

105

110

115

120

125

130

Die Temperature (°C)

D014

D015

VBUS = 5V

VBAT = 7.6V

Figure 13. TREG Profiles

ICHG = 100mA

VBUS = 5V

VBAT = 7.6V

ICHG = 0.5A, 1.0A, 1.4A

Figure 14. Max Current Temperature Profile

Submit Documentation Feedback

15

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8 Detailed Description

8.1 Overview

The BQ25883 device is a highly integrated 2-A switch-mode battery charger for 2s Li-Ion and Li-Polymer battery.

It integrates the input blocking FET (Q1, QBLK), high-side switching FET (Q2, QHS), low-side switching FET

(Q3, QLS), and battery FET (Q4, QBAT). The device also integrates the boot-strap diode for high-side gate drive.

8.2 Functional Block Diagram

VBUS

PMID

V_{VBUS_UVLO_RISING}

QBLK

(Q1)

+

UVLO

QBLK

CONTROL

REGN

BTST

REGN

LDO

EN_HIZ

VBUS_OVP

V_{VBUS_OV}

V_O,REF

SYS

OTG_OVP⁽¹⁾

V_VBUS

+

V_{OTG_OVP}

QHS

(Q2)

OTG_Q2_OCP⁽¹⁾

+

I_Q2

I_HSOCP

V_VBUS

V_INDPM

SYS

+

V_SYSMIN

+

SW

BAT_OVP

BAT

I_IN

BAT

+

QLS

(Q3)

V_{BAT_OVP}

REGN

DC-DC

CONTROL

V_{BAT_REG}

I_INDPM

IC_T_J

T_REG

ICHG

GND

I_{CHG_REG}

EN_CHARGE

I_Q3

+

Q3_OCP

GND

EN_HIZ

I_LSOCP

EN_OTG

V_BTSTœ V_SW

REFRESH

SYS

V_{BTST_REFRESH}

V_POORSRC

CONVERTER

CONTROL

STATE

+

POORSRC

V_VBUS

REF

DAC

IC_T_J

T_SHUT

MACHINE

TSHUT

ICHG

ILIM

IBUS

ICHG

VBUS

VBAT

VSYS

VTS

QBAT

(Q4)

D-

V_{BAT_REG}

I_{CHG_REG}

QBAT

CONTROL

D+

ADC

USB

DETECTION

PG

BAT

TDIE

V_REG- V_RECHG

RECHRG

+

BAT

ICHG

I_TERM

STAT

TERMINATION

BATLOWV

+

CHARGE

CONTROL

STATE

V_{BAT_LOWV}

BAT

MACHINE

INT

V_{BAT_UVLO_RISING}

BATUVLO

+

BAT

BATTERY

SENSING

VTS

I2C

INTERFACE

TS_SUSPEND

TS

THERMISTOR

SCL

SDA

CE

16

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.3 Feature Description

8.3.1 Device Power-On-Reset

The internal bias circuits are powered from either VBAT or VBUS when it rises above V_{VBUS_UVLO_RISING}or

V_{BAT_UVLO_RISING}. When VBUS rises above V_{VBUS_UVLO_RISING}or BAT rises above V_{BAT_UVLO_RISING}, the BATFET

driver is active. I2C interface is ready for communication and all the registers are reset to default value. The host

can access all the registers after POR.

8.3.2 Device Power Up from Battery without Input Source

If only the battery is present and the voltage is above UVLO threshold (V_{BAT_UVLO_RISING}), the BATFET turns on

and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low R_DS(ON)of

BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

8.3.3 Device Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the

bias circuits. It detects and sets the input current limit before the boost converter is started. The power up

sequence from input source is as listed:

1. Poor Source Qualification

2. Input Source Type Detection based on D+/D– to set default Input Current Limit (IINDPM) register and input

source type

3. Power Up REGN LDO

4. Converter Power-up

8.3.3.1 Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has

to meet the following requirements in order to start the boost converter.

1. VBUS voltage below V_{VBUS_OVP}

2. VBUS voltage above V_POORSRCwhen pulling I_POORSRC(typical 30mA)

If V_{BUS_OVP}is detected (condition 1 above), the device automatically retries detection once the over-voltage fault

goes away. If a poor source is detected (condition 2 above), the device repeats poor source qualification routine

every 2 seconds. After 7 consecutive failures, the device goes to HIZ mode. The battery powers up the system

when the device is in HIZ. On BQ25883 adapter re-plugin and/or EN_HIZ bit toggle is required to restart device

operation. The EN_HIZ bit is cleared automatically when the adapter is plugged in. If the fault is not removed, the

part will enter HIZ mode again after the 7 consecutive failures.

8.3.3.2 Input Source Type Detection

After input source is qualified, the charger device runs input source type detection.

The BQ25883 follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source

(SDP/CDP/DCP) and non-standard adapter through USB D+/D- lines. After input source type detection, the

following registers and pins are changed:

1. Input Current Limit (IINDPM) register is changed to set current limit

2. Input Voltage Limit (VINDPM) register is changed to set default limit (if EN_VINDPM_RST = 1, otherwise

VINDPM value remains unchanged)

3. VBUS_STAT bits change to reflect the detected source

4. INT pin pulses to notify the host

5. PG pin is pulled LOW, and PG_STAT bit is set to '1'

After detection is completed, the host can over-write IINDPM or VINDPM registers to change the input current, or

input voltage limit if needed. The charger input current is always limited by the lower of IINDPM register , ILIM

pin, or Input Current Optimizer (ICO) setting when ICO is enabled.

When AUTO_INDET_EN is disabled, the Input Source Type Detection is bypassed, and the Input Current Limit

(IINDPM) register remains unchanged from previous value. When EN_VINDPM_RST is disabled, the Input

Voltage Limit (VINDPM) register remains unchanged from previous value.

Submit Documentation Feedback

17

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Feature Description (continued)

8.3.3.2.1 D+/D– Detection Sets Input Current Limit

The BQ25883 contains a D+/D- based input source detection to program the input current limit. The D+/D-

detection has three major steps: Data Contact Detect (DCD), Primary Detection, and Secondary Detection.

Unknown/500mA

Divider 3/1A

Divider 1/2.1A

Divider 4/2.4A

Non-Standard

Adapter

Data Detection

Contact

Adapter Plug-in

or

FORCE_INDET

Secondary

Detection

Primary

Detection

DCP

(3000mA)

VBUS Detection

(DCD)

USB BC1.2 Standard

CDP

SDP

(1500mA)

(500mA)

Figure 15. D+/D- Detection Flow

Table 2. Non-Standard Adapter Detection

NON-STANDARD

ADAPTER

D+ THRESHOLD

D– THRESHOLD

INPUT CURRENT LIMIT

Divider 1

Divider 3

Divider 4

V_D+within V_{2P8_VTH}

V_D+within V_{2P0_VTH}

V_D+within V_{2P8_VTH}

V_D–within V_{2P0_VTH}

V_D–within V_{2P8_VTH}

2.1A

1A

2.4A

After the Input Source Type Detection is done, an INT pulse is asserted to the host. In addition, the following

registers including Input Current Limit register (IINDPM), and VBUS_STAT are updated as below:

Table 3. Input Current Limit Setting from D+/D– Detection

D+/D– DETECTION

USB SDP (USB500)

USB CDP

INPUT CURRENT LIMIT (IINDPM)

VBUS_STAT

001

500mA

1.5A

3.0A

1A

010

USB DCP

011

Divider 3

110

Divider 1

2.1A

2.4A

500mA

110

Divider 4

110

Unknown 5V Adapter

101

8.3.3.2.2 Force Input Current Limit Detection

In host mode, the host can force the device to run Input Current Limit Detection by setting FORCE_INDET bit.

After the detection is completed, FORCE_INDET bit returns to 0 by itself and input result is updated.

8.3.3.3 Power Up REGN Regulator (LDO)

The REGN LDO supplies internal bias circuits as well as the QHS and QLS gate drive. The LDO also provides

bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well. The

REGN is enabled when all the below conditions are valid.

1. VBUS above V_{VBUS_UVLO_RISING}in boost mode or VBUS below V_{VBUS_UVLO_RISING}in buck mode

2. Poor Source Qualification detects a valid input source

3. Input Source Type Detection completes and sets appropriate input current limit

18

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

4. After 220 ms delay is complete

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The

device draws less than I_{VBUS_HIZ}from VBUS during HIZ state. The battery powers up the system when the device

is in HIZ.

8.3.3.4 Converter Power Up

After the input current limit is set, the PG pin is pulled LOW, the PG_STAT and VBUS_STAT bits are changed,

and the converter is enabled, allowing the HSFET and LSFET to start switching. If battery charging is disabled,

BATFET turns off. Otherwise, BATFET stays on to charge the battery. The device provides soft-start when is

ramped up.

Before charging begins, the battery discharge source (IBAT_DISCHG) is enabled automatically to detect the

presence of battery. The host can enable IBAT_DISCHG via the EN_BAT_DISCHG bit at any point during

operation, including in Battery Only or HIZ modes.

As a battery charger, the device deploys a highly efficient 1.5 MHz boost switching regulator. The fixed frequency

oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,

charge current and temperature, simplifying output filter design.

In order to improve light-load efficiency, the device switches to PFM (Pulse Frequency Modulation) control at light

load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation,

the switching duty cycle is set by the ratio of SYS and VBUS.

8.3.4 Input Current Optimizer (ICO)

The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without

overloading the input source. The algorithm automatically identifies maximum input current limit of a power

source without staying in VINDPM to avoid input source overload.

On BQ25883, this feature is enabled by default (EN_ICO=1) and can be disabled by setting EN_ICO bit to 0.

After DCP type input source is detected based on the procedures describe above (Input Source Type Detection).

The algorithm runs automatically when EN_ICO bit is set. The algorithm can also be forced to execute by setting

FORCE_ICO bit regardless of input source type detected .

Table 4. Input Current Optimizer Automatic Operation

AUTOMATIC START ICO

ALGORITHM WHEN EN_ICO =

1

INPUT CURRENT LIMIT

DEVICE

INPUT SOURCE

(IINDPM)

USB SDP (USB500)

USB CDP

500mA

1.5A

3.0A

1A

Disable

Enable

Disable

USB DCP

BQ25883 (D+/D–)

Divider 3

Divider 1

2.1A

2.4A

500mA

Divider 4

Unknown 5V Adapter

The actual input current limit used by the Dynamic Power Management is reported in ICO_ILIM register while

Input Current Optimizer is enabled (EN_ICO = 1) or set by IINDPM register when the algorithm is disabled

(EN_ICO=0). In addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin

function.

When the algorithm is enabled, it runs continuously to adjust input current limit of Dynamic Power Management

(IINDPM) using ICO_ILIM register until ICO_STAT[1:0] and ICO_FLAG bits are set (the ICO_FLAG bit indicates

any change in ICO_STAT[1:0] bits). The algorithm operates depending on battery voltage:

1. When voltage at BAT pin is below SYS_MIN, the algorithm starts ICO_ILIM register with IINDPM which is the

maximum input current limit allowed by system

2. When voltage at BAT is above SYS_MIN, the algorithm starts ICO_ILIM register with 500mA which is the

minimum input current limit to minimize adapter overload

Submit Documentation Feedback

19

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

When optimal input current is identified, the ICO_STAT[1:0] and ICO_FLAG bits are set to indicate input current

limit in ICO_ILIM register would not be changed until the algorithm is forced to run by the following event (these

events also reset the ICO_STAT[1:0] bits to '01'):

1. A new input source is plugged-in, or EN_HIZ bit is toggled

2. IINDPM register is changed

3. VINDPM register is changed

4. FORCE_ICO bit is set to 1

5. VBUS_OVP event

8.3.5 Buck Mode Operation from Battery (OTG)

The device supports buck converter operation to deliver power from the battery to other portable devices through

USB port. The buck mode output current rating meets the USB On-The-Go 500 mA (OTG_ILIM bits = 000)

output requirement. The maximum output current is up to 2.0 A. The buck operation can be enabled if the

following conditions are valid:

1. BAT above V_{OTG_BAT}

2. VBUS less than V_{VBUS_PRESENT}

3. ADC is enabled

4. Buck mode operation is enabled (EN_OTG = 1 and EN_CHG = 0)

5. Voltage at TS (thermistor) pin is within range configured by Buck Mode Temperature Monitor as configured

by BHOT and BCOLD register bits

6. After 30 ms delay from buck mode enable

In buck mode, the device employs 1.5 MHz step-down switching regulator based on system requirements.

During buck mode, the status register VBUS_STAT bits are set to 111, the VBUS output is 5.1V by default

(selectable via OTG_VLIM register bits) and the output current can reach up to 2.0 A, selected via I2C

(OTG_ILIM bits). The buck output is maintained when BAT is above V_{OTG_BAT}threshold, and VBUS is above

V_{VBUS_PRESENT}threshold. After OTG startup, the ADC maybe disabled.

8.3.6 Power Path Management

The device accommodates a wide range of input sources from USB, to wall adapter, to power bank. The device

provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or

both.

8.3.6.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated

above the minimum system voltage (default 6.2V ).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is typically 200mV above the minimum system voltage setting. As the battery voltage rises above

the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is

the V_DSof BATFET.

When the battery charging is disabled and VBAT is above minimum system voltage setting or charging is

terminated, the system is always regulated at typically 50mV above battery voltage. The status register

VSYS_STAT bit goes high when the system is in minimum system voltage regulation.

20

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

9.0

8.6

8.2

Charge Enabled

7.8

7.4

7.0

Charge Disabled

Minimum System Voltage

6.6

6.2

5.4

5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6

BAT (V)

Figure 16. System Voltage vs. Battery Voltage

8.3.6.2 Dynamic Power Management

To meet the maximum current limit in the USB spec and avoid over loading the adapter, the device features

Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When

input source is over-loaded, either the current exceeds the input current limit (IINDPM or ICO_ILIM or ILIM pin

setting) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current

until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the Supplement

Mode where the BATFET turns on and battery starts discharging so that the system is supported from both the

input source and battery.

During DPM mode, the status register bits VINDPM_STAT (VINDPM) and/or IINDPM_STAT (IINDPM) go high.

The figure shows the DPM response with 5V/3A adapter, 6.4V battery, 1.5A charge current and 6.8V minimum

system voltage setting.

Submit Documentation Feedback

21

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

V_SYS

7.0V

6.8V

V_BAT

6.4V

6.0V

V_BUS

5.0V

4.0V

3A

I_BUS

2A

I_BAT

1A

I_SYS

0A

-1A

DPM

CC

DPM

CC

Supplement

Figure 17. DPM Response

8.3.6.3 Supplement Mode

When the voltage falls below the battery voltage, the BATFET turns on.

As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce R_DSONuntil the

BATFET is in full conduction. At this point onwards, the BATFET V_DSlinearly increases with discharge current.

The figure shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit Supplement

Mode when the battery is below battery depletion threshold (V_{BAT_UVLO_RISING}).

90

85

80

75

70

65

60

55

50

45

40

35

30

25

20

15

10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

IBAT(A)

D001

Figure 18. BATFET I-V Curve

22

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.3.7 Battery Charging Management

The BQ25883 charges 2-cell Li-Ion battery with up to 2.2-A charge current for high capacity battery. The low

R_DS(ON)BATFET improves charging efficiency and minimize the voltage drop during discharging.

8.3.7.1 Autonomous Charging Cycle

When battery charging is enabled (EN_CHG bit =1 and CE pin is LOW; ), the device autonomously completes a

charging cycle without host involvement. The device default charging parameters are listed in Table below. On

BQ25883, the host can always control the charging operation and optimize the charging parameters by writing to

the corresponding registers through I²C.

Table 5. Charging Parameter Default Settings

DEFAULT MODE

Charging Voltage

Charging Current

Pre-Charge Current

Termination Current

Temperature Profile

Safety Timer

BQ25883

8.40 V

1.50 A

150 mA

JEITA

12 hours

Disabled

Topoff Timer

A new charge cycle starts when the following conditions are valid:

1. Converter starts

2. Battery charging is enabled by I2C register bit (EN_CHG = 1 and CE pin is LOW and ICHG register is not 0

mA)

3. No thermistor fault on TS

4. No safety timer fault

The charger device automatically terminates the charging cycle when the charging current is below termination

threshold, charge voltage is above recharge threshold, and device is not in DPM mode or thermal regulation.

When a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG[1:0] bits

on BQ25883), the device automatically starts a new charging cycle. After the charge is done, either toggle CE

pin or EN_CHG bit can initiate a new charging cycle.

The STAT output indicates the charging status of: charging (LOW), charging complete or charge disable (HIGH)

or charging fault (Blinking). If no battery is connected, the STAT pin blinks as capacitance connected at BAT

charges, discharges, then recharges. The STAT output can be disabled by setting STAT_DIS bit. In addition, the

status register (CHRG_STAT) indicates the different charging phases as:

•

000 – Not Charging

001 – Trickle Charge (VBAT < V_{BAT_SHORT}

010 – Pre-charge (V_{BAT_SHORT}< VBAT < V_{BAT_LOWV}

011 – Fast-charge (CC mode)

100 – Taper Charge (CV mode)

101 – Top-off Timer Charging

110 – Charge Termination Done

)

8.3.7.2 Battery Charging Profile

The device charges the battery in five phases: trickle charge, pre-charge, constant current, constant voltage, and

top-off timer charging. At the beginning of a charging cycle, the device checks the battery voltage and regulates

current/voltage accordingly.

Table 6. Default Charging Current Setting

VBAT

CHARGING CURRENT

I_{BAT_SHORT}

REGISTER DEFAULT SETTING

CHRG_STAT

< V_{BAT_SHORT}

100 mA

150 mA

001

010

V_{BAT_SHORT}– V_{BAT_LOWV}

I_PRECHG

Submit Documentation Feedback

23

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Table 6. Default Charging Current Setting (continued)

VBAT

CHARGING CURRENT

REGISTER DEFAULT SETTING

CHRG_STAT

011

> V_{BAT_LOWV}

I_CHG

1500 mA

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will

be less than the programmed value. In this case, termination is temporarily disabled and the charging safety

timer is counted at half the clock rate, as explained in the Charging Safety Timer section.

Regulation Voltage

VREG[7:0]

Battery Voltage

Charge Current

ICHG[5:0]

Charge Current

V_BATLOWV

V_{BAT_SHORT}

IPRECHG[3:0]

ITERM[3:0]

I_{BAT_SHORT}

Trickle Charge

001

Pre-charge

010

Fast-Charge

CC

Taper-Charge

CV

Top-off Timer

(optional)

CHRG_STAT[2:0]

011

101

110

100

Precharge Timer

(2hrs)

Safety Timer

CHG_TIMER[1:0]

Figure 19. Battery Charging Profile

8.3.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is

below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps

running to power the system, and BATFET can turn on again to engage Supplement Mode.

When termination occurs, the STAT pin goes HIGH (charge current will continue to taper if top-off timer is

enabled), status register CHRG_STAT is set to 110, and an INT pulse is asserted to the host. Termination is

temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can

be permanently disabled by writing 0 to EN_TERM bit prior to charge termination.

At low termination currents (50mA-100mA), due to the comparator offset, the actual termination current may be

up to 20% higher than the termination target. In order to compensate for comparator offset, a programmable top-

off timer (default disabled) can be applied after termination is detected.The top-off timer will follow safety timer

constraints, such that if safety timer is suspended, so will the top-off timer. Similarly, if safety timer is doubled, so

will the top-off timer. CHRG_STAT reports whether the top off timer is active via the 101 code. Once the Top-Off

timer expires, the CHRG_STAT register is set to 110 and an INT pulse is asserted to the host.

Top-off timer gets reset (set to 0 and counting resumes when appropriate) for any of the following conditions:

24

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

1. Charge disable to enable

2. Termination status low to high

3. REG_RST register bit is set (disables top-off timer)

The top-off timer settings are read in once termination is detected by the charger. Programming a top-off timer

value after termination will have no effect unless a recharge cycle is initiated. An INT is asserted to the host

when entering top-off timer segment as well as when top-off timer expires. All charge cycle related INT pulses

(including top-off timer INT pulses) can be masked by CHRG_MASK bit.

8.3.7.4 Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

8.3.7.4.1 JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline

emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high

temperature ranges.

To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds

the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5

range. At cool temperature (T1-T2), JEITA recommends the charge current to be reduced to half of the charge

current or lower. At warm temperature (T3-T5), JEITA recommends charge voltage less than 4.1V / cell.

On BQ25883, the charger provides flexible voltage/current settings beyond the JEITA requirement. The voltage

setting at warm temperature (T3-T5) can be VREG, 8.0V, 8.3V, or charge suspend (configured by JEITA_VSET

[1:0]). The fast charge current setting at warm temperature (T3-T5) can be 100%, or 40% of fast charge current,

ICHG (configured by JEITA_ISETH). The fast charge current setting at cool temperature (T1-T2) can be 100%,

40%, or 20% of fast charge current, ICHG, or charge suspend (configured by JEITA_ISETC[1:0]). Whenever the

charger detects "warm" or "cool" temperature, termination is automatically disabled regardless of JEITA_VSET,

JEITA_ISETH and JEITA_ISETC register bit settings.

REGN

TS

BQ2588x

Figure 20. TS Resistor Network

ISETC=11

VSET =11

ISETH=1

100%

V_REG

80%

60%

40%

20%

VSET =10

VSET = 01

8.3V

8.0V

ISETC=10

ISETC=01

ISETC=00

ISETH=0

VSET = 00

T1

0°C

T2

10°C

T3

45°C

T5

60°C

T1

0°C

T2

10°C

T3

45°C

T5

60°C

TS Temperature

Submit Documentation Feedback

25

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Figure 21. TS Charging Values

Assuming a 103AT NTC (Negative Temperature Coefficient) thermistor on the battery pack as shown above, the

value of RT1 and RT2 can be determined by:

≈

∆

«

’

÷

◊

1

R_NTC,T1ì R_{NTC,T 5}

ì

-

V_{T 5}V_T1

RT2 =

RT1=

≈

∆

«

’

≈

∆

«

’

÷

◊

1

R_NTC,T1

ì

-1 - R

ì

-1

÷

NTC,T 5

V_T1

V_{T 5}

◊

(1)

(2)

1

-1

V_T1

1

+

R_{T 2}R_NTC,T1

Select 0°C to 60°C range for Li-ion or Li-polymer battery:

R_NTC,T1= 27.28kΩ

R_NTC,T5= 3.02kΩ

RT1 = 5.24kΩ

RT2 = 30.31kΩ

8.3.7.4.2 Cold/Hot Temperature Window in OTG Buck Mode

For battery protection during OTG buck mode, the device monitors the battery temperature to be within the

VBCOLD to VBHOT thresholds. When temperature is outside of the temperature thresholds, the OTG mode is

suspended. In addition, VBUS_STAT bits are set to 000 and corresponding TS_STAT is reported. Once

temperature returns within thresholds, the OTG mode is recovered and TS_STAT is cleared.

Temperature Range for OTG Buck Mode

VREGN

Buck Disable

V_BCOLDx

(œ10°C / œ20°C)

Buck Enable

V_BHOTx

(55°C / 60°C / 65°C)

Buck Disable

GND

Figure 22. TS Pin Thermistor Sense Threshold in OTG Buck Mode

26

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.3.7.5 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The

user can program fast charge safety timer through I²C (CHG_TIMER bits). When safety timer expires, the fault

register TMR_STAT bit is set to 1, and an INT pulse is asserted to the host. The safety timer feature can be

disabled by clearing EN_TIMER bit.

During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge

current is likely to be below the register setting. For example, if the charger is in input current regulation

(IINDPM_STAT=1) throughout the whole charging cycle, and the safety timer is set to 12 hours, then the timer

will expire in 24 hours. This half clock rate feature can be disabled by setting TMR2X_EN = 0. Changing the

TMR2X_EN bit while the device is running has no effect on the safety timer count, other than forcing the timer to

count at half the rate under the conditions dictated above.

During faults which disable charging, or supplement mode, timer is suspended. Since the timer is not counting in

this state, the TMR2X_EN bit has no effect. Once the fault goes away, safety timer resumes. If the charging

cycle is stopped and started again, the timer gets reset (toggle CE pin or EN_CHG bit restarts the timer).

The safety timer is reset for the following events:

1. Charging cycle stop and restart (toggle CE pin, EN_CHG bit, or charged battery falls below recharge

threshold).

2. BAT voltage changes from pre-charge to fast-charge or vice versa (in host-mode or default mode).

The precharge safety timer (fixed 2hr counter that runs when VBAT < V_{BAT_LOWV}), follows the same rules as the

fast-charge safety timer in terms of getting suspended, reset, and counting at half-rate when TMR2X_EN is set.

8.3.8 Integrated 16-Bit ADC for Monitoring

The device includes a 16-bit ADC to monitor critical system information based on the device’s modes of

operation. The control of the ADC is done through the ADC Control Register (Address = 15h) [reset = 30h]. The

ADC_EN bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows

continuous conversion or one-shot behavior. After a one-shot conversion finishes, the ADC_EN bit is cleared,

and must be re-asserted to start a new conversion.

To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either the

V_VBUS>V_{VBUS_UVLO_RISING}or V_BAT>V_{BAT_UVLO_RISING}is valid. If no adapter is present, and the VBAT is less than

V_{BAT_UVLO_RISING}, the device will not perform an ADC measurement, nor update the ADC read-back values in

REG17 through REG24. Additionally, the device will immediately reset ADC_EN bit without sending any interrupt.

The same will happen if the ADC is enabled when all ADC channels are disabled. It is recommended to read

back ADC_EN after setting it to '1' to ensure ADC is running a conversion. If the charger changes mode (for

example, if adapter is connected, EN_HIZ goes to '1', or EN_OTG goes to '1') while an ADC conversion is

running, the conversion is interrupted. Once the mode change is complete, the ADC resumes conversion,

starting with the channel where it was interrupted. When device is in HIZ mode, ADC conversion can still be

enabled through I2C. In HIZ mode, device power up internally to start ADC convertion and turn back down when

ADC conversion is completed.

When TS_ADC conversion performs in battery only mode, the REGN is powered and extra battery current would

be drawn. Battery current can be kept low by disabling the TS_ADC conversion in battery only mode.

The integrated ADC has two rate conversion options: a one-shot mode and a continuous conversion mode set by

the ADC_RATE bit. By default, all ADC parameters will be converted in one-shot or continuous conversion mode

unless disabled in the ADC Function Disable Register (Address = 16h) [reset = 00h]. If an ADC parameter is

disabled by setting the corresponding bit in REG16, then the read-back value in the corresponding register will

be from the last valid ADC conversion or the default POR value (all zeros if no conversions have taken place). If

an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish the conversion

of that parameter, but will not convert the parameter starting the next conversion cycle. Even though no

conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is active and

ready to begin conversion as soon as one of the bits in the ADC Function Disable register is set to ‘0’. If all

channels are disabled in one-shot conversion mode, the ADC_EN bit is cleared.

The ADC_DONE_STAT and ADC_DONE_FLAG bits signal when a conversion is completed in one-shot mode

only. This event produces an INT pulse, which can be masked with ADC_DONE_MASK. During continuous

conversion mode, the ADC_DONE_STAT bit has no meaning and will be '0'. The ADC_DONE_FLAG bit will

remain unchanged in continuous conversion mode.

Submit Documentation Feedback

27

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

ADC conversion operates independently of the faults present in the device. ADC conversion will continue even

after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set

ADC_EN = ‘0’ to disable the ADC. ADC conversion is interrupted upon adapter plug-in, and will only resume until

after Input Source Type Detection is complete. ADC readings are only valid for DC states and not for transients.

When host writes ADC_EN=0, the ADC stops immediately, and ADC measurement values correspond to last

valid ADC reading.

A recommended method to exit ADC conversion is described below:

1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or

2. Disable all ADC conversion channels, and the ADC will stop at the end of the current measurement.

8.3.9 Status Outputs

8.3.9.1 Power Good Indicator (PG)

The PG_STAT bit goes HIGH and open drain PG pin goes low to indicate a good input source when:

1. VBUS above V_{VBUS_UVLO_RISING}

2. VBUS below V_{VBUS_OV}threshold

3. VBUS above V_POORSRC(typ. 3.7 V) when I_POORSRC(typ. 30 mA) current is applied (not a poor source)

4. Input Source Type Detection is completed

8.3.9.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.

Table 7. STAT Pin State

CHARGING STATE

STAT INDICATOR

Charging in progress (including trickle charge, pre-charge, fast-

charge, recharge)

LOW

Charging complete (including top-off)

Sleep mode, charge disable

HIGH

Charge suspend (Input over-voltage, TS fault, timer fault or battery

over-voltage)

Blinking at 1Hz

OTG Buck Mode suspend (due to TS fault)

8.3.9.3 Interrupt to Host

In some applications, the host does not always monitor the charger operation. The INT pin notifies the system

host on the device operation. By default, the following events will generate an active-low, 256µs INT pulse.

1. Good input source detected

–

V_VBUS< V_{VBUS_OV}threshold

V_VBUS> V_POORSRC(typ. 3.7 V) when I_POORSRC(typ. 30 mA) current is applied (not a poor source)

2. VBUS_STAT changes state (VBUS_STAT any bit change)

3. Good input source removed

4. Entering IINDPM regulation

5. Entering VINDPM regulation

6. Entering IC junction temperature regulation (TREG)

7. I2C Watchdog timer expired

–

At initial power up, this INT gets asserted to signal I2C is ready for communication

8. Charger status changes state (CHRG_STAT value change), including Charge Complete

9. TS_STAT changes state (TS_STAT any bit change)

10. VBUS over-voltage detected (VBUS_OVP)

11. Junction temperature shutdown (TSHUT)

12. Battery over-voltage detected (BATOVP)

28

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

13. Charge safety timer expired

14. A rising edge on any of the *_STAT bits

Each one of these INT sources can be masked off to prevent INT pulses from being sent out when they occur.

Three bits exist for each one of these events:

•

The STAT bit holds the current status of each INT source

The FLAG bit holds information on which source produced an INT, regardless of the current status

The MASK bit is used to prevent the device from sending out INT for each particular event

When one of the above conditions occurs (a rising edge on any of the *_STAT bits), the device sends out an INT

pulse and keeps track of which source generated the INT via the FLAG registers. The FLAG register bits are

automatically reset to zero after the host reads them, and a new edge on STAT bit is required to re-assert the

FLAG.

IINDPM_STAT

IINDPM_FLAG

TREG_STAT

TREG_FLAG

INT

I2C Flag Read

Figure 23. INT Generation Behavior Example

8.3.10 Input Current Limit on ILIM Pin

For safe operation, the BQ2588x has an additional hardware pin on ILIM to limit maximum input current. The

maximum input current is set by a resistor from ILIM pin to ground as:

K_ILIM

=

I

INMAX

R_ILIM

(3)

Submit Documentation Feedback

29

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

The actual input current limit is the lower value between ILIM pin setting and register setting (IINDPM). For

example, if the register setting is 3.3A (0x1C), and ILIM has a 820-Ω resistor (KILIM = 1276 max) to ground for

1.55A, the input current limit is 1.55A. ILIM pin can be used to set the input current limit rather than the register

settings when EN_ILIM bit is set. The device regulates ILIM pin at 0.8V. If ILIM voltage exceeds 0.8V, the device

enters input current regulation (Refer to Dynamic Power Management section). Entering IINDPM through ILIM

pin sets the IINDPM_STAT and FLAG bits, and produces and interrupt to host. The interrupt can be masked via

the IINDPM_MASK bit.

The ILIM pin can also be used to monitor input current when EN_ILIM is set. The voltage on ILIM pin is

proportional to the input current. ILIM can be used to monitor input current with the following relationship:

K_ILIMìV_ILIM

R_ILIMì0.8V

I_IN

=

(4)

For example, if ILIM pin is set with 820-Ω resistor, and the ILIM voltage 0.5V, the actual input current is 0.795A to

0.973A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 0.8V. If ILIM pin is

shorted, the input current limit is set by the register.

The ILIM pin function can be disabled by setting the EN_ILIM bit to 0. When the pin is disabled, both input

current limit function and monitoring function are not available.

8.3.11 Voltage and Current Monitoring

The device closely monitors the input voltage and system voltage, as well as internal FET currents for safe boost

and buck mode operation.

8.3.11.1 Voltage and Current Monitoring in Boost Mode

8.3.11.1.1 Input Over-Voltage Protection

The valid input voltage range for boost mode operation is V_{VBUS_OP}. If VBUS voltage exceeds V_{VBUS_OV}, the

device stops switching immediately to protect the power FETs. During input over-voltage, an INT pulse is

asserted to signal the host, and the VBUS_OVP_STAT and VBUS_OVP_FLAG fault registers get set. The

device automatically starts switching again when the over-voltage condition goes away.

8.3.11.1.2 Input Under-Voltage Protection

The valid input voltage range for boost mode operation is V_{VBUS_OP}. If VBUS voltage falls below V_POORSRCduring

operation, the device stops switching. During input under-voltage, an INT pulse is asserted to signal the host,

and the PG_STAT bit gets cleared. The PG_FLAG bit will get set to signal this event. The device automatically

attempts to restart switching when the under-voltage condition goes away.

8.3.11.1.3 System Over-Voltage Protection

The charger device clamps the system voltage during load transient so that the components connect to system

would not be damaged due to high voltage. SYSOVP threshold is 350 mV above system regulation voltage.

Upon SYSOVP, converter stops immediately to clamp the overshoot.

8.3.11.1.4 System Over-Current Protection

The charger device continually monitors and compares VBUS to VSYS to protect against a system short-circuit

event. In the event that VSYS drops to within 250 mV of VBUS during operation, a short circuit event is flagged

and the converter stops switching. The SYS_SHORT_FLAG or SNS_SHORT_FLAG bit is set and an INT pulse

is asserted to the host. The device attempts to recover from this condition automatically.

8.3.11.2 Voltage and Current Monitoring in OTG Buck Mode

The device closely monitors the VBUS voltage, as well as RBFET (Q1, QBLK) and LSFET (Q3, QLS) current to

ensure safe buck mode operation.

8.3.11.2.1 VBUS Over-voltage Protection

When the VBUS voltage rises above regulation target and exceeds V_{OTG_OVP}, the device enters over-voltage

protection which stops switching, clears the EN_OTG bit and exits buck mode. During the over-voltage duration,

the OTG_FLAG bits are set high to indicate a fault in buck mode operation. An INT is also asserted to the host.

30

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.3.11.2.2 VBUS Over-Current Protection

The device monitors output current to provide output short protection. The OTG buck mode has built-in constant

current regulation to allow OTG to adapt to various types of loads. If short circuit is detected on VBUS, the OTG

turns off and retries 7 times. If the retries are not successful, OTG is disabled with EN_OTG bit cleared. In

addition OTG_FLAG bits are set high to indicate the fault, and an INT is asserted to the host.

8.3.12 Thermal Regulation and Thermal Shutdown

8.3.12.1 Thermal Protection in Boost Mode

The device monitors internal junction temperature, T_J, to avoid overheating and limits the IC surface temperature

in boost mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits),

the device reduces charge current. A wide thermal regulation range from 60°C to 120°C allows optimization for

the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed value in ICHG registers.

Therefore, termination is disabled, the safety timer runs at half the clock rate, the status register TREG_STAT bit

goes high, and an INT is asserted to the host.

Additionally, the device has thermal shutdown to turn off the converter when IC surface temperature exceeds

T_SHUT. The fault register bits TSHUT_STAT and TSHUT_FLAG are set and an INT pulse is asserted to the host.

The converter turns back on when IC temperature is below T_{SHUT_HYS}

.

8.3.12.2 Thermal Protection in OTG Buck Mode

The BQ2588x monitors the internal junction temperature to provide thermal shutdown during OTG buck mode.

8.3.13 Battery Protection

8.3.13.1 Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at 4% above the battery regulation voltage while charging. When

battery over-voltage occurs, the charger device immediately disables charge. The fault register BATOVP_STAT

bit goes high and an INT pulse is asserted to signal the host. The battery regulation voltage can be changed by

JEITA_VSET bits and battery temperature, but BATOVP set point will not change.

8.3.13.2 Battery Over-Discharge Protection

When the battery is discharged below V_{BAT_SHORT_HYS}, the BATFET is turned off to protect battery from over-

discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is

plugged in, the BATFET turns on. The battery is charged with I_{BAT_SHORT}current when the VBAT < V_{BAT_SHORT}, or

pre-charge current as set in IPRECHG registers when the battery voltage is between V_{BAT_SHORT}and V_{BAT_LOWV}

.

8.3.14 Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial

data line (SDA), and a serial clock line (SCL). Devices can be considered as masters or slaves when performing

data transfers. A master is a device which initiates a data transfer on the bus and generates the clock signals to

permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 0x6B, receiving control inputs from the master device like

micro-controller or digital signal processor through REG00 – REG25. Register read beyond REG25 (0x25),

returns 0xFF. The I2C interface supports both standard mode (up to 100kbits/s), and fast mode (up to

400kbits/s). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be

connected to the positive supply voltage via a current source or pull-up resistor.

8.3.14.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on SCL line is LOW. One clock pulse is generated for each data

bit transferred.

Submit Documentation Feedback

31

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

SDA

SCL

Data line stable;

Data valid

Change of

data allowed

Figure 24. Bit Transfers on the I2C bus

8.3.14.2 START and STOP Conditions

All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

Figure 25. START and STOP conditions on the I2C bus

START (S)

8.3.14.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most

Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has

performed some other function, it can hold the SCL line low to force the master into a wait state (clock

stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL

line.

32

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Acknowledgeme

nt signal from

receiver

Acknowledgement

signal from slave

MSB

1

SDA

2

7

8

9

1

2

8

9

SCL S or Sr

P or Sr

ACK

START or

Repeated

START

STOP or

Repeate

d START

Figure 26. Data Transfer on the I2C Bus

8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The ACK signaling takes place after byte. The ACK bit allows the receiver to signal the transmitter that the byte

was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9^thclock

pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this 9^thclock pulse.

A NACK is signaled when the SDA line remains HIGH during the 9^thclock pulse. The master can then generate

either a STOP to abort the transfer or a repeated START to start a new transfer.

8.3.14.5 Slave Address and Data Direction Bit

After the START signal, a slave address is sent. This address is 7 bits long, followed by the 8 bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

The device 7-bit address is defined as 1101 011' (0x6B) by default. The address bit arrangement is shown

below.

Slave Address

1

0

1

0

1

R/W

Figure 27. 7-Bit Addressing (0x6B)

SDA

SCL

S

8

9

8

9

8

9

P

1-7

DATA

START

ADDRESS

R/W ACK

DATA

ACK

STOP

Figure 28. Complete Data Transfer on the I2C Bus

8.3.14.6 Single Write and Read

Figure 29. Single Write

Submit Documentation Feedback

33

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Figure 30. Single Read

If the register address is not defined, the charger IC sends back NACK and returns to the idle state.

8.3.14.7 Multi-Write and Multi-Read

The charger device supports multi-read and multi-write of all registers.

Figure 31. Multi-Write

Figure 32. Multi-Read

8.4 Device Functional Modes

8.4.1 Host Mode and Default Mode

The BQ2588x is a host controlled charger, but it can operate in default mode without host management. In

default mode, the device can be used as an autonomous charger with no host or while host is in sleep mode.

When the charger is in default mode, WD_STAT bit is HIGH. When the charger is in host mode, WD_STAT bit is

LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the

registers are in the default settings.

In default mode, the device keeps charging the battery with default 12-hour fast charging safety timer. At the end

of the 12-hour, the charging is stopped and the boost converter continues to operate to supply system load.

A I2C write to the registers transitions the charger from default mode to host mode and watchdog timer is reset.

All the device parameters can be programmed by the host. To keep the device in host mode, the host has to

reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WD_STAT bit is set), or

disable watchdog timer by setting WATCHDOG bits=00.

34

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Device Functional Modes (continued)

When the watchdog timer (WD_STAT bit = 1) is expired, the device returns to default mode and all registers are

reset to default values except as detailed in the Register Maps section. The Watchdog timer will be reset on any

write if the watchdog timer has expired.

POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Y

I2C Write?

N

Start watchdog timer

Host programs registers

Default Mode

Reset watchdog timer

Reset selective registers

Y

N

WD_RST bit = 1?

N

Y

I2C Write?

Watchdog Timer

Expired?

Figure 33. Watchdog Timer Flow Chart

8.5 Register Maps

Default I2C Slave Address: 0x6B (1101 011B + R/W)

Table 8. I²C Registers

Address

00h

Access Type

Acronym

REG00

REG01

REG02

REG03

REG04

REG05

REG06

REG07

REG08

REG09

REG0A

REG0B

REG0C

REG0D

REG0E

Register Name

Section

Go

R/W

R

Battery Voltage Limit

Charge Current Limit

Input Voltage Limit

Input Current Limit

Precharge and Termination Control

Charger Control 1

Charger Control 2

Charger Control 3

Charger Control 4

OTG Control

01h

Go

02h

Go

03h

Go

04h

Go

05h

Go

06h

Go

07h

Go

08h

Go

09h

Go

0Ah

0Bh

0Ch

0Dh

0Eh

ICO Current Limit

Charger Status 1

Charger Status 2

NTC Status

Go

R

Go

R

Go

R

Go

R

FAULT Status

Go

Submit Documentation Feedback

35

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Table 8. I²C Registers (continued)

Address

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

Access Type

Acronym

REG0F

REG10

REG11

REG12

REG13

REG14

REG15

REG16

REG17

REG18

REG19

REG1A

REG1B

REG1C

REG1D

REG1E

REG1F

REG20

REG21

REG22

REG23

REG24

REG25

Register Name

Charger Flag 1

Charger Flag 2

Fault Flag

Section

Go

R

R/W

R

Charger Mask 1

Charger Mask 2

Fault Mask

ADC Control

ADC Function Disable

IBUS ADC1

R

IBUS ADC0

R

ICHG ADC1

ICHG ADC0

VBUS ADC1

VBUS ADC0

VBAT ADC1

VBAT ADC0

VSYS ADC1

VSYS ADC0

TS ADC1

R

TS ADC0

R

TDIE ADC1

R

TDIE ADC0

R/W

Part Information

Complex bit access types are encoded to fit into small table cells. Table 9 shows the codes that are used for

access types in this section.

Table 9. I²C Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

Reset Value

-n

Value after reset

Undefined value

-X

36

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.1 Battery Voltage Regulation Limit Register (Address = 00h) [reset = A0h]

REG00 is shown in Figure 34 and described in Table 10.

Return to Summary Table.

Figure 34. REG00 Register

Bit

7

6

5

4

3

2

1

0

Reset

Field

A0h

VREG[7:0]

Table 10. REG00 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VREG[7]

VREG[6]

VREG[5]

VREG[4]

VREG[3]

VREG[2]

VREG[1]

VREG[0]

R/W

Yes

1280 mV

640 mV

320 mV

160 mV

80 mV

Battery Charge voltage limit

Offset: 6.80 V

Range: 6.80 V to 9.20 V

Default 8.40 V

Yes

40 mV

Yes

20 mV

Yes

10 mV

Submit Documentation Feedback

37

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.2 Charger Current Limit Register (Address = 01h) [reset = 5Eh]

REG01 is shown in Figure 35 and described in Table 11.

Return to Summary Table.

Figure 35. REG01 Register

Bit

7

0h

6

1h

5

4

3

2

1

0

Reset

Field

1Eh

EN_HIZ

EN_ILIM

ICHG[5:0]

Table 11. REG01 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

EN_HIZ

R/W

Yes

Enable HIZ Mode:

0 – Disable (default)

1 – Enable

6

EN_ILIM

R/W

Yes

Enable ILIM Pin Function:

0 – Disable

1 – Enable (default)

5

4

3

2

1

0

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

R/W

Yes

1600 mA

800 mA

400 mA

200 mA

100 mA

50 mA

Fast Charge Current Limit

Offset: 100 mA

Range: 100mA – 2200mA

Default 1500 mA

Note: ICHG > 2.2A (2Ch) clamped to 2.2A. ICHG < 100mA (01h)

clamped at 100mA

38

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.3 Input Voltage Limit Register (Address = 02h) [reset = 84h]

REG02 is shown in Figure 36 and described in Table 12.

Return to Summary Table.

Figure 36. REG02 Register

Bit

7

6

5

4

3

2

1

0

Reset

Field

1h

0h

04h

EN_VINDPM_R EN_BAT_DISC PFM_OOA_DIS

ST HG

VINDPM[4:0]

Table 12. REG02 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

EN_VINDPM_RST

R/W

Yes

Enable VINDPM automatic reset upon adapter plugin:

0 – Disable VINDPM reset when adapter is plugged in

1 – Enable VINDPM reset when adapter is plugged in (VINDPM resets to default

value after Input Source Type Detection) (Default)

6

5

EN_BAT_DISCHG

PFM_OOA_DIS

R/W

Yes

No

Enable BAT pin discharge load (IBAT_DISCHG):

0 – Disable load (Default)

1 – Enable BAT discharge load

PFM Out-of-Audio (OOA) Mode Disable:

0 – Out-of-audio mode enabled while converter is in PFM (Default)

1 – Out-of-audio mode disabled while converter is in PFM

4

3

2

1

0

VINDPM[4]

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

R/W

Yes

No

1600 mV

800 mV

400 mV

200 mV

100 mV

Absolute Input Voltage Limit:

Offset: 3.9 V

Range: 3.9V – 5.5V

Default: 4.3 V

Note: VINDPM > 5.5V (10h) clamped to 5.5V. VINDPM register is

reset upon adapter plug-in if EN_VINDPM_RST = 1.

Submit Documentation Feedback

39

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.4 Input Current Limit Register (Address = 03h) [reset = 39h ]

REG03 is shown in Figure 37 and described in Table 13.

Return to Summary Table.

Figure 37. REG03 Register

Bit

7

0h

6

0h

5

1h

4

3

2

1

0

Reset

Field

19h

FORCE_ICO

FORCE_INDET

EN_ICO

IINDPM[4:0]

Table 13. REG03 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

FORCE_ICO

R/W

Yes

Force Start Input Current Optimizer (ICO):

0 – Do not force ICO (default)

1 – Force ICO start

Note: This bit can only be set and always returns 0 after ICO starts. This bit only

valid when EN_ICO = 1.

6

5

FORCE_INDET

EN_ICO

R/W

Yes

No

Force D+/D– Detection:

0 – Not in D+/D– detection (default)

1 – Force D+/D– detection

Input Current Optimization (ICO) Algorithm Control:

0 – Disable ICO

1 – Enable ICO (default)

4

3

2

1

0

IINDPM[4]

IINDPM[3]

IINDPM[2]

IINDPM[1]

IINDPM[0]

R/W

Yes

No

1600 mA

800 mA

400 mA

200 mA

100 mA

Input Current Limit:

Offset: 500 mA

Range: 500mA – 3300mA

Default: 3000mA

Note: IINDPM > 3300 mA (1Ch) clamped to 3300mA. Actual input

current limit is lower of I2C, ICO_ILIM,ILIM pin or D+/D-.

40

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.5 Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]

REG04 is shown in Figure 38 and described in Table 14.

Return to Summary Table.

Figure 38. REG04 Register

Bit

7

6

5

4

3

2

1

0

Reset

Field

2h

IPRECHG[3:0]

ITERM[3:0]

Table 14. REG04 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

IPRECHG[3]

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

ITERM[3]

R/W

Yes

400 mA

200 mA

100 mA

50 mA

Precharge Current Limit:

Offset: 50 mA

Range: 50mA – 800mA

Default: 150mA

Yes

400 mA

200 mA

100 mA

50 mA

Termination Current Limit:

Offset: 50 mA

Range: 50mA – 800mA

Default: 150mA

ITERM[2]

Yes

ITERM[1]

Yes

ITERM[0]

Yes

Submit Documentation Feedback

41

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Dh]

REG05 is shown in Figure 39 and described in Table 15.

Return to Summary Table.

Figure 39. REG05 Register

Bit

7

1h

6

0h

5

4

3

1h

2

1

0

1h

Reset

Field

1h

WATCHDOG[1:0]

2h

CHG_TIMER[1:0]

EN_TERM

STAT_DIS

EN_TIMER

TMR2X_EN

Table 15. REG05 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

EN_TERM

R/W

Yes

Termination Control:

0 – Disable termination

1 – Enable termination (default)

6

STAT_DIS

R/W

Yes

STAT Pin Disable:

0 – Enable STAT pin function (default)

1 – Disable STAT pin function

5

4

WATCHDOG[1]

WATCHDOG[0]

R/W

Yes

I2C Watchdog Timer Settings:

00 – Disable WD Timer

01 – 40s (default)

10 – 80s

11 – 160s

3

EN_TIMER

R/W

Yes

Charging Safety Timer Enable

0 – Disable

1 – Enable (Default)

2

1

CHG_TIMER[1]

CHG_TIMER[0]

R/W

Yes

Fast Charge Timer Setting

00 – 5 hrs

01 – 8 hrs

10 – 12 hrs (Default)

11 – 20 hrs

0

TMR2X_EN

R/W

Yes

Safety Timer during DPM or TREG

0 – Safety timer always count normally

1 – Safety timer slowed by 2X during input DPM or TREG (Default)

42

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.7 Charger Control 2 Register (Address = 06h) [reset = 7Dh]

REG06 is shown in Figure 40 and described in Table 16.

Return to Summary Table.

Figure 40. REG06 Register

Bit

7

0h

6

5

4

3

1h

2

1h

1

0

Reset

Field

1h

3h

0h

EN_OTG

AUTO_INDET_

EN

TREG[1:0]

EN_CHG

BATLOWV

VRECHG[1:0]

Table 16. REG06 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

EN_OTG

R/W

Yes

Buck (OTG) Mode control:

0 – Disable OTG (default)

1 – Enable OTG

Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority

6

AUTO_INDET_EN

R/W

Yes

Automatic D+/D– Detection Enable:

0 – Disable D+/D–L detection when VBUS plugs in

1 – Enable D+/D– detection when VBUS plugs in (default)

5

4

TREG[1]

TREG[0]

R/W

Yes

Thermal Regulation Threshold

00 – 60°C

01 – 80°C

10 – 100°C

11 – 120°C (Default)

3

2

EN_CHG

R/W

Yes

Charger Enable Configuration

0 – Charge Disable

1 – Charge Enable (default)

Note: If EN_OTG and EN_CHG are set simultaneously, EN_CHG takes priority

BATLOWV

Battery precharge to fast-charge threshold:

0 – 5.6V

1 – 6.0V (default)

1

0

VRECHG[1]

VRECHG[0]

R/W

Yes

No

200 mV

100 mV

Battery Recharge Threshold Offset (below VREG):

Offset: 100mV

Range: 100mV – 400mV

Default: 200mV

Submit Documentation Feedback

43

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.8 Charger Control 3 Register (Address = 07h) [reset = 02h]

REG07 is shown in Figure 41 and described in Table 17.

Return to Summary Table.

Figure 41. REG07 Register

Bit

Reset

Field

7

0h

6

0h

5

4

3

2

1

0

0h

TOPOFF_TIMER[1:0]

2h

PFM_DIS

WD_RST

SYS_MIN[3:0]

Table 17. REG07 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

PFM_DIS

R/W

Yes

No

PFM Mode Disable control:

0 – Enable PFM operation (default)

1 – Disable PFM operation

6

WD_RST

R/W

Yes

I2C Watchdog Timer Reset:

0 – Normal

1 – Reset (Bit goes back to 0 after timer reset)

5

4

TOPOFF_TIMER[1]

TOPOFF_TIMER[0]

R/W

Yes

Top-off Timer Control :

00 – Disabled (default)

01 – 15 mins

10 – 30 mins

11 – 45 mins

3

2

1

0

SYS_MIN[3]

SYS_MIN[2]

SYS_MIN[0]

R/W

Yes

No

800 mV

400 mV

200 mV

100 mV

Minimum System Voltage Limit

Offset: 6.0 V

Range: 6.0 V – 7.5V

Default: 6.2 V

44

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.9 Charger Control 4 Register (Address = 08h) [reset = 0Dh]

REG08 is shown in Figure 42 and described in Table 18.

Return to Summary Table.

Figure 42. REG08 Register

Bit

7

6

5

0h

4

3

2

1h

1

0

Reset

Field

0h

1h

JEITA_VSET[1:0]

1h

JEITA_ISETC[1:0]

BHOT[1:0]

BCOLD

JEITA_ISETH

Table 18. REG08 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

BHOT[1]

BHOT[0]

R/W

Yes

OTG Mode TS HOT Temperature Threshold:

00 – VBHOT1 threshold (34.75%) (default)

01 – VBHOT0 threshold (37.75%)

Yes

10 – VBHOT2 threshold (31.25%)

11 – Disable OTG mode thermal protection

5

BCOLD

R/W

Yes

OTG Mode TS COLD Temperature Threshold:

0 – VBCOLD0 threshold (77%) (default)

1 – VBCOLD1 threshold (80%)

4

3

JEITA_VSET[1]

JEITA_VSET[0]

R/W

Yes

JEITA High Temp. (45C – 60C) Voltage Setting:

00 – Charge Suspend

01 – Set VREG to 8.0V (default)

10 – Set VREG to 8.3V

11 – VREG unchanged

2

JEITA_ISETH

R/W

Yes

JEITA High Temp. (45C – 60C) Current Setting (percentage with respect to

ICHG REG01[5:0]):

0 – 40% of ICHG

1 – 100% of ICHG (default)

1

0

JEITA_ISETC[1]

JEITA_ISETC[0]

R/W

Yes

JEITA Low Temp. (0C – 10C) Current Setting (percentage with respect to ICHG

REG01[5:0]):

00 – Charge Suspend

01 – 20% of ICHG (default)

10 – 40% of ICHG

11 – 100% of ICHG

Submit Documentation Feedback

45

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.10 OTG Control Register (Address = 09h) [reset = F6h]

REG09 is shown in Figure 43 and described in Table 19.

Return to Summary Table.

Figure 43. REG09 Register

Bit

7

6

5

4

3

2

1

0

Reset

Field

Fh

6h

OTG_ILIM[3:0]

OTG_VLIM[3:0]

Table 19. REG09 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

OTG_ILIM[3]

OTG_ILIM[2]

OTG_ILIM[1]

OTG_ILIM[0]

OTG_VLIM[3]

OTG_VLIM[2]

OTG_VLIM[1]

OTG_VLIM[0]

R/W

Yes

800 mA

400 mA

200 mA

100 mA

800 mV

400 mV

200 mV

100 mV

Buck (OTG) Mode Current Limit:

Offset: 0.5A

Range: 0.5A – 2.0A

Default: 2.0A

Yes

Buck (OTG) Mode Regulation Voltage:

Offset: 4.5V

Range: 4.5V – 5.5V

Default: 5.1V

Yes

Note: Values above 5.5V (Ah) will be clamped to 5.5V

Yes

46

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.11 ICO Current Limit in Use Register (Address = 0Ah) [reset = XXh]

REG0A is shown in Figure 44 and described in Table 20.

Return to Summary Table.

Figure 44. REG0A Register

Bit

7

6

5

4

3

2

1

0

Reset

Field

0

X

RESERVED

ICO_ILIM[4:0]

Table 20. REG0A Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

RESERVED

ICO_ILIM[4]

ICO_ILIM[3]

ICO_ILIM[2]

ICO_ILIM[1]

ICO_ILIM[0]

R

No

Reserved bit always reads 0

1600 mA

800 mA

400 mA

200 mA

100 mA

Input Current Limit in use when ICO is enabled:

Offset: 500 mA

Range: 500mA – 3300mA

Submit Documentation Feedback

47

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]

REG0B is shown in Figure 45 and described in Table 21.

Return to Summary Table.

Figure 45. REG0B Register

Bit

7

X

6

5

4

3

X

2

1

0

Reset

Field

X

Reserved

IINDPM_STAT VINDPM_STAT

TREG_STAT

WD_STAT

CHRG_STAT[2:0]

Table 21. REG0B Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

Reserved

R

No

Reserved bit always reads 0

IINDPM_STAT

VINDPM_STAT

TREG_STAT

WD_STAT

IINDPM Status:

0 – Normal

1 – In IINDPM Regulation (ILIM pin or IINDPM register)

5

4

3

R

No

VINDPM Status:

0 – Normal

1 – In VINDPM Regulation

IC Thermal regulation Status:

0 – Normal

1 – In Thermal Regulation

I2C Watchdog Timer Status bit:

0 – Normal

1 – WD Timer expired

2

1

0

CHRG_STAT[2]

CHRG_STAT[1]

CHRG_STAT[0]

R

No

Charge Status bits:

000 – Not Charging

001 – Trickle Charge (VBAT < VBAT_SHORT)

010 – Pre-charge (VBAT_UVLO_RISING < VBAT < VBAT_LOWV)

011 – Fast-charge (CC mode)

100 – Taper Charge (CV mode)

101 – Top-off Timer Charging

110 – Charge Termination Done

111 – Reserved

48

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]

REG0C is shown in Figure 46 and described in Table 22.

Return to Summary Table.

Figure 46. REG0C Register

Bit

7

X

6

5

4

3

2

1

0

Reset

Field

X

0

X

PG_STAT

VBUS_STAT[2:0]

RESERVED

ICO_STAT[1]

ICO_STAT[0]

VSYS_STAT

Table 22. REG0C Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

PG_STAT

R

No

Power Good Status:

0 – Not Power Good

1 – Power Good

6

5

4

VBUS_STAT[2]

VBUS_STAT[1]

VBUS_STAT[0]

R

No

VBUS Detection Status

000 – No Input

001 – USB Host SDP

010 - USB CDP (1.5 A)

011 – Adapter (3.0A)

100 – POORSRC detected 7 consecutive times

101 - Unknown Adapter (500 mA)

110 - Non-standard Adapter (1 A/2 A/2.1 A/2.4 A)

111 – OTG

3

2

1

RESERVED

ICO_STAT[1]

ICO_STAT[0]

R

No

Reserved bit always reads 0h

Input Current Optimizer (ICO) Status:

00 – ICO Disabled

01 – ICO Optimization is in progress

10 – Maximum input current detected

11 – Reserved

0

VSYS_STAT

R

No

VSYS Regulation Status:

0 – Not in SYS_MIN regulation (BAT > VSYS_MIN)

1 – In SYS_MIN regulation (BAT < VSYS_MIN)

Submit Documentation Feedback

49

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]

REG0D is shown in Figure 47 and described in Table 23.

Return to Summary Table.

Figure 47. REG0D Register

Bit

7

0

6

0

5

4

3

2

1

0

Reset

Field

0

X

RESERVED

TS_STAT[2:0]

Table 23. REG0D Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

RESERVED

TS_STAT[2]

TS_STAT[1]

TS_STAT[0]

R

Yes

No

Reserved bit always reads 0h

Yes

No

NTC (TS) Status:

000 – Normal

010 – TS Warm

011 – TS Cool

101 – TS Cold

110 – TS Hot

No

50

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]

REG0E is shown in Figure 48 and described in Table 24.

Return to Summary Table.

Figure 48. REG0E Register

Bit

7

6

5

4

X

3

2

1

0

X

Reset

Field

X

0

VBUS_OVP_ST TSHUT_STAT BATOVP_STAT

AT

TMR_STAT

RESERVED

Reserved

Table 24. REG0E Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

VBUS_OVP_STAT

R

No

Input over-voltage Status:

0 – Normal

1 – Device in over-voltage protection

TSHUT_STAT

BATOVP_STAT

TMR_STAT

R

No

IC Temperature shutdown Status:

0 – Normal

1 – Device in thermal shutdown protection

Battery over-voltage Status:

0 – Normal

1 – BATOVP (VBAT > VBATOVP)

Charge Safety timer Status:

0 – Normal

1 – Charge Safety timer expired

3

2

1

0

RESERVED

R

No

Reserved bit always reads 0h

Submit Documentation Feedback

51

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]

REG0F is shown in Figure 49 and described in Table 25.

Return to Summary Table.

Figure 49. REG0F Register

Bit

7

0

6

0

5

0

4

3

0

2

1

0

Reset

Field

0

Reserved

IINDPM_FLAG VINDPM_FLAG

TREG_FLAG

WD_FLAG

RESERVED

CHRG_FLAG

Table 25. REG0F Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

Reserved

R

Yes

No

Reserved bit always reads 0

IINDPM_FLAG

VINDPM_FLAG

TREG_FLAG

WD_FLAG

Yes

IINDPM Regulation INT Flag:

0 – Normal

1 – IINDPM signal rising edge detected

5

4

3

R

Yes

No

VINDPM regulation INT Flag:

0 – Normal

1 – VINDPM signal rising edge detected

IC Temperature Regulation INT Flag:

0 – Normal

1 – TREG signal rising edge detected

I2C Watchdog INT Flag:

0 – Normal

1 – WD_STAT signal rising edge detected

2

1

0

RESERVED

CHRG_FLAG

R

Yes

No

Reserved bit always reads 0h

Charge Status INT Flag:

0 – Normal

1 – CHRG_STAT[2:0] bits changed (transition to any state)

52

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]

REG10 is shown in Figure 50 and described in Table 26.

Return to Summary Table.

Figure 50. REG10 Register

Bit

7

0

6

5

4

3

2

0

1

0

Reset

Field

0

PG_FLAG

RESERVED

VBUS_FLAG

RESERVED

TS_FLAG

ICO_FLAG

VSYS_FLAG

Table 26. REG10 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

PG_FLAG

R

Yes

No

Power Good INT Flag:

0 – Normal

1 – PG signal toggle detected

6

5

4

RESERVED

VBUS_FLAG

R

Yes

No

Reserved bit always reads 0h

VBUS Status INT Flag:

0 – Normal

1 – VBUS_STAT[2:0] bits changed (transition to any state)

3

2

RESERVED

TS_FLAG

R

Yes

No

Reserved bit always reads 0h

TS Status INT Flag:

0 – Normal

1 – TS_STAT[2:0] bits changed (transition to any state)

1

0

ICO_FLAG

R

Yes

No

Input Current Optimizer (ICO) INT Flag:

0 – Normal

1 – ICO_STAT[1:0] changed (transition to any state)

VSYS_FLAG

VSYS Regulation INT Flag:

0 – Normal

1 – Entered or exited SYS_MIN regulation

Submit Documentation Feedback

53

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]

REG11 is shown in Figure 51 and described in Table 27.

Return to Summary Table.

Figure 51. REG11 Register

Bit

7

0

6

0

5

0

4

3

2

1

0

Reset

Field

0

VBUS_OVP_FL TSHUT_FLAG BATOVP_FLAG

AG

TMR_FLAG

RESERVED

OTG_FLAG

Table 27. REG11 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

VBUS_OVP_FLAG

R

Yes

No

Input over-voltage INT Flag:

0 – Normal

1 – Entered VBUS_OVP Fault

TSHUT_FLAG

BATOVP_FLAG

TMR_FLAG

R

Yes

IC Temperature shutdown INT Flag:

0 – Normal

1 – Entered TSHUT Fault

Battery over-voltage INT Flag:

0 – Normal

1 – Entered BATOVP Fault

Charge Safety timer Fault INT Flag:

0 – Normal

1 – Charge Safety timer expired rising edge detected

3

2

1

0

RESERVED

OTG_FLAG

R

Yes

No

Reserved bit always reads 0

Reserved bit always reads 0h

OTG Buck Mode Fault INT Flag:

0 – Normal

1 – Entered OTG_STAT (OTG Fault)

54

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]

REG12 is shown in Figure 52 and described in Table 28.

Return to Summary Table.

Figure 52. REG12 Register

Bit

7

0

6

0

5

0

4

0

3

2

1

0

Reset

Field

0

ADC_DONE_M IINDPM_MASK VINDPM_MASK TREG_MASK

ASK

WD_MASK

RESERVED

CHRG_MASK

Table 28. REG12 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

ADC_DONE_MASK

R/W

Yes

No

ADC Conversion INT Mask Flag (only one-shot mode)

0 – ADC_DONE does produce INT pulse

1 – ADC_DONE does produce not INT pulseReserved bit always reads 0

IINDPM_MASK

VINDPM_MASK

TREG_MASK

WD_MASK

R/W

Yes

IINDPM Regulation INT Mask

0 – IINDPM entry produces INT pulse

1 – IINDPM entry does not produce INT pulse

VINDPM Regulation INT Mask

0 – VINDPM entry produces INT pulse

1 – VINDPM entry not produce INT pulse

IC Temperature Regulation INT Mask

0 – TREG entry produces INT pulse

1 – TREG entry produce INT pulse

I2C Watchdog Timer INT Mask

0 – WD_STAT rising edge produces INT pulse

1 – WD_STAT rising edge does not produce INT

2

1

0

RESERVED

CHRG_MASK

R

Yes

No

Reserved bit always reads 0h

R

R/W

Charge Status INT Mask

0 – CHRG_STAT[2:0] bit change produces INT

1 – CHRG_STAT[2:0] bit change does not produce INT pulse

Submit Documentation Feedback

55

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]

REG13 is shown in Figure 53 and described in Table 29.

Return to Summary Table.

Figure 53. REG13 Register

Bit

7

0

6

5

4

3

2

0

1

0

Reset

Field

0

PG_MASK

RESERVED

VBUS_MASK

RESERVED

TS_MASK

ICO_MASK

VSYS_MASK

Table 29. REG13 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

PG_MASK

R/W

Yes

No

Power Good INT Mask:

0 – PG toggle produces INT pulse

1 – PG toggle does not produce INT pulse

6

5

4

RESERVED

VBUS_MASK

R

Yes

No

Reserved bit always reads 0h

R

R/W

VBUS Status INT Mask:

0 – VBUS_STAT[2:0] bit change produces INT

1 – VBUS_STAT[2:0] bit change does not produces INT

3

2

RESERVED

TS_MASK

R

Yes

No

Reserved bit always reads 0h

R/W

TS Status INT Mask:

0 – TS_STAT[2:0] bit change produces INT

1 – TS_STAT[2:0] bit change does not produces INT pulse

1

0

ICO_MASK

R/W

Yes

No

Input Current Optimizer (ICO) INT Mask:

0 – ICO_STAT rising edge produces INT

1 – ICO_STAT rising edge does not produce INT

VSYS_MASK

VSYS Regulation INT Mask:

0 – Entering or exiting SYS_MIN produces INT

1 – Entering or exiting SYS_MIN does not produce INT

56

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]

REG14 is shown in Figure 54 and described in Table 30.

Return to Summary Table.

Figure 54. REG14 Register

Bit

7

0

6

0

5

0

4

3

0

2

1

0

Reset

Field

0

VBUS_OVP_M TSHUT_MASK BATOVP_MAS

ASK

TMR_MASK

SYS_SHORT_

MASK

RESERVED

OTG_MASK

K

Table 30. REG14 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

VBUS_OVP_MASK

R/W

Yes

No

Input over-voltage INT Mask:

0 – VBUS_OVP rising edge produces INT pulse

1 – VBUS_OVP rising edge does not produce INT pulse

6

5

4

3

TSHUT_MASK

R/W

Yes

Thermal Shutdown INT Mask:

0 – TSHUT rising edge produces INT pulse

1 – TSHUT rising edge does not produce INT pulse

BATOVP_MASK

TMR_MASK

Battery overvoltage INT Mask:

0 – BATOVP rising edge produces INT pulse

1 – BATOVP rising edge does not produce INT pulse

Charge Safety Timer Fault INT Mask:

0 – Timer expired rising edge produces INT pulse

1 – Timer expired rising edge does not produce INT pulse

SYS_SHORT_MASK

System Short Fault INT Mask:

0 – System short rising edge produces INT pulse

1 – System short rising edge does not produce INT pulse

2

1

0

RESERVED

OTG_MASK

R

Yes

No

Reserved bit always reads 0h

R

R/W

OTG Buck Mode Fault INT Mask:

0 – OTG_STAT event produces INT

1 – OTG_STAT event does not produce INT

Submit Documentation Feedback

57

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.22 ADC Control Register (Address = 15h) [reset = 30h]

REG15 is shown in Figure 55 and described in Table 31.

Return to Summary Table.

Figure 55. REG15 Register

Bit

7

0

6

5

1

4

1

3

2

1

0

Reset

Field

0

ADC_EN

ADC_RATE

ADC_SAMPLE[1:0]

RESERVED

Table 31. REG15 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

ADC_EN

R/W

Yes

ADC Control:

0 – Disable ADC

1 – Enable ADC

6

ADC_RATE

R/W

Yes

No

0 – Continuous conversion

1 – One-shot conversion

5

4

ADC_SAMPLE[1]

ADC_SAMPLE[0]

R/W

Yes

No

Sample Speed of ADC:

00 – 15 bit effective resolution

01 – 14 bit effective resolution

10 – 13 bit effective resolution

11 – 12 bit effective resolution

3

2

1

0

RESERVED

R

Yes

No

Reserved bit always reads 0h

58

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]

REG16 is shown in Figure 56 and described in Table 32.

Return to Summary Table.

Figure 56. REG16 Register

Bit

7

0

6

0

5

0

4

0

3

0

2

1

0

Reset

Field

0

IBUS_ADC_DIS ICHG_ADC_DI VBUS_ADC_DI VBAT_ADC_DI VSYS_ADC_DI

TS_ADC_DIS

Reserved

TDIE_ADC_DIS

S

Table 32. REG16 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

IBUS_ADC_DIS

R/W

Yes

No

0 – Enable conversion

1 – Disable conversion

ICHG_ADC_DIS

VBUS_ADC_DIS

VBAT_ADC_DIS

VSYS_ADC_DIS

TS_ADC_DIS

R/W

Yes

0 – Enable conversion

1 – Disable conversion

0 – Enable conversion

1 – Disable conversion

0 – Enable conversion

1 – Disable conversion

0 – Enable conversion

1 – Disable conversion

0 – Enable conversion

1 – Disable conversion

1

0

RESERVED

R

Yes

No

Reserved bit always reads 1h

TDIE_ADC_DIS

R/W

0 – Enable conversion

1 – Disable conversion

Submit Documentation Feedback

59

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]

REG17 is shown in Figure 57 and described in Table 33.

Return to Summary Table.

Figure 57. REG17 Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

IBUS_ADC[15:8]

Table 33. REG17 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

IBUS_ADC[15]

IBUS_ADC[14]

IBUS_ADC[13]

IBUS_ADC[12]

IBUS_ADC[11]

IBUS_ADC[10]

IBUS_ADC[9]

IBUS_ADC[8]

R

Yes

No

Sign bit: overall results reported in two's complement.

Yes

16384 mA

8192 mA

4096 mA

Yes

2048 mA

1024 mA

512 mA

256 mA

VBUS Current Reading (positive current flows into VBUS pin,

negative current flows out ot VBUS pin):

Range: 0A – 4A

Yes

8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]

REG18 is shown in Figure 58 and described in Table 34.

Return to Summary Table.

Figure 58. REG18 Register

Bit

7

0

6

0

5

4

3

2

0

1

0

Reset

Field

0

IBUS_ADC[7:0]

Table 34. REG18 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

IBUS_ADC[7]

IBUS_ADC[6]

IBUS_ADC[5]

IBUS_ADC[4]

IBUS_ADC[3]

IBUS_ADC[2]

IBUS_ADC[1]

IBUS_ADC[0]

R

Yes

No

128 mA

64 mA

32 mA

16 mA

8 mA

VBUS Current Reading (positive current flows into VBUS pin,

negative current flows out ot VBUS pin):

Range: 0A – 4A

Yes

4 mA

Yes

2 mA

Yes

1 mA

60

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]

REG19 is shown in Figure 59 and described in Table 35.

Return to Summary Table.

Figure 59. REG19 Register

Bit

7

6

0

5

0

4

0

3

2

0

1

0

Reset

Field

0

RESERVED

ICHG_ADC[14:8]

Table 35. REG19 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

Reserved

R

Yes

No

Reserved register always reads 0h.

ICHG_ADC[14]

ICHG_ADC[13]

ICHG_ADC[12]

ICHG_ADC[11]

ICHG_ADC[10]

ICHG_ADC[9]

ICHG_ADC[8]

Yes

16384 mA

8192 mA

4096 mA

Yes

2048 mA

1024 mA

512 mA

256 mA

Charge Current Reading:

Range: 0A – 4A

Yes

8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]

REG1A is shown in Figure 60 and described in Table 36.

Return to Summary Table.

Figure 60. REG1A Register

Bit

7

0

6

0

5

4

3

2

0

1

0

Reset

Field

0

ICHG_ADC[7:0]

Table 36. REG1A Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

ICHG_ADC[7]

ICHG_ADC[6]

ICHG_ADC[5]

ICHG_ADC[4]

ICHG_ADC[3]

ICHG_ADC[2]

ICHG_ADC[1]

ICHG_ADC[0]

R

Yes

No

128 mA

64 mA

32 mA

16 mA

8 mA

Charge Current Reading:

Range: 0A – 4A

Yes

4 mA

Yes

2 mA

Yes

1 mA

Submit Documentation Feedback

61

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]

REG1B is shown in Figure 61 and described in Table 37.

Return to Summary Table.

Figure 61. REG1B Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VBUS_ADC[15:8]

Table 37. REG1B Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VBUS_ADC[15]

VBUS_ADC[14]

VBUS_ADC[13]

VBUS_ADC[12]

VBUS_ADC[11]

VBUS_ADC[10]

VBUS_ADC[9]

VBUS_ADC[8]

R

Yes

No

Sign bit: overall results reported in two's complement.

16384 mV

Yes

8192 mV

4096 mV

2048 mV

1024 mV

512 mV

VBUS Voltage reading

Range: 0V – 10V

Yes

256 mV

8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]

REG1C is shown in Figure 62 and described in Table 38.

Return to Summary Table.

Figure 62. REG1C Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VBUS_ADC[7:0]

Table 38. REG1C Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VBUS_ADC[7]

VBUS_ADC[6]

VBUS_ADC[5]

VBUS_ADC[4]

VBUS_ADC[3]

VBUS_ADC[2]

VBUS_ADC[1]

VBUS_ADC[0]

R

Yes

No

128 mV

64 mV

32 mV

16 mV

8 mV

VBUS Voltage Reading:

Range: 0V – 10V

Yes

4 mV

Yes

2 mV

Yes

1 mV

62

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]

REG1D is shown in Figure 63 and described in Table 39.

Return to Summary Table.

Figure 63. REG1D Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VBAT_ADC[15:8]

Table 39. REG1D Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VBAT_ADC[15]

VBAT_ADC[14]

VBAT_ADC[13]

VBAT_ADC[12]

VBAT_ADC[11]

VBAT_ADC[10]

VBAT_ADC[9]

VBAT_ADC[8]

R

Yes

No

Sign bit: overall results reported in two's complement.

16384 mV

Yes

8192 mV

4096 mV

2048 mV

1024 mV

512 mV

VBAT Voltage reading:

Range: 0V – 10V

Yes

256 mV

8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]

REG1E is shown in Figure 64 and described in Table 40.

Return to Summary Table.

Figure 64. REG1E Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VBAT_ADC[7:0]

Table 40. REG1E Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VBAT_ADC[7]

VBAT_ADC[6]

VBAT_ADC[5]

VBAT_ADC[4]

VBAT_ADC[3]

VBAT_ADC[2]

VBAT_ADC[1]

VBAT_ADC[0]

R

Yes

No

128 mV

64 mV

32 mV

16 mV

8 mV

VBAT Voltage reading:

Range: 0V – 10V

Yes

4 mV

Yes

2 mV

Yes

1 mV

Submit Documentation Feedback

63

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.32 VSYS ADC 1 Register (Address = 1Fh) [reset = 00h]

REG1F is shown in Figure 65 and described in Table 41.

Return to Summary Table.

Figure 65. REG1F Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VSYS_ADC[15:8]

Table 41. REG1F Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VSYS_ADC[15]

VSYS_ADC[14]

VSYS_ADC[13]

VSYS_ADC[12]

VSYS_ADC[11]

VSYS_ADC[10]

VSYS_ADC[9]

VSYS_ADC[8]

R

Yes

No

Sign bit: overall results reported in two's complement.

16384 mV VSYS Voltage reading:

Yes

Range: 0V – 10V

Yes

8192 mV

Yes

4096 mV

2048 mV

1024 mV

512 mV

256 mV

Yes

8.5.33 VSYS ADC 0 Register (Address = 20h) [reset = 00h]

REG20 is shown in Figure 66 and described in Table 42.

Return to Summary Table.

Figure 66. REG20 Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

VSYS_ADC[7:0]

Table 42. REG20 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

VSYS_ADC[7]

VSYS_ADC[6]

VSYS_ADC[5]

VSYS_ADC[4]

VSYS_ADC[3]

VSYS_ADC[2]

VSYS_ADC[1]

VSYS_ADC[0]

R

Yes

No

128 mV

64 mV

32 mV

16 mV

8 mV

VSYS Voltage reading:

Range: 0V – 10V

Yes

4 mV

Yes

2 mV

Yes

1 mV

64

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]

REG21 is shown in Figure 67 and described in Table 43.

Return to Summary Table.

Figure 67. REG21 Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

TS_ADC[15:8]

Table 43. REG21 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

Sign bit: overall results reported in two's complement.

7

6

5

4

3

2

1

0

TS_ADC[15]

TS_ADC[14]

TS_ADC[13]

TS_ADC[12]

TS_ADC[11]

TS_ADC[10]

TS_ADC[9]

TS_ADC[8]

R

Yes

No

Yes

50.0 %

25.0 %

TS as percentage of REGN reading:

Range: 0% – 94.9%

Yes

8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]

REG22 is shown in Figure 68 and described in Table 44.

Return to Summary Table.

Figure 68. REG22 Register

Bit

7

0

6

0

5

4

3

2

0

1

0

Reset

Field

0

TS_ADC[7:0]

Table 44. REG22 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

TS_ADC[7]

TS_ADC[6]

TS_ADC[5]

TS_ADC[4]

TS_ADC[3]

TS_ADC[2]

TS_ADC[1]

TS_ADC[0]

R

Yes

No

12.50 %

6.25 %

TS as percentage of REGN reading:

Range: 0% – 94.9%

Yes

3.125 %

1.563 %

0.781 %

0.391 %

0.195 %

0.098 %

Yes

Submit Documentation Feedback

65

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]

REG23 is shown in Figure 69 and described in Table 45.

Return to Summary Table.

Figure 69. REG23 Register

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Field

TDIE_ADC[15:8]

Table 45. REG23 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

Sign bit: overall results reported in two's complement.

7

6

5

4

3

2

1

0

TDIE_ADC[15]

TDIE_ADC[14]

TDIE_ADC[13]

TDIE_ADC[12]

TDIE_ADC[11]

TDIE_ADC[10]

TDIE_ADC[9]

TDIE_ADC[8]

R

Yes

No

Yes

128 °C

TDIE (IC Temperature) reading:

Range: 0°C – 128°C

8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]

REG24 is shown in Figure 70 and described in Table 46.

Return to Summary Table.

Figure 70. REG24 Register

Bit

7

0

6

0

5

4

3

2

0

1

0

Reset

Field

0

TDIE_ADC[7:0]

Table 46. REG24 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

6

5

4

3

2

1

0

TDIE_ADC[7]

TDIE_ADC[6]

TDIE_ADC[5]

TDIE_ADC[4]

TDIE_ADC[3]

TDIE_ADC[2]

TDIE_ADC[1]

TDIE_ADC[0]

R

Yes

No

64 °C

32 °C

16 °C

8 °C

TDIE (IC Temperature) reading:

Range: 0°C – 128°C

Yes

4°C

Yes

2 °C

Yes

1 °C

Yes

0.5 °C

66

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

8.5.38 Part Information Register (Address = 25h) [reset = 18h]

REG25 is shown in Figure 71 and described in Table 47.

Return to Summary Table.

Figure 71. REG25 Register

Bit

7

0

6

0

5

0

4

1

3

1

2

0

1

0

Reset

Field

0

REG_RST

PN[3:0]

DEV_REV[2:0]

Table 47. REG25 Register Field Descriptions

Reset by

REG_RST

Reset by

WATCHDOG

Bit

Field

Type

Description

7

REG_RST

R/W

Yes

No

Register Reset:

0 – Keep current register settings

1 – Reset to default register value and reset safety timer (bit resets to 0 after

register reset is complete)

6

5

4

3

2

1

0

PN[3]

R

Yes

No

0011: BQ25883

PN[2]

PN[1]

PN[0]

DEV_REV[2]

DEV_REV[1]

DEV_REV[0]

Device revision: 001

Submit Documentation Feedback

67

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

A typical application consists of the BQ25883 configured as an I2C controlled power path management device

and a 2s battery charger for Li-Ion and Li-polymer batteries used in a wide range of portable devices. It

integrates an input blocking FET (QBLK, Q1), high-side switching FET (QHS, Q2), low-side switching FET (QLS,

Q3), and battery FET (QBAT, Q4) between system and battery. The device also integrates a bootstrap diode for

the high-side gate drive.

9.2 Typical Application

5V @ 3A

VBUS

PMID

_{10K ꢁ}VREF

STAT

ILIM

1 ꢀF

Q1

383Ω

10 ꢀF

Q2

SYSTEM

LOAD

1ꢀH

6.4V to 8.8V

ICHG=2A

10 ꢀF

SYS

SW

47nF

44…F

BTST

Q4

BAT

4.7ꢀF

REGN

Q3

VREGN

D+

USB

Host

Dœ

VREF

TS

SDA

`

SCL

INT

PG

BQ25883

CE

GND

Figure 72. BQ25883 (I2C, OTG, and Power Path) Typical Application Diagram

68

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

Typical Application (continued)

9.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

Table 48. Design Parameters

PARAMETER

VALUE

3.9 V to 6.2 V

2.4 A

VBUS voltage range

Input current limit (IINDPM[4:0])

Fast charge current limit (ICHG[5:0])

Minimum System Voltage (SYS_MIN[3:0])

Battery Regulation Voltage (VREG[7:0])

1.5 A

6.2 V

8.4 V

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The device has 1.5MHz switching frequency to allow the use of small inductor and capacitor values. The inductor

saturation current should be higher than the input current (I_IN) plus half the ripple current (I_RIPPLE):

I

RIPPLE

ISAT í IIN +

2

(5)

The inductor ripple current (I_RIPPLE) depends on input voltage (V_VBUS), duty cycle (D = V_BAT/V_BUS), switching

frequency (f_SW) and inductance (L):

V

^BUSì(V^SYS-VBUS)

IRIPPLE

=

V^SYSì f^SWì L

(6)

The maximum inductor ripple current happens in the vicinity of D = 0.5. Usually inductor ripple is designed in the

range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical

design.

9.2.2.2 Input (VBUS / PMID) Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current occurs when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the

worst case capacitor RMS current I_PMIDoccurs where the duty cycle is closest to 50% and can be estimated by

I

RIPPLE

IPMID

=

ö 0.29ì IRIPPLE

2ì 3

(7)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed close to the PMID and GND pins of the IC. Voltage rating of the capacitor must be higher than normal

input voltage level. 25-V rating or higher capacitor is preferred for up to 5-V input voltage. 10-μF capacitor is

suggested for up to 3.3-A input current.

9.2.2.3 Output (VSYS) Capacitor

SYS capacitor is the boost converter output capacitor and should also have enough ripple current rating to

absorb output switching ripple current. The output capacitor RMS current I_COUTis given:

D

ICSYS, rms = IOUT ì

1- D

(8)

The output capacitor voltage ripple is a function of the boost output current (I_OUT), and can be calculated as

follows:

I

OUT ì D

DV^SYS

=

f

^SWìCSYS

(9)

69

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

Low ESR ceramic capacitor such as X7R or X5R is preferred for SYS decoupling capacitor and should be placed

close to theSYS and GND pins of the IC. Voltage rating of the capacitor must be higher than normal output

voltage level. 16-V rating or higher capacitor is preferred. 44-μF capacitor is suggested for up to 2.2-A boost

converter output current.

70

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

9.2.3 Application Curves

C_VBUS= 1µF, C_PMID= 10µF, C_BAT= 10µF, C_SYS= 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)

VBUS = 5V

VBAT = 6.0V

ICHG = 1A

VBUS = 5V

VBAT = 7.4V

ICHG = 1A

Figure 73. Adapter Power Up with Charge Enabled

Figure 74. Charge Enable

VBUS = 5V

VBAT = Open

Charge enabled

VBUS = 5V

VBAT = 7.4V

ICHG = 1A

Figure 76. Adapter Plug-in with No Battery

Figure 75. Charge Disabled

VBUS = 5V

VBAT = Open

Charge disabled

VBAT = 7.6V

VBUS = 5.1V

No IBUS load

Figure 77. Adapter Plug-in with No Battery Charge

Disabled

Figure 78. Buck Mode (OTG) Startup

Submit Documentation Feedback

71

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

C_VBUS= 1µF, C_PMID= 10µF, C_BAT= 10µF, C_SYS= 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)

VBAT = 7.6V

Adapter removed

with EN_OTG = 1

R_BUS= 25Ω

VBAT = 7.6V

VBUS = 5.1V

IBUS = 1A

Figure 80. Buck Mode (OTG) PWM Switching

Figure 79. Buck Mode Startup After Adapter Removal

VBAT = 7.6V

VBUS = 5.1V

IBUS = 0mA

VBUS = 5V

VBAT = 7.6V

ICHG = 1A

Figure 81. Buck Mode (OTG) PFM Switching

Figure 82. Boost Mode PWM Switching

VBUS = 5V

VBAT = 8.4V

Charge disabled

VBUS = 5V

VBAT = 8.4V

Charge disabled

Figure 83. Boost Mode PFM Switching

Figure 84. System Load Transient Response

72

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

C_VBUS= 1µF, C_PMID= 10µF, C_BAT= 10µF, C_SYS= 44µF, L = DFE252012F-1R0 (1µH) (unless otherwise specified)

DCP Adapter

VBAT = 8.0V

Charge enabled

DCP Adapter

VBAT = 8.0V

Charge enabled

Figure 85. VINDPM Transient Response

Figure 86. IINDPM Transient Response

VBAT = 7.6V

VBUS = 5.1V

Figure 87. Buck Mode (OTG) Load Transient Response

Submit Documentation Feedback

73

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

10 Power Supply Recommendations

In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 6.2 V input

with at least 500-mA current rating connected to VBUS or a 2s Li-Ion battery with voltage > VBAT_UVLO

connected to BAT The source current rating needs to be at least 3-A in order for the boost converter of the

charger to provide maximum output power to SYS.

11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loops is important to prevent electrical and magnetic field

radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB

according to this specific order is essential.

1. Put SYS output capacitor as close to SYS and GND pins as possible. Ground connections need to be tied to

the IC ground with a short copper trace connection or GND plane.

2. Place PMID input capacitor as close as possible to PMID pins and PGND pins and use shortest copper trace

connection or GND plane.

3. Place inductor input terminal to SW pins as close as possible. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the input current. Minimize

parasitic capacitance from this area to any other trace or plane.

4. Decoupling capacitors should be placed on the same side of and next to the IC and make trace connection

as short as possible.

5. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using thermal pad as the single ground

connection point. Or using a 0-Ω resistor to tie analog ground to power ground.

6. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB

ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on

the other layers.

7. Via size and number should be enough for a given current path.

Refer to the EVM design and the Layout Example below for the recommended component placement with trace

and via locations.

74

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

11.2 Layout Example

Figure 88. PCB Layout Example

Submit Documentation Feedback

75

Product Folder Links: BQ25883

BQ25883

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•

BQ2588x EVM User's Guide (SLUUBU6)

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

76

Submit Documentation Feedback

Product Folder Links: BQ25883

BQ25883

www.ti.com

SLUSDL3A –FEBRUARY 2019–REVISED APRIL 2019

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

77

Product Folder Links: BQ25883

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ25883RGER

BQ25883RGET

VQFN

RGE

24

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Apr-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ25883RGER

BQ25883RGET

VQFN

RGE

24

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGE 24

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4204104/H

PACKAGE OUTLINE

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

A

4.1

3.9

B

4.1

3.9

PIN 1 INDEX AREA

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ

(0.2) TYP

2X 2.5

12

7

20X 0.5

6

13

25

2X

SYMM

2.5

1

18

0.30

PIN 1 ID

(OPTIONAL)

24X

0.18

24

19

0.1

0.05

C A B

C

SYMM

0.48

0.28

24X

4219016 / A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

2.7)

(

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

25

SYMM

(3.825)

2X

(1.1)

ꢆꢄꢂꢁꢇꢀ9,$

TYP

6

13

(R0.05)

7

12

2X(1.1)

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGE0024H

PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)

24

19

24X (0.58)

24X (0.24)

1

18

20X (0.5)

SYMM

(3.825)

(0.694)

TYP

6

13

25

(R0.05) TYP

METAL

TYP

7

12

(0.694)

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

78% PRINTED COVERAGE BY AREA

SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25883RGET
厂家：	TEXAS INSTRUMENTS
描述：	采用 WQFN 封装、具有电源路径且适用于 USB 输入的 I2C 2 节 2A 升压电池充电器 \| RGE \| 24 \| -40 to 85 电池
文件：	总86页 (文件大小：3739K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ25883RGET [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E