BQ25890_技术文档

BQ25890, BQ25892

ZHCSDI4D –MARCH 2015 –REVISED OCTOBER 2022

BQ25890/2 采用MaxCharge^TM技术实现高输入电压和可调电压USB On-the-Go

升压模式的I²C 控制型单节电池5A 快速充电器

1 特性

2 应用

• 高效5A、1.5MHz 开关模式降压充电

• 智能手机

• 平板电脑

• 便携式网络设备

– 2A 充电电流下的充电效率为93%；3A 充电电

流下的充电效率为91%

– 针对高电压输入（9V 至12V）进行了优化

– 低功耗PFM 模式，适合轻负载运行

• USB On-the-Go (OTG)，可调输出电压范围为4.5V

至5.5V

3 说明

BQ25890 和 BQ25892 是适用于单节锂离子电池和锂

聚合物电池的高度集成型 5A 开关模式电池充电管理和

系统电源路径管理器件。此类器件支持高输入电压快速

充电。低阻抗电源路径对开关模式运行效率进行了优

化、缩短了电池充电时间并延长了放电阶段的电池使用

寿命。

– 具有高达2.4A 输出以及500kHz 和1.5MHz 可

选频率的升压转换器

– 5V (1A) 输出时的升压效率为93%

– 精确的断续模式过流保护

器件信息

封装⁽¹⁾

• 单个输入，支持USB 输入和可调高电压适配器

封装尺寸（标称值）

器件型号

BQ25890

BQ25892

– 支持3.9V 至14V 输入电压范围

– 输入电流限制（100mA 至3.25A，分辨率为

50mA），支持USB2.0、USB3.0 标准和高电压

适配器

– 通过高达14V 的输入电压限制进行最大功率跟

踪，适用于各类适配器

WQFN (24)

4.00mm x 4.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Input

3.9Vœ14V at 3A

– 自动检测USB SDP、CDP、DCP 以及非标准适

SYS 3.5Vœ4.5V

配器(BQ25890)

• 输入电流优化器(ICO)，无需过载适配器即可更大

限度地提高输入功率

• 充电器输出与电池终端间的电阻补偿(IRCOMP)

• 借助11mΩ电池放电MOSFET 实现超高的电池放

电效率，放电电流高达9A

VBUS

SW

USB

Host

OTG

5V at 2.4A

SYS

Ichg = 5A

BAT

I2C Bus

QON

REGN

BQ2589x

Optional

• 集成ADC，用于系统监视

Host Control

（电压、温度和充电电流）

TS

• 窄VDC (NVDC) 电源路径管理

– 无需电池或深度放电的电池即可瞬时启动

– 电池充电模式下实现理想的二极管运行

• BATFET 控制，支持运输模式、唤醒和完全系统复

位

简化版原理图

• 灵活的自主和I²C 模式，可实现出色的系统性能

• 高集成度包括所有MOSFET、电流感测和环路补偿

• 12µA 低电池漏电流，支持运输模式

• 高精度

– ±0.5% 充电电压调节

– ±5% 充电电流调节

– ±7.5% 输入电流调节

• 安全

– 用于充电模式和升压模式的电池温度检测

– 热调节和热关断

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSC86

BQ25890, BQ25892

ZHCSDI4D –MARCH 2015 –REVISED OCTOBER 2022

www.ti.com.cn

Table of Contents

9.4 Register Maps...........................................................37

10 Application and Implementation................................54

10.1 Application Information........................................... 54

10.2 Typical Application.................................................. 54

10.3 System Examples................................................... 58

11 Power Supply Recommendations..............................59

12 Layout...........................................................................60

12.1 Layout Guidelines................................................... 60

12.2 Layout Example...................................................... 60

13 Device and Documentation Support..........................61

13.1 Device Support....................................................... 61

13.2 接收文档更新通知................................................... 61

13.3 支持资源..................................................................61

13.4 Trademarks.............................................................61

13.5 Electrostatic Discharge Caution..............................61

13.6 术语表..................................................................... 61

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................4

6 Device Comparison Table...............................................5

7 Pin Configuration and Functions...................................6

8 Specifications.................................................................. 9

8.1 Absolute Maximum Ratings⁽¹⁾....................................9

8.2 ESD Ratings............................................................... 9

8.3 Recommended Operating Conditions.........................9

8.4 Thermal Information..................................................10

8.5 Electrical Characteristics...........................................10

8.6 Timing Requirements................................................15

8.7 Typical Characteristics..............................................16

9 Detailed Description......................................................18

9.1 Functional Block Diagram.........................................18

9.2 Feature Description...................................................19

9.3 Device Functional Modes..........................................35

Information.................................................................... 61

4 Revision History

Changes from Revision C (May 2018) to Revision D (October 2022)

Page

• 删除了整个数据表中的WEBENCH.................................................................................................................... 1

• 在整个数据表中更新了包容性术语......................................................................................................................1

Changes from Revision B (May 2016) to Revision C (May 2018)

Page

• 向数据表添加了WEBENCH 链接.......................................................................................................................1

• Added "SW (peak for 10 ns duration)" To the 节8.1 ......................................................................................... 9

• Updated the 节8.4 values.................................................................................................................................. 9

• Changed V_SYSTYP value From: V_BAT+ 50 mV To: I_(SYS)+ 150 mV................................................................10

• Changed the title of 图8-4 From: Charge Current Accuracy To: I²C Setting ...................................................16

• Changed axis title of 图8-8 From: BAT Voltage (V) To: Input Current Limit (mA)............................................ 16

• Changed V_VREFto V_REGNin 方程式2 ..............................................................................................................26

• Changed V_REFto V_REGNin 图9-8 ....................................................................................................................28

• Added sentence to the Battery Monitor secton "In battery only mode, ..".........................................................28

• Changed the Description values of 表9-27 From: mV To: mA.........................................................................52

• Changed the Type values of Bits 6 to Bit 0 in 表9-29 From: R/W To: R.......................................................... 53

• Added V_REFsystem pullup voltage to 表10-1 ................................................................................................. 54

2

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Changes from Revision A (June 2015) to Revision B (May 2016)

Page

• 添加了“引脚配置和功能”部分、“ESD 等级”表、“特性说明”部分、“器件功能模式”、“应用和实施”

部分、“电源相关建议”部分、“布局”部分、“器件和文档支持”部分以及“机械、封装和可订购信息”部

分。.....................................................................................................................................................................1

Changes from Revision * (March 2015) to Revision A (June 2015)

Page

• 在数据表标题中添加了“技术”一词.................................................................................................................. 1

• Deleted text form the OTG pin Description "OTG = High, IINLIM is set to USB500 mode". ..............................6

• Changed the Description of the OTG pin in the Pin Functions table ................................................................. 6

• Changed V_(SLEEP) and V_(SLEEPZ)Unit From: V To: mV ....................................................................................10

• Added TYP values to I_{IN(DPM_ACC)}in the 节8.5 table ...................................................................................... 10

• Deleted D+/D- DETECTION (bq25890) from the 节8.6 ..................................................................................15

• Added condition "DCR = 10 mΩ" to 图8-1 ......................................................................................................16

• Deleted V_{CHG_REG}and I_{BAT_REG}at Q4 gate Control in the 节9.1 ................................................................... 18

• Deleted "SDP_STAT bit is updated to indicate USB100 or other input source" from 节9.2.3.3 ......................20

• Changed 图9-1, SDP(USB100/USB500) To: SDP (USB500) .........................................................................20

• Deleted USB SDP (USB100) and the OTG Pin column from 表9-3 and 表9-4 ............................................. 20

• Added text to the 节9.2.3.3.2 section: "To implement USB100 in the system...".............................................21

• Deleted section: Plug in USB100 Source ........................................................................................................ 21

• Added text to 节9.2.3.4, "After Input Voltage Limit Threshold..." .................................................................... 22

• Changed text in 节9.2.4 From: "After DCP type..." To: "After DCP or MaxCharge type" ................................22

• Changed 方程式1, From: BATCOMP, VREG + V_CLAMPTo: BATCOMP, V_CLAMP............................................ 26

• Changed the Description of the INLIM Bits in 表9-9 .......................................................................................37

• Changed , Bits 3 to 0, From: Default: 128mA (0011) To: Default: 256mA (0011)............................................. 42

• Changed Bit 1 From: SDP_STAT To: Reserved .............................................................................................. 48

• Changed V_INTo: V_BUSin 方程式6 ...................................................................................................................55

• Changed Input Capacitor To: 节10.2.2.2 ........................................................................................................ 55

• Changed I_CINto I_PMIDin 节10.2.2.2 and 方程式7 ...........................................................................................55

• Changed "15-V input voltage. 22-μF capacitanc" To: "14-V input voltage. 8.2-μF capacitance" in 节10.2.2.2

..........................................................................................................................................................................55

• Changed Output Capacitor To: 节10.2.2.3 ......................................................................................................55

• Changed I_COUTTo: I_CSYSin 方程式8 , Changed 方程式9 .............................................................................. 55

• Deleted Graph "Power UP"...............................................................................................................................56

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5 说明（续）

具有充电和系统设置的I²C 串行接口使得此器件成为真正的灵活解决方案。

BQ25890/2 是一款适用于单节锂离子电池和锂聚合物电池的高度集成型 5A 开关模式电池充电管理和系统电源路

径管理器件。该器件支持高输入电压快速充电，适用于各类智能手机、平板电脑和便携式设备。其低阻抗电源路

径对开关模式运行效率进行了优化、缩短了电池充电时间并延长了放电阶段的电池使用寿命。该器件还集成了输

入电流优化器 (ICO) 和电阻补偿 (IRCOMP)，从而为电池提供最大充电功率。该解决方案在系统和电池之间高度

集成输入反向阻断 FET（RBFET，Q1）、高侧开关 FET（HSFET，Q2）、低侧开关 FET（LSFET，Q3）以及

电池 FET（BATFET，Q4）。它还集成了自举二极管以进行高侧栅极驱动和电池监视，从而简化系统设计。具有

充电和系统设置的I²C 串行接口使得此器件成为一个真正的灵活解决方案。

该器件支持多种输入源，包括标准 USB 主机端口、USB 充电端口以及兼容USB 的可调高电压适配器。为支持通

过可调高电压适配器进行快速充电，BQ25890 提供了 MaxCharge^TM握手支持（使用 D+/D– 引脚和 DSEL 引

脚）来进行 USB 开关控制。此外，BQ25890 和 BQ25892 还提供有相应的接口，以支持采用输入电流脉冲协议

的可调高电压适配器。为了设置默认输入电流限值，器件使用内置 USB 接口 (BQ25890) 或者从 USB PHY 器件

等系统检测电路中获取结果 (BQ25892)。该器件符合USB 2.0 和USB 3.0 电源规范，具有输入电流和电压调节功

能。此外，输入电流优化器 (ICO) 还能够检测输入源未发生过载时的最大功率点。该器件还具有高达 2.4A 的限流

能力，能够为VBUS 提供5V（4.5V 至5.5V 可调）电压，符合USB On-the-Go (OTG) 运行功率额定值规范。

电源路径管理将系统电压调节为稍稍高于电池电压，但是又不会下降到低于3.5V 最小系统电压（可编程）。借助

于这个特性，即使在电池电量完全耗尽或者电池被拆除时，系统也能保持运行。当达到输入电流限值或电压限值

时，电源路径管理技术自动将充电电流减至0。随着系统负载持续增加，电源路径将使电池放电，直到满足系统电

源需求。该补充模式操作可防止输入源过载。

此器件在无需软件控制情况下启动并完成一个充电周期。它自动检测电池电压并通过三个阶段为电池充电：预充

电、恒定电流和恒定电压。在充电周期的末尾，当充电电流低于在恒定电压阶段中预设定的限值时，充电器自动

终止。当整个电池下降到低于再充电阈值时，充电器将自动启动另外一个充电周期。

此充电器提供针对电池充电和系统运行的多种安全特性，其中包括电池负温度系数热敏电阻监视、充电安全性定

时器和过压/过流保护。当结温超过 120°C（可编程）时，热调节会减小充电电流。STAT 输出报告充电状态和任

何故障状况。PG 输出(BQ25892) 指示电源是否正常。当故障发生时，INT 会立即通知主机。

该器件还提供了一个7 位模数转换器 (ADC)，用于监视充电电流和输入/电池/系统（VBUS、BAT、SYS、TS）电

压。QON 引脚提供BATFET 使能/复位控制，以使器件退出低功耗出厂模式或完全系统复位功能。

该器件系列采用24 引脚4mm x 4mm²x 0.75mm 薄型WQFN 封装。

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6 Device Comparison Table

BQ25890

BQ25892

I²C Address

Charge Mode Frequency

Boost Mode Frequency

USB Detection

6AH (1101010B + R/ W)

6BH (1101011B + R/ W)

1.5 MHz

1.5 MHz (default) / 500 KHz

PSEL/OTG

14 V

D+/D–

14 V

VBUS Overvoltage

REGN LDO

6 V

Default Adapter Current Limit

Default Battery Charge Voltage

Maximum Charge Current

Default Charge Current

Default Pre-charge Current

Maximum Pre-charge Current

Maximum Boost Mode Output Current

Charging Temperature Profile

Pin 24

3.25 A

4.208 V

5.056 A

2.048 A

128 mA

1.024 A

2.4A

3.25 A

4.208 V

5.056A

2.048 A

128 mA

1.024A

2.4A

JEITA

DSEL

STAT

JEITA

NC

Status Output

STAT, PG

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7 Pin Configuration and Functions

23

22

20

19

24

21

VBUS

D+

1

2

3

4

5

6

18

17

PGND

SYS

16

15

D–

STAT

SCL

SYS

14

BAT

13

SDA

7

8

9

10

11

12

图7-1. RTW Package 24-Pin WQFN Top View

23

22

20

19

24

21

VBUS

PSEL

1

2

3

4

5

6

18

17

PGND

SYS

16

15

PG

SYS

STAT

SCL

SDA

14

BAT

13

7

8

9

10

11

12

图7-2. RTW Package 24-Pin WQFN Top View

TYPE⁽¹⁾

DESCRIPTION

NAME

BQ25890

BQ25892

Charger Input Voltage.

The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with

VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as

possible to IC.

VBUS

1

P

Positive line of the USB data line pair.

D+

2

AIO

DI

D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD),

primary and secondary detection in BC1.2, and Adjustable high voltage adapter.

–

Power source selection input.

High indicates a USB host source and Low indicates an adapter source.

PSEL

2

–

6

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TYPE⁽¹⁾

DESCRIPTION

NAME

BQ25890

BQ25892

Negative line of the USB data line pair.

3

AIO

D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD),

primary and secondary detection in BC1.2, and Adjustable high voltage adapter.

D–

–

Open drain active low power good indicator.

Connect to the pull up rail via 10-kΩresistor. LOW indicates a good input source if the input voltage

is within V_{VBUS_OP}, above SLEEP mode threshold (V_SLEEPZ), and current limit is above I_BATSRC(30

mA).

PG

3

4

DO

–

Open drain charge status output to indicate various charger operation.

Connect to the pull up rail via 10-kΩresistor. LOW indicates charge in progress. HIGH indicates

charge complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz.

The STAT pin function can be disabled when STAT_DIS bit is set.

STAT

4

I²C Interface clock.

Connect SCL to the logic rail through a 10-kΩresistor.

SCL

SDA

5

6

5

6

DI

I²C Interface data.

Connect SDA to the logic rail through a 10-kΩresistor.

DIO

Open-drain Interrupt Output.

INT

OTG

CE

7

8

9

7

8

9

DO

DI

Connect the INT to a logic rail via 10-kΩresistor. The INT pin sends active low, 256-µs pulse to host

to report charger device status and fault.

Active high enable pin during boost mode.

The boost mode is activated when OTG_CONFIG =1 and OTG pin is high

Active low Charge Enable pin.

Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High

or Low.

DI

Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input

current

ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is

connected from ILIM pin to ground to set the maximum limit as I_INMAX= K_ILIM/R_ILIM. The actual input

current limit is the lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input

current limit of less than 500 mA is not support on ILIM pin.

ILIM

10

AI

ILIM pin can also be used to monitor input current when the voltage is below 0.8 V. The input current

is proportional to the voltage on ILIM pin and can be calculated by I_IN= (K_ILIMx V_ILIM) / (R_ILIMx 0.8)

The ILIM pin function can be disabled when EN_ILIM bit is 0.

Temperature qualification voltage input.

Connect a negative temperature coefficient thermistor. Program temperature window with a resistor

divider from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend

103AT-2 thermistor.

TS

11

12

11

12

AI

DI

BATFET enable/reset control input.

When BATFET is in ship mode, a logic low of t_SHIPMODE(typical 1sec) duration turns on BATFET to

exit shipping mode. .

When VBUS is not plugged-in, a logic low of t_{QON_RST}(typical 15sec) duration resets SYS (system

power) by turning BATFET off for t_{BATFET_RST}(typical 0.3sec) and then re-enable BATFET to provide

full system power reset.

QON

The pin contains an internal pull-up to maintain default high logic

Battery connection point to the positive terminal of the battery pack.

The internal BATFET is connected between BAT and SYS. Connect a 10 µF closely to the BAT pin.

BAT

SYS

13,14

15,16

13, 14

15,16

P

System connection point.

The internal BATFET is connected between BAT and SYS. When the battery falls below the

minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage.

Connect a 20 µF closely to the SYS pin.

Power ground connection for high-current power converter node.

Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect

directly to ground connection of input and output capacitors of the charger. A single point connection

is recommended between power PGND and the analog GND near the IC PGND pin.

PGND

17,18

P

Switching node connecting to output inductor.

SW

19,20

21

19,20

21

P

Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel

LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST.

PWM high side driver positive supply.

Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 µF

bootstrap capacitor from SW to BTST.

BTST

PWM low side driver positive supply output.

Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 µF (10 V

rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC.

REGN also serves as bias rail of TS pin.

REGN

PMID

22

23

22

23

P

Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET.

Given the total input capacitance, put 1 µF on VBUS to PGND, and the rest capacitance on PMID to

PGND.

DO

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TYPE⁽¹⁾

DESCRIPTION

Open-drain D+/D- multiplexer selection output.

NAME

BQ25890

BQ25892

Connect the DSEL to a logic rail via 10-KΩ resistor. The pin is normally float and pull-up by external

resistor. During 节9.2.3.3, the pin drives low to indicate the BQ25890 D+/D- detection is in progress

and needs to take control of D+, D- signals. When detection is completed, the pin keeps low when

MaxCharge™ adapter is detected. The pin returns to float and pulls high by external resistor when

other input source type is detected.

DSEL

24

DO

–

NC

24

No Connect

–

Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and

have vias on the PowerPAD plane star-connecting to PGND and ground plane for high-current power

converter.

PowerPAD^™

P

(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)

8

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8 Specifications

8.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–2

MAX

22

20

7

VALUE

V

VBUS (converter not switching)

PMID (converter not switching)

V

–0.3

–2

STAT

V

PG (BQ25892)

DSEL (BQ25890)

BTST

V

20

16

6

V

SW

V

SW (peak for 10 ns duration)

BAT, SYS (converter not switching)

SDA, SCL, INT, OTG, REGN, TS, CE, QON

PSEL (BQ25892)

V

Voltage range (with respect to GND)

–3

V

–0.3

7

V

7

V

7

V

D+, D–(BQ25890)

BTST TO SW

PGND to GND

ILIM

7

V

0.3

5

V

INT, STAT

6

mA

°C

Output sink current

PG (BQ25892)

DSEL (BQ25890)

6

150

Junction temperature

–40

–65

Storage temperature range, T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

±2000

V

V_ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

14⁽¹⁾

3.25

5

UNIT

V_IN

Input voltage

3.9

V

A

V

I_IN

Input current (VBUS)

Output current (SW)

Battery voltage

I_SYS

V_BAT

4.608

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8.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

5

UNIT

A

Fast charging current

Up to 6 (continuos)

A

I_BAT

Discharging current with internal MOSFET

9 (peak)

(Up to 1 sec duration)

A

T_A

Operating free-air temperature range

85

°C

–40

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight

layout minimizes switching noise.

8.4 Thermal Information

BQ25890

BQ25892

THERMAL METRIC⁽¹⁾

UNIT

RTW (WQFN)

24-PINS

31.8

27.9

8.7

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC((op)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JT

8.7

ψ_JB

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

QUIESCENT CURRENTS

V_BAT= 4.2 V, V_(VBUS)< V_(UVLO), leakage

between BAT and VBUS

5

µA

High-Z mode, no VBUS, BATFET disabled

(REG09[5]=1), battery monitor disabled, T_J

85°C

<

12

32

23

I_BAT

Battery discharge current (BAT, SW, SYS) in buck mode

High-Z mode, no VBUS, BATFET enabled

(REG09[5]=0), battery monitor disabled, T_J

85°C

60

µA

V_(VBUS)= 5 V, High-Z mode, no battery, battery

monitor disabled

15

25

1.5

3

35

50

3

µA

Input supply current (VBUS) in buck mode when High-Z mode

is enabled

I_{(VBUS_HIZ)}

V_(VBUS)= 12 V, High-Z mode, no battery, battery

monitor disabled

V_BUS> V_(UVLO), V_BUS> V_BAT, converter not

switching

mA

V_BUS> V_(UVLO), V_BUS> V_BAT, converter

switching, V_BAT= 3.2 V, I_SYS= 0A

I_(VBUS)

Input supply current (V_BUS) in buck mode

Battery discharge current in boost mode

V_BUS> V_(UVLO), V_BUS> V_BAT, converter

switching, V_BAT= 3.8 V, I_SYS= 0 A

3

V_BAT= 4.2 V, boost mode, I_(VBUS)= 0 A,

converter switching

I_(BOOST)

5

VBUS/BAT POWER UP

V_{(VBUS_OP)}

V_{(VBUS_UVLOZ)}

V_(SLEEP)

VBUS operating range

3.9

3.6

25

14

V

VBUS for active I²C, no battery

Sleep mode falling threshold

Sleep mode rising threshold

65

120

370

mV

V_(SLEEPZ)

130

250

10

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

14

TYP

MAX

14.6

14

UNIT

V

VBUS over-voltage rising threshold

VBUS over-voltage falling threshold

Battery for active I2C, no VBUS

Battery depletion falling threshold

Battery depletion rising threshold

Bad adapter detection threshold

Bad adapter detection current source

V_(ACOV)

13.5

2.3

V

V_BAT(UVLOZ)

V_BAT(DPL)

V_BAT(DPLZ)

V_(VBUSMIN)

I_(BADSRC)

V

2.15

2.35

2.5

2.7

V

3.8

30

V

mA

POWER-PATH MANAGEMENT

I_(SYS)= 0 A, V_BAT> V_SYS(MIN), BATFET Disabled

(REG09[5]=1)

V_BAT

50 mV

+

V

V_SYS

Typical system regulation voltage

I_(SYS)= 0 A, V_BAT< V_SYS(MIN), BATFET Disabled

(REG09[5]=1)

V_SYS(MIN)

+

150 mV

V_BAT< V_SYS(MIN), SYS_MIN = 3.5 V

(REG03[3:1]=101), I_SYS= 0 A

V_SYS(MIN)

Minimum DC system voltage output

Maximum DC system voltage output

3.50

3.65

4.40

V_BAT= 4.35 V, SYS_MIN = 3.5V

(REG03[3:1]=101), I_SYS= 0 A

V_SYS(MAX)

4.42

27

38

44

39

47

24

28

T_J= –40°C to +85°C

T_J= –40°C to +125°C

T_J= –40°C to +85°C

T_J= –40°C to +125°C

T_J= –40°C to +85°C

T_J= –40°C to +125°C

BAT discharge current 10 mA

V_BATrising

mΩ

mV

V

Top reverse blocking MOSFET(RBFET) on-resistance between

VBUS and PMID

R_ON(RBFET)

R_ON(HSFET)

R_ON(LSFET)

27

Top switching MOSFET (HSFET) on-resistance between PMID

and SW

27

16

Bottom switching MOSFET (LSFET) on-resistance between

SW and GND

16

V_(FWD)

BATFET forward voltage in supplement mode

Battery good comparator rising threshold

Battery good comparator falling threshold

30

V_BAT(GD)

3.4

3.55

100

3.7

V_{BAT(GD_HYST)}

BATTERY CHARGER

V_{BAT(REG_RANGE)}

V_{BAT(REG_STEP)}

V_BATfalling

mV

Typical charge voltage range

Typical charge voltage step

3.840

4.608

V

16

64

mV

V_BAT= 4.208 V (REG06[7:2]=010111) or

V_BAT= 4.352 V (REG06[7:2]=100000)

T_J= –40°C to +85°C

V_BAT(REG)

Charge voltage resolution accuracy

-0.5%

0

0.5%

5056

I_{(CHG_REG_RANGE)}

I_{(CHG_REG_STEP)}

Typical fast charge current regulation range

Typical fast charge current regulation step

mA

V_BAT= 3.1 V or 3.8 V, I_CHG= 128 mA

T_J= –40°C to +85°C

-20%

-10%

-5%

20%

10%

5%

V_BAT= 3.1 V or 3.8 V, I_CHG= 256 mA

T_J= –40°C to +85°C

I_{(CHG_REG_ACC)}

Fast charge current regulation accuracy

V_BAT= 3.1 V or 3.8 V, I_CHG=1792 mA

T_J= –40°C to +85°C

Battery LOWV falling threshold

Battery LOWV rising threshold

Fast charge to precharge, BATLOWV

(REG06[1]) = 1

2.6

2.8

3

2.9

V

V_BAT(LOWV)

Precharge to fast charge, BATLOWV

(REG06[1])=1

(Typical 200-mV hysteresis)

2.8

64

3.1

I_{(PRECHG_RANGE)}

I_{(PRECHG_STEP)}

I_{(PRECHG_ACC)}

I_{(TERM_RANGE)}

I_{(TERM_STEP)}

Precharge current range

1024

mA

Typical precharge current step

Precharge current accuracy

Termination current range

Typical termination current step

64

V_BAT=2.6 V, I_PRECHG= 256 mA

+10%

1024

–10%

64

mA

I_TERM= 256 mA, I_CHG<= 1344 mA

T_J= –20°C to +85°C

12%

20%

–12%

–20%

I_{(TERM_ACC)}

Termination current accuracy

I_TERM= 256 mA, I_CHG> 1344 mA

T_J= –20°C to +85°C

V_(SHORT)

Battery short voltage

VBAT falling

VBAT rising

VBAT < 2.2 V

2

200

100

V

V_{(SHORT_HYST)}

I_(SHORT)

Battery short voltage hysteresis

Battery short current

mV

mA

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

V_BATfalling, VRECHG (REG06[0]=0) = 0

V_BATfalling, VRECHG (REG06[0]=0) = 1

V_BAT= 4.2 V

MIN

TYP

100

200

MAX

UNIT

mV

V_(RECHG)

Recharge threshold below V_BATREG

mV

I_BAT(LOAD)

I_SYS(LOAD)

Battery discharge load current

System discharge load current

15

30

mA

V_SYS= 4.2 V

mA

T_J= 25°C

11

13

19

mΩ

R_ON(BATFET)

SYS-BAT MOSFET (BATFET) on-resistance

T_J= –40°C to +125°C

INPUT VOLTAGE / CURRENT REGULATION

V_{IN(DPM_RANGE)}

V_{IN(DPM_STEP)}

V_{IN(DPM_ACC)}

I_{IN(DPM_RANGE)}

I_{IN(DPM_STEP)}

I_{IN(DPM100_ACC)}

Typical Input voltage regulation range

3.9

15.3

V

Typical Input voltage regulation step

Input voltage regulation accuracy

Typical Input current regulation range

Typical Input current regulation step

100

mV

VINDPM = 4.4 V, 9 V

3%

100

3250

mA

50

90

Input current 100-mA regulation accuracy

V_BAT= 5 V, current pulled from SW

IINLIM (REG00[5:0]) =100 mA

85

100

mA

USB150, IINLIM (REG00[5:0]) = 150 mA

USB500, IINLIM (REG00[5:0]) = 500 mA

USB900, IINLIM (REG00[5:0]) = 900 mA

Adapter 1.5 A, IINLIM (REG00[5:0]) = 1500 mA

V_SYS= 2.2 V, IINLIM (REG00[5:0])> = 200 mA

Input current regulation by ILIM pin = 1.5 A

125

440

135

470

150

500

mA

Input current regulation accuracy

V_BAT= 5 V, current pulled from SW

I_{IN(DPM_ACC)}

750

825

900

mA

1300

1400

1500

200

mA

I_IN(START)

K_ILIM

Input current regulation during system start up

I_INMAX= K_ILIM/R_ILIM

mA

320

355

390

A x Ω

D+/D- DETECTION (BQ25890)

V_{(0P6_VSRC)}

V_{(3P3_VSRC)}

V_{(3p45_VSRC)}

I_{(10UA_ISRC)}

I_{(100UA_ISINK)}

I_{(DPDM_LKG)}

0.5

3.2

3.3

7

0.6

3.3

0.7

3.4

3.6

14

V

D+/D–voltage source (0.6 V)

D+ voltage source (3.3V)

For HVDCP detection

3.45

10

V

D+/D–voltage source (3.45 V)

D+ connection check current source

D+/D–current sink (100 µA)

D+/D–leakage current

µA

50

100

150

1

D–, switch open

–1

D+, switch open

1

1.75

400

0.8

µA

mV

V

I_{(1P6MA_ISINK)}

V_{(0P4_VTH)}

1.45

250

1.60

D+/D–current sink (1.6 mA)

D+/D–low comparator threshold

D+ low comparator threshold

V_{(0P8_VTH)}

V_{(2P7HI_VTH)}

Internal only

2.85

2.35

2.55

2.15

1.6

3.1

V

D+/D–comparator threshold for non-standard adapter

detection (Divider 1, 3, or 4)

V_{(2P7LO_VTH)}

2.55

2.85

2.35

1.85

2.15

1.60

1.05

1.35

V

D+/D–comparator threshold for non-standard adapter

detection (Divider 1, 3, or 4)

V_{(2P7_VTH)}

D+/D- comparator threshold for non-standard adapter

detection (Divider 1, 3, or 4)

V_{(2P0HI_VTH)}

V_{(2P0LO_VTH)}

V_{(2P0_VTH)}

Internal only

D+/D–comparator threshold for non-standard adapter

detection (Divider 1, 3)

D+/D–comparator threshold for non-standard adapter

detection (Divider 1, 3)

1.85

1.35

0.85

1.05

D+/D–comparator threshold for non-standard adapter

detection (Divider 1, 3)

V_{(1P2HI_VTH)}

V_{(1P2LO_VTH)}

V_{(1P2_VTH)}

Internal only

D+/D–comparator threshold for non-standard adapter

detection (Divider 2)

D+/D–comparator threshold for non-standard adapter

detection (Divider 2)

D+/D–comparator threshold for non-standard adapter

detection (Divider 2)

R_{(D–_DWN)}

V_{(6P5_VTH)}

14.25

6.3

24.8

6.7

D–pulldown for connection check

kΩ

VBUS comparator threshold

Internal only

V

BAT OVERVOLTAGE/CURRENT PROTECTION

V_BAT(OVP)

Battery over-voltage threshold

Battery over-voltage hysteresis

System over-current threshold

V_BATrising, as percentage of V_BAT(REG)

V_BATfalling, as percentage of V_BAT(REG)

104%

2%

V_{BAT(OVP_HYST)}

I_{BAT(FET_OCP)}

9

A

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL REGULATION AND THERMAL SHUTDOWN

T_REG

Junction temperature regulation accuracy

Thermal shutdown rising temperature

Thermal shutdown hysteresis

REG08[1:0] = 11

120

160

30

°C

T_SHUT

Temperature rising

Temperature falling

T_SHUT(HYS)

JEITA THERMISTOR COMPARATOR (BUCK MODE)

T1 (0°C) threshold, charge suspended T1 below this

temperature.

V_(T1)

As percentage to V_(REGN)

72.75%

67.75%

44.25v

73.25%

1.4%

73.75%

68.75%

45.25%

34.875%

Charge back to ICHG/2 (REG04[6:0]) and VREG (REG06[7:2])

above this temperature.

V_{(T1_HYS)}

T2 (10°C) threshold, charge back to ICHG/2 (REG04[6:0]) and

VREG (REG06[7:2]) below this temperature.

V_(T2)

68.25%

1.4%

Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])

above this temperature.

V_{(T2_HYS)}

T3 (45°C) threshold, charge back to ICHG (REG04[6:0]) and

VREG-200 mV (REG06[7:2]) above this temperature.

V_(T3)

44.75%

1%

Charge back to ICHG (REG04[6:0]) and VREG (REG06[7:2])

below this temperature.

V_{(T3_HYS)}

T5 (60°C) threshold, charge suspended above this

temperature.

V_(T5)

33.875%

34.375%

1.25%

Charge back to ICHG (REG04[6:0]) and VREG-200 mV

(REG06[7:2]) below this temperature.

V_{(T5_HYS)}

COLD/HOT THERMISTOR COMPARATOR (BOOST MODE)

As percentage to V_REGN, REG01[5] = 0

(Approx. -10°C w/ 103AT)

V_(BCOLD0)

Cold temperature threshold, TS pin voltage rising threshold

76.5%

79.5%

77%

1%

77.5%

80.5%

V_{(BCOLD0_HYS)}

V_(BCOLD1)

V_{(BCOLD1_HYS)}

V_(BHOT0)

V_{(BHOT0_HYS)}

V_(BHOT1)

V_{(BHOT1_HYS)}

V_(BHOT2)

Cold temperature threshold, TS pin voltage falling threshold

Cold temperature threshold 1, TS pin voltage rising threshold

Cold temperature threshold 1, TS pin voltage falling threshold

Hot temperature threshold, TS pin voltage falling threshold

Hot temperature threshold, TS pin voltage rising threshold

Hot temperature threshold 1, TS pin voltage falling threshold

Hot temperature threshold 1, TS pin voltage rising threshold

Hot temperature threshold 2, TS pin voltage falling threshold

Hot temperature threshold 2, TS pin voltage rising threshold

As percentage to V_REGNREG01[5] = 0

As percentage to V_REGNREG01[5] = 1

(Approximately –20°C w/ 103AT)

80%

As percentage to V_REGNREG01[5] = 1

1%

As percentage to V_REGNREG01[7:6] = 01

(Approx. 55°C w/ 103AT)

37.25%

33.875%

30.75%

37.75%

3%

38.25%

34.875%

31.75%

As percentage to V_REGNREG01[7:6] = 01

As percentage to V_REGNREG01[7:6] = 00

(Approx. 60°C w/ 103AT)

34.375%

3%

As percentage to V_REGNREG01[7:6] = 00

As percentage to V_REGNREG01[7:6] = 10

(Approx. 65°C w/ 103AT)

31.25%

3%

V_{(BHOT2_HYS)}

PWM

As percentage to V_REGNREG01[7:6] =10

F_SW

PWM switching frequency, and digital clock

Maximum PWM duty cycle

Oscillator frequency

1.32

1.68

MHz

D_MAX

97%

64

BOOST MODE OPERATION

V_{(OTG_REG_RANGE)}Typical boost mode regulation voltage range

V_{(OTG_REG_STEP)}

4.55

5.55

3%

V

Typical boost mode regulation voltage step

Boost mode regulation voltage accuracy

mV

I(VBUS) = 0 A, BOOSTV=4.998V (REG0A[7:4]

= 0111)

V_{(OTG_REG_ACC)}

–3%

V_{(OTG_BAT)}

I_(OTG)

Battery voltage exiting boost mode

BAT falling

2.6

0.5

1.2

5.8

2.9

2.45

1.65

V

A

V

Typical boost mode output current range

Boost mode RBFET over-current protection accuracy

Boost mode over-voltage threshold

I_{(OTG_OCP_ACC)}

V_{(OTG_OVP)}

REGN LDO

V_(REGN)

BOOST_LIM =1.2 A (REG0A[2:0]=010)

Rising threshold

6

REGN LDO output voltage

REGN LDO current limit

V_(VBUS)= 9 V, I_(REGN)= 40 mA

V_(VBUS)= 5 V, I_(REGN)= 20 mA

V_(VBUS)= 9 V, V_(REGN)= 3.8 V

5.6

4.7

50

6

6.4

V

4.8

I_(REGN)

mA

ANALOG-TO-DIGITAL CONVERTER (ADC)

RES

Resolution

Rising threshold

7

bits

V

V_(VBUS)> V_BAT+ V_(SLEEP)or OTG mode is

enabled

2.304

4.848

V_BAT(RANGE)

Typical battery voltage range

V_(VBUS)< V_BAT+ V_(SLEEP)and OTG mode is

disabled

V_{SYS_MIN}

V

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8.5 Electrical Characteristics (continued)

V_{VBUS_UVLOZ}< V_VBUS< V_ACOVand V_VBUS> V_BAT+ V_SLEEP, T_J= –40°C to +125°C and T_J= 25°C for typical values (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{(BAT_RES)}

Typical battery voltage resolution

20

mV

V_(VBUS)> V_BAT+ V_(SLEEP)or OTG mode is

enabled

2.304

4.848

V

V_{(SYS_RANGE)}

Typical system voltage range

V_(VBUS)< V_BAT+ V_(SLEEP)and OTG mode is

disabled

V_{SYS_MIN}

V_{(SYS_RES)}

Typical system voltage resolution

Typical V_VBUSvoltage range

20

mV

V

V_(VBUS)> V_BAT+ V_(SLEEP)or OTG mode is

enabled

2.6

15.3

V_{(VBUS_RANGE)}

V_{(VBUS_RES)}

I_BAT(RANGE)

Typical V_VBUSvoltage resolution

Typical battery charge current range

100

mV

A

V_(VBUS)> V_BAT+ V_(SLEEP)and V_BAT

V_BAT(SHORT)

>

0

6.4

I_BAT(RES)

Typical battery charge current resolution

Typical TS voltage range

50

mA

V_{(TS_RANGE)}

V_{(TS_RES)}

21%

80%

Typical TS voltage resolution

0.47%

LOGIC I/O PIN (OTG, CE, PSEL, QON)

V_IH

Input high threshold level

1.3

V_IL

Input low threshold level

0.4

1

V

µA

V

I_IN(BIAS)

High Level Leakage Current

Pull-up rail 1.8 V

Battery only mode

V_(VBUS)= 9 V

BAT

5.8

V_(QON)

Internal /QON pull-up

V

V_(VBUS)= 5 V

4.3

V

200

R_(QON)

Internal /QON pull-up resistance

kΩ

LOGIC I/O PIN (INT, STAT, PG , DSEL)

V_OL

Output low threshold level

High level leakage current

Sink current = 5 mA, sink current

Pull-up rail 1.8 V

0.4

1

V

I_{OUT_BIAS}

µA

I²C INTERFACE (SCL, SDA)

V_IH

Input high threshold level, SCL and SDA

Pull-up rail 1.8 V

1.3

V_IL

Input low threshold level

Output low threshold level

High level leakage current

Pull-up rail 1.8 V

0.4

1

V

V_OL

I_BIAS

Sink current = 5 mA, sink current

Pull-up rail 1.8 V

µA

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8.6 Timing Requirements

MIN

NOM

MAX UNIT

VBUS/BAT POWER UP

t_BADSRC

Bad Adapter detection duration

30

msec

BAT OVER-VOLTAGE PROTECTION

Battery over-voltage deglitch time to disable

charge

t_BATOVP

1

µs

BATTERY CHARGER

t_RECHG

Recharge deglitch time

20

ms

CURRENT PULSE CONTROL

t_{PUMPX_STOP}

t_{PUMPX_ON1}

t_{PUMPX_ON2}

t_{PUMPX_OFF}

t_{PUMPX_DLY}

Current pulse control stop pulse

430

240

70

570

360

130

225

ms

Current pulse control long on pulse

Current pulse control short on pulse

Current pulse control off pulse

70

Current pulse control stop start delay

80

BATTERY MONITOR

t_CONV

Conversion time

CONV_RATE(REG02[6]) = 0

8

1000

ms

QON AND SHIPMODE TIMING

QON low time to turn on BATFET and exit ship

mode

t_SHIPMODE

1.25

2.25

s

T_J= –10°C to +60°C

t_{QON_RST}

t_{BATFET_RST}

t_{SM_DLY}

QON low time to enable full system reset

BATFET off time during full system reset

Enter ship mode delay

12

350

10

18

550

15

s

ms

s

T_J= –10°C to +60°C

I2C INTERFACE

f_SCL

SCL clock frequency

400 kHz

DIGITAL CLOCK and WATCHDOG TIMER

f_LPDIG

f_DIG

Digital low power clock

Digital clock

REGN LDO disabled

REGN LDO enabled

18

30

45 kHz

1320

1500

1680 kHz

WATCHDOG (REG07[5:4])=11,

REGN LDO disabled

100

136

160

s

t_WDT

Watchdog reset time

WATCHDOG (REG07[5:4])=11,

REGN LDO enabled

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8.7 Typical Characteristics

95%

94%

93%

92%

91%

90%

89%

88%

87%

86%

85%

95%

93%

91%

89%

87%

85%

83%

81%

79%

77%

75%

VBUS = 5 V

VBUS = 9 V

VBUS = 12 V

VBUS = 5 V

VBUS = 9 V

VBUS = 12 V

0

0.5

1

System Load Current (A)

1.5

2

0

1

2 3

Charge Current (A)

4

5

D002

D001

图8-2. System Light Load Efficiency vs System Light Load

VBAT = 3.8 V

DCR = 10 mΩ

Current

图8-1. Charge Efficiency vs Charge Current

96%

94%

92%

90%

88%

86%

84%

82%

80%

6%

5%

4%

3%

2%

1%

0

-1%

-2%

-3%

-4%

VBAT = 3.1 V

VBAT = 3.8 V

VBUS = 3.2 V

VBUS = 3.8 V

-5%

-6%

0.5

1

1.5

2

2.5

3

Charge Current (A)

3.5

4

4.5

5

0

0.5

1

1.5

VBUS (A)

2

2.5

D005

D003

VBUS = 9 V

图8-3. Boost Mode Efficiency vs VBUS Load Current

图8-4. Charge Current Accuracy vs Charge Current I²C Setting

3.7

3.68

3.66

3.64

3.62

3.6

4.5

4.45

4.4

4.35

4.3

4.25

4.2

3.58

3.56

3.54

4.15

4.1

3.52

4.05

VBUS = 5 V

3.5

4

0

0.5

1

System Load Current (A)

1.5

2

2.5

3

0

0.5

1

System Load Current (A)

1.5

2

2.5

3

D006

D007

VBAT = 2.9 V

VBUS = 5 V

SYSMIN = 3.5 V

VBAT = 4.2 V

图8-5. SYS Voltage Regulation vs System Load Current

图8-6. SYS Voltage Regulation vs System Load Current

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8.7 Typical Characteristics (continued)

4.42

4.4

1600

1400

1200

1000

800

600

400

200

0

4.38

4.36

4.34

4.32

4.3

4.28

4.26

4.24

4.22

4.2

4.18

4.16

4.14

4.12

4.1

IINLM = 500 mA

IINLM = 900 mA

IINLIM = 1.5 A

VBUS = 5 V

VBUS = 12 V

-60 -40 -20

0

20 40 60 80 100 120 140150

Temperature (èC)

-50

0

50

Temperature (èC)

100

150

D009

D008

图8-8. Input Current Limit vs Temperature

图8-7. BAT Voltage vs Temperature

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9 Detailed Description

The device is a highly integrated 5-A siwtch-mode battery charger for single cell Li-Ion and Li-polymer battery. It

is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side siwtching FET (HSFET, Q2) ,

low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap

diode for the high-side gate drive.

9.1 Functional Block Diagram

VBUS

RBFET

PMID

(Q1)

V_{VBUS_UVLOZ}

UVLO

Q1 Gate

Control

V

_BATZ+80mV

SLEEP

ACOV

REGN

BTST

REGN

LDO

EN_HIZ

V

ACOV

FBO

VBUS

VBUS_OVP_BOOST

Q2_UCP_BOOST

V _{OTG_OVP}

I_Q2

V_INDPM

V

OTG_HSZCP

SW

I_Q3

Q3_OCP_BOOST

HSFET (Q2)

REGN

V

CONVERTER

CONTROL

I_INDPM

OTG_BAT

BAT

BATOVP

IC T_J

T_REG

104%xV_{BAT_REG}

BAT

I _{LSFET_UCP}

LSFET (Q3)

V _{BAT_REF}

PGND

UCP

I_Q2

Q2_OCP

I_Q3

SYS

I _{HSFET_OCP}

I_CHG

V_SYSMIN

EN_HIZ

EN_CHARGE

EN_BOOST

V _BTST-V_SW

I_{CHG_REF}

REFRESH

V_{BTST_REFRESH}

SYS

I_CHG

REF

DAC

Q4 Gate

Control

I_BADSRC

BATFET

(Q4)

BAD_SRC

I_DC

ILIM

Converter

Control State

Machine

DSEL (BQ25890)

IC T_J

TSHUT

T_SHUT

BAT

V_QON

BAT

D+ (BQ25890)

Dœ (BQ25890)

PSEL(BQ25892)

OTG

BAT_GD

Input

Source

Detection

V_BATGD

/QON

USB

I_CHG

ADC Control

Adapter

VBUS

BAT

SYS

TS

-V_RECHG

V_REG

BAT

RECHRG

ADC

INT

I_CHG

TERMINATION

BATLOWV

CHARGE

CONTROL

STATE

I_TERM

V _BATLOWV

BAT

STAT

BQ25890/892

MACHINE

V _SHORT

BAT

I2C

Interface

BATSHORT

SUSPEND

/PG(BQ25892)

Battery

Sensing

Thermistor

TS

SCL SDA

CE

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9.2 Feature Description

9.2.1 Device Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above

V_{VBUS_UVLOZ}or BAT rises above V_{BAT_UVLOZ}, the sleep comparator, battery depletion comparator and BATFET

driver are active. I²C interface is ready for communication and all the registers are reset to default value. The

host can access all the registers after POR.

9.2.2 Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (V_{BAT_DPLZ}), the BATFET turns on and

connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low R_DS(ON)of

BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.

The device always monitors the discharge current through BATFET (节 9.2.6.3). When the system is overloaded

or shorted (IBAT > I_{BATFET_OCP}), the device turns off BATFET immediately and set BATFET_DIS bit to indicate

BATFET is disabled until the input source plugs in again or one of the methods describe in 节 9.2.10.2 is applied

to re-enable BATFET.

9.2.3 Device Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all

the bias circuits. It detects and sets the input current limit before the buck converter is started when

AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:

1. Power Up REGN LDO

2. Poor Source Qualification

3. 节9.2.3.3 based on D+/D- (BQ25890) or PSEL (BQ25892) to set default Input Current Limit (IINLIM) register

and input source type

4. Input Voltage Limit Threshold Setting (VINDPM threshold)

5. Converter Power-up

9.2.3.1 Power Up REGN Regulation (LDO)

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also

provides bias rail to TS external resistors. The pull-up rail of STAT and PG can be connected to REGN as well.

The REGN is enabled when all the below conditions are valid.

1. VBUS above V_{VBUS_UVLOZ}

2. VBUS above V_BAT+ V_SLEEPZin buck mode or VBUS below V_BAT+ V_SLEEPin boost mode

3. After 220 ms delay is completed

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The

device draws less than I_{VBUS_HIZ}from VBUS during HIZ state. The battery powers up the system when the

device is in HIZ.

9.2.3.2 Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has

to meet the following requirements in order to start the buck converter.

1. VBUS voltage below V_ACOV

2. VBUS voltage above V_VBUSMINwhen pulling I_BADSRC(typical 30mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT

pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source

qualification every 2 seconds.

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9.2.3.3 Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs 节 9.2.3.3 when

AUTO_DPDM_EN bit is set.

The BQ25890 follows the USB Battery Charging Specification 1.2 (BC1.2) and to detect input source (SDP/CDP/

DCP) and non-standard adapter through USB D+/D- lines. In addition, when USB DCP is detected, it initiates

adjustable high voltage adapter handshake on D+/D-. The device supports MaxCharge™ handshake when

MAXC_EN or HVDCP_EN is set. The BQ25892 sets input current limit through PSEL and OTG pins.

After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin

are changed:

1. Input Current Limit (IINLIM) register is changed to set current limit

2. PG_STAT bit is set

3. PG pin goes low (BQ25892)

The host can over-write IINLIM register to change the input current limit if needed. The charger input current is

always limited by the lower of IINLIM register or ILIM pin at all-time regardless of Input Current Optimizer (ICO)

is enable or disabled.

When AUTO_DPDM_EN is disabled, the 节 9.2.3.3 is bypassed. The Input Current Limit (IINLIM) register,

VBUS_STAT, and SPD_STAT bits are unchanged from previous values.

9.2.3.3.1 D+/D–Detection Sets Input Current Limit (BQ25890)

The BQ25890 contains a D+/D– based input source detection to set the input current limit automatically. The

D+/D- detection includes standard USB BC1.2, non-standard adapter, and adjustable high voltage adapter

detections. When input source is plugged-in, the device starts standard USB BC1.2 detections. The USB BC1.2

is capable to identify Standard Downstream Port (SDP), Charging Downstream Port (CDP), and Dedicated

Charging Port (DCP). When the Data Contact Detection (DCD) timer of 500ms is expired, the non-standard

adapter detection is applied to set the input current limit.

When DCP is detected, the device initates adjustable high voltage adapter handshake including MaxCharge™,

etc. The handshake connects combinations of voltage source(s) and/or current sink on D+/D- to signal input

source to raise output voltage from 5 V to 9 V / 12 V. The adjustable high voltage adapter handshake can be

disabled by clearing MAXC_EN and/or HVDCP_EN bits.

Non-Standard Adapter

(Divider 1: 2.1A)

(Divider 2: 2A)

(Divider 3: 1A)

Non-Standard

Adapter

(Divider 4: 2.4A)

Adapter Plug-in

or

EN_DPDM

USB BC1.2

Detection

Ajustable High Voltage Adapter

Handshake

SDP (USB500)

(500mA)

CDP

(1.5A)

MaxCharge™ Apapter

(1.5A)

DCP

(3.25A)

图9-1. USB D+/D- Detection

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表9-1. Non-Standard Adapter Detection

NON-STANDARD

ADAPTER

D+ THRESHOLD

D- THRESHOLD

INPUT CURRENT LIMIT

Divider 1

Divider 2

Divider 3

Divider 4

V_D+within V_{2P7_VTH}

V_D+within V_{1P2_VTH}

V_D+within V_{2P0_VTH}

V_D+within V_{2P7_VTH}

V_D-within V_{2P0_VTH}

V_D-within V_{1P2_VTH}

V_D-within V_{2P7_VTH}

2.1A

2A

1A

2.4A

表9-2. Adjustable High Voltage Adapter D+/D- Output Configurations

ADJUSTABLE HIGH VOLTAGE HANDSHAKE

D+

D-

OUTPUT

MaxCharge (12V)

I_{1P6MA_ISINK}

V_{3p45_VSRC}

I_{1P6MA_ISINK}

12 V

MaxCharge (9V)

9 V

After the 节 9.2.3.3 is done, an INT pulse is asserted to the host. In addition, the following registers including

Input Current Limit register (IINLIM), VBUS_STAT, and SDP_STAT are updated as below:

表9-3. BQ25890 Result

INPUT CURRENT LIMIT (IINLIM)

D+/D- DETECTION

SDP_STAT

VBUS_STAT

(1)

USB SDP (USB500)

USB CDP

500 mA

1.5 A

3.25 A

1 A

1

001

010

011

110

100

101

USB DCP

Divider 3

Divider 1

2.1 A

2.4 A

2 A

Divider 4

Divider 2

MaxCharge

Unknown Adapter

1.5 A

500 mA

(1) 500 mA current limit for 2 min.

9.2.3.3.2 PSEL/OTG Pins Set Input Current Limit (BQ25892)

The BQ25892 has PSEL/OTG interface for input current limit setting to interface with USB PHY. It directly takes

the USB PHY device output to decide whether the input is USB host or charging port. To implement USB100 in

the system, the host can enter HiZ mode by setting EN_HIZ bit after 2 min charging with 500 mA input current

limit.

表9-4. BQ25892 Result

INPUT CURRENT LIMIT

INPUT DETECTION

BAT VOLTAGE

PSEL PIN

SDP_STAT

VBUS_STAT

(IINLIM)

500mA

3.25A

USB SDP (USB500)

Adapter

X

High

Low

1

001

010

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9.2.3.3.3 Force Input Current Limit Detection

In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is

completed, FORCE_DPDM bit returns to 0 by itself and Input Result is updated.

9.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two

methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.

1. Absolute VINDPM (FORCE_VINDPM=1)

By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM

is writable and allows host to set the absolute threshold of VINDPM function.

2. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)

When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM

register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The

algorithm allows a wide range of adapter (V_{VBUS_OP}) to be used with flexible VINDPM threshold.

After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.

9.2.3.5 Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery

charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input

current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the

device limits input current to the lower value of ILIM pin and IILIM register (ICO_EN = 0) or IDPM_LIM register

(ICO_EN = 1).

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed

frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery

voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-

tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp

height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below

minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is

set by the ratio of SYS and VBUS.

9.2.4 Input Current Optimizer (ICO)

The device provides innovative Input Current Optimizer (ICO) to identify maximum power point without overload

the input source. The algorithm automatically identify maximum input current limit of power source without

entering VINDPM to avoid input source overload.

This feature is enabled by default (ICO_EN=1) and can be disabled by setting ICO_EN bit to 0. After DCP or

MaxCharge type input source is detected based on the procedures previously described (节 9.2.3.3). The

algorithm runs automatically when ICO_EN bit is set. The algorithm can also be forced to execute by setting

FORCE_ICO bit regardless of input source type detected.

The actual input current limit used by the 节 9.2.6.2 is reported in IDPM_LIM register while Input Current

Optimizer is enabled (ICO_EN = 1) or set by IINLIM register when the algorithm is disabled (ICO_EN = 0). In

addition, the current limit is clamped by ILIM pin unless EN_ILIM bit is 0 to disable ILIM pin function.

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9.2.5 Boost Mode Operation from Battery

The device supports boost converter operation to deliver power from the battery to other portable devices

through USB port. The boost mode output current rating meets the USB On-The-Go 500 mA (BOOST_LIM bits =

000) output requirement. The maximum output current is up to 2.4 A. The boost operation can be enabled if the

conditions are valid:

1. BAT above BAT_LOWV

2. VBUS less than BAT+V_SLEEP(in sleep mode)

3. Boost mode operation is enabled (OTG pin HIGH and OTG_CONFIG bit =1)

4. Voltage at TS (thermistor) pin is within range configured by Boost Mode Temperature Monitor as configured

by BHOT and BCOLD bits

5. After 30 ms delay from boost mode enable

In boost mode, the device employs a 500 KHz or 1.5 MHz (selectable using BOOST_FREQ bit) step-up

switching regulator based on system requirements. To avoid frequency change during boost mode operations,

write to boost frequency configuration bit (BOOST_FREQ) is ignored when OTG_CONFIG is set.

During boost mode, the status register VBUS_STAT bits is set to 111, the VBUS output is 5V by default

(selectable via BOOSTV register bits) and the output current can reach up to 2.4 A, selected via I²C

(BOOST_LIM bits). The boost output is maintained when BAT is above V_{OTG_BAT}threshold

9.2.6 Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device

provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or

both.

9.2.6.1 Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The

minimum system voltage is set by SYS_MIN bits. Even with a fully depleted battery, the system is regulated

above the minimum system voltage (default 3.5 V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode),

and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the

minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the

V_DSof BATFET. The status register VSYS_STAT bit goes high when the system is in minimum system voltage

regulation.

4.4

Minimum System Voltage

SYS (Charge Disabled)

SYS (Charge Enabled)

4.2

4

3.8

3.6

3.4

2.7

2.9

3.1

3.3

3.5

BAT (V)

3.7

3.9

4.1

4.3

D011

图9-2. V(SYS) vs V(BAT)

9.2.6.2 Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic

Power Management (DPM), which continuously monitors the input current and input voltage. When input source

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is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below

the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below

the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to

drop. Once the system voltage falls below the battery voltage, the device automatically enters the 节 9.2.6.3

where the BATFET turns on and battery starts discharging so that the system is supported from both the input

source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high.

图 9-3 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum

system voltage setting.

Voltage

VBUS

SYS

BAT

3.6V

3.4V

3.2V

3.18V

Current

4A

ICHG

3.2A

2.8A

ISYS

1.2A

1.0A

IIN

0.5A

-0.6A

DPM

Supplement

图9-3. DPM Response

9.2.6.3 Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is

regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low.

This prevents oscillation from entering and exiting the 节 9.2.6.3. As the discharge current increases, the

BATFET gate is regulated with a higher voltage to reduce R_DS(ON)until the BATFET is in full conduction. At this

point onwards, the BATFET VDS linearly increases with discharge current. 图 9-4 shows the V-I curve of the

BATFET gate regulation operation. BATFET turns off to exit 节 9.2.6.3 when the battery is below battery

depletion threshold.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0

5

10 15 20 25 30 35 40 45 50 55

V_{(BAT_SYS)}(mV)

D010

图9-4. BATFET V-I Curve

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9.2.7 Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 5-A charge current for high capacity battery. The 11-mΩ

BATFET improves charging efficiency and minimize the voltage drop during discharging.

9.2.7.1 Autonomous Charging Cycle

With battery charging is enabled (CHG_CONFIG bit = 1 and CE pin is low), the device autonomously completes

a charging cycle without host involvement. The device default charging parameters are listed in 表 9-5. The host

can always control the charging operations and optimize the charging parameters by writing to the

corresponding registers through I²C.

表9-5. Charging Parameter Default Setting

DEFAULT MODE

Charging Voltage

Charging Current

Pre-charge Current

Termination Current

Temperature Profile

Safety Timer

BQ25890

4.208 V

2.048 A

128 mA

256 mA

JEITA

BQ25892

4.208 V

2.048 A

128 mA

256 mA

JEITA

12 hour

A new charge cycle starts when the following conditions are valid:

• Converter starts

• Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA

• No thermistor fault on TS pin

• No safety timer fault

• BATFET is not forced to turn off (BATFET_DIS bit = 0)

The charger device automatically terminates the charging cycle when the charging current is below termination

threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When

a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device

automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit

can initiate a new charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH)

or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status

register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast

charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an

INT is asserted to notify the host.

9.2.7.2 Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the

beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.

表9-6. Charging Current Setting

VBAT

< 2 V

CHARGING CURRENT

REG DEFAULT SETTING

CHRG_STAT

I_BATSHORT

01

10

–

I_PRECHG

128 mA

2048 mA

2 V –3 V

> 3 V

I_CHG

If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less

than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is

counted at half the clock rate.

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Regulation Voltage

(3.84V t 4.608V)

Battery Voltage

Charge Current

Fast Charge Current

(128mA-5056mA)

V

BAT_LOWV (2.8V/3V)

V

BAT_SHORT (2V)

I

PRECHARGE (64mA-1024mA)

TERMINATION (64mA-1024mA)

BATSHORT (100mA)

I

Fast Charge and Voltage Regulation

Trickle Charge

Pre-charge

Safety Timer

Expiration

图9-5. Battery Charging Profile

9.2.7.3 Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is

below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps

running to power the system, and BATFET can turn on again to engage 节9.2.6.3.

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host.

Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation.

Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

9.2.7.4 Resistance Compensation (IRCOMP)

For high current charging system, resistance between charger output and battery cell terminal such as board

routing, connector, MOSFETs and sense resistor can force the charging process to move from constant current

to constant voltage too early and increase charge time. To speed up the charging cycle, the device provides

resistance compensation (IRCOMP) feature which can extend the constant current charge time to delivery

maximum power to battery.

The device allows the host to compensate for the resistance by increasing the voltage regulation set point based

on actual charge current and the resistance as shown below. For safe operation, the host should set the

maximum allowed regulation voltage register (V_CLAMP) and the minimum resistance compensation (BATCOMP).

V_{REG_ACTUAL}= VREG + min(I_{CHRG_ACTUAL}x BATCOMP, V_CLAMP

)

(1)

9.2.7.5 Thermistor Qualification

9.2.7.5.1 JEITA Guideline Compliance in Charge Mode

To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline

emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high

temperature ranges.

The device continuously monitors battery temperature by measuring the voltage between the TS pins and

ground, typically determined by a negative temperature coefficient thermistor (NTC) and an external voltage

divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To

initiate a charge cycle, the voltage on TS pin must be within the V_T1to V_T5thresholds. If TS voltage exceeds the

T1–T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5

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range. At cool temperature (T1–T2), JEITA recommends the charge current to be reduced to at least half of the

charge current or lower. At warm temperature (T3–T5), JEITA recommends charge voltage below nominal

charge voltage.

The device provides flexible voltage/current settings beyond the JEITA requirement. The voltage setting at warm

temperature (T3–T5) can be 200 mV below charge voltage (JEITA_VSET=0). The current setting at cool

temperature (T1–T2) can be further reduced to 20% or 50% of fast charge current (JEITA_ISET bit).

REGN

BQ2589x

RT1

TS

RTH

RT2

103AT

图9-6. TS Resistor Network

VREG

VREG - 200 mV

图9-7. Charging Values

Assuming a 103AT NTC thermistor on the battery pack as shown in 图 9-6, the value RT1 and RT2 can be

determined by using 方程式2:

1

æ

ö

V_REGN´RTH_COLD´RTH_HOT

´

-

VT1 VT5

ç

÷

è

ø

RT2 =

V

æ

ö

æ

ö

REGN

RTH_HOT

´

-1 - RTH_COLD

´

ç

-1

÷

ç

÷

VT5

VT1

è

ø

è

ø

V_REGN

VT1

-1

RT1=

1

+

RT2 RTH_COLD

(2)

Select 0°C to 60°C range for Li-ion or Li-polymer battery,

RTH_T1= 27.28 kΩ

RTH_T5= 3.02 kΩ

RT1 = 5.24 kΩ

RT2 = 30.31 kΩ

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9.2.7.5.2 Cold/Hot Temperature Window in Boost Mode

For battery protection during boost mode, the device monitors the battery temperature to be within the V_BCOLDx

to V_BHOTxthresholds unless boost mode temperature is disabled by setting BHOT bits to 11. When temperature

is outside of the temperature thresholds, the boost mode is suspended. Once temperature is within thresholds,

the boost mode is recovered.

Temperature Range to

Boost

V_REGN

Boost Disable

V

BCOLDx

(-

10ºC / 20ºC)

Boost Enable

V

BHOTx

(55ºC / 60ºC / 65ºC)

Boost Disable

AGND

图9-8. TS Pin Thermistor Sense Thresholds in Boost Mode

9.2.7.6 Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The

safety timer is 4 hours when the battery is below V_BATLOWVthreshold. The user can program fast charge safety

timer through I²C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to

11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.

During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge

current is likely to be below the register setting. For example, if the charger is in input current regulation

(IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will

expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

9.2.8 Battery Monitor

The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system

voltage, thermistor ratio, and charging current, and charging current based on the device modes of operation.

The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be

configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second

continuous conversion.

For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the

conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The

conversion result is ready after t_CONV(maximum 1 second).

For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During

active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides

conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when

CONV_RATE is cleared.

When battery monitor is active, the REGN power is enabled and can increase device quiescent current. In

battery only mode, the battery monitor is only active when V_(BAT)> SYS_MIN setting in REG03.

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表9-7. Battery Monitor Modes of Operation

MODES OF OPERATION

PARAMETER

REGISTER

CHARGE

MODE

DISABLE CHARGE

BATTERY ONLY

MODE

BOOST MODE

MODE

Yes

Battery Voltage (V_BAT

System Voltage (V_SYS

Temperature (TS) Voltage (V_TS

VBUS Voltage (V_VBUS

Charge Current (I_BAT

)

REG0E

REG0F

REG10

REG11

REG12

Yes

NA

Yes

NA

)

Yes

)

Yes

)

Yes

)

NA

9.2.9 Status Outputs ( PG, STAT, and INT)

9.2.9.1 Power Good Indicator ( PG)

In BQ25892, the PG goes LOW to indicate a good input source when:

1. VBUS above V_{VBUS_UVLO}

2. VBUS above battery (not in sleep)

3. VBUS below V_ACOVthreshold

4. VBUS above V_VBUSMIN(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

5. Completed 节9.2.3.3

9.2.9.2 Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in 图

10-1. The STAT pin function can be disable by setting STAT_DIS bit.

表9-8. STAT Pin State

CHARGING STATE

STAT INDICATOR

LOW

Charging in progress (including recharge)

Charging complete

HIGH

Sleep mode, charge disable

HIGH

Charge suspend (Input overvoltage, TS fault, timer fault, input or system overvoltage).

Boost Mode suspend (due to TS Fault)

blinking at 1 Hz

9.2.9.3 Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the

device operation. The following events will generate 256-µs INT pulse.

• USB/adapter source identified (through PSEL or DPDM detection, with OTG pin)

• Good input source detected

– VBUS above battery (not in sleep)

– VBUS below V_ACOVthreshold

– VBUS above V_VBUSMIN(typical 3.8 V) when I_BADSRC(typical 30 mA) current is applied (not a poor source)

• Input removed

• Charge Complete

• Any FAULT event in REG0C

When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads

the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send

any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively.

The 1^stread reports the pre-existing fault register status and the 2^ndread reports the current fault register status.

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9.2.10 BATET (Q4) Control

9.2.10.1 BATFET Disable Mode (Shipping Mode)

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage,

the device can turn off BATFET so that the system voltage is zero to minimize the battery leakage current. When

the host set BATFET_DIS bit, the charger can turn off BATFET immediately or delay by t_{SM_DLY}as configurated

by BATFET_DLY bit.

9.2.10.2 BATFET Enable (Exit Shipping Mode)

When the BATFET is disabled (in shipping mode) and indicated by setting BATFET_DIS, one of the following

events can enable BATFET to restore system power:

1. Plug in adapter

2. Clear BATFET_DIS bit

3. Set REG_RST bit to reset all registers including BATFET_DIS bit to default (0)

4. A logic high to low transition on QON pin with t_SHIPMODEdeglitch time to enable BATFET to exit shipping

mode

9.2.10.3 BATFET Full System Reset

The BATFET functions as a load switch between battery and system when input source is not plugged-in. By

changing the state of BATFET from off to on, system connects to SYS can be effectively have a power-on-reset.

The QON pin supports push-button interface to reset system power without host by change the state of BATFET.

When the QON pin is driven to logic low for t_{QON_RST}(typical 15 seconds) while input source is not plugged in

and BATFET is enabled (BATFET_DIS=0), the BATFET is turned off for t_{BATFET_RST}and then it is re-enabled to

reset system power. This function can be disabled by setting BATFET_RST_EN bit to 0.

9.2.11 Current Pulse Control Protocol

The device provides the control to generate the VBUS current pulse protocol to communicate with adjustable

high voltage adapter in order to signal adapter to increase or decrease output voltage. To enable the interface,

the EN_PUMPX bit must be set. Then the host can select the increase/decrease voltage pulse by setting one of

the PUMPX_UP or PUMPX_DN bit (but not both) to start the VBUS current pulse sequence. During the current

pulse sequence, the PUMPX_UP and PUMPX_DN bits are set to indicate pulse sequence is in progress and the

device pulses the input current limit between current limit set forth by IINLIM or IDPM_LIM register and the

100mA current limit (I_{INDPM100_ACC}). When the pulse sequence is completed, the input current limit is returned to

value set by IINLIM or IDPM_LIM register and the PUMPX_UP or PUMPX_DN bit is cleared. In addition, the

EN_PUMPX can be cleared during the current pulse sequence to terminate the sequence and force charger to

return to input current limit as set forth by the IINLIM or IDPM_LIM register immediately. When EN_PUMPX bit is

low, write to PUMPX_UP and PUMPX_DN bit would be ignored and have no effect on VBUS current limit.

9.2.12 Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin.

The input maximum current is set by a resistor from ILIM pin to ground as:

K

ILIM

I

=

INMAX

R

ILIM

(3)

The actual input current limit is the lower value between ILIM setting and register setting (IINLIM). For example,

if the register setting is 111111 for 3.25 A, and ILIM has a 260-Ωresistor (KILIM = 390 max.) to ground for 1.5 A,

the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings

when EN_ILIM bit is set. The device regulates ILIM pin at 0.8 V. If ILIM voltage exceeds 0.8 V, the device enters

input current regulation (refer to 节9.2.6.2).

The ILIM pin can also be used to monitor input current when EN_ILIM is enabled. The voltage on ILIM pin is

proportional to the input current. ILIM pin can be used to monitor the input current following 方程式4:

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K

x V

ILIM

I

=

IN

R

x 0.8 V

ILIM

(4)

For example, if ILIM pin is set with 260-Ωresistor, and the ILIM voltage is 0.4 V, the actual input current 0.615 A

- 0.75 A (based on KILM specified). If ILIM pin is open, the input current is limited to zero since ILIM voltage

floats above 0.8 V. If ILIM pin is short, the input current limit is set by the register.

The ILIM pin function can be disabled by setting EN_ILIM bit to 0. When the pin is disabled, both input current

limit function and monitoring function are not available.

9.2.13 Thermal Regulation and Thermal Shutdown

9.2.13.1 Thermal Protection in Buck Mode

The device monitors the internal junction temperature T_Jto avoid overheat the chip and limits the IC surface

temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit

(TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C

allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current.

Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register

THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface

temperature exceeds T_SHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host.

The BATFET and converter is enabled to recover when IC temperature is below T_{SHUT_HYS}

.

9.2.13.2 Thermal Protection in Boost Mode

The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC

surface temperature exceeds T_SHUT, the boost mode is disabled (converter is turned off) by setting

OTG_CONFIG bit low and BATFET is turned off. When IC surface temperature is below T_{SHUT_HYS}, the BATFET

is enabled automatically to allow system to restore and the host can re-enable OTG_CONFIG bit to recover.

9.2.14 Voltage and Current Monitoring in Buck and Boost Mode

9.2.14.1 Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck and boost

mode operations.

9.2.14.1.1 Input Overvoltage (ACOV)

The input voltage for buck mode operation is V_{VBUS_OP}. If VBUS voltage exceeds V_ACOV, the device stops

switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT

is asserted to the host..

9.2.14.1.2 System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system

would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to

clamp the overshoot.

9.2.14.2 Voltage and Current Monitoring in Boost Mode

The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode

operation.

9.2.14.2.1 VBUS Overcurrent Protection

The charger device closely monitors the RBFET (Q1), and LSFET (Q3) current to ensure safe boost ode

operation. During overcurrent condition when output current exceed (I_{OTG_OCP}) the device operates in hiccup

mode for protection. While in hiccup mode cycle, the device turns off RBFET for t_{OTG_OCP_OFF}(30 ms typical)

and turns on RBFET for t_{OTG_OCP_ON}(250 µs typical) in an attempt to restart. If the overcurrent condition is

removed, the boost converter returns to normal operation. When overcurrent condition continues to exist, the

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device repeats the hiccup cycle until overcurrent condition is removed. When overcurrent condition is detected

the fault register bit BOOST_FAULT is set high to indicate fault in boost operation. An INT is also asserted to the

host.

9.2.14.2.2 Boost Mode Overvoltage Protection

When the VBUS voltage rises above regulation target and exceeds V_{OTG_OVP}, the device enters overvoltage

protection which stops switching, clears OTG_CONFIG bit and exits boost mode. During the overvoltage

duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also

asserted to the host.

9.2.15 Battery Protection

9.2.15.1 Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage

occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT

is asserted to the host.

9.2.15.2 Battery Over-Discharge Protection

When battery is discharged below V_{BAT_DPL}, the BATFET is turned off to protect battery from over discharge. To

recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the

BATFET turns on. Thy is charged with I_BATSHORT(typically 100 mA) current when the VBAT < V_SHORT, or

precharge current as set in IPRECHG register when the battery voltage is between V_SHORTand V_BATLOWV

.

9.2.15.3 System Overcurrent Protection

When the system is shorted or significantly overloaded (I_BAT> I_BATOP) so that its current exceeds the overcurrent

limit, the device latches off BATFET. 节9.2.10.2 can reset the latch-off condition and turn on BATFET.

9.2.16 Serial Interface

The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device

status reporting. I²C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial

data line (SDA) and a serial clock line (SCL). Devices can be considered as hosts or targets when performing

data transfers. A host is the device which initiates a data transfer on the bus and generates the clock signals to

permit that transfer. At that time, any device addressed is considered a target.

The device operates as a target device with address 6AH (BQ25890) and 6BH (BQ25892), receiving control

inputs from the host device like micro controller or a digital signal processor through REG00-REG14. Register

read beyond REG14 (0x14) returns 0xFF. The I²C interface supports both standard mode (up to 100 kbits), and

fast mode (up to 400 kbits). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain

and must be connected to the positive supply voltage via a current source or pull-up resistor.

9.2.16.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

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SDA

SCL

Change

of data

allowed

Data line stable;

Data valid

图9-9. Bit Transfer on the I²C Bus

9.2.16.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the host. The bus is considered busy after the START

condition, and free after the STOP condition.

SDA

SCL

SDA

SCL

STOP (P)

START (S)

图9-10. START and STOP conditions

9.2.16.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant

Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some

other function, it can hold the clock line SCL low to force the host into a wait state (clock stretching). Data

transfer then continues when the target is ready for another byte of data and release the clock line SCL.

Acknowledgement

signal from host

signal from target

MSB

SDA

1

2

7

8

9

1

2

8

9

SCL S or Sr

START or

P or Sr

ACK

STOP or

Repeate

d START

Repeated

START

图9-11. Data Transfer on the I²C Bus

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9.2.16.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9^thclock pulse, are generated by the host.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9^thclock pulse, this is the Not Acknowledge signal. The host can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

9.2.16.5 Target Address and Data Direction Bit

After the START, a target address is sent. This address is 7 bits long followed by the eighth bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

SDA

S

8

9

8

9

8

9

P

SCL

1-7

START

ADDRESS

R/W ACK

DATA

ACK

DATA

ACK

STOP

图9-12. Complete Data Transfer

9.2.16.6 Single Read and Write

S

Target Addr

0

ACK

Reg Addr

ACK

Data to Addr

ACK

P

图9-13. Single Write

S

Target Addr

0

ACK

Reg Addr

ACK

S

Target Addr

ACK

1

Data

NCK

P

图9-14. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

9.2.16.7 Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.

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S

Target Addr

0

ACK

Reg Addr

Data to Addr

ACK

Data to Addr+1 ACK

Data to Addr+N

ACK

P

图9-15. Multi-Write

S

Target Addr

0

ACK

Reg Addr

ACK

S

Target Addr

ACK

1

Data @ Addr

ACK Data @ Addr+1 ACK

Data @ Addr+N NCK

P

图9-16. Multi-Read

REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For

example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the

fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault

information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT

which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and

multi-write.

9.3 Device Functional Modes

9.3.1 Host Mode and Default Mode

The device is a host controlled charger, but it can operate in default mode without host management. In default

mode, the device can be used an autonomous charger with no host or while host is in sleep mode. When the

charger is in default mode, WATCHDOG_FAULT bit is HIGH. When the charger is in host mode,

WATCHDOG_FAULT bit is LOW.

After power-on-reset, the device starts in default mode with watchdog timer expired, or default mode. All the

registers are in the default settings.

In default mode, the device keeps charging the battery with 12-hour fast charging safety timer. At the end of the

12-hour, the charging is stopped and the buck converter continues to operate to supply system load. Any write

command to device transitions the charger from default mode to host mode. All the device parameters can be

programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1

to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by

setting WATCHDOG bits=00.

When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all

registers are reset to default values except IINLIM, VINDPM, VINDPM_OS, BATFET_RST_EN, BATFET_DLY,

and BATFET_DIS bits.

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POR

watchdog timer expired

Reset registers

I2C interface enabled

Host Mode

Start watchdog timer

Y

I2C Write?

Host programs registers

N

Default Mode

Reset watchdog timer

Reset selective registers

Y

WD_RST bit = 1?

N

Y

N

I2C Write?

Y

N

Watchdog Timer

Expired?

图9-17. Watchdog Timer Flow Chart

36

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9.4 Register Maps

I2C Target Address: 6AH (1101010B + R/ W) (BQ25890)

I2C Target Address: 6BH (1101011B + R/ W) (BQ25892)

9.4.1 REG00

图9-18. REG00

7

0

6

0

5

0

4

3

2

0

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-9. REG00

Bit

Field

Type

Reset

Description

Enable HIZ Mode

0 –Disable (default)

1 –Enable

by REG_RST

by Watchdog

7

EN_HIZ

R/W

Enable ILIM Pin

0 –Disable

1 –Enable (default: Enable ILIM pin (1))

by REG_RST

by Watchdog

6

EN_ILIM

R/W

5

4

3

2

1

IINLIM[5]

IINLIM[4]

IINLIM[3]

IINLIM[2]

IINLIM[1]

R/W

by REG_RST

1600mA

800mA

400mA

200mA

100mA

Input Current Limit

Offset: 100mA

Range: 100mA (000000) –3.25A (111111)

Default:0001000 (500mA)

(Actual input current limit is the lower of I2C or ILIM pin)

IINLIM bits are changed automaticallly after input source

type detection is completed

BQ25890

USB Host SDP = 500mA

USB CDP = 1.5A

USB DCP = 3.25A

Adjustable High Voltage (MaxCharge) DCP = 1.5A

Unknown Adapter = 500mA

Non-Standard Adapter = 1A/2A/2.1A/2.4A

BQ25892

0

IINLIM[0]

R/W

by REG_RST

50mA

PSEL= Hi (USB500) = 500mA

PSEL= Lo = 3.25A

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9.4.2 REG01

图9-19. REG01

7

0

6

0

5

0

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-10. REG01

Bit

Field

Type

Reset

Description

by REG_RST

by Watchdog

Boost Mode Hot Temperature Monitor Threshold

00 –V_BHOT1Threshold (34.75%) (default)

01 –V_BHOT0Threshold (Typ. 37.75%)

10 –V_BHOT2Threshold (Typ. 31.25%)

11 –Disable boost mode thermal protection

7

BHOT[1]

R/W

by REG_RST

by Watchdog

6

5

BHOT[0]

BCOLD

R/W

Boost Mode Cold Temperature Monitor Threshold

0 –V_BCOLD0Threshold (Typ. 77%) (default)

1 –V_BCOLD1Threshold (Typ. 80%)

by REG_RST

by Watchdog

4

3

2

1

VINDPM_OS[4]

VINDPM_OS[3]

VINDPM_OS[2]

VINDPM_OS[1]

R/W

by REG_RST

1600mV

800mV

400mV

200mV

Input Voltage Limit Offset

Default: 600mV (00110)

Range: 0mV –3100mV

Minimum VINDPM threshold is clamped at 3.9V

Maximum VINDPM threshold is clamped at 15.3V

When VBUS at noLoad is ≤6V, the VINDPM_OS is used

to calculate VINDPM threhold

0

VINDPM_OS[0]

R/W

by REG_RST

100mV

When VBUS at noLoad is > 6V, the VINDPM_OS multiple

by 2 is used to calculate VINDPM threshold.

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9.4.3 REG02

图9-20. REG02

7

0

6

0

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-11. REG02

Bit

Field

Type

Reset

Description

ADC Conversion Start Control

0 –ADC conversion not active (default).

1 –Start ADC Conversion

This bit is read-only when CONV_RATE = 1. The bit stays high during

ADC conversion and during input source detection.

by REG_RST

by Watchdog

7

CONV_START

R/W

ADC Conversion Rate Selection

0 –One shot ADC conversion (default)

1 –Start 1s Continuous Conversion

by REG_RST

by Watchdog

6

5

4

3

2

1

0

CONV_RATE

BOOST_FREQ

ICO_EN

R/W

Boost Mode Frequency Selection

0 –1.5MHz (default)

Note: Write to this bit is ignored when OTG_CONFIG is enabled.

by REG_RST

by Watchdog

Input Current Optimizer (ICO) Enable

0 –Disable ICO Algorithm

1 –Enable ICO Algorithm (default)

by REG_RST

High Voltage DCP Enable (BQ25890 only)

0 –Disable HVDCP handshake

1 –Enable HVDCP handshake (default)

HVDCP_EN

MaxCharge Adapter Enable (BQ25890 only)

0 –Disable MaxCharge handshake

1 –Enable MaxCharge handshake (default)

MAXC_EN

Force D+/D- Detection

0 –Not in D+/D- or PSEL detection (default)

1 –Force D+/D- detection

by REG_RST

by Watchdog

FORCE_DPDM

AUTO_DPDM_EN

Automatic D+/D- Detection Enable

0 –Disable D+/D- or PSEL detection when VBUS is plugged-in

1 –Enable D+/D- or PEL detection when VBUS is plugged-in (default)

by REG_RST

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9.4.4 REG03

图9-21. REG03

7

0

6

0

5

0

4

3

2

0

1

0

1

R/W

RW

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-12. REG03

Bit

Field

Type

Reset

Description

Battery Load (I_BATLOAD) Enable

0 –Disabled (default)

1 –Enabled

by REG_RST

by Watchdog

7

BAT_LOADEN

R/W

I2C Watchdog Timer Reset

0 –Normal (default)

1 –Reset (Back to 0 after timer reset)

by REG_RST

by Watchdog

6

5

4

WD_RST

R/W

Boost (OTG) Mode Configuration

0 –OTG Disable (default)

1 –OTG Enable

by REG_RST

by Watchdog

OTG_CONFIG

CHG_CONFIG

Charge Enable Configuration

0 - Charge Disable

1- Charge Enable (default)

by REG_RST

by Watchdog

3

2

1

SYS_MIN[2]

SYS_MIN[1]

SYS_MIN[02]

R/W

by REG_RST

0.4V

0.2V

0.1V

Minimum System Voltage Limit

Offset: 3.0V

Range 3.0V-3.7V

Default: 3.5V (101)

by REG_RST

by Watchdog

0

Reserved

R/W

Reserved (default = 0)

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9.4.5 REG04

图9-22. REG04

7

0

6

0

5

1

4

3

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-13. REG04

Bit

Field

Type

Reset

Description

Current pulse control Enable

0 - Disable Current pulse control (default)

1- Enable Current pulse control (PUMPX_UP and PUMPX_DN)

4096mA

by Software

by Watchdog

7

EN_PUMPX

R/W

by Software

by Watchdog

6

5

4

3

2

1

0

ICHG[6]

ICHG[5]

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

R/W

by Software

by Watchdog

2048mA

Fast Charge Current Limit

Offset: 0mA

by Software

by Watchdog

1024mA

512mA

256mA

128mA

64mA

Range: 0mA (0000000) –5056mA (1001111)

Default: 2048mA (0100000)

Note:

ICHG=000000 (0mA) disables charge

ICHG > 1001111 (5056mA) is clamped to register value

1001111 (5056mA)

by Software

by Watchdog

by Software

by Watchdog

by Software

by Watchdog

by Software

by Watchdog

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9.4.6 REG05

图9-23. REG05

7

0

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-14. REG05

Bit

Field

Type

Reset

Description

by Software

by Watchdog

7

IPRECHG[3]

R/W

512mA

256mA

128mA

64mA

by Software

by Watchdog

Precharge Current Limit

Offset: 64mA

Range: 64mA –1024mA

Default: 128mA (0001)

6

5

4

3

2

1

0

IPRECHG[2]

IPRECHG[1]

IPRECHG[0]

ITERM[3]

R/W

by Software

by Watchdog

by Software

by Watchdog

by Software

by Watchdog

512mA

256mA

128mA

64mA

by Software

by Watchdog

Termination Current Limit

Offset: 64mA

Range: 64mA –1024mA

Default: 256mA (0011)

ITERM[2]

by Software

by Watchdog

ITERM[1]

by Software

by Watchdog

ITERM[0]

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9.4.7 REG06

图9-24. REG06

7

0

6

1

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-15. REG06

Bit

Field

Type

Reset

Description

by Software

by Watchdog

7

VREG[5]

R/W

512mV

256mV

128mV

64mV

by Software

by Watchdog

6

5

4

3

2

VREG[4]

VREG[3]

VREG[2]

VREG[1]

VREG[0]

R/W

Charge Voltage Limit

Offset: 3.840V

Range: 3.840V –4.608V (110000)

Default: 4.208V (010111)

Note:

by Software

by Watchdog

by Software

by Watchdog

VREG > 110000 (4.608V) is clamped to register value

110000 (4.608V)

by Software

by Watchdog

32mV

by Software

by Watchdog

16mV

Battery Precharge to Fast Charge Threshold

0 –2.8V

1 –3.0V (default)

by Software

by Watchdog

1

0

BATLOWV

VRECHG

R/W

Battery Recharge Threshold Offset

(below Charge Voltage Limit)

0 –100mV (V_RECHG) below VREG (REG06[7:2]) (default)

1 –200mV (V_RECHG) below VREG (REG06[7:2])

by Software

by Watchdog

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9.4.8 REG07

图9-25. REG07

7

1

6

0

5

0

4

3

2

1

0

1

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-16. REG07

Bit

Field

Type

Reset

Description

Charging Termination Enable

0 –Disable

1 –Enable (default)

by Software

by Watchdog

7

EN_TERM

R/W

STAT Pin Disable

0 –Enable STAT pin function (default)

1 –Disable STAT pin function

by Software

by Watchdog

6

STAT_DIS

R/W

by Software

by Watchdog

I2C Watchdog Timer Setting

00 –Disable watchdog timer

01 –40s (default)

10 –80s

5

4

WATCHDOG[1]

WATCHDOG[0]

R/W

by Software

by Watchdog

11 –160s

Charging Safety Timer Enable

0 –Disable

1 –Enable (default)

by Software

by Watchdog

3

EN_TIMER

R/W

by Software

by Watchdog

Fast Charge Timer Setting

00 –5 hrs

01 –8 hrs

10 –12 hrs (default)

11 –20 hrs

2

1

CHG_TIMER[1]

CHG_TIMER[0]

R/W

by Software

by Watchdog

JEITA Low Temperature Current Setting

0 –50% of ICHG (REG04[6:0])

1 –20% of ICHG (REG04[6:0]) (default)

by Software

by Watchdog

0

JEITA_ISET (0C-10C)

R/W

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9.4.9 REG08

图9-26. REG08

7

0

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-17. REG08

Bit

Field

Type

Reset

Description

by Software

by Watchdog

7

BAT_COMP[2]

R/W

80mΩ

40mΩ

20mΩ

128mV

64mV

32mV

IR Compensation Resistor Setting

Range: 0 –140mΩ

Default: 0Ω (000) (i.e. Disable IRComp)

by Software

by Watchdog

6

5

4

3

2

1

BAT_COMP[1]

BAT_COMP[0]

VCLAMP[2]

VCLAMP[1]

VCLAMP[0]

TREG[1]

R/W

by Software

by Watchdog

by Software

by Watchdog

IR Compensation Voltage Clamp

above VREG (REG06[7:2])

Offset: 0mV

Range: 0-224mV

Default: 0mV (000)

by Software

by Watchdog

by Software

by Watchdog

by Software

by Watchdog

Thermal Regulation Threshold

00 –60°C

01 –80°C

10 –100°C

11 –120°C (default)

by Software

by Watchdog

0

TREG[0]

R/W

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9.4.10 REG09

图9-27. REG09

7

0

6

1

5

0

4

3

2

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-18. REG09

Bit

Field

Type

Reset

Description

Force Start Input Current Optimizer (ICO)

0 –Do not force ICO (default)

1 –Force ICO

by Software

by Watchdog

7

FORCE_ICO

R/W

Note:

This bit is can only be set only and always returns to 0 after ICO starts

Safety Timer Setting during DPM or Thermal Regulation

0 –Safety timer not slowed by 2X during input DPM or thermal

regulation

1 –Safety timer slowed by 2X during input DPM or thermal regulation

(default)

by Software

by Watchdog

6

TMR2X_EN

R/W

Force BATFET off to enable ship mode

0 –Allow BATFET turn on (default)

1 –Force BATFET off

5

4

BATFET_DIS

R/W

by Software

JEITA High Temperature Voltage Setting

0 –Set Charge Voltage to VREG-200mV during JEITA hig temperature

(default)

by Software

by Watchdog

JEITA_VSET (45C-60C)

1 –Set Charge Voltage to VREG during JEITA high temperature

BATFET turn off delay control

3

2

BATFET_DLY

R/W

by Software

0 –BATFET turn off immediately when BATFET_DIS bit is set (default)

1 –BATFET turn off delay by t_{SM_DLY}when BATFET_DIS bit is set

BATFET full system reset enable

0 –Disable BATFET full system reset

1 –Enable BATFET full system reset (default)

BATFET_RST_EN

Current pulse control voltage up enable

0 –Disable (default)

by Software

by Watchdog

1 –Enable

Note:

1

0

PUMPX_UP

PUMPX_DN

R/W

This bit is can only be set when EN_PUMPX bit is set and returns to 0

after current pulse control sequence is completed

Current pulse control voltage down enable

0 –Disable (default)

1 –Enable

Note:

by Software

by Watchdog

This bit is can only be set when EN_PUMPX bit is set and returns to 0

after current pulse control sequence is completed

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9.4.11 REG0A

图9-28. REG0A

7

0

6

1

5

1

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-19. REG0A

Bit

Field

Type

Reset

Description

by Software

by Watchdog

7

BOOSTV[3]

R/W

512mV

Boost Mode Voltage Regulation

Offset: 4.55V

Range: 4.55V –5.51V

Default:4.998V(0111)

by Software

by Watchdog

6

5

4

BOOSTV[2]

BOOSTV[1]

BOOSTV[0]

R/W

256mV

128mV

64mV

by Software

by Watchdog

by Software

by Watchdog

3

2

1

Reserved

R/W

Reserved (default = 0)

by Software

by Watchdog

000: 0.5A

001: 0.75A

010: 1.2A

BOOST_LIM[2]

BOOST_LIM[1]

by Software

by Watchdog

011: 1.4A

Boost Mode Current Limit

Default: 1.4A (011)

100: 1.65A

101: 1.875A

110: 2.15A

111: 2.45A

by Software

by Watchdog

0

BOOST_LIM[0]

R/W

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9.4.12 REG0B

图9-29. REG0B

7

x

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-20. REG0B

Bit

7

Field

Type

R

Reset

Description

VBUS_STAT[2]

VBUS_STAT[1]

N/A

VBUS Status register

BQ25890

000: No Input 001: USB Host SDP

010: USB CDP (1.5A)

6

R

N/A

011: USB DCP (3.25A)

100: Adjustable High Voltage DCP (MaxCharge) (1.5A)

101: Unknown Adapter (500mA)

110: Non-Standard Adapter (1A/2A/2.1A/2.4A)

111: OTG

BQ25892

5

VBUS_STAT[0]

R

N/A

000: No Input

001: USB Host SDP

010: Adapter (3.25A)

111: OTG

Note: Software current limit is reported in IINLIM register

4

3

CHRG_STAT[1]

CHRG_STAT[0]

R

N/A

Charging Status

00 –Not Charging

01 –Pre-charge ( < V_BATLOWV

10 –Fast Charging

)

11 –Charge Termination Done

Power Good Status

0 –Not Power Good

1 –Power Good

2

1

0

PG_STAT

Reserved

R

N/A

Reserved: Always reads 0

VSYS Regulation Status

0 –Not in VSYSMIN regulation (BAT > VSYSMIN)

1 –In VSYSMIN regulation (BAT < VSYSMIN)

VSYS_STAT

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9.4.13 REG0C

图9-30. REG0C

7

x

6

x

5

x

4

3

2

x

1

x

0

x

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-21. REG0C

Bit

Field

Type

Reset

Description

Watchdog Fault Status

7

WATCHDOG_FAULT

R

N/A

Status 0 –Normal

1- Watchdog timer expiration

Boost Mode Fault Status

0 –Normal

6

5

BOOST_FAULT

CHRG_FAULT[1]

R

N/A

1 –VBUS overloaded in OTG, or VBUS OVP, or battery is too low in

boost mode

Charge Fault Status

00 –Normal

01 –Input fault (VBUS > V_ACOVor VBAT < VBUS < V_VBUSMIN(typical

3.8V) )

4

CHRG_FAULT[0]

R

N/A

10 - Thermal shutdown

11 –Charge Safety Timer Expiration

Battery Fault Status

3

BAT_FAULT

R

N/A

0 –Normal

1 –BATOVP (VBAT > V_BATOVP

)

2

1

NTC_FAULT[2]

NTC_FAULT[1]

R

N/A

NTC Fault Status

Buck Mode:

000 –Normal

010 –TS Warm

011 –TS Cool

101 –TS Cold

110 –TS Hot

Boost Mode:

0

NTC_FAULT[0]

R

N/A

000 –Normal

101 –TS Cold

110 –TS Hot

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9.4.14 REG0D

图9-31. REG0D

7

0

6

0

5

0

4

3

2

0

1

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-22. REG0D

Bit

Field

Type

Reset

Description

VINDPM Threshold Setting Method

7

FORCE_VINDPM

R/W

by Software

0 –Run Relative VINDPM Threshold (default)

1 –Run Absolute VINDPM Threshold

6

5

4

3

2

1

0

VINDPM[6]

VINDPM[5]

VINDPM[4]

VINDPM[3]

VINDPM[2]

VINDPM[1]

VINDPM[0]

R/W

by Software

6400mV

3200mV

1600mV

800mV

400mV

200mV

100mV

Absolute VINDPM Threshold

Offset: 2.6V

Range: 3.9V (0001101) –15.3V (1111111)

Default: 4.4V (0010010)

Note:

Value < 0001101 is clamped to 3.9V (0001101)

Register is read only when FORCE_VINDPM=0 and can be

written by internal control based on relative VINDPM

threshold setting

Register can be read/write when FORCE_VINDPM = 1

9.4.15 REG0E

图9-32. REG0E

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-23. REG0E

Bit

Field

Type

Reset

Description

Thermal Regulation Status

0 –Normal

7

THERM_STAT

R

N/A

1 –In Thermal Regulation

6

5

4

3

2

1

0

BATV[6]

BATV[5]

BATV[4]

BATV[3]

BATV[2]

BATV[1]

BATV[0]

R

N/A

1280mV

640mV

ADC conversion of Battery Voltage (V_BAT

Offset: 2.304V

Range: 2.304V (0000000) –4.848V (1111111)

)

320mV

160mV

80mV

40mV

20mV

Default: 2.304V (0000000)

50

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9.4.16 REG0F

图9-33. REG0F

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-24. REG0F

Bit

7

Field

Type

R

Reset

N/A

Description

Reserved

SYSV[6]

SYSV[5]

SYSV[4]

SYSV[3]

SYSV[2]

SYSV[1]

SYSV[0]

Reserved: Always reads 0

1280mV

6

R

5

R

640mV

ADDC conversion of System Voltage (V_SYS

Offset: 2.304V

Range: 2.304V (0000000) –4.848V (1111111)

)

4

R

320mV

160mV

80mV

40mV

20mV

3

R

2

R

Default: 2.304V (0000000)

1

R

0

R

9.4.17 REG10

图9-34. REG10

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-25. REG10

Bit

7

Field

Type

R

Reset

N/A

Description

Reserved

TSPCT[6]

TSPCT[5]

TSPCT[4]

TSPCT[3]

TSPCT[2]

TSPCT[1]

TSPCT[0]

Reserved: Always reads 0

29.76%

6

R

5

R

14.88%

ADC conversion of TS Voltage (TS) as percentage of REGN

Offset: 21%

Range 21% (0000000) –80% (1111111)

Default: 21% (0000000)

4

R

7.44%

3.72%

1.86%

0.93%

0.465%

3

R

2

R

1

R

0

R

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9.4.18 REG11

图9-35. REG11

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-26. REG11

Bit

Field

Type

Reset

Description

VBUS Good Status

7

VBUS_GD

R

N/A

0 –Not VBUS attached

1 –VBUS Attached

6

5

4

3

2

1

0

VBUSV[6]

VBUSV[5]

VBUSV[4]

VBUSV[3]

VBUSV[2]

VBUSV[1]

VBUSV[0]

R

N/A

6400mV

3200mV

ADC conversion of VBUS voltage (V_BUS

Offset: 2.6V

Range 2.6V (0000000) –15.3V (1111111)

)

1600mV

800mV

400mV

200mV

100mV

Default: 2.6V (0000000)

9.4.19 REG12

图9-36. REG12

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-27. REG12

Bit

7

Field

Type

R

Reset

N/A

Description

Unused

Always reads 0

3200mA

6

ICHGR[6]

ICHGR[5]

ICHGR[4]

ICHGR[3]

ICHGR[2]

ICHGR[1]

ICHGR[0]

R

5

R

1600mA

800mA

400mA

200mA

100mA

50mA

ADC conversion of Charge Current (I_BAT) when V_BAT>

V_BATSHORT

Offset: 0mA

Range 0mA (0000000) –6350mA (1111111)

Default: 0mA (0000000)

4

R

3

R

2

R

Note:

1

R

This register returns 0000000 for V_BAT< V_BATSHORT

0

R

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9.4.20 REG13

图9-37. REG13

7

0

6

0

5

0

4

3

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-28. REG13

Bit

Field

Type

Reset

Description

VINDPM Status

0 –Not in VINDPM

1 –VINDPM

7

VDPM_STAT

R

N/A

IINDPM Status

0 –Not in IINDPM

1 –IINDPM

6

IDPM_STAT

R

N/A

5

4

3

2

1

0

IDPM_LIM[5]

IDPM_LIM[4]

IDPM_LIM[3]

IDPM_LIM[2]

IDPM_LIM[1]

IDPM_LIM[0]

R

N/A

1600mA

800mA

Input Current Limit in effect while Input Current Optimizer

(ICO) is enabled

Offset: 100mA (default)

400mA

200mA

100mA

50mA

Range 100mA (0000000) –3.25mA (1111111)

9.4.21 REG14

图9-38. REG14

7

0

6

0

5

0

4

3

2

0

1

0

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表9-29. REG14

Bit

Field

Type

Reset

Description

Register Reset

0 –Keep current register setting (default)

7

REG_RST

R/W

N/A

1 –Reset to default register value and reset safety timer

Note:

Reset to 0 after register reset is completed

Input Current Optimizer (ICO) Status

0 –Optimization is in progress

6

ICO_OPTIMIZED

R

N/A

1 –Maximum Input Current Detected

5

4

3

PN[2]

PN[1]

PN[0]

R

N/A

Device Configuration

011: BQ25890

000: BQ25892

Temperature Profile

1- JEITA (default)

2

TS_PROFILE

R

N/A

1

0

DEV_REV[1]

DEV_REV[0]

R

N/A

Device Revision: 01

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

A typical application consists of the device configured as an I²C controlled power path management device and

a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other

portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),

low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also

integrates a bootstrap diode for the high-side gate drive.

10.2 Typical Application

Input

3.9Vœ14V at 3A

OTG

5V at 2.4A

1ꢀH

SYS 3.5Vœ4.5V

10ꢀF 10ꢀF

VBUS

PMID

SW

1ꢀF

8.2ꢀF

47nF

SYS

Optional

10YQ

BTST

REGN

DSEL

D+

USB

4.7ꢀF

D-

PGND

SYS

260Q

SYS

ILIM

Ichg=5A

10uF

BAT

VREF

QON

2.2YQ

STAT

SDA

10YQ 10YQ 10YQ

Host

Optional

REGN

SCL

INT

OTG

5.23YQ

TS

/CE

30.1YQ

10YQ

BQ25890

图10-1. BQ25890 with D+/D- Interface and USB On-The-Go (OTG)

10.2.1 Design Requirements

For this design example, use the parameters shown in 表10-1.

表10-1. Design Parameter

PARAMETERS

Input voltage range

Input current limit

VALUES

3.9 V to 14 V

1.5 A

Fast charge current

Output voltage

5000 mA

4.352 V

V_REFsystem pullup voltage

1.8 V - 3.3 V

54

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10.2.2 Detailed Design Procedure

10.2.2.1 Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The

Inductor saturation current should be higher than the charging current (I_CHG) plus half the ripple current (I_RIPPLE):

I

³ I

CHG

+ (1/2) I

RIPPLE

BAT

(5)

The inductor ripple current depends on input voltage (V_BUS), duty cycle (D = V_BAT/V_VBUS), switching frequency

(fs) and inductance (L):

V

x D x (1-D)

BUS

I

=

RIPPLE

f s x L

(6)

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in

the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a

practical design.

10.2.2.2 Buck Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case

RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at

50% duty cycle, then the worst case capacitor RMS current I_PMIDoccurs where the duty cycle is closest to 50%

and can be estimated by 方程式7:

I

= I x D x (1 - D)

CHG

PMID

(7)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be

placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage

rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred

for up to 14-V input voltage. 8.2-μF capacitance is suggested for typical of 3 A –5 A charging current.

10.2.2.3 System Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The

output capacitor RMS current I_COUTis given:

I

RIPPLE

I

=

» 0.29 x I

RIPPLE

CSYS

2 x

3

(8)

The output capacitor voltage ripple can be calculated as follows:

æ

ö

÷

V

SYS

ç

DV

=

ç1-

O

ç

è

2

÷

ø

V

BUS

8 LC

SYS

f s

(9)

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the

output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum

of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.

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10.2.3 Application Curves

VBAT = 3.2 V

图10-3. Power Up with Charge Enabled

图10-2. Power Up with Charge Disabled

VBUS = 5 V

VBUS = 12 V

图10-4. Charge Enable

图10-5. Charge Disable

VBUS = 5 V

I_IN= 3 A

Charge Disable

VBUS = 9 V

I_CHG= 2 A

I_IN= 1.5 A

VBAT = 3.8 V

I_SYS= 0 A - 4 A

图10-6. Input Current DPM Response without

Battery

图10-7. Load Transient During Supplement Mode

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VBUS = 12 V

VBAT = 3.8 V

ICHG = 3 A

VBUS = 9V

No Battery

I_SYS= 10 mA,

Charge Disable

图10-8. PWM Switching Waveform

图10-9. PFM Switching Waveform

VBAT = 3.8 V

I_LOAD= 1 A

VBAT = 3.8 V

I_LOAD= 0 A - 1 A

图10-10. Boost Mode Switching Waveform

图10-11. Boost Mode Load Transient

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10.3 System Examples

Input

3.9Vœ14V at 3A

OTG

5V at 2.4A

SYS 3.5Vœ4.5V

1ꢀH

VBUS

PMID

SW

1ꢀF

8.2ꢀF

47nF

USB

10ꢀF 10ꢀF

BTST

REGN

4.7ꢀF

PSEL

ILIM

PHY

PGND

SYS

260Q

SYS

Ichg=5A

10uF

BAT

VREF

QON

2.2YQ

STAT

/PG

10YQ 10YQ 10YQ

Host

Optional

REGN

SDA

SCL

INT

OTG

/CE

5.23YQ

TS

10YQ

30.1YQ

BQ25892

图10-12. BQ25892 with PSEL Interface and USB On-The-Go (OTG)

Input

3.9Vœ14V at 3A

OTG

5V at 2.4A

1ꢀH

SYS 3.5Vœ4.5V

10ꢀF 10ꢀF

VBUS

PMID

SW

1ꢀF

8.2ꢀF

47nF

USB

BTST

REGN

4.7ꢀF

PSEL

ILIM

PHY

PGND

SYS

260Q

SYS

Ichg=5A

10uF

BAT

VREF

QON

2.2YQ

STAT

/PG

10YQ 10YQ 10YQ

Host

Optional

REGN

SDA

SCL

INT

OTG

/CE

10YQ

TS

10YQ

BQ25892

图10-13. BQ25892 with PSEL Interface and USB On-The-Go (OTG) No Thermistor Connections

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11 Power Supply Recommendations

In order to provide an output voltage on SYS, the device requires a power supply between 3.9 V and 14 V input

with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage > V_BATUVLO

connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter of the

charger to provide maximum output power to SYS.

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12 Layout

12.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see 图 12-1) is important to prevent electrical and

magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper

layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper

trace connection or GND plane.

2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower

electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not

use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other

trace or plane.

3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground

with a short copper trace connection or GND plane.

4. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using power pad as the single ground

connection point. Or using a 0Ωresistor to tie analog ground to power ground.

5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC.

Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.

6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.

Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the

other layers.

8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the VQFN

information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB

Attachment Application Report.

12.2 Layout Example

图12-1. High Frequency Current Path

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13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RTW 24

4 x 4, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224801/A

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ25890
厂家：	TEXAS INSTRUMENTS
描述：	采用 Maxcharge™ 技术、支持高输入且具有 D+/D- 的 I2C 单节 5A 降压电池充电器电池
文件：	总70页 (文件大小：3078K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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