BQ25960 [TI]
具有旁路模式和双输入选择器的 I2C 控制型单节 8A 开关电容并联电池充电器;
| 型号： | BQ25960 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有旁路模式和双输入选择器的 I2C 控制型单节 8A 开关电容并联电池充电器 电池 开关 |
| 文件： | 总75页 (文件大小：2200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ25960
ZHCSNF1 –FEBRUARY 2021
具有集成旁路模式和双输入选择器的BQ25960 I2C 控制型、单节8A 开关电容
并联电池充电器
1 特性
2 应用
• 峰值效率达98.1% 的开关电容并联充电器支持8A
快速充电
• 智能手机
• 平板电脑
• 正在申请专利的两相开关电容架构经优化可实现超
高效率
3 说明
BQ25960 是一款峰值效率为 98.1% 的 8A 电池充电解
决方案，采用开关电容结构，适用于 1 节锂离子电
池。开关电容结构允许电缆电流为充电电流的一半，从
而减少电缆功率损耗并限制温度上升。两相结构可提高
充电效率并降低输入和输出电容要求。当与 BQ2561x
或 BQ2589x 等主充电器一起使用时，系统可在恒定电
流 (CC) 和恒定电压 (CV) 模式下实现从涓流充电到终
端的完整充电周期。
– 输入电压是电池电压的2 倍
– 输出电流是输入电流的2 倍
– 减少输入电缆的功率损耗
• 集成式5A 旁路模式快速充电
– 21mΩ Rdson 充电路径电阻支持5A 输入和5A 输
出充电电流
• 用于在快速充电和USB On-The-Go (OTG)/反向TX
模式期间选择输入源的双输入电源多路复用控制器
• 支持宽输入电压范围
BQ25960 通过内部 MOSFET 支持 5A 旁路模式充电
（以前称为电池开关模式充电）。旁路模式充电路径中
的Rdson 为21mΩ，用于大电流操作。集成的旁路模式
可向后兼容 5V 快速充电适配器，从而为 1 节电池充
电。
– 高达12.75V 的工作输入电压
– 带可选外部ACFET 时最大40V 输入电压，不带
外部ACFET 时最大20V 输入电压
• 通过双通道同步BQ25960 运行实现并联充电，充
电电流最高可达13A
• 可实现安全运行的集成可编程保护功能
– 输入过压保护(BUSOVP) 和电池过压保护
(BATOVP)
该器件通过集成多路复用控制和驱动器支持外部 N-
FET 的双输入配置。它还允许无需外部 N-FET 的单输
入或单N-FET。
器件信息
– 输入过流保护(BUSOCP) 和电池过流保护
(BATOCP)
– 输出过压保护(VOUTOVP)
器件型号(1)
BQ25960
封装尺寸（标称值）
封装
DSBGA (36)
2.55mm x 2.55mm
– 输入欠流保护(BUSUCP) 和输入反向电流保护
(BUSRCP) 可检测适配器断开并防止升压
– 电池和连接器温度监控（TSBAT_FLT 和
TSBUS_FLT）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Phone
BQ25960
(Parallel charger)
– 接点过热保护(TDIE_FLT)
VOUT
SC Phase
#1
• 用于系统优化的可编程设置
– 中断和中断屏蔽
SC Phase
#2
Adapter
SW
VBUS
SYSTEM
AC/DC
Converter
– ADC 读数和配置
– 用于主机控制的警报功能
VBUS
D+/D-
SYS
BAT
Main charger
D+/D-
• 用于电压、电流和温度监控的集成16 位ADC
Host + PD Controller
CC1/ CC2
PD Controller
I2C
AP
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSE08
BQ25960
ZHCSNF1 –FEBRUARY 2021
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Table of Contents
9.4 Programming............................................................ 28
9.5 Register Maps...........................................................31
10 Application and Implementation................................61
10.1 Application Information........................................... 61
10.2 Typical Application.................................................. 61
11 Power Supply Recommendations..............................67
12 Layout...........................................................................68
12.1 Layout Guidelines................................................... 68
12.2 Layout Example...................................................... 68
13 Device and Documentation Support..........................69
13.1 Device Support....................................................... 69
13.2 Documentation Support.......................................... 69
13.3 接收文档更新通知................................................... 69
13.4 支持资源..................................................................69
13.5 Trademarks.............................................................69
13.6 静电放电警告.......................................................... 69
13.7 术语表..................................................................... 69
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings ....................................... 7
8.2 ESD Ratings .............................................................. 7
8.3 Recommended Operating Conditions ........................7
8.4 Thermal Information ...................................................8
8.5 Electrical Characteristics ............................................8
8.6 Timing Requirements ...............................................12
8.7 Typical Characteristics..............................................13
9 Detailed Description......................................................14
9.1 Overview...................................................................14
9.2 Functional Block Diagram.........................................15
9.3 Feature Description...................................................16
Information.................................................................... 70
4 Revision History
DATE
REVISION
NOTES
February 2021
*
Initial release.
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5 Description (continued)
The device integrates all the necessary protection features to support safe charging, including input overvoltage
and overcurrent protection, output overvoltage and overcurrent protection, input undercurrent and reverse-
current protection, temperature sensing for the battery and cable, and junction overtemperature protection in
both Switched Cap and Bypass Mode.
The device includes a 16-bit analog-to-digital converter (ADC) to provide VAC voltage, bus voltage, bus current,
output voltage, battery voltage, battery current, input connector temperature, battery temperature, junction
temperature, and other calculated measurements needed to manage the charging of the battery from the
adapter, or wireless input, or power bank.
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6 Device Comparison Table
表6-1. Device Comparison
FUNCTION
Package
BQ25960
BQ25970
BQ25968
BQ25980
YBG-36
6.5 mm2
1 cell
YFF-56
YFF-56
YFF-80
Die size
9.5 mm2
9.5 mm2
1 cell
13.2 mm2
2 cell
Battery
1 cell
Input MUX control
Dual input power MUX
control
Single OVPFET
Single OVPFET
Dual input power MUX
control
Bypass Mode
Yes
8 A
No
No
Yes
8 A
Recommended 8-A
charging current
8 A
6 A
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7 Pin Configuration and Functions
1
2
3
4
5
6
PMID
VOUT
GND
CFL1
CFL1
CFH1
VBUS
A
B
C
D
E
F
CFH1
CFH2
CFH2
GND
GND
VOUT
VOUT
VOUT
PMID
PMID
VBUS
VBUS
CFL2
SRN_
SYNCIN
/INT
SCL
SDA
CDRVH
CFL2
TSBAT_
SYNCOUT
BATN_
SRP
CDRVL_
ADDRMS
VAC2
VAC1
TSBUS
REGN
ACDRV1
BATP
ACDRV2
图7-1. YBG Package - BQ25960 36-Pin DSBGA Top View
表7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Input FETs Driver Pin 1 - The charge pump output to drive the port #1 input N-channel
MOSFET (ACFET1) and the reverse blocking N-channel MOSFET (RBFET1). ACDRV1
voltage becomes 5 V above the common drain connection of the ACFET1 and RBFET1, when
the turn-on condition is met. If ACFET1 and RBFET1 are not used, connect ACDRV1 to
ground.
F3
ACDRV1
ACDRV2
P
Input FETs Driver Pin 2 -The charge pump output to drive the port #2 input N-channel
MOSFET (ACFET2) and the reverse blocking N-channel MOSFET (RBFET2). ACDRV2
voltage becomes 5 V above the common drain connection of the ACFET2 and RBFET2, when
the turn-on condition is met. If ACFET2 and RBFET2 are not used, connect ACDRV2 to
ground.
F2
E6
P
Negative input for battery voltage sensing and positive input for battery current
sensing- Connect to negative terminal of battery pack. It is also used for battery current
sensing. Place RSNS (2 mΩ or 5 mΩ) between BATN_SRP and SRN_SYNCIN. Short
BATN_SRP to SRN_SYNCIN together and place 100-Ωseries resistance between pin and
negative terminal if RSNS is not being used.
BATN_SRP
AI
Positive input for battery voltage sensing - Connect to positive terminal of battery pack.
Place 100-Ωseries resistance between pin and positive terminal.
F6
D1
BATP
AI
Charge pump for gate drive - Connect a 0.22-µF cap between CDRVH and
CDRVL_ADDRMS.
CDRVH
AIO
Charge pump for gate drive - Connect a 0.22-µF cap between CDRVH and
CDRVL_ADDRMS. During Power ON Reset (POR), this pin is used to assign the address of
the device and the mode of the device as Standalone, Primary, or Secondary.
E1
CDRVL_ADDRMS
AIO
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
and CFL1.
A4, B4
C4, D4
A2, B2
CFH1
CFH2
CFL1
P
P
P
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
and CFL2.
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
and CFH1.
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表7-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
Switched cap flying cap connection -Connect 1 to 3 22-µF caps in parallel between this pin
and CFH2.
C2, D2
CFL2
P
DO
P
Open drain, active low interrupt output - Pull up to voltage with 10-kΩ resistor. Normally
D5
INT
GND
PMID
high, the device asserts low to report status and faults. INT is pulsed low for tINT
.
A1, B1,
C1
Ground return
A5, B5,
C5
P
Input to the switched cap power stage -Connect 10-µF cap to PMID.
Charger internal LDO output - Connect a 4.7-µF cap between this pin and GND. When in
Primary/Secondary Mode, connect through 1-kΩresistor to the TSBAT_SYNCOUT and
SRN_SYNCIN pins. Do not use REGN for any other function.
F1
REGN
AO
I2C interface clock - Pull up to 3.3 V with 10-kΩ resistor.
I2C interface data - Pull up to 3.3 V with 10-kΩ resistor.
E5
F5
SCL
SDA
DI
DIO
Negative input for battery current sensing - Place RSNS (2 mΩ or 5 mΩ) between
SRN_SYNCIN and SRP. Short to SRP and SRN_SYNCIN together if not used. If configured
as a secondary for dual charger configuration, this pin functions as SYNCIN, and connect to
TSBAT_SYNCOUT of Primary, and connect a 1-kΩpullup resistor to REGN.
D6
SRN_SYNCIN
AI
AI
Battery temperature voltage input and Primary Mode SYNCOUT - Requires external
resistor divider, NTC, and voltage reference. See the TSBAT section for choosing the resister
divider values. If the device is in Primary Mode, connect this pin to SRN_SYNCIN of the
Secondary device.
E4
F4
TSBAT_SYNCOUT
BUS temperature voltage input - Requires external resistor divider, NTC, and voltage
reference. See the TSBUS section for choosing the resister divider values.
TSBUS
VBUS
VOUT
AI
P
A6, B6,
C6
Device power input - Connect 1-µF capacitor from VBUS to GND.
Device power output - Connect 22-µF capacitor from VOUT to GND.
A3, B3,
C3, D3
P
E3
E2
VAC1
VAC2
AI
AI
VAC1 input detection - Connected to VBUS if ACFET1 and RBFET1 are not used.
VAC2 input detection - Connected to VBUS if ACFET2 and RBFET2 are not used.
(1) Type: P = Power , AIO = Analog Input/Output , AI = Analog Input, DO = Digital Output, AO = Analog Output, DIO = Digital Input/Output
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
40
20
20
30
7
UNIT
V
VAC1, VAC2 (converter not switching)
VBUS (converter not switching)
PMID (converter not switching)
ACDRV1, ACDRV2
V
–2
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
CFL1, CFL2
V
Voltage
CFH1 to VOUT, CFH2 to VOUT
7
V
VOUT
7
V
BATP, BATN_SRP
6
V
INT, SDA, SCL, CDRVL_ADDRMS, SRN_SYNCIN,
TSBAT_SYNCOUT, TSBUS
6
V
–0.3
–0.3
CDRVH
20
6
V
Output Sink Current
INT
mA
°C
°C
TJ
Junction temperature
Storage temperature
150
150
–40
–55
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
12
12
12
6
UNIT
V
VAC1, VAC2
Input voltage at VAC1 and VAC2
Input voltage at VBUS
VBUS
V
PMID
Input voltage at PMID
V
PMID-CFH1, PMID-CFH2
Voltage across QCH1, QCH2
Voltage across QDH1, QDH2
Voltage across QCL1, QCL2
Voltage across QDL1, QDL2
Charging current
V
CFH1-VOUT, CFH2-VOUT
6
V
VOUT-CFL1, VOUT-CFL2
6
V
CFL1, CFL2
ICHG
TA
6
V
8
A
Ambient temperature
85
120
°C
°C
µF
µF
µF
–40
–40
6.6
0.2
2
TJ
Junction temperature
CCFLY
CVBUS
CPMID
Effective CFLY capacitance
Effective VBUS capacitance
Effective PMID capacitance
20
1
10
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8.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
10
MAX
UNIT
µF
COUT
CREGN
CDRV
Effective VOUT capacitance
Effective REGN capacitance
Effective DRV capacitance
1
4.7
µF
44
220
nF
8.4 Thermal Information
BQ25960
THERMAL METRIC(1)
YBG (DSBGA)
UNIT
36 PINS
54.8
0.2
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance (JEDEC(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
)
°C/W
°C/W
°C/W
°C/W
°C/W
12
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
11.9
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
QUIESCENT CURRENTS
ADC disabled, charge disabled,
VBUS, VAC1, and VAC2 not present,
VBAT=4V
12
20 µA
IQ_BAT
Quiescent battery current
Quiescent VAC current
ADC enabled (slowest mode), charge
disabled, VBUS, VAC1, and VAC2
not present, VBAT=4V
480
750 µA
ADC disabled, charge disabled,
ACDRV disabled, EN_HIZ=1, VAC1
or VAC2 =8V
90
µA
µA
IQ_VAC
ADC enabled, charge disabled,
ACDRV enabled, VAC1 or VAC2= 8V
660
INTERNAL THRESHOLD
VAC rising threshold for active
I2C, no VOUT, no VBUS
VVACUVLOZ
VAC1 or VAC2 rising
VAC1 or VAC2 falling
VAC1 or VAC2 rising
VAC1 or VAC2 falling
VBUS rising
3.24
3.05
3.3
3.4
3.2
3.4
3.2
3.4
2.8
3.6
3.4
V
V
V
V
V
V
VAC falling threshold for I2C stop
working
VVACUVLO
VAC rising threshold to turn on
ACFET-RBFET
3.5
VVACPRESENT
VAC falling threshold to turn off
ACFET-RBFET
3.1
3.3
VBUS rising threshold for active
I2C, no VOUT, no VAC
VVBUSUVLOZ
VVBUSUVLO
3.24
2.65
3.6
VBUS falling threshold for I2C
stop working
VBUS falling
2.95
VBUS rising threshold to allow
user set CHG_EN =1
VBUS rising
VBUS falling
3.3
3.1
3.4
3.2
3.5
3.3
V
V
VVBUSPRESENT
VBUS falling
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8.5 Electrical Characteristics (continued)
VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOUT rising threshold for active
VVOUTUVLOZ
VVOUTUVLO
VOUT rising
2.48
2.6
2.72
2.55
V
V
I2C, no VAC, no VBUS
VOUT falling threshold for I2C
stop working
VOUT falling
2.25
2.4
VOUT rising to threshold allow
user set CHG_EN =1
VOUT rising
VOUT falling
3.0
2.9
3.1
3.0
3.2
3.1
V
V
VVOUTPRESENT
VOUT falling
RESISTANCE
RON_BLK
RON_CH1
RON_DH1
RON_CL1
RON_DL1
RON_CH2
RON_DH2
RON_CL2
RON_DL2
RVBUS_PD
VBUS to PMID resistance
PMID to CFH1 resistance
CFH1 to VOUT resistance
VOUT to CFL1 resistance
CFL1 to GND resistance
PMID to CFH2 resistance
CFH2 to VOUT resistance
VOUT to CFL2 resistance
CFL2 to GND resistance
VBUS pull down resistance
VBUS=8V
PMID=8V
CFLY=4V
VOUT=4V
CFLY=4V
PMID=8V
CFLY=4V
VOUT=4V
CFLY=4V
6.1
19.3
11.4
11.8
12
10.5
26.8
16.8
18
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
mΩ
kΩ
18.3
26.8
16.8
18
19.3
11.4
11.8
12
18.3
5
VAC pull down resistance for
both VAC1 and VAC2
RVAC_PD
VAC=10V
125
Ω
PROTECTION AND ALARM THRESHOLD AND ACCURACY
VBATOVP_RANGE
VBATOVP_STEP
IBATP
Battery over-voltage range
Typical battery over-voltage step
BATP leakage current
3.491
4.759
V
9.985
mV
1.2 µA
IBATN
BATN leakage current
1
4.434
5.1
nA
V
VBATOVP_ACC
VOUTOVP_ACC
IBATOCP_RANGE
IBATOCP_STEP
Battery over-voltage accuracy
VOUT over-voltage accuracy
Battery over-current range
Typical battery over-current step
VBATOVP = 4.390V
VOUTOVP= 5V
4.346
4.9
4.390
5
V
2.05
8.7125
A
102.5
6.15
mA
IBATOCP=6.15A, RSNS=2mΩ
TJ = –20°C - 85°C
IBATOCP_ACC
Battery over-current accuracy
VBUS over-voltage range
5.842
6.458
A
V
Switched Cap Mode
Bypass Mode
7
12.75
6.5
VBUSOVP_RANGE
3.5
Switched Cap Mode
Bypass Mode
50
25
mV
mV
V
VBUSOVP_STEP
Typical VBUS over-voltage step
VBUS over-voltage accuracy
VBUSOVP = 4.45V
VBUSOVP = 9V
4.39
8.91
4.45
9
4.488
9.09
VBUSOVP_ACC
V
VBUS ERRHI rising threshold for
switched cap mode stop
switching
VBUS_ERRHI_RISING_SC
VOUT=4V
VOUT=4V
9.6
9.4
V
V
VBUS ERRHI falling threshold
for switched cap mode start
switching
VBUS_ERRHI_FALLING_SC
VBUS ERRHI rising threshold for
bypass mode stop switching
VBUS_ERRHI_RISING_BYPASS
VBUS_ERRHI_FALLING_BYPASS
VOUT=4V
VOUT=4V
4.8
V
V
VBUS ERRHI falling threshold
for bypass mode start switching
4.68
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MAX UNIT
8.5 Electrical Characteristics (continued)
VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VVACOVP_RANGE
VAC over-voltage range
6.5
18
6.6
V
V
VACOVP=6.5V
6.3
6.5
10.5
12
VVACOVP_ACC
VAC over-voltage accuracy
VACOVP=10.5V
VACOVP=12V
10.2
11.7
10.7
12.2
V
V
VVACOVP_HYS
VACOVP hysteresis
3
%
A
Switched Cap Mode
Bypass Mode
1.0175
1.0475
4.579
6.809
IBUSOCP_RANGE
Input over-current range
A
Switched Cap Mode
Bypass Mode
254
262
mA
mA
IBUSOCP_STEP
Typical input over current step
IBUSOCP=3.05A, switched cap
mode
TJ = –20°C - 85°C
2.897
3.05
3.14
3.206
3.297
A
A
IBUSOCP_ACC
Input over current accuracy
Input under-current accuracy
IBUSOCP=3.14A, bypass mode
TJ = –20°C - 85°C
2.983
100
BUSUCP=250mA, TJ = –20°C -
85°C
IBUSUCP_ACC
250
300
450 mA
450 mA
IBUSRCP_ACC
Input reverse-current accuracy
TSBUS fault % of VREGN range
BUSRCP=300mA, TJ = -20°C - 85°C
TSBUS_FLT=20.12%
150
0
TSBUS_FLT_RANGE
50
%
%
TSBUS fault % of VREGN step
size
TSBUS_FLT_STEP
0.1953
20.12
TSBUSFLT_ACC
TSBUS fault accuracy
18.5
0
21.5
50
%
%
TSBAT_FLT_RANGE
TSBAT fault % of VREGN range
TSBAT fault % of VREGN step
size
TSBAT_FLT_STEP
0.1953
20.12
%
%
TSBAT_FLT_ACC
TDIE_FLT_RANGE
TDIE_FLT_STEP
TSBAT voltage accuracy
TSBAT_FLT=20.12%
18.5
80
21.5
TDIE over-temperature range
TDIE over-temperature step
140 °C
°C
20
TDIE over-temperature alarm
range
TDIE_ALM_RANGE
TDIE_ALM_STEP
25
150 °C
°C
TDIE over-temperature alarm
step
0.5
ADC MEASUREMENT PERFORMANCE
ADC_SAMPLE[1:0] = 00
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
ADC_SAMPLE[1:0] = 00
ADC_SAMPLE[1:0] = 01
ADC_SAMPLE[1:0] = 10
ADC_SAMPLE[1:0] = 11
24
12
6
ms
ms
ms
ms
bit
Conversion-time, Each
Measurement
tADC_CONV
3
14
13
12
10
15
14
13
11
bit
ADCRES
Effective Resolution
bit
bit
ADC MEASUREMENT RANGES AND ACCURACY
IBUSADC_RANGE
ADC BUS current range
ADC BUS current LSB
ADC BUS current LSB
ADC BUS current offset
ADC BUS current offset
0
7
A
Switched Cap Mode
Bypass Mode
0.9972
1.0279
66
mA
mA
mA
mA
IBUSADC_LSB
Switched Cap Mode
Bypass Mode
IBUSADC_OFFSET
64
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8.5 Electrical Characteristics (continued)
VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IBUS=2A, ADC_SAMPLE[1:0]=00,
TJ = –20°C - 85°C
1.9
2
2.1
A
A
IBUSADC_ACC
ADC BUS current accuracy
IBUS=3A, ADC_SAMPLE[1:0]=00,
TJ = –20°C - 85°C
2.85
0
3
3.15
VBUSADC_RANGE
VBUSADC_LSB
ADC BUS voltage range
ADC BUS voltage LSB
16.39
V
mV
V
1.002
VBUS=4V, ADC_SAMPLE[1:0]=00
VBUS=8V, ADC_SAMPLE[1:0]=00
3.96
7.92
0
4
8
4.04
8.08
14
VBUSADC_ACC
ADC BUS voltage accuracy
V
VAC1ADC_RANGE
VAC1ADC_STEP
VAC1ADC_OFFSET
ADC VAC1 voltage range
ADC VAC1 voltage LSB
ADC VAC1 voltage offset
V
1.0008
mV
mV
V
3
4
8
VAC1=4V, ADC_SAMPLE[1:0]=00
VAC1=8V, ADC_SAMPLE[1:0]=00
3.96
7.92
0
4.04
8.08
14
VAC1ADC_ACC
ADC VAC1 voltage accuracy
V
VAC2ADC_RANGE
VAC2ADC_LSB
ADC VAC2 voltage range
ADC VAC2 voltage LSB
ADC VAC2 voltage offset
ADC VAC2 voltage accuracy
ADC VAC2 voltage accuracy
ADC BAT voltage range
ADC BAT voltage LSB
V
1.0006
mV
mV
V
VAC2ADC_OFFSET
VAC2ADC_ACC
VAC2ADC_ACC
VBATADC_RANGE
VBATADC_LSB
5
4
8
VAC2=4V, ADC_SAMPLE[1:0]=00
VAC2=8V, ADC_SAMPLE[1:0]=00
3.96
7.92
0
4.04
8.08
6
V
V
1.017
1
mV
mV
V
VBATADC_OFFSET
ADC BAT voltage offset
VBAT=4V, ADC_SAMPLE[1:0]=00
VBAT=4.4V, ADC_SAMPLE[1:0]=00
3.96
4.356
0
4
4.04
4.444
6
VBATADC_ACC
ADC BAT voltage accuracy
4.4
V
VOUTADC_RANGE
VOUTADC_LSB
ADC VOUT voltage range
ADC VOUT voltage LSB
ADC VOUT voltage offset
V
1.0037
mV
mV
V
VOUTADC_OFFSET
2
4
VOUT=4V, ADC_SAMPLE[1:0]=00
VOUT=4.4V, ADC_SAMPLE[1:0]=00
3.98
4.378
-12
4.02
4.422
12
VOUTADC_ACC
ADC VOUT voltage accuracy
4.4
V
IBATADC_RANGE
IBATADC_LSB
ADC battery current range
ADC battery current LSB
ADC battery current offset
A
0.999
-150
mA
mA
IBATADC_OFFSET
IBAT=4A, ADC_SAMPLE[1:0]=00, TJ
= –20°C - 85°C
3.92
4.00
6.00
4.08
A
ADC battery current accuracy
through 2mOhm sense resistor
IBATADC_ACC_2mOhm
IBAT=6A, ADC_SAMPLE[1:0]=00, TJ
= –20°C - 85°C
5.88
0
6.12
50
A
%
%
TSBUSADC_RANGE
TSBUSADC_STEP
ADC TSBUS % of VREGN range
ADC TSBUS % of VREGN range
LSB
0.0986
0.1
ADC TSBUS % of VREGN range
offset
TSBUSADC_OFFSET
%
TSBUS=20% of VREGN
ADC_SAMPLE[1:0]=00
,
TSBUSADC_ACC
TSBATADC_RANGE
TSBATADC_STEP
ADC TSBUS accuracy
19
0
20
21
50
%
%
%
ADC TSBAT % of VREGN range
ADC TSBAT % of VREGN range
LSB
0.0976
0.065
ADC TSBAT % of VREGN range
offset
TSBATADC_OFFSET
%
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MAX UNIT
8.5 Electrical Characteristics (continued)
VBUS=8V, VOUT=4V, TJ= -40°C to +85°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TSBAT=20% of VREGN
ADC_SAMPLE[10]=00
MIN
TYP
,
TSBATADC_ACC
ADC TSBAT accuracy
19
20
21
%
TDIE_ADC_RANGE
TDIE_ADC_STEP
TDIE_ADC_OFFSET
REGN LDO
VREGN
ADC TDIE range
ADC TDIE step
ADC TDIE offset
-40
150 °C
°C
0.5079
-3.5
°C
REGN LDO output voltage
REGN LDO current limit
VBUS=8V, IREGN=20mA
VBUS=8V, VREGN=4.5V
5.0
V
IREGN
40
mA
I2C INTERFACE (SCL, SDA)
Input high threshold level, SDA
and SCL
VIH
Pull up rail 1.8V
1.3
V
VIL
Input low threshold level
Output low threshold level
High-level leakage current
Pull up rail 1.8V
Sink current = 5mA
Pull up rail 1.8V
0.4
0.4
1
V
V
VOL
IBIAS
µA
LOGIC OUTPUT PIN (INT, TSBAT_SYNCOUT)
Output low threshold level, INT
pin
VOL
Sink current = 5mA
Pull up rail 1.8V
0.4
1
V
High-level leakage current, INT
pin
IOUT
µA
LOGIC INPUT PIN (SRN_SYNCIN)
Input high threshold level,
SRN_SYNCIN
VIH_SRN_SYNCIN
1.3
V
Input low threshold level,
SRN_SYNCIN
VIL_SRN_SYNCIN
IIN_SRN_SYNCIN
0.4
1
V
High level leakage current
Pull-up rail 1.8V
µA
8.6 Timing Requirements
MIN
NOM
MAX
UNIT
TIMINGS
tVACOVP
VAC OVP response time
IBAT OCP response time
100
640
256
120
ns
µs
µs
ms
tBATOCP
tINT
Duration that INT is pulled low when an event occurs
Time between consecutive faults for ALM indication
tALM_DEBOUNCE
I2C INTERFACE
fSCL
SCL clock frequency
1000
kHz
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8.7 Typical Characteristics
Typical characteristics are taken with the BMS041 for switching test and GRM188R61C226M is used as CFLY.
97.75
97.25
96.75
96.25
95.75
95.25
94.75
94.25
93.75
93.25
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
Charge current (A)
4
5
6
7
8
0
1
2
3
Charge current (A)
4
5
6
7
8
VBAT = 4.0 V, FSW = 500 kHz
VBAT = 4.0 V, FSW = 500 kHz
图8-1. Battery Charge Efficiency vs. Charge Current, 1 x 22-µF
图8-2. Battery Charge Power Loss vs. Charge Current, 1 x 22-
CFLY per Phase Switching Frequency
µF CFLY per Phase Switching Frequency
1.8
1.6
1.4
1.2
1
98
97.6
97.2
96.8
96.4
96
0.8
0.6
0.4
0.2
0
95.6
95.2
94.8
0.5
1.5
2.5
3.5
4.5
5.5
Charge current (A)
6.5
7.5
8.5
0.5
1.5
2.5
3.5
4.5
5.5
Charge current (A)
6.5
7.5
8.5
VBAT = 4.0 V, FSW = 500 kHz
VBAT = 4.0 V, FSW = 500 kHz
图8-3. Battery Charge Efficiency vs. Charge Current, 2 x 22-µF
图8-4. Battery Charge Power Loss vs. Charge Current, 2 x 22-
CFLY per Phase
µF CFLY per Phase
98.2
98
1.6
1.4
1.2
1
97.8
97.6
97.4
97.2
97
96.8
96.6
96.4
96.2
96
0.8
0.6
0.4
0.2
0
95.8
95.6
95.4
0.5
1.5
2.5
3.5
4.5
5.5
Charge current (A)
6.5
7.5
8.5
0.5
1.5
2.5
3.5
4.5
5.5
Charge current (A)
6.5
7.5
8.5
VBAT = 4.0 V, FSW = 500 kHz
VBAT = 4.0 V, FSW = 500 kHz
图8-6. Battery Charge Power Loss vs. Charge Current, 3 x 22-
图8-5. Battery Charge Efficiency vs. Charge Current, 3 x 22-µF
µF CFLY per Phase
CFLY per Phase
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9 Detailed Description
9.1 Overview
The BQ25960 is a 98.1% peak efficiency, 8-A battery charging solution using a switched cap architecture for 1-
cell Li-ion battery. This architecture allows the cable current to be half the charging current, reducing the cable
power loss, and limiting temperature rise. The dual-phase architecture increases charging efficiency and reduces
the input and output cap requirements. When used with a main charger such as BQ2561x or BQ2589x, the
system the system enables full charging cycle from trickle charge to termination with low power loss at Constant
Current (CC) and Constant Voltage (CV) mode.
The device also operates in bypass mode charging the battery directly from VBUS through QB, QCH1 and
QDH1 in parallel with QCH2 and QDH2. The impedance in bypass mode is limited to 21 mΩ for 5-A charging
current.
The device supports dual input power path management which manages the power flowing from two different
input sources. The inputs selection is controlled by host through I2C with default source #1 as the primary input
and the source #2 as the secondary source.
The device integrates all the necessary protection features to ensure safe charging, including input overvoltage
and overcurrent protection, output overvoltage and overcurrent protection, temperature sensing for the battery
and cable, and monitoring the die temperature.
The device includes a 16-bit ADC to provide bus voltage, bus current, output voltage, battery voltage, battery
current, input connector temperature, battery temperature, junction temperature, and other calculated
measurements needed to manage the charging of the battery from the smart wall adapter or wireless input or
power bank.
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9.2 Functional Block Diagram
VVBUSUVLOZ
BQ25960
+
UVLO
Block Diagram
+
REGN
REGN
LDO
VVBUSOVP
REGN
EN_HIZ
VBUSOVP
CDRVH
QB
CDRVL_ADDRMS
IBUS
PMID
VBUS
ACDRV1
ACDRV2
QCH1
QCH2
Switched
Cap
Control
CFH2
CFH1
VAC1
INPUT
SELECTOR
VAC2
QDH1
QDH2
VOUT
Digital Core,
I2C Control
and System
Feedback to HOST
SCL
SDA
QCL1
QCL2
SYNCOUT
CFL2
CFL1
SYNCIN
INT
QDL2
QDL1
+
TSBUS
GND
TSBUS_FLT
VBUS_ADC
VBAT_ADC
IBAT_ADC
TSBUS_ADC
TSBAT_ADC
TDIE_ADC
VAC1_ADC
VAC2_ADC
BATP
+
TSBAT_SYNCOUT
TSBAT_FLT
ADC
IBUS_ADC
SYNCOUT
VOUT_ADC
BATN_SRP
+
VBUS
+
+
+
+
VBATOVP
VBUSOVP
SRN_SYNCIN
+
IBUS
+
IBATOCP
Protection
IBUSOCP
VOUT
IBUSUCP
IBUS
+
+
SYNCIN
VOUTOVP
IBUS
IC_TJ
TDIE_FTL
+
IBUSRCP
VAC2
+
+
VAC1
VAC1OVP
VAC2OVP
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9.3 Feature Description
9.3.1 Charging System
BQ25960 is a single-cell high efficiency switched cap charger, used in parallel with a switching mode charger. A
host must set up the protections and alarms on BQ25960 prior to enabling the BQ25960. The host must monitor
the alarms generated by BQ25960 and communicate with the smart adapter to control the current delivered to
the charger.
Phone
BQ25960
(Parallel charger)
VOUT
SC Phase
#1
SC Phase
#2
Adapter
SW
VBUS
SYSTEM
AC/DC
Converter
VBUS
D+/D-
SYS
BAT
Main charger
D+/D-
Host + PD Controller
CC1/ CC2
PD Controller
I2C
AP
图9-1. BQ25960 System Diagram
9.3.2 Battery Charging Profile
The system will have a specific battery charging profile that is unique due to the switched cap architecture. The
charging will be controlled by the main charger such as the BQ2561x or BQ2589x until ystem voltage reaches
minimum system regulation voltage VSYSMIN. Once the battery voltage reaches VSYSMIN (3.5 V), the adapter can
negotiate for a higher bus voltage, enable BQ25960 charging, and regulate the current on VBUS to charge the
battery. In the CC phase, the protection in BQ25960 will not regulate the battery voltage, but will provide
feedback to the system to increase and decrease current as needed, as well as disable the blocking and
switching FETs if the voltage is exceeded. Once the CV point is reached, the BQ25960 will provide feedback to
the adapter to reduce the current, effectively tapering the current until a point where the main charger takes over
again. The BQ25960 can operate as long as input current is above the BUSUCP threshold.
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8A
7A
Note: Current and Voltage steps are exaggerated for
example only œ actual current steps are much
smaller
BATOVP
BATOVP_ALM
6A
5A
4A
Battery Current
Battery Voltage
Cable Current
3.5V
3A
3.5
2A
1A
3.0
3.0V
Pre-Charge
Pre-Charge
Main charger
CC CC
Main charger BQ25960
CV
BQ25960
CV
Main charger
T1 T2 T3
T4
T5
图9-2. BQ25960 System Charging Profile
9.3.3 Device Power Up
The device is powered from the higher of VAC1 or VAC2 (with VAC1 being primary input), VBUS or VOUT
(battery). The voltage must be greater than the VVACUVLOZ, VVBUSUVLOZ or VVOUTUVLOZ threshold to be a valid
supply. When VAC1 or VAC2 rises above VVACUVLOZ or VBUS rises above VVBUSUVLOZ or VOUT rises above
VVOUTUVLOZ, I2C interface is ready for communication and all the registers are reset to default value. The host
needs to wait VBUSPRESENT_STAT and VOUTPRESENT_STAT go high before setting CHG_EN =1 and start
charging.
9.3.4 Device HIZ State
The device enters HIZ mode when EN_HIZ bit is set to '1'. When device is in HIZ mode, the converter stops
switching, ADC stops converting, ACDRV is turned off and REGN LDO is forced off even when the adapter is
present and no fault condition is present. The device exits HIZ Mode when EN_HIZ is set to '0' by host or device
POR.
The faults conditions force the converter stop switching and clear CHG_EN bit, but keep REGN on and EN_HIZ
bit = 0. More details can be found in the Device Protection section.
9.3.5 Dual Input Bi-Directional Power Path Management
The device has two ACDRV pins to drive two sets of N-channel ACFET-RBFET, which select and manage the
input power from two different input sources. In the POR sequence, the device detects if the ACFET-RBFET is
populated based on if ACDRV pin is shorted to ground or not, and then updates the status register
ACRB1_CONFIG_STAT or ACRB2_CONFIG_STAT to indicate the presence of ACFET-RBFET. If the external
ACFET-RBFET is not populated in the schematic, then tie VAC to VBUS and connect ACDRV to GND. The
device supports:
1. single input without external FET
2. single input with one single ACFET
3. dual input with one set of ACFET-RBFET
4. dual input with two sets of ACFET-RBFET
The power-up sequences for different applications are described in detail below.
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9.3.5.1 ACDRV Turn-On Condition
The ACDRV controls input power MUX for both BQ25960 and main charger. In order to turn the ACDRV, all of
the following conditions must be valid:
1. The corresponding AC-RB FET is populated: VAC is not short to VBUS and ACDRV is not short to ground
2. VAC is above VVACpresent threshold
3. VAC is below VVACOVP threshold
4. DIS_ACDRV_BOTH is not set to '1'
5. EN_HIZ is not set to '1'
6. VBUS is below VVBUSpresent threshold
9.3.5.2 Single Input from VAC to VBUS without ACFET-RBFET
In this scenario, VAC1 and VAC2 are both shorted to VBUS, ACDRV1 and ACDRV2 are pulled down to ground.
The table below summarizes the VAC1/VAC2, ACDRV1/ACDRV2 connection, register control, and status
functions.
表9-1. Single Input without External FET Summary
INPUT CONFIGURATION
SINGLE INPUT
External FET connection
No external FET
Input pin connection
ACDRV pin connection
ACDRV1_STAT
VAC1 and VAC2 short to VBUS
ACDRV1 and ACDRV2 short to ground
0
ACDRV2_STAT
0
DIS_ACDRV_BOTH
ACRB1_CONFIG_STAT
ACRB2_CONFIG_STAT
EN_HIZ
1
0
0
No impact on ACDRV
ACDRV2
VAC2
PMID
Adapter
VBUS
QB
VAC1
ACDRV1
BQ25960
图9-3. Single input without ACFET-RBFET
9.3.5.3 Single Input with ACFET1
In this scenario, ACFET1 without RBFET1 is populated, but ACFET2-RBFET2 is not. VAC2 is short to VBUS
and ACDRV2 is pulled down to ground. The table below summarizes the VAC1/ VAC2, ACDRV1/ACDRV2
connection, register control, and status functions. Use VAC1 for single input configuration.
表9-2. Single Input with Single ACFET1
INPUT CONFIGURATION
External FET connection
SINGLE INPUT
ACFET1, no ACFET2-RBFET2
Input pin connection
ACDRV pin connection
ACDRV1_STAT
VAC1 connected to input source
VAC2 short to VBUS
ACDRV1 active
ACDRV2 tie to ground
1: ACDRV1 is ON
0: ACDRV1 is OFF
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表9-2. Single Input with Single ACFET1 (continued)
INPUT CONFIGURATION
SINGLE INPUT
ACDRV2_STAT
0
DIS_ACDRV_BOTH
0: Allow ACDRV1 to turn on if the conditions of ACDRV turn on are met.
1: Force ACDRV1 OFF
ACRB1_CONFIG_STAT
ACRB2_CONFIG_STAT
EN_HIZ
1
0
0: Allow ACDRV1 to turn on if the conditions of ACDRV turn on are met.
1: Force ACDRV1 OFF
ACDRV2
VAC2
ACFET1
Adapter
PMID
VBUS
QB
ACDRV1
VAC1
BQ25960
图9-4. Single Input with ACFET1
9.3.5.4 Dual Input with ACFET1-RBFET1
In this scenario, ACFET1-RBFET1 is populated, but ACFET2-RBFET2 is not. VAC2 is short to VBUS and
ACDRV2 is pulled down to ground. The table below summarizes the connection, register control and status
functions. Use VAC1 for adapter input and VBUS for wireless input.
表9-3. Dual Input with ACFET1-RBFET1
INPUT CONFIGURATION
External FET connection
DUAL INPUT
ACFET1-RBFET1, no ACFET2-RBFET2
Input pin connection
ACDRV pin connection
ACDRV1_STAT
VAC1 connected to input source 1
VAC2 short to VBUS
ACDRV1 active
ACDRV2 short to ground
0: ACDRV1 OFF
1: ACDRV1 ON
ACDRV2_STAT
0
DIS_ACDRV_BOTH
0: Allow ACDRV1 to turn on if other conditions of ACDRV turn on are met
1: Force ACDRV1 OFF
ACRB1_CONFIG_STAT
ACRB2_CONFIG_STAT
EN_HIZ
1
0
0: Allow ACDRV1 to turn on if other conditions of ACDRV turn on are met
1: Force ACDRV1 OFF
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ACDRV2
VAC2
PMID
Wireless
Adapter
VBUS
QB
ACDRV1
VAC1
BQ25960
ACFET1
RBFET1
图9-5. Dual Input with ACFET-RBFET1
9.3.5.5 Dual Input with ACFET1-RBFET1 and ACFET2-RBFET2
In this scenario, both ACFET1-RBFET1 and ACFET2-RBFET2 are populated and the device supports dual
input. The table below summarizes the connection, register control and status functions. Connect input with high
OVP threshold to VAC1.
表9-4. Dual Input with Both ACFET1-RBFET1 and ACFET2-RBFET2 Summary
INPUT CONFIGURATION
DUAL INPUT
External FET connection
ACFET1-RBFET1, ACFET1-RBFET2
Input pin connection
VAC1 connected to input source 1
VAC2 connected to input source 2
No input source allowed to connect to VBUS
ACDRV pin connection
ACDRV1_STAT
ACDRV1 and ACDRV2 active
0: ACDRV1 OFF
1: ACDRV1 ON
Once device is in dual input configuration with ACFET1-RBFET1 and ACFET2-RBFET2, the
host can use this bit to swap the input between VAC1 and VAC2 if both VAC1 and VAC2 are
valid.
ACDRV2_STAT
0: ACDRV2 OFF
1: ACDRV2 ON
Once device is in dual input configuration with ACFET1-RBFET1 and ACFET2-RBFET2, the
host can use this bit to swap the input between VAC1 and VAC2 if both VAC1 and VAC2 are
valid.
DIS_ACDRV_BOTH
0: Allow ACDRV to turn on. By default, ACDRV1 is turned on if the conditions of ACDRV turn
on are met, ACDRV1_STAT=1 and ACDRV2_STAT =0. In On-The-GO (OTG) or Reverse TX
Mode, refer to OTG and Reverse TX Mode Operation session for turn on precedence.
1: Force both ACDRV to turn off, both ACDRV1_STAT and ACDRV2_STAT become 0.
ACRB1_CONFIG_STAT
ACRB2_CONFIG_STAT
EN_HIZ
1
1
0: Allow ACDRV to turn on for the port w/ VAC present if the conditions of ACDRV turn on
are met.
ACDRV1 is turned on since VAC1 is the primary input source when both VAC1 and VAC2
present and the turn on conditions are met.
1: Turns off both ACDRV
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ACDRV2
VAC2
RBFET2
ACFET2
Wireless
Adapter
VBUS
PMID
QB
ACDRV1
VAC1
ACFET1
RBFET1
BQ25960
图9-6. Two Inputs with ACFET-RBFET1 and ACFET-RBFET2
9.3.5.6 OTG and Reverse TX Mode Operation
When the main charger is in OTG or reverse TX Mode, the input power MUX (ACFET-RBFET) also controls
which port is desired for OTG output.
To enter OTG or reverse TX Mode, the host should follow the steps below:
1. Host writes EN_OTG =1
2. BQ25960 sets DIS_ACDRV_BOTH =1
3. Host writes DIS_ACDRV_BOTH=0, and then writes ACDRV1_STAT=1 or ACDRV2_STAT=1 depending on
which port is desired for OTG or reverse TX output
4. Host enables OTG Mode on main charger
5. If VBUSOVP or VACOVP fault occurs, ACDRV will be disabled but EN_OTG is still '1'. Host needs to write
ACDRV1_STAT high or ACDRV2_STAT high when the fault is cleared. Set VAC1OVP and VAC2OVP to the
same threshold in the OTG Mode
6. EN_OTG is cleared when watchdog timer expires
To exit OTG or Reverse TX Mode, the host should follow the steps below:
1. Turn off main OTG or reverse TX source
2. Turn on VBUS pulldown resistor (RVBUS_PD) by setting BUS_PD_EN=1 or VAC pulldown resistor RVAC_PD by
setting VAC1_PD_EN=1 or VAC2_PD_EN=1, depending on which port is to be discharged
3. Wait for VBUS and VAC to be discharged
4. Turn off ACDRV by setting ACDRV1_STAT=0 or ACDRV2_STAT=0
5. Exit OTG Mode by setting EN_OTG=0
9.3.6 Bypass Mode Operation
When host determines the adapter support bypass mode charging, the device can enable Bypass mode by
setting EN_BYPASS=1. Blocking FET (QB) and four high side switching FET (QCH1 and QDH1/ QCH2 and
QDH2) are turned on to charge from adapter to battery. During Bypass Mode, when fault occurs, CHG_EN is
cleared but EN_BYPASS stays ‘1’.
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ACDRV2
VBUS
VAC2
BQ25960
Adapter
Wireless
SDA
ACDRV1
Digital
Core
QB
SCL
/INT
Host
VAC1
PMID
QCH1
QCH2
CFH2
CFH1
QDH1
CFLY2
QDH2
QCL2
QDL2
CFLY1
VOUT
QCL1
CFL2
CFL1
QDL1
GND
图9-7. BQ25960 Bypass Mode
To change from Bypass Mode to Switched Cap Mode or from Switched Cap to Bypass Mode, the host would first
set CHG_EN=0 to stop the converter and then set EN_BYPASS to desired value. The host sets desired
protection threshold based on the selected operation modes and then host enables charge by setting
CHG_EN=1.
9.3.7 Charging Start-Up
The host can start Switched Cap or Bypass Mode charging follow the steps below:
1. Both VBUS and VOUT need to be present. Host can check the status through VBUSPRESENT_STAT
(REG15[2]) and VOUTPRSENT_STAT (REG15[5]). Both of them need to be '1'.
2. Host sets all the protections to the desired thresholds. Refer to the Device Modes and Protection Status
section for proper setting.
3. Host sets either Switched Cap Mode or Bypass Mode through EN_BYPASS bit (REG0F[3]) based on
adapter type.
4. Host sets the desired switching frequency in Switched Cap Mode through FSW_SET [2:0] bits (REG10[7:5]).
5. Host sets BUS under current protection (BUSUCP) to 250 mA though BUSUCP bit (REG05[6])=1
6. Host sets charger configuration bits: CHG_CONFIG_1 (REG05[3])=1.
7. Host can enable charge by setting CHG_EN=1.
8. Once charge has been enabled, the CONV_ACTIVE_STAT bit is set to '1' to indicate either switched cap or
bypass is active, and current starts to flow to the battery.
9. When watchdog timer expires, CHG_EN is reset to '0' and charging stops. Host needs to read or write any
register bit before watchdog expires, or disable watchdog timer (set REG10[2]=1) to prevent watchdog timer
from expiring.
9.3.8 Adapter Removal
If adapter is removed during soft start timer, CHG_EN will be cleared after soft-start timer expires. The user can
program the soft-start timer in SS_TIMEOUT register. If adapter is removed after soft-start timer expires,
converter stops switching and CHG_EN is cleared after the deglitch time programmed in
IBUSUCP_FALL_DG_SEL register. The device prevents boost back when the adapter is removed during and
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after the soft-start timer. To accelerate VBUS or VAC discharge after adapter removal, the user to turn on the
VBUS pulldown resistor (RVBUS_PD) and VAC pulldown current resistor (RVAC_PD) by setting BUS_PD_EN or
VAC1_PD_EN or VAC2_PD_EN to '1'.
9.3.9 Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
The integrated 16-bit ADC of the device allows the user to get critical system information for optimizing the
behavior of the charger control. The control of the ADC is done through the ADC control register. The ADC_EN
bit provides the ability to enable and disable the ADC to conserve power. The ADC_RATE bit allows continuous
conversion or one-shot behavior. The ADC_AVG bit enables or disables (default) averaging. ADC_AVG_INIT
starts average using the existing (default) or using a new ADC value.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if the
VVAC>VVACPRESENT, VVBUS>VVBUSPRESENT or VVOUT>VVOUTPRESENT is valid. If ADC_EN is set to ‘1’ before
VAC, VBUS or VOUT reach their respective PRESENT threshold, then the ADC conversion will be postponed
until one of the power supplies reaches the threshold.
The ADC_SAMPLE bits control the sample speed of the ADC, with conversion times of tADC_CONV. The
integrated ADC has two rate conversion options: a 1-shot mode and a continuous conversion mode set by the
ADC_RATE bit. By default, all ADC parameters will be converted in 1-shot or continuous conversion mode
unless disabled in the ADC CONTROL 1 and ADC_CONTROL 2 register. If an ADC parameter is disabled by
setting the corresponding bit in the ADC CONTROL 1 and ADC_CONTROL 2 register, then the value in that
register will be from the last valid ADC conversion or the default POR value (all zeros if no conversions have
taken place). If an ADC parameter is disabled in the middle of an ADC measurement cycle, the device will finish
the conversion of that parameter, but will not convert the parameter starting the next conversion cycle. Even
though no conversion takes place when all ADC measurement parameters are disabled, the ADC circuitry is
active and ready to begin conversion as soon as one of the bits in the ADC CONTROL 1 and ADC_CONTROL 2
register is set to ‘0’.
The ADC_DONE_* bits signal when a conversion is complete in 1-shot mode only. During continuous conversion
mode, the ADC_DONE_* bits have no meaning and will be ‘0’.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (such as one that causes the power stage to be disabled), and the host must set
ADC_EN = ‘0’ to disable the ADC. ADC readings are only valid for DC states and not for transients. When
host writes ADC_EN=0, the ADC stops immediately. If the host wants to exit ADC more gracefully, it is possible
to do either of the following:
1. Write ADC_RATE to one-shot, and the ADC will stop at the end of a complete cycle of conversions, or
2. Write all the DIS bits low, and the ADC will stop at the end of the current measurement.
When external sense resistor (RSNS) is placed and IBATADC is used, it is recommended to use 375-kHz
switching frequency.
9.3.10 Device Modes and Protection Status
表9-5 shows the features and modes of the device depending on the conditions of the device.
表9-5. Device Modes and Protection Status
STATE
BATTERY ONLY VAC1/
VAC2/ VBUS NOT
PRESENT
INPUT PRESENT
INPUT PRESENT
INPUT PRESENT
FUNCTIONS AVAILABLE
DURING SOFTSTART
TIMER
AFTER SOFTSTART
TIMER
CHARGE DISABLED
I2C allowed
ADC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACDRV gate drive
VACOVP
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表9-5. Device Modes and Protection Status (continued)
STATE
BATTERY ONLY VAC1/
VAC2/ VBUS NOT
PRESENT
INPUT PRESENT
INPUT PRESENT
INPUT PRESENT
FUNCTIONS AVAILABLE
DURING SOFTSTART
TIMER
AFTER SOFTSTART
TIMER
CHARGE DISABLED
TDIE_ALM
TDIE_TFL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BUSOVP_ALM
BUSOCP_ALM
BATOVP_ALM
BATOCP_ALM
BATUCP_ALM
VOUTOVP
TSBUS_FLT
TSBAT_ FLT
BUSOVP
X
X
X
X
X
BATOVP
BATOCP
BUSOCP
BUSUCP
BUSRCP
X
Tripping any of these protections causes QB to be off and converter stops switching. Masking the fault or alarm
does NOT disable the protection, but only keeps an INT from being triggered by the event. Disabling the fault or
alarm protection other than BUSUCP holds that STAT and FLAG bits in reset, and also prevents an interrupt
from occurring. Disable BUSUCP protection still sets STAT and FLAT bits and sends interrupt to alert host but
keeps converter running when triggered.
When any OVP, OCP, RCP or overtemperature fault event is triggered, the CHG_EN bit is set to ‘0’to disable
charging, and the charging start-up sequence must be followed to begin charging again.
9.3.10.1 Input Overvoltage, Overcurrent, Undercurrent, Reverse-Current and Short-Circuit Protection
Input overvoltage protection with external single or back-to-back N-channel FET(s): The device integrates
the functionality of an input overvoltage protector. With external single or back-to-back N-channel FET(s), the
device blocks high input voltage exceeding VACOVP threshold (VAC1OVP or VAC2OVP). This eliminates the
need for a separate OVP device to protect the overall system. The integrated VACOVP feature has a response
time of tVACOVP (the actual time to turn off external FET(s) will be longer and depends upon the FET(s) gate
capacitance). The VAC1OVP and VAC2OVP setting is adjustable in the VAC control register. The part allows the
user to have different VAC1OVP and VAC2OVP settings. Always put the high VACOVP threshold input to VAC1.
When VAC1OVP or VAC2OVP is tripped, corresponding ACDRV is turned off and VAC1OVP_STAT or
VAC2OVP_STAT and VAC1OVP_FLAG or VAC2OVP_FLAG is set to ‘1’, and INT is asserted low to alert the
host (unless masked by VAC1OVP_MASK or VAC2OVP_MASK). When VAC2OVP is triggered, the device
sends multiple interrupts when the fault persists. Use VAC1 as input unless both VAC1 and VAC2 are needed.
Input overvoltage protection (BUSOVP): The BUSOVP threshold is adjustable in the BUSOVP register. When
BUSOVP is tripped, switched cap or bypass mode is disabled and CHG_EN is set to ‘0’. BUSOVP_STAT and
BUSOVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSOVP_MASK).
The start-up sequence must be followed to resume charging.
Input overcurrent protection (BUSOCP): Input overcurrent protection monitors the current flow into VBUS.
The overcurrent protection threshold is adjustable in the BUSOCP register. When BUSOCP is tripped, Switched
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Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSOCP_STAT and BUSOCP_FLAG is set to
‘1’, and INT is asserted low to alert the host (unless masked by BUSOCP_MASK). The start-up sequence
must be followed to resume charging.
Input undercurrent protection (BUSUCP): BUS undercurrent protection (UCP) is implemented to detect
adapter unplug. Set BUSUCP =1 (REG05[6]) before enable charge. When BUSUCP is enabled
(BUSUCP_DIS=0), if the current is below BUSUCP after soft start timer (programmable in SS_TIMEOUT[2:0])
expires, Switched Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSUCP_STAT and
BUSUCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSUCP_MASK).
The start-up sequence must be followed to resume charging. The deglitch time for BUSUCP is programmable in
IBUSUCP_FALL_DG_SET[1:0] register. Please note that BUSUCP deglitch time needs to be set shorter than
soft start timer in order for BUSUCP to be effective.
When BUSUCP is disabled (BUSUCP_DIS=1), if the current is below BUSUCP after soft-start timer expires,
CHG_EN is not set to ‘0’, BUSUCP_STAT and BUSUCP_FLAG is set to ‘1’, and INT is asserted low to
alert the host (unless masked by BUSUCP_MASK). The host can determine if charge needs to be stopped in
this case.
Input reverse-current protection (BUSRCP): The device monitors the current flow from VBUS to VBAT to
ensure there is no reverse current (current flow from VBAT to VBUS). In an event that a reverse current flow is
detected when BUSRCP_DIS is set to ‘0’, the Switched Cap or Bypass is disabled and CHG_EN is set to
‘0’. The start-up sequence must be followed to resume charging. To disable BUSRCP, set REG05[1:0] to '00'
and then set BUSRCP_DIS=1.
RCP is always active when converter is switching and BUSRCP_DIS is set to '0'. When RCP is tripped,
BUSRCP_STAT and BUSRCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked
by BUSRCP_MASK).
Input overvoltage and overcurrent protection alarm (BUSOVP_ALM and BUSOCP_ALM): In addition to
input overvoltage and overcurrent, the device also integrates alarm function BUSOVP_ALM and BUSOCP_ALM.
When alarm is triggered, the corresponding STAT and FLAG bit is set to ‘1’ and INT is asserted low to alert
the host (unless it is masked by the MASK bit). However, CHG_EN is not cleared and host can reduce input
voltage or input current to prevent VBUS reaching VBUSOVP threshold or IBUS reaching IBUSOCP threshold.
VBUS_ERRHI: the device monitors VBUS to VOUT voltage ratio. If VBUS/VOUT is greater than
VBUS_ERRHI_RISING threshold, the converter does not switch but CHG_EN is kept at '1'. The converter
automatically starts switching when the VBUS/VOUT drops below VBUS_ERRHI_FALLING threshold.
9.3.10.2 Battery Overvoltage and Overcurrent Protection
BATOVP and BATOVP_ALM: The device integrates both overcurrent and overvoltage protection for the battery.
The device monitors the battery voltage on BATP and BATN_SRP. In order to reduce the possibility of battery
terminal shorts during manufacturing, 100-Ω series resistors on BATP is required. If external sense resistor is
not used, place 100-Ω series resistors on BATN as well. The device is intended to be operated within the
window formed by the BATOVP and BATOVP_ALM. When the BATOVP_ALM is reached, an interrupt is sent to
the host to reduce the charge current and thereby not reaching the BATOVP threshold. If BATOVP is reached,
the switched cap or bypass is disabled and CHG_EN is set to ‘0’, and the start-up sequence must be
followed to resume charging. At the same time, BATOVP_STAT and BATOVP_FLAG are set to ‘1’, and INT is
asserted low to alert the host (unless masked by BATOVP_MASK). BATOVP and BATOVP_ALM is disabled
when BATOVP_DIS and BATOVP_ALM_DIS is set to ‘1’.
BATOCP and BATOCP_ALM: The device monitors current through the battery by monitoring the voltage across
the external series battery sense resistor. The differential voltage of this sense resistor is measured on
BATN_SRP and SRN_SYNCIN. The device is intended to be operated within the window formed by the
BATOCP and BATOCP_ALM. When the BATOCP_ALM is reached, an interrupt is sent to the host to reduce the
charge current from reaching the BATOCP threshold. If BATOCP is reached, the Switched Cap or Bypass is
disabled after a deglitch time of tBATOCP and CHG_EN is set to ‘0’, and the start-up sequence must be
followed to resume charging. At the same time, BATOCP_STAT and BATOCP_FLAG are set to ‘1’, and INT
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is asserted low to alert the host (unless masked by BATOCP_MASK). BATOCP and BATOCP_ALM is disabled
when BATOCP_DIS and BATOCP_ALM_DIS is set to ‘1’.
VOUTOVP: The device also monitors output voltage between VOUT and ground in case of battery removal to
protect the system. If VOUTOVP is reached and VOUTOVP_DIS=0, the Switched Cap or Bypass is disabled and
CHG_EN is set to ‘0’, and the start-up sequence must be followed to resume charging. At the same time,
VOUTOVP_STAT and VOUTOVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless
masked by VOUTOVP_MASK). If VOUTOVP_DIS =1, the protection is disabled.
9.3.10.3 IC Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
The device has three temperature sensing mechanisms to protect the device and system during charging:
1. TSBUS for monitoring the cable connector temperature
2. TSBAT for monitoring the battery temperature
3. TDIE for monitoring the internal junction temperature of the device
The TSBUS and TSBAT both rely on a resistor divider that has an external pullup voltage to REGN. Place a
negative coefficient thermistor (NTC) in parallel to the low-side resistor. A fault on the TSBUS and TSBAT pin is
triggered on the falling edge of the voltage threshold, signifying a “hot”temperature. The threshold is adjusted
using the TSBUS_FLT and TSBAT_FLT registers.
The typical TS resistor network on TSBAT_SYNCOUT is illustrated in 图 9-8. The resistor network on TSBUS is
the same.
REGN
TSBAT_SYNCOUT
BQ25960
图9-8. TSBAT_SYNCOUT Resistor Network
The RLO and RHI resistors should be chosen depending on the NTC used. If a 10-kΩ NTC is used, use 10-kΩ
resistors for RLO and RHI. If a 100-kΩ NTC is used, use 100-kΩ resistors for RLO and RHI. The ratio of VTS/
REGN can be from 0% to 50%, and the voltage at the TS pin is determined by the following equation.
1
1
1
406% 4.1
(
+
)
65$75 KN 65$#6 (8) =
× 84')0
1
4*+ +
1
1
(
+
)
(1)
The percentage of the TS pin voltage is determined by the following equation.
1
1
1
406% 4.1
(
+
)
65$75 KN 65$#6 (%) =
1
4*+ +
1
1
406% 4.1
(
+
)
(2)
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Additionally, the device measures internal junction temperature, with adjustable threshold TDIE_FLT in
TDIE_FLT register.
If the TSBUS_FLT, TSBAT_FLT, and TDIE_FLT thresholds are reached, the Switched Cap or Bypass Mode is
disabled and CHG_EN is set to ‘0’, and the start-up sequence must be followed to resume charging. The
corresponding STAT and FLAG bit is set to ‘1’ unless it is masked by the MASK bit. If TSBUS, TSBAT, or
TDIE protections are not used, the functions can be disabled in the register by setting the TSBUS_FLT_DIS,
TSBAT_FLT_DIS, or TDIE_FLT_DIS bit to ‘1’.
TSBUS_TSBAT_ALM_STAT and FLAG is set to ‘1’ unless it is masked by corresponding mask bit when one
of the following conditions is met: 1) TSBUS is within 5% of TSBUS_FLT threshold or 2) TSBAT is within of
TSBAT_FLT. If the TSBUS_FLT or TSBAT_FLT is disabled, it will not trigger a TSBUS_TSBAT_ALM interrupt.
Using the TDIE_ALM register, an alarm can be set to notify the host when the device die temperature exceeds a
threshold. The TDIE_ALM_STAT and TDIE_ALM_FLAG bit is set to ‘1 ’ unless it is masked by
TDIE_ALM_MASK bit. The device will not automatically stop switching when reaching the alarm threshold and
the host may decide on the steps to take to lower the temperature, such as reducing the charge current.
9.3.11 INT Pin, STAT, FLAG, and MASK Registers
The INT pin is an open drain pin that needs to be pulled up to a voltage with a pullup resistor. INT is normally
high and will assert low for tINT when the device needs to alert the host of a fault or status change.
The fields in the STAT registers show the current status of the device, and are updated as the status changes.
The fields in the FLAG registers indicate that the event has occurred, and the field is cleared when read. If the
event persists after the FLAG register has been read and cleared, another INT signal is not sent to prevent host
keep receiving interrupts. The fields in the MASK registers allow the user to disable the interrupt on the INT pin,
but the STAT and FLAG registers are still updated even though INT is not pulled low.
9.3.12 Dual Charger Operation Using Primary and Secondary Modes
For higher power systems, it is possible to use two devices in dual charger configuration. This allows each
device to operate at lower charging current with higher efficiency compared with single device operating at the
same total charging current. The CDRVL_ADDRMS pin is used to configure the functionality of the device as
Standalone, Primary or Secondary during POR. Refer to 节 9.3.13 for proper setting. When configured as a
primary, the TSBAT_SYNCOUT pin functions as SYNCOUT, and the SRN_SYNCIN pin functions as SRN. When
configured as a Secondary, the TSBAT_SYNCOUT pin functions as TSBAT, and the SRN_SYNCIN pin functions
as SYNCIN. ACDRV1 and ACDRV2 are controlled by the primary, and ACDRV1 and ACDRV2 on the secondary
should be grounded. Pull the SYNCIN/SYNCOUT pins to REGN on the primary BQ25960 through a 1-kΩ
resistor. The maximum switching frequency in primary and secondary mode is 500 kHz.
The dual charger can operate in Primary and Secondary Mode in Bypass Mode as well. In both Bypass and
Switched Cap Mode, the current distribution between the two devices depends on loop impedance and the
chargers do not balance it. In order balance the current, the board layout needs to be as symmetrical as
possible.
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System
SYS
BAT
VBUS
GND
Main Charger
RX
ACDRV2 VAC2
VAC1
ACDRV2 VAC2
BQ25960_Primary
BQ25960_Secondary
ACDRV1
VBUS
Adapter
VBUS
Host
SDA/
Digital Core
SCL
ACDRV1
SDA/
SCL
Digital Core
QB
QB
VAC1
PMID
PMID
CFH1
CFH1
VOUT
VOUT
SC Phase
#1
SC Phase
#1
CFLY1
CFLY2
CFLY1
CFLY2
CFL1
CFH2
CFL2
CFL1
CFH2
PMID
PMID
BATP
BATP
SC Phase
#2
SC Phase
#2
CFL2
BATN_SRP
BATN_SRP
CDRVH
CDRVH
Protection
16 bit ADC
16 bit ADC
Protection
CDRVL_
ADDRMS
CDRVL_
ADDRMS
SRN_SYNCIN
TSBAT_SYNCOUT
REGN
SRN_SYNCIN
1kΩ
图9-9. Parallel Operation of BQ25960
9.3.13 CDRVH and CDRVL_ADDRMS Functions
The device requires a cap between the CDRVH and CDRVL_ADDRMS pin to operate correctly. The
CDRVL_ADDRMS pin also allows setting the default I2C address and device operation mode. Pull to GND with a
resistor for the desired setting shown in 表 9-6. The surface mount resistor with ±1% tolerance is recommended.
After POR, the host can read back the device's configuration from MS register (REG12[1:0]).
表9-6. I2C Address and Mode Selection
I2C ADDRESS
CONFIGURATION
Standalone
RADDRMS (kΩ)
>75.0
0x65
6.19
0x67
Standalone
8.06
10.5
0x66
Dual charger (Secondary)
0x66
0x66
0x67
Dual charger (Primary)
14.0
18.2
Standalone
Dual charger (Secondary)
27.4
0x65
Dual charger (Primary)
9.4 Programming
The device uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial
interface developed by NXP (formerly Philips Semiconductor, see I2C BUS Specification, Version 5, October
2012). The BUS consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the BUS is
idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C BUS through
open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal processor,
controls the BUS. The master is responsible for generating the SCL signal and device addresses. The master
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also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives
and/or transmits data on the BUS under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C BUS™
Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery
management solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. The I2C circuitry is powered from the battery in active battery mode. The
battery voltage must stay above VBATUVLO when no VIN is present to maintain proper operation.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is determined
by the ADDR pin on the device.
9.4.1 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in the figure below. All I2C-compatible devices
should recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
图9-10. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see 图 9-11). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see 图 9-12) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
图9-11. Bit Transfer on the Serial Interface
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Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
8
SCL From
Master
9
1
2
Clock Pulse for
Acknowledgement
START
Condition
图9-12. Acknowledge on the I2C BUS
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see 图 9-13). This releases the BUS and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the BUS is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section will result in 0xFFh being read out.
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
or
P
ACK
ACK
Sr
图9-13. BUS Protocol
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9.5 Register Maps
9.5.1 I2C Registers
表 9-7 lists the I2C registers. All register offset addresses not listed in 表 9-7 should be considered as reserved
locations and the register contents should not be modified. All register bits marked 'RESERVED' in Field column
should not be modified.
表9-7. I2C Registers
Offset
0h
Acronym
Register Name
Section
Go
REG00_BATOVP
BATOVP
1h
REG01_BATOVP_ALM
REG02_BATOCP
BATOVP_ALM
BATOCP
Go
2h
Go
3h
REG03_BATOCP_ALM
REG04_BATUCP_ALM
REG05_CHARGER_CONTROL 1
REG06_BUSOVP
BATOCP_ALM
BATUCP_ALM
CHARGER_CONTROL 1
BUSOVP
Go
4h
Go
5h
Go
6h
Go
7h
REG07_BUSOVP_ALM
REG08_BUSOCP
BUSOVP_ALM
BUSOCP
Go
8h
Go
9h
REG09_BUSOCP_ALM
Go
BUSOCP_ALM
Ah
Bh
REG0A_TEMP_CONTROL
REG0B_TDIE_ALM
REG0C_TSBUS_FLT
REG0D_TSBAT_FLT
REG0E_VAC_CONTROL
REG0F_CHARGER_CONTROL 2
REG10_CHARGER_CONTROL 3
REG11_CHARGER_CONTROL 4
REG12_CHARGER_CONTROL 5
REG13_STAT 1
TEMP CONTROL
TDIE_ALM
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Ch
TSBUS_FLT
TSBAT_FLT
VAC CONTROL
CHARGER CONTROL 2
CHARGER CONTROL 3
CHARGER CONTROL 4
CHARGER CONTROL 5
STAT 1
Dh
Eh
Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
27h
REG14_STAT 2
STAT 2
REG15_STAT 3
STAT 3
REG16_STAT 4
STAT 4
REG17_STAT 5
STAT 5
REG18_FLAG 1
FLAG 1
REG19_FLAG 2
FLAG 2
REG1A_FLAG 3
FLAG 3
REG1B_FLAG 4
FLAG 4
REG1C_FLAG 5
FLAG 5
REG1D_MASK 1
MASK 1
REG1E_MASK 2
MASK 2
REG1F_MASK 3
MASK 3
REG20_MASK 4
MASK 4
REG21_MASK 5
MASK 5
REG22_DEVICE_INFO
REG23_ADC_CONTROL 1
REG24_ADC_CONTROL 2
REG25_IBUS_ADC
REG27_VBUS_ADC
DEVICE INFO
ADC_CONTROL 1
ADC_CONTROL 2
IBUS_ADC
VBUS_ADC
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表9-7. I2C Registers (continued)
Register Name
VAC1_ADC
Offset
29h
Acronym
Section
Go
REG29_VAC1_ADC
REG2B_VAC2_ADC
REG2D_VOUT_ADC
REG2F_VBAT_ADC
REG31_IBAT_ADC
REG33_TSBUS_ADC
REG35_TSBAT_ADC
REG37_TDIE_ADC
2Bh
2Dh
2Fh
31h
VAC2_ADC
Go
VOUT_ADC
Go
VBAT_ADC
Go
IBAT_ADC
Go
33h
TSBUS_ADC
Go
35h
TSBAT_ADC
Go
37h
TDIE_ADC
Go
Complex bit access types are encoded to fit into small table cells. 表 9-8 shows the codes that are used for
access types in this section.
表9-8. I2C Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
9.5.1.1 REG00_BATOVP Register (Offset = 0h) [reset = 5Ah]
REG00_BATOVP is shown in 表9-9
Return to the Summary Table.
BATOVP
表9-9. REG00_BATOVP Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATOVP_DIS
R/W
0h
Reset by: Disable BATOVP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BATOVP_6:0
R/W
5Ah
Reset by: Battery Overvoltage Setting. When the battery voltage reaches
REG_RST the programmed threshold, QB and switching FETs are turned
off and CHG_EN is set to '0'. The host controller should
monitor the bus voltage to ensure that the adapter keeps the
voltage under the BATOVP threshold for proper operation.
Type : R/W
POR: 4390 mV (5Ah)
Range : 3491 mV - 4759 mV
Fixed Offset : 3491 mV
Bit Step Size : 9.985 mV
9.5.1.2 REG01_BATOVP_ALM Register (Offset = 1h) [reset = 46h]
REG01_BATOVP_ALM is shown in 表9-10.
Return to the Summary Table.
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BATOVP_ALM
表9-10. REG01_BATOVP_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATOVP_ALM_DIS
R/W
0h
Reset by: Disable BATOVP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BATOVP_ALM_6:0
R/W
46h
Reset by: When battery voltage goes above the programmed threshold,
REG_RST an INT is sent.
The BATOVP_ALM should be set lower than BATOVP and the
host controller should monitor the battery voltage to ensure
that the adapter keeps the voltage under BATOVP threshold
for proper operation.
Type : R/W
POR: 4200 mV (46h)
Range : 3500 mV - 4770 mV
Fixed Offset : 3500 mV
Bit Step Size : 10 mV
9.5.1.3 REG02_BATOCP Register (Offset = 2h) [reset = 47h]
REG02_BATOCP is shown in 表9-11.
Return to the Summary Table.
BATOCP
表9-11. REG02_BATOCP Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATOCP_DIS
R/W
0h
Reset by: Disable BATOCP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BATOCP_6:0
R/W
47h
Reset by: Battery Overcurrent Protection Setting. When battery current
REG_RST reaches the programmed threshold, the QB and switching
FETs are disabled and CHG_EN is set to '0'. The host
controller should monitor the battery current to ensure that the
adapter keeps the current under the threshold for proper
operation.
Type : R/W
POR: 7277.5 mA (47h)
Range : 2050 mA - 8712.5 mA
Fixed Offset : 0 mA
Bit Step Size : 102.5 mA
9.5.1.4 REG03_BATOCP_ALM Register (Offset = 3h) [reset = 46h]
REG03_BATOCP_ALM is shown in 表9-12.
Return to the Summary Table.
BATOCP_ALM
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表9-12. REG03_BATOCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATOCP_ALM_DIS
R/W
0h
Reset by: Disable BATOCP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BATOCP_ALM_6:0
R/W
46h
Reset by: Battery Overcurrent Alarm Setting. When battery current
REG_RST reaches the programmed threshold, an INT is sent.
The BATOCP_ALM should be set lower than BATOCP and the
host controller should monitor the battery current to ensure
that the adapter keeps the current under BATOCP threshold
for proper operation.
Type : R/W
POR: 7000 mA (46h)
Range : 0 mA - 12700 mA
Fixed Offset : 0 mA
Bit Step Size : 100 mA
9.5.1.5 REG04_BATUCP_ALM (Offset = 4h) [reset = 28h]
REG04_BATUCP_ALM is shown in 表9-13.
Return to the Summary Table.
BATUCP_ALM
表9-13. REG04_BATUCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATUCP_ALM_DIS
R/W
0h
Reset by: Disable BATUCP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BATUCP_ALM_6:0
R/W
28h
Reset by: Battery Undercurrent Alarm setting. When battery current falls
REG_RST below the programmed threshold, an INT is sent. The host
controller should monitor the battery current to determine
when to disable the device and hand over charging to the
main charger.
Type : R/W
POR: 2000 mA (28h)
Range : 0 mA - 4500 mA
Fixed Offset : 0 mA
Bit Step Size : 50 mA
9.5.1.6 REG05_CHARGER_CONTROL 1 Register (Offset = 5h) [reset = 2h]
REG05_CHARGER_CONTRL 1 is shown in 表9-14.
Return to the Summary Table.
CHARGER_CONTROL 1
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表9-14. REG05_CHARGER_CONTROL 1 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BUSUCP_DIS
R/W
0h
Reset by: Disable BUSUCP
REG_RST Type : R/W
POR: 0b
0h = Enable, BUSUCP turns off QB and switching FETs,
BUSUCP_STAT and FLAG is set to '1', and INT is sent to host.
1h = Disable, BUSUCP does not turn off QB or switching FETs,
but BUSUCP_STAT and FLAG is set to '1', and INT is sent to
host.
6
BUSUCP
R/W
0h
Reset by: BUSUCP Setting. If input current is below BUSUCP threshold
REG_RST after soft start timer expires, the QB and switching FETs are
turned off and CHG_EN is set to '0' and INT is sent if
BUSUCP_DIS=0. If BUSUCP_DIS=1, INT is sent to host but
converter keeps running. Change this bit to '1' before
CHG_EN is set to '1' in order for BUSUCP to be effective.
Type : R/W
POR: 0b
0h = RESERVED
1h = 250 mA
5
4
BUSRCP_DIS
BUSRCP
R/W
R/W
0h
0h
Reset by:
REG_RST
Disable BUSRCP
Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: BUSRCP Setting, if IBUS is below BUSRCP threshold, the QB
REG_RST and switching FETs are turned off and CHG_EN is set to '0'
and INT is sent. Keep this bit set to '0' in order for BUSRCP to
be effective.
Type : R/W
POR: 0b
0h = 300 mA
1h = RESERVED
3
2
CHG_CONFIG_1
R/W
R/W
0h
0h
Reset by: Charger Configuration 1. Set this bit to '1' before CHG_EN is
REG_RST set to '1'.
Type : R/W
POR: 0h
VBUS_ERRHI_DIS
Reset by: Disable VBUS_ERRHI
REG_RST Type : R/W
POR: 0b
0h = Enable, converter does not switching, but QB is turned on
when device is in VBUS_ERRHI
1h = Disable, both converter and QB is turned on when device
is in VBUS_ERRHI
1-0
RESERVED
R/W
2h
Reset by: RESERVED
REG_RST Type : R/W
POR: 10b
9.5.1.7 REG06_BUSOVP Register (Offset = 6h) [reset = 26h]
REG06_BUSOVP is shown in 表9-15.
Return to the Summary Table.
BUSOVP
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表9-15. REG06_BUSOVP Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BUS_PD_EN
R/W
0h
Reset by: VBUS Pulldown Resistor Control
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable
6-0
BUSOVP_6:0
R/W
26h
Reset by: Bus Overvoltage Setting. When the bus voltage reaches the
REG_RST programmed threshold, QB and switching FETs are turned off
and CHG_EN is set to '0'. The host controller should monitor
the bus voltage to ensure that the adapter keeps the voltage
under the BUSOVP threshold for proper operation.
Switched cap mode:
Type : R/W
POR: 8900 mV (26h)
Range : 7000 mV - 12750 mV
Fixed Offset : 7000 mV
Bit Step Size : 50 mV
Bypass Mode:
Type : R/W
POR: 4450 mV (26h)
Range : 3500 mV - 6500 mV
Fixed Offset : 3500 mV
Bit Step Size : 25 mV
9.5.1.8 REG07_BUSOVP_ALM Register (Offset = 7h) [reset = 22h]
REG07_BUSOVP_ALM is shown in 表9-16.
Return to the Summary Table.
BUSOVP_ALM
表9-16. REG07_BUSOVP_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BUSOVP_ALM_DIS
R/W
0h
Reset by: Disable BUSOVP_ALM
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6-0
BUSOVP_ALM_6:0
R/W
22h
Reset by: Bus Overvoltage Alarm Setting. When the bus voltage reaches
REG_RST the programmed threshold, an INT is sent. The host controller
should monitor the bus voltage to ensure that the adapter
keeps the voltage under the BUSOVP threshold for proper
operation.
Switched Cap Mode:
Type : R/W
POR: 8700 mV (22h)
Range : 7000 mV - 13350 mV
Fixed Offset : 7000 mV
Bit Step Size : 50 mV
Bypass Mode:
Type : R/W
POR: 4350 mV (22h)
Range : 3500 mV - 6675 mV
Fixed Offset : 3500 mV
Bit Step Size : 25 mV
9.5.1.9 REG08_BUSOCP Register (Offset = 8h) [reset = Bh]
REG08_BUSOCP is shown in 表9-17.
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Return to the Summary Table.
BUSOCP
表9-17. REG08_BUSOCP Register Field Descriptions
Bit
7-5
4-0
Field
Type
Reset
Note
Description
RESERVED
BUSOCP_4:0
R
0h
RESERVED
R/W
Bh
Reset by: BUS Overcurrent Protection Setting. When the bus current
REG_RST reaches the programmed threshold, the output is disabled.
The host controller should monitor the bus current to ensure
that the adapter keeps the current under this threshold for
proper operation.
Type : R/W
Switched Cap Mode:
POR: 3816 mA (Bh)
Range: 1017.5 mA - 4579 mA
Fixed Offset : 1017.5 mA
Bit Step Size : 254 mA
Bypass Mode:
POR: 3928 mA (Bh)
Range: 1047.5 mA - 6809 mA
Fixed Offset : 1047.5 mA
Bit Step Size : 262 mA
9.5.1.10 REG09_BUSOCP_ALM Register (Offset = 9h) [reset = Ch]
REG09_BUSOCP_ALM is shown in 表9-18.
Return to the Summary Table.
BUSOCP_ALM
表9-18. REG09_BUSOCP_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
R/W
0h
Reset by: Disable BUSOCP_ALM
BUSOCP_ALM_DIS
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
RESERVED
6-5
4-0
R
0h
Ah
RESERVED
BUSOCP_ALM_4:0
R/W
Reset by: Bus Overvoltage Alarm Setting. When the bus current reaches
REG_RST the programmed threshold, an INT is sent. The host controller
should monitor the bus current to ensure that the adapter
keeps the current under the BUSOCP threshold for proper
operation.
Type : R/W
POR: 3500 mA (Ah)
Range : 1000 mA - 8750 mA
Fixed Offset : 1000 mA
Bit Step Size : 250 mA
9.5.1.11 REG0A_TEMP_CONTROL Register (Offset = Ah) [reset = 60h]
REG0A_TEMP_CONTROL is shown in 表9-19.
Return to the Summary Table.
TEMP_CONTROL
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表9-19. REG0A_TEMP_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
TDIE_FLT_DIS
R/W
0h
Reset by: Disable TDIE Overtemperature Protection
REG_RST Type : R/W
POR: 0b
0h = TDIE_FLT enable
1h = TDIE_FLT disable
6-5
TDIE_FLT_1:0
R/W
3h
Reset by: TDIE Overtemperature Setting. When the junction temperature
REG_RST reaches the programmed threshold, the QB and switching
FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 11b
0h = 80C
1h = 100C
2h = 120C
3h = 140C
4
3
TDIE_ALM_DIS
TSBUS_FLT_DIS
TSBAT_FLT_DIS
RESERVED
R/W
R/W
R/W
R
0h
0h
0h
0h
Reset by: Disable TDIE Overtemperature Alarm
REG_RST Type : R/W
POR: 0b
0h = TDIE_ALM enable
1h = TDIE_ALM disable
Reset by: Disable TSBUS_FLT
REG_RST Type : R/W
POR: 0b
0h = TSBUS_FLT enable
1h = TSBUS_FLT disable
2
Reset by: Disable TSBAT_FLT
REG_RST Type : R/W
POR: 0b
0h = TSBAT_FLT enable
1h = TSBAT_FLT disable
1-0
RESERVED
Type : R
POR: 00b
9.5.1.12 REG0B_TDIE_ALM Register (Offset = Bh) [reset = C8h]
REG0B_TDIE_ALM is shown in 表9-20.
Return to the Summary Table.
TDIE_ALM
表9-20. REG0B_TDIE_ALM Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7-0
TDIE_ALM_7:0
R/W
C8h
Reset by: Die Overtemperature Alarm Setting. When the junction
REG_RST temperature reaches the programmed threshold, an INT is
sent.
Type : R/W
POR: 125°C (C8h)
Range : 25°C - 150°C
Fixed Offset : 25°C
Bit Step Size : 0.5°C
9.5.1.13 REG0C_TSBUS_FLT Register (Offset = Ch) [reset = 15h]
REG0C_TSBUS_FLT is shown in 表9-21.
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Return to the Summary Table.
TSBUS_FLT
表9-21. REG0C_TSBUS_FLT Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7-0
TSBUS_FLT_7:0
R/W
15h
Reset by: TSBUS Percentage Fault Threshold. When the TSBUS/REGN
REG_RST ratio drops below the programmed threshold, the QB and
switching FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 4.10151% (15h)
Range : 0% - 49.8041%
Fixed Offset : 0%
Bit Step Size : 0.19531%
9.5.1.14 REG0D_TSBAT_FLT Register (Offset = Dh) [reset = 15h]
REG0D_TSBAT_FLG is shown in 表9-22.
Return to the Summary Table.
TSBAT_FLG
表9-22. REG0D_TSBAT_FLT Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7-0
TSBAT_FLT_7:0
R/W
15h
Reset by: TSBAT Percentage Fault Threshold. When the TSBAT/REGN
REG_RST ratio drops below the programmed threshold, the QB and
switching FETs are turned off and CHG_EN is set to '0'.
Type : R/W
POR: 4.10151% (15h)
Range : 0% - 49.8041%
Fixed Offset : 0%
Bit Step Size : 0.19531%
9.5.1.15 REG0E_VAC_CONTROL Register (Offset = Eh) [reset = 0h]
REG0E_VAC_CONTROL is shown in 表9-23.
Return to the Summary Table.
VAC_CONTROL
表9-23. REG0E_VAC_CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7-5
VAC1OVP_2:0
R/W
0h
Reset by: VAC1OVP Setting. When VAC1 voltage reaches the
REG_RST programmed threshold, ACDRV1 is turned off.
Type : R/W
POR: 000b
0h = 6.5 V
1h = 10.5 V
2h = 12 V
3h = 14 V
4h = 16 V
5h = 18 V
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表9-23. REG0E_VAC_CONTROL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
4-2
VAC2OVP_2:0
R/W
0h
Reset by: VAC2OVP Setting. When VAC2 voltage reaches the
REG_RST programmed threshold, ACDRV2 is turned off.
Type : R/W
POR: 000b
0h = 6.5 V
1h = 10.5 V
2h = 12 V
3h = 14 V
4h = 16 V
5h = 18 V
1
0
VAC1_PD_EN
VAC2_PD_EN
R/W
R/W
0h
0h
Reset by: Enable VAC1 Pulldown Resistor
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable
Reset by: Enable VAC2 Pulldown Resistor
REG_RST Type : R/W
POR: 0b
0h = Disable
1h = Enable
9.5.1.16 REG0F_CHARGER_CONTROL 2 Register (Offset = Fh) [reset = 0h]
REG0F_CHARGER_CONTROL 2 is shown in 表9-24.
Return to the Summary Table.
CHARGER CONTROL 2
表9-24. REG0F_CHARGER_CONTROL 2 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
REG_RST
R/W
0h
Reset by:
Register Reset. Reset registers to default values and reset
REG_RST
timer. This bit automatically goes back to '0' after reset.
Type : R/W
POR: 0b
0h = Not reset register
1h = Reset register
6
EN_HIZ
R/W
0h
Reset by:
REG_RST
Enable HIZ Mode. When device is in HIZ mode, converter
stops switching, ADC stops converting, ACDRV is turned off
and the REGN LDO is forced off.
Type : R/W
POR: 0b
0h = Disable HIZ mode
1h = Enable HIZ mode
5
4
EN_OTG
CHG_EN
R/W
R/W
0h
0h
Reset by:
WATCHDOG Type : R/W
REG_RST
Power Path Control During the OTG and Reverse TX Mode
POR: 0b
0h = Don't allow host to control ACDRV(s)
1h = Allow host to control ACDRV(s)
Reset by:
Charge Enable
WATCHDOG Type : R/W
REG_RST
POR: 0b
0h = Disable charge
1h = Enable charge
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表9-24. REG0F_CHARGER_CONTROL 2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
3
EN_BYPASS
R/W
0h
Reset by:
Enable Bypass Mode
WATCHDOG Type : R/W
REG_RST
POR: 0b
0h = Disable Bypass Mode
1h = Enable Bypass Mode
2
1
0
DIS_ACDRV_BOTH
R/W
R/W
R/W
0h
0h
0h
Disable Both ACDRV. When this bit is set, the device forces
both ACDRV off. It is not reset by the REG_RST or the
WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV1 and ACDRV2 can be turned on
1h = ACDRV1 and ACDRV2 are forced off
ACDRV1_STAT
ACDRV2_STAT
External ACFET1-RBFET1 Gate Driver Status. For dual input
with two sets ACFET-RBFET, this bit can be used to swap
input. It is not reset by the REG_RST or the WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV1 is OFF
1h = ACDRV1 is ON
External ACFET2-RBFET2 Gate Driver Status. For dual input
with two sets ACFET-RBFET, this bit can be used to swap
input. It is not reset by the REG_RST or the WATCHDOG.
Type : R/W
POR: 0b
0h = ACDRV2 is OFF
1h = ACDRV2 is ON
9.5.1.17 REG10_CHARGER_CONTROL 3 Register (Offset = 10h) [reset = 83h]
REG10_CHARGER_CONTROL 3 is shown in 表9-25.
Return to the Summary Table.
CHARGER CONTROL 3
表9-25. REG10_CHARGER_CONTROL 3 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7-5
FSW_SET_2:0
R/W
4h
Set Switching Frequency in Switched Cap Mode. It is not reset
by the REG_RST or the WATCHDOG.
Type : R/W
POR: 100b
0h = 187.5 kHz
1h = 250 kHz
2h = 300 kHz
3h = 375 kHz
4h = 500 kHz
5h = 750 kHz
The maximum switching frequency is 500 kHz in dual charger
configuration.
4-3
WATCHDOG_1:0
R/W
0h
Reset by: Watchdog Timer
REG_RST Type : R/W
POR: 00b
0h = 0.5 s
1h = 1 s
2h = 5 s
3h = 30 s
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表9-25. REG10_CHARGER_CONTROL 3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
2
WATCHDOG_DIS
R/W
0h
Reset by: Watchdog Timer Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
1-0
RESERVED
R
3h
RESERVED
9.5.1.18 REG11_CHARGER_CONTROL 4 Register (Offset = 11h) [reset = 71h]
REG11_CHARGER_CONTROL 4 is shown in 表9-26.
Return to the Summary Table.
CHARGER CONTROL 4
表9-26. REG11_CHARGER_CONTROL 4 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
RSNS
R/W
0h
Reset by: Battery Current Sense Resistor Value
REG_RST Type : R/W
POR: 0b
0h = 2 mΩ
1h = 5 mΩ
6-4
SS_TIMEOUT_2:0
R/W
7h
Soft Start Timeout to Check if Input Current is Above
BUSUCP Threshold. It is not reset by the REG_RST or
the WATCHDOG.
Type : R/W
POR: 111b
0h = 6.25 ms
1h = 12.5 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 400 ms
6h = 1.5 s
7h = 10 s
3-2
IBUSUCP_FALL_DG_SEL_1:0
R/W
0h
Reset by: BUSUCP Deglitch Timer
REG_RST Type : R/W
POR: 00b
0h = 0.01 ms
1h = 5 ms
2h = 50 ms
3h = 150 ms
1-0
RESERVED
R/W
1h
Reset by:
REG_RST
RESERVED
Type : R/W
POR: 1b
9.5.1.19 REG12_CHARGER_CONTROL 5 Register (Offset = 12h) [reset = 60h]
REG12_CHARGER_CONTROL 5 is shown in 表9-27.
Return to the Summary Table.
CHARGER CONTROL 5
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表9-27. REG12_CHARGER_CONTROL 5 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
VOUTOVP_DIS
R/W
0h
Reset by: Disable VOUTOVP
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: VOUTOVP Protection. When output voltage is above the
REG_RST programmed threshold, QB and switching FETs are turned off
6-5
VOUTOVP_1:0
R/W
3h
and CHG_EN is set to '0'.
Type : R/W
POR: 11b
0h = 4.7 V
1h = 4.8 V
2h = 4.9 V
3h = 5.0 V
4-3
FREQ_SHIFT_1:0
R/W
0h
Reset by: Adjust Switching Frequency
REG_RST Type : R/W
POR: 00b
0h = Nominal switching frequency set in REG10[7:5]
1h = Set switching frequency 10% higher than normal
2h = Set switching frequency 10% lower than normal
2
RESERVED
MS_1:0
R/W
R
0h
0h
Reset by:
REG_RST
RESERVED
Type : R/W
POR: 0b
1-0
Primary, Secondary, Standalone Operation
Type : R
POR: 00b
0h = Standalone
1h = Secondary
2h = Primary
9.5.1.20 REG13_STAT 1 Register (Offset = 13h) [reset = 0h]
REG13_STAT 1 is shown in 表9-28.
Return to the Summary Table.
STAT 1
表9-28. REG13_STAT 1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BATOVP_STAT
R
0h
BATOVP Status
Type : R
POR: 0b
0h = Not in BATOVP
1h = In BATOVP
6
5
BATOVP_ALM_STAT
VOUTOVP_STAT
R
R
0h
0h
BATOVP_ALM Status
Type : R
POR: 0b
0h = Not in BATOVP_ALM
1h = In BATOVP_ALM
VOUTOVP Status
Type : R
POR: 0b
0h = Not in VOUTOVP
1h = in VOUTOVP
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表9-28. REG13_STAT 1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
BATOCP_STAT
R
0h
BATOCP Status
Type : R
POR: 0b
0h = Not in BATOCP
1h = In BATOCP
3
2
1
0
BATOCP_ALM_STAT
R
R
R
R
0h
0h
0h
0h
BATOCP_ALM Status
Type : R
POR: 0b
0h = Not in BATOCP_ALM
1h = In BATOCP_ALM
BATUCP_ALM Status
Type : R
POR: 0b
0h = Not in BATUCP_ALM
1h = In BATUCP_ALM
BATUCP_ALM_STAT
BUSOVP_STAT
VBUSOVP Status
Type : R
POR: 0b
0h = Not in VBUS OVP
1h = In VBUS OVP
BUSOVP_ALM_STAT
BUSOVP_ALM Status
Type : R
POR: 0b
0h = Not in BUSOVP_ALM
1h = In BUSOVP_ALM
9.5.1.21 REG14_STAT 2 Register (Offset = 14h) [reset = 0h]
REG14_STAT 2 is shown in 表9-29.
Return to the Summary Table.
STAT 2
表9-29. REG14_STAT 2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUSOCP_STAT
R
0h
BUSOCP Status
Type : R
POR: 0b
0h = Not in BUSOCP
1h = In BUSOCP
6
5
4
BUSOCP_ALM_STAT
BUSUCP_STAT
R
R
R
0h
0h
0h
BUSOCP_ALM Status
Type : R
POR: 0b
0h = Not in BUSOCP_ALM
1h = In BUSOCP_ALM
BUSUCP Status
Type : R
POR: 0b
0h = Not in BUSUCP
1h = In BUSUCP
BUSRCP_STAT
BUSRCP Status
Type : R
POR: 0b
0h = Not in BUSRCP
1h = In BUSRCP
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表9-29. REG14_STAT 2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
R
0h
RESERVED
RESERVED
2
CFLY_SHORT_STAT
R
0h
CFLY Short Detection Status
Type : R
POR: 0b
0h = CFLY not shorted
1h = CFLY shorted
1-0
RESERVED
R
0h
RESERVED
9.5.1.22 REG15_STAT 3 Register (Offset = 15h) [reset = 0h]
REG15_STAT 3 is shown in 表9-30.
Return to the Summary Table.
STAT 3
表9-30. REG15_STAT 3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VAC1OVP_STAT
R
0h
VAC1 OVP Status
Type : R
POR: 0b
0h = Not in VAC1 OVP
1h = In VAC1 OVP
6
5
VAC2OVP_STAT
R
R
0h
0h
VAC2 OVP Status
Type : R
POR: 0b
0h = Not in VAC2 OVP
1h = In VAC2 OVP
VOUTPRESENT_STAT
VOUT Present Status
Type : R
POR: 0b
0h = VOUT not present
1h = VOUT present
4
3
2
1
VAC1PRESENT_STAT
VAC2PRESENT_STAT
VBUSPRESENT_STAT
ACRB1_CONFIG_STAT
R
R
R
R
0h
0h
0h
0h
VAC1 Present Status
Type : R
POR: 0b
0h = VAC1 not present
1h = VAC1 present
VAC2 Present Status
Type : R
POR: 0b
0h = VAC2 not present
1h = VAC2 present
VBUS Present Status
Type : R
POR: 0b
0h = VBUS not present
1h = VBUS present
ACFET1-RBFET1 Status
Type : R
POR: 0b
0h = ACFET1-RBFET1 is not placed
1h = ACFET1-RBFET1 is placed
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表9-30. REG15_STAT 3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
ACRB2_CONFIG_STAT
R
0h
ACFET2-RBFET2 Status
Type : R
POR: 0b
0h = ACFET2-RBFET2 is not placed
1h = ACFET2-RBFET2 is placed
9.5.1.23 REG16_STAT 4 Register (Offset = 16h) [reset = 0h]
REG16_STAT 4 is shown in 表9-31.
Return to the Summary Table.
STAT 4
表9-31. REG16_STAT 4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC_DONE_STAT
R
0h
ADC Conversion Status (in One-Shot Mode only)
Note: Always reads 0 in continuous mode
Type : R
POR: 0b
0h = Conversion not complete
1h = Conversion complete
6
5
SS_TIMEOUT_STAT
R
R
0h
0h
Soft-Start Timeout Status
Type : R
POR: 0b
0h = Device not in soft timeout
1h = Device in soft timeout
TSBUS_TSBAT_ALM_STAT
TSBUS and TSBAT ALM Status
Type : R
POR: 0b
0h = TSBUS or TSBAT threshold is NOT within 5% of the
TSBUS_FLT or TSBAT_FLT set threshold
1h = TSBUS or TSBAT threshold is within 5% of the
TSBUS_FLT or TSBAT_FLT set threshold
4
3
2
1
TSBUS_FLT_STAT
TSBAT_FLT_STAT
TDIE_FLT_STAT
TDIE_ALM_STAT
R
R
R
R
0h
0h
0h
0h
TSBUS_FLT Status
Type : R
POR: 0b
0h = Not in TSBUS_FLT
1h = In TSBUS_FLT
TSBAT_FLT Status
Type : R
POR: 0b
0h = Not in TSBAT_FLT
1h = In TSBAT_FLT
TDIE Fault Status
Type : R
POR: 0b
0h = Not in TDIE fault
1h = In TDIE fault
TDIE_ALM Status
Type : R
POR: 0b
0h = Not in TDIE_ALM
1h = In TDIE_ALM
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表9-31. REG16_STAT 4 Register Field Descriptions (continued)
Bit
Field
WD_STAT
Type
Reset
Description
0
R
0h
I2C Watch Dog Status
Type : R
POR: 0b
0h = Normal
1h = WD timer expired
9.5.1.24 REG17_STAT 5 Register (Offset = 17h) [reset = 0h]
REG17_STAT 5 is shown in 表9-32.
Return to the Summary Table.
STAT 5
表9-32. REG17_STAT 5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REGN_GOOD_STAT
R
0h
REGN_GOOD Status
Type : R
POR: 0b
0h = REGN not good
1h = REGN good
6
CONV_ACTIVE_STAT
R
0h
Converter Active Status
Type : R
POR: 0b
0h = Converter not running
1h = Converter running
5
4
RESERVED
R
R
0h
0h
RESERVED
VBUS_ERRHI_STAT
VBUS_ERRHI Status
Type : R
POR: 0b
0h = Not in VBUS_ERRHI status
1h = In VBUS_ERRHI status
3-0
RESERVED
R
0h
RESERVED
9.5.1.25 REG18_FLAG 1 Register (Offset = 18h) [reset = 0h]
REG18_FLAG 1 is shown in 表9-33.
Return to the Summary Table.
FLAG 1
表9-33. REG18_FLAG 1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BATOVP_FLAG
R
0h
BATOVP Flag
Type : R
POR: 0b
0h = Normal
1h = BATOVP status changed
6
BATOVP_ALM_FLAG
R
0h
BATOVP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATOVP_ALM status changed
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表9-33. REG18_FLAG 1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
VOUTOVP_FLAG
R
0h
VOUTOVP Flag
Type : R
POR: 0b
0h = Normal
1h = VOUTOVP status changed
4
3
2
1
0
BATOCP_FLAG
R
R
R
R
R
0h
0h
0h
0h
0h
BATOCP Flag
Type : R
POR: 0b
0h = Normal
1h = BATOCP status changed
BATOCP_ALM_FLAG
BATUCP_ALM_FLAG
BUSOVP_FLAG
BATOCP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATOCP_ALM status changed
BATUCP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BATUCP_ALM status changed
BUSOVP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOVP status changed
BUSOVP_ALM_FLAG
BUSOVP_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOVP_ALM status changed
9.5.1.26 REG19_FLAG 2 Register (Offset = 19h) [reset = 0h]
REG19_FLAG 2 is shown in 表9-34.
Return to the Summary Table.
FLAG 2
表9-34. REG19_FLAG 2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BUSOCP_FLAG
R
0h
BUSOCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSOCP status changed
6
5
R
R
0h
0h
BUSOCP_ALM Flag
Type : R
POR: 0b
BUSOCP_ALM_FLAG
BUSUCP_FLAG
0h = Normal
1h = BUSOCP_ALM status changed
BUSUCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSUCP status changed
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表9-34. REG19_FLAG 2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
BUSRCP_FLAG
R
0h
BUSRCP Flag
Type : R
POR: 0b
0h = Normal
1h = BUSRCP status changed
3
2
RESERVED
R
R
0h
0h
RESERVED
CFLY_SHORT_FLAG
CFLY Short Flag
Type : R
POR: 0b
0h = Normal
1h = CFLY_SHORT status changed
1-0
RESERVED
R
0h
RESERVED
9.5.1.27 REG1A_FLAG 3 Register (Offset = 1Ah) [reset = 0h]
REG1A_FLAG 3 is shown in 表9-35.
Return to the Summary Table.
FLAG 3
表9-35. REG1A_FLAG 3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
VAC1OVP_FLAG
R
0h
VAC1OVP Flag
Type : R
POR: 0b
0h = Normal
1h = VAC1 OVP status changed
6
5
VAC2OVP_FLAG
R
R
0h
0h
VAC2OVP Flag
Type : R
POR: 0b
0h = Normal
1h = VAC2 OVP status changed
VOUTPRESENT_FLAG
VOUT Present Flag
Type : R
POR: 0b
0h = Normal
1h = VOUT present status changed
4
3
2
VAC1PRESENT_FLAG
VAC2PRESENT_FLAG
VBUSPRESENT_FLAG
R
R
R
0h
0h
0h
VAC1 Present Flag
Type : R
POR: 0b
0h = Normal
1h = VAC1 present status changed
VAC2 Present Flag
Type : R
POR: 0b
0h = Normal
1h = VAC2 present status changed
VBUS Present Flag
Type : R
POR: 0b
0h = Normal
1h = VBUS present status changed
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表9-35. REG1A_FLAG 3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
ACRB1_CONFIG_FLAG
R
0h
ACFET1-RBFET1_CONFIG Flag
Type : R
POR: 0b
0h = Normal
1h = ACFET1-RBFET1_CONFIG status changed
0
ACRB2_CONFIG_FLAG
R
0h
ACFET2-RBFET2_CONFIG Flag
Type : R
POR: 0b
0h = Normal
1h = ACFET2-RBFET2_CONFIG status changed
9.5.1.28 REG1B_FLAG 4 Register (Offset = 1Bh) [reset = 0h]
REG1B_FLAG 4 is shown in 表9-36.
Return to the Summary Table.
FLAG 4
表9-36. REG1B_FLAG 4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ADC_DONE_FLAG
R
0h
ADC Conversion Flag (in One-Shot Mode only)
Type : R
POR: 0b
0h = Normal
1h = ADC conversion done status changed
6
5
4
3
2
1
SS_TIMEOUT_FLAG
TSBUS_TSBAT_ALM_FLAG
TSBUS_FLT_FLAG
TSBAT_FLT_FLAG
TDIE_FLT_FLAG
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
Soft-Start Timeout Flag
Type : R
POR: 0b
0h = Normal
1h = Soft start timeout status changed
TSBUS_TSBAT_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = Converter active status changed
TSBUS_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TSBUS_FLT status changed
TSBAT_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TSBAT_FLT status changed
TDIE_FLT Flag
Type : R
POR: 0b
0h = Normal
1h = TDIE_FLT status changed
TDIE_ALM_FLAG
TDIE_ALM Flag
Type : R
POR: 0b
0h = Normal
1h = TDIE_ALM status changed
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表9-36. REG1B_FLAG 4 Register Field Descriptions (continued)
Bit
Field
WD_FLAG
Type
Reset
Description
0
R
0h
I2C Watch Dog Timer Flag
Type : R
POR: 0b
0h = Normal
1h = WD timer status changed
9.5.1.29 REG1C_FLAG 5 Register (Offset = 1Ch) [reset = 0h]
REG1C_FLAG 5 is shown in 表9-37.
Return to the Summary Table.
FLAG 5
表9-37. REG1C_FLAG 5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REGN_GOOD_FLAG
R
0h
REGN_GOOD Flag
Type : R
POR: 0b
0h = Normal
1h = REGN_GOOD status changed
6
CONV_ACTIVE_FLAG
R
0h
Converter Active Flag
Type : R
POR: 0b
0h = Normal
1h = Converter active status changed
5
4
RESERVED
R
R
0h
0h
RESERVED
VBUS_ERRHI_FLAG
VBUS_ERRHI Flag
Type : R
POR: 0b
0h = Normal
1h = VBUS_ERRHI status changed
3-0
RESERVED
R
0h
RESERVED
9.5.1.30 REG1D_MASK 1 Register (Offset = 1Dh) [reset = 0h]
REG1D_MASK 1 is shown in 表9-38.
Return to the Summary Table.
MASK 1
表9-38. REG1D_MASK 1 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
BATOVP_MASK
R/W
0h
Reset by: BATOVP Mask
REG_RST Type : R/W
POR: 0b
0h = BATOVP flag produce INT
1h = BATOVP flag does not produce INT
Reset by: BATOVP_ALM Mask
6
BATOVP_ALM_MASK R/W
0h
REG_RST Type : R/W
POR: 0b
0h = BATOVP_ALM flag produce INT
1h = BATOVP _ALM flag does not produce INT
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表9-38. REG1D_MASK 1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
5
VOUTOVP_MASK
R/W
0h
Reset by: VOUTOVP Mask
REG_RST Type : R/W
POR: 0b
0h = VOUTOVP flag produce INT
1h = VOUTOVP flag does not produce INT
Reset by: BATOCP Mask
REG_RST Type : R/W
POR: 0b
0h = BATOCP flag produce INT
1h = BATOCP flag does not produce INT
Reset by: BATOCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BATOCP_ALM flag produce INT
1h = BATOCP_ALM flag does not produce INT
Reset by: BATUCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BATUCP_ALM flag produce INT
1h = BATUCP_ALM flag does not produce INT
Reset by: BUSOVP Mask
REG_RST Type : R/W
POR: 0b
4
3
2
1
0
BATOCP_MASK
R/W
0h
0h
0h
0h
0h
BATOCP_ALM_MASK R/W
R/W
R/W
BATUCP_ALM_MASK
BUSOVP_MASK
0h = BUSOVP flag produce INT
1h = BUSOVP flag does not produce INT
Reset by: BUSOVP_ALM Mask
BUSOVP_ALM_MASK R/W
REG_RST Type : R/W
POR: 0b
0h = BUSOVP_ALM flag produce INT
1h = BUSOVP_ALM flag does not produce INT
9.5.1.31 REG1E_MASK 2 Register (Offset = 1Eh) [reset = 0h]
REG1E_MASK 2 is shown in 表9-39.
Return to the Summary Table.
MASK 2
表9-39. REG1E_MASK 2 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
R/W
0h
BUSOCP Mask
Type : R/W
POR: 0b
BUSOCP_MASK
Reset by:
REG_RST
0h = BUSOCP flag produce INT
1h = BUSOCP flag does not produce INT
6
5
BUSOCP_ALM_MASK R/W
0h
0h
Reset by: BUSOCP_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = BUSOCP_ALM flag produce INT
1h = BUSOCP_ALM flag does not produce INT
Reset by: BUSUCP Mask
BUSUCP_MASK
R/W
REG_RST Type : R/W
POR: 0b
0h = BUSUCP flag produce INT
1h = BUSUCP flag does not produce INT
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表9-39. REG1E_MASK 2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
4
BUSRCP_MASK
R/W
0h
Reset by: BUSRCP Mask
REG_RST Type : R/W
POR: 0b
0h = BUSRCP flag produce INT
1h = BUSRCP flag does not produce INT
Reset by: RESERVED
3
2
RESERVED
R/W
0h
0h
REG_RST
CFLY_SHORT_MASK R/W
Reset by: CFLY_SHORT Mask
REG_RST Type : R/W
POR: 0b
0h = CFLY_SHORT flag produce INT
1h = CFLY_SHORT flag does not produce INT
Reset by: RESERVED
REG_RST Type : R/W
POR: 0h
1
0
RESERVED
RESERVED
R/W
R
0h
0h
RESERVED
9.5.1.32 REG1F_MASK 3 Register (Offset = 1Fh) [reset = 0h]
REG1F_MASK 3 is shown in 表9-40.
Return to the Summary Table.
MASK 3
表9-40. REG1F_MASK 3 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
VAC1OVP_MASK
R/W
0h
Reset by: VAC1OVP Mask
REG_RST Type : R/W
POR: 0b
0h = VAC1OVP flag produce INT
1h = VAC1OVP flag does not produce INT
Reset by: VAC2OVP Mask
REG_RST Type : R/W
POR: 0b
0h = VAC2OVP flag produce INT
1h = VAC2OVP flag does not produce INT
Reset by: VOUTPRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VOUTPRESENT flag produce INT
1h = VOUTPRESENT flag does not produce INT
Reset by: VAC1PRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VAC1PRESENT flag produce INT
1h = VAC1PRESENT flag does not produce INT
Reset by: VAC2PRESENT Mask
6
5
4
3
VAC2OVP_MASK
R/W
R/W
R/W
R/W
0h
0h
0h
0h
VOUTPRESENT_MASK
VAC1PRESENT_MASK
VAC2PRESENT_MASK
REG_RST Type : R/W
POR: 0b
0h = VAC2PRESENT flag produce INT
1h = VAC2PRESENT flag does not produce INT
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表9-40. REG1F_MASK 3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
2
VBUSPRESENT_MASK
R/W
0h
Reset by: VBUSPRESENT Mask
REG_RST Type : R/W
POR: 0b
0h = VBUSPRESENT flag produce INT
1h = VBUSPRESENT flag does not produce INT
Reset by: ACFET1-RBFET1 CONFIG Mask
REG_RST Type : R/W
POR: 0b
0h = ACRB1_CONFIG flag produce INT
1h = ACRB1_CONFIG flag does not produce INT
Reset by: ACFET2-RBFET2 CONFIG Mask
1
0
ACRB1_CONFIG_MASK
ACRB2_CONFIG_MASK
R/W
R/W
0h
0h
REG_RST Type : R/W
POR: 0b
0h = ACRB2_CONFIG flag produce INT
1h = ACRB2_CONFIG flag does not produce INT
9.5.1.33 REG20_MASK 4 Register (Offset = 20h) [reset = 0h]
REG20_MASK 4 is shown in 表9-41.
Return to the Summary Table.
MASK 4
表9-41. REG20_MASK 4 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
ADC_DONE_MASK
R/W
0h
Reset by: ADC_DONE Mask
REG_RST Type : R/W
POR: 0b
0h = ADC_DONE flag produce INT
1h = ADC_DONE flag does not produce INT
Reset by: SS_TIMEOUT Mask
REG_RST Type : R/W
POR: 0b
0h = SS_TIMEOUT flag produce INT
1h = SS_TIMEOUT flag does not produce INT
Reset by: TSBUS_TSBAT_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = TSBUS_TSBAT_ALM flag produce INT
1h = TSBUS_TSBAT_ALM flag does not produce INT
Reset by: TSBUS_FLT Mask
REG_RST Type : R/W
POR: 0b
0h = TSBUS_FLT flag produce INT
1h = TSBUS_FLT flag does not produce INT
Reset by: TSBAT_FLT Mask
REG_RST Type : R/W
POR: 0b
6
5
4
3
2
SS_TIMEOUT_MASK
R/W
0h
0h
0h
0h
0h
TSBUS_TSBAT_ALM_MASK R/W
TSBUS_FLT_MASK
TSBAT_FLT_MASK
TDIE_FLT_MASK
R/W
R/W
R/W
0h = TSBAT_FLT flag produce INT
1h = TSBAT_FLT flag does not produce INT
Reset by: TDIE_FLT Mask
REG_RST Type : R/W
POR: 0b
0h = TDIE_FLT flag produce INT
1h = TDIE_FLT flag does not produce INT
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表9-41. REG20_MASK 4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Note
Description
1
TDIE_ALM_MASK
R/W
0h
Reset by: TDIE_ALM Mask
REG_RST Type : R/W
POR: 0b
0h = TDIE_ALM flag produce INT
1h = TDIE_ALM flag does not produce INT
Reset by: Watchdog Mask
0
WD_MASK
R/W
0h
REG_RST Type : R/W
POR: 0b
0h = WD flag produce INT
1h = WD flag does not produce INT
9.5.1.34 REG21_MASK 5 Register (Offset = 21h) [reset = 0h]
REG21_MASK 5 is shown in 表9-42.
Return to the Summary Table.
MASK 5
表9-42. REG21_MASK 5 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
REGN_GOOD_MASK R/W
0h
Reset by: REGN_GOOD Mask
REG_RST Type : R/W
POR: 0b
0h = REGN_GOOD flag produce INT
1h = REGN_GOOD flag does not produce INT
Reset by: CONV_ACTIVE Mask
6
CONV_ACTIVE_MASK R/W
0h
REG_RST Type : R/W
POR: 0b
0h = CONV_ACTIVE flag produce INT
1h = CONV_ACTIVE flag does not produce INT
5
4
RESERVED
R/W
R/W
0h
0h
Reset by:
REG_RST
RESERVED
Type : R/W
POR: 0h
VBUS_ERRHI_MASK
Reset by: VBUS_ERRHI Mask
REG_RST Type : R/W
POR: 0b
0h = VBUS_ERRHI flag produce INT
1h = VBUS_ERRHI flag does not produce INT
3-0
RESERVED
R
0h
RESERVED
9.5.1.35 REG22_DEVICE_INFO Register (Offset = 22h) [reset = 0h]
REG22_DEVICE_INFO is shown in 表9-43.
Return to the Summary Table.
DEVICE INFO
表9-43. REG22_DEVICE_INFO Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DEVICE_REV_3:0
R
0h
Device Revision
Type : R
POR: 0h
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表9-43. REG22_DEVICE_INFO Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
DEVICE_ID_3:0
R
0h
Device ID
Type : R
POR: 0h
9.5.1.36 REG23_ADC_CONTROL 1 Register (Offset = 23h) [reset = 0h]
REG23_ADC_CONTROL 1 is shown in 表9-44.
Return to the Summary Table.
ADC_CONTROL 1
表9-44. REG23_ADC_CONTROL 1 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
ADC_EN
R/W
0h
Reset by:
ADC Enable
WATCHDOG Type : R/W
REG_RST
POR: 0b
0h = Disable
1h = Enable
6
5
ADC_RATE
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Reset by:
REG_RST
ADC Rate
Type : R/W
POR: 0b
0h = Continuous conversion
1h = 1 shot
ADC_AVG
Reset by:
REG_RST
ADC Average
Type : R/W
POR: 0b
0h = Single value
1h = Running average
4
ADC_AVG_INIT
ADC_SAMPLE_1:0
Reset by:
REG_RST
ADC Average Initial Value
Type : R/W
POR: 0b
0h = Start average using the existing register value
1h = Start average using a new conversion
3-2
Reset by:
REG_RST
ADC Sample Speed
Type : R/W
POR: 00b
0h = 15 bit
1h = 14 bit
2h = 13 bit
3h = 11 bit
1
0
IBUS_ADC_DIS
VBUS_ADC_DIS
R/W
R/W
0h
0h
Reset by:
REG_RST
IBUS ADC Control
Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by:
REG_RST
VBUS ADC Control
Type : R/W
POR: 0b
0h = Enable
1h = Disable
9.5.1.37 REG24_ADC_CONTROL 2 Register (Offset = 24h) [reset = 0h]
REG24_ADC_CONTROL 2 is shown in 表9-45.
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Return to the Summary Table.
ADC_CONTROL 2
表9-45. REG24_ADC_CONTROL 2 Register Field Descriptions
Bit
Field
Type
Reset
Note
Description
7
VAC1_ADC_DIS
R/W
0h
Reset by: VAC1 ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
6
5
4
3
2
1
0
VAC2_ADC_DIS
VOUT_ADC_DIS
VBAT_ADC_DIS
IBAT_ADC_DIS
TSBUS_ADC_DIS
TSBAT_ADC_DIS
TDIE_ADC_DIS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Reset by: VAC2 ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: VOUT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: VBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: IBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: TSBUS ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: TSBAT ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
Reset by: TDIE ADC Control
REG_RST Type : R/W
POR: 0b
0h = Enable
1h = Disable
9.5.1.38 REG25_IBUS_ADC Register (Offset = 25h) [reset = 0h]
REG25_IBUS_ADC is shown in 表9-46.
Return to the Summary Table.
IBUS_ADC
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表9-46. REG25_IBUS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
IBUS_ADC_15:0
R
0h
IBUS ADC Reading
Type : R
POR: 0 mA (0h)
Range : 0 mA - 7000 mA
Switched Cap Mode:
Fixed Offset : 66 mA
Bit Step Size : 0.9972 mA
Bypass Mode:
Fixed Offset : 64 mA
Bit Step Size : 1.0279 mA
9.5.1.39 REG27_VBUS_ADC Register (Offset = 27h) [reset = 0h]
REG27_VBUS_ADC is shown in 表9-47.
Return to the Summary Table.
VBUS_ADC
表9-47. REG27_VBUS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
VBUS_ADC_15:0
R
0h
VBUS ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 16385 mV
Fixed Offset : 0 mV
Bit Step Size : 1.002 mV
9.5.1.40 REG29_VAC1_ADC Register (Offset = 29h) [reset = 0h]
REG29_VAC1_ADC is shown in 表9-48.
Return to the Summary Table.
VAC1_ADC
表9-48. REG29_VAC1_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
VAC1_ADC_15:0
R
0h
VAC1 ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 14000 mV
Fixed Offset : 3 mV
Bit Step Size : 1.0008 mV
9.5.1.41 REG2B_VAC2_ADC Register (Offset = 2Bh) [reset = 0h]
REG2B_VAC2_ADC is shown in 表9-49.
Return to the Summary Table.
VAC2_ADC
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表9-49. REG2B_VAC2_ADC Register Field Descriptions
Bit
Field
VAC2_ADC_15:0
Type
Reset
Description
15-0
R
0h
VAC2 ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 14000 mV
Fixed Offset : 5 mV
Bit Step Size : 1.0006 mV
9.5.1.42 REG2D_VOUT_ADC Register (Offset = 2Dh) [reset = 0h]
REG2D_VOUT_ADC is shown in 表9-50.
Return to the Summary Table.
VOUT_ADC
表9-50. REG2D_VOUT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
VOUT_ADC_15:0
R
0h
VOUT ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 6000 mV
Fixed Offset : 2 mV
Bit Step Size : 1.0037 mV
9.5.1.43 REG2F_VBAT_ADC Register (Offset = 2Fh) [reset = 0h]
REG2F_VBAT_ADC is shown in 表9-51.
Return to the Summary Table.
VBAT_ADC
表9-51. REG2F_VBAT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
VBAT_ADC_15:0
R
0h
VBAT ADC Reading
Type : R
POR: 0 mV (0h)
Range : 0 mV - 6000 mV
Fixed Offset : 1 mV
Bit Step Size : 1.017 mV
9.5.1.44 REG31_IBAT_ADC Register (Offset = 31h) [reset = 0h]
REG31_IBAT_ADC is shown in 表9-52.
Return to the Summary Table.
IBAT_ADC
表9-52. REG31_IBAT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
IBAT_ADC_15:0
R
0h
IBAT ADC Reading
Type : R
POR: 0 mA (0h)
Range : 0 mA - 12000 mA
Fixed Offset : -150 mA
Bit Step Size : 0.999 mA
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9.5.1.45 REG33_TSBUS_ADC Register (Offset = 33h) [reset = 0h]
REG33_TSBUS_ADC is shown in 表9-53.
Return to the Summary Table.
TSBUS_ADC
表9-53. REG33_TSBUS_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
TSBUS_ADC_15:0
R
0h
TSBUS ADC Reading
Type : R
POR: 0% (0h)
Range : 0% - 50%
Fixed Offset : 0.1%
Bit Step Size : 0.09860%
9.5.1.46 REG35_TSBAT_ADC Register (Offset = 35h) [reset = 0h]
REG35_TSBAT_ADC is shown in 表9-54.
Return to the Summary Table.
TSBAT_ADC
表9-54. REG35_TSBAT_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
TSBAT_ADC_15:0
R
0h
TSBAT ADC Reading
Type : R
POR: 0% (0h)
Range : 0% - 50%
Fixed Offset : 0.065%
Bit Step Size : 0.09762%
9.5.1.47 REG37_TDIE_ADC Register (Offset = 37h) [reset = 0h]
REG37_TDIE_ADC is shown in 表9-55.
Return to the Summary Table.
TDIE_ADC
表9-55. REG37_TDIE_ADC Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
TDIE_ADC_15:0
R
0h
TDIE ADC Reading
Type : R
POR: 0°C (0h)
Range : -40°C - 150°C
Fixed Offset : -3.5°C
Bit Step Size : 0.5079°C
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
A typical application consists of the device configured as an I2C controlled parallel charger along with a standard
switching charger, however, it can also be used with a linear charger or PMIC with integrated charger as well.
BQ25960 can start fast charging after the main charger completes pre-charging. BQ25960 will then hand back
charging to the main charger when final current tapering is desired. This point is usually where the efficiency of
the main charger is acceptable for the application. The device can be used to charge Li-Ion and Li-polymer
batteries used in a wide range of smartphones and other portable devices. To take advantage of the high charge
current capabilities of the BQ25960, it may be necessary to charge in excess of 1C. In this case, be sure to
follow the battery manufacturers recommendations closely.
10.2 Typical Application
A typical schematic is shown below with all the optional and required components shown.
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10.2.1 Standalone Application Information (for use with main charger)
System
SYS
BAT
VBUS
Main Charger
GND
Adapter
Wireless
ACDRV2
VAC2
VBUS
BQ25960
1µF
SDA
ACDRV1
Digital
Core
QB
Host
SCL
/INT
VAC1
PMID
10µF
QCH1
QCH2
CFH2
CFH1
CFLY1
1-3×22µF
CFLY2
1-3×22µF
QDH1
QDH2
QCL2
QDL2
VOUT
22µF
QCL1
CFL2
CFL1
100Ω
QDL1
GND
BATP
BATN_SRP
Protection
16 bit ADC
2mΩ
SRN_SYNCIN
REGN
10kΩ
REGN
10kΩ
TSBUS
CDRVH
10kΩ
10kΩ
TSBAT_SYNCOUT
REGN
10kΩ
10kΩ
220nF
CDRVL_
ADDRMS
75kΩ
4.7µF
图10-1. BQ25960 Typical Application Diagram with Dual Input
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System
SYS
BAT
VBUS
GND
Main Charger
Optional
Adapter
ACDRV2
VAC2
VBUS
1µF
BQ25960
ACDRV1
VAC1
SDA
Digital
Core
QB
Host
SCL
INT
PMID
10µF
QCH1
QCH2
CFH2
CFH1
CFLY1
1-3×22µF
CFLY2
1-3×22µF
QDH1
QDH2
QCL2
QDL2
VOUT
22µF
QCL1
CFL2
CFL1
100Ω
QDL1
GND
BATP
BATN_SRP
Protection
16 bit ADC
2mΩ
SRN_SYNCIN
REGN
10kΩ
TSBUS
CDRVH
REGN
10kΩ
10kΩ
10kΩ
10kΩ
TSBAT_SYNCOUT
REGN
10kΩ
220nF
CDRVL_
ADDRMS
75kΩ
4.7µF
图10-2. BQ25960 Typical Application Diagram with Single Input
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10.2.1.1 Design Requirements
The design requires a smart wall adapter to provide the proper input voltage and input current to the BQ25960,
following the USB_PD Programmable Power Supply (PPS) voltage steps and current steps. The design shown
is capable of charging up to 8 A, although this may not be practical for some applications due to the total power
loss at this operating point. Careful consideration of the thermal constraints, space constraints, and operating
conditions should be done to ensure acceptable performance.
10.2.1.2 Detailed Design Procedure
The first step is to determine the number of CFLY caps to put on each phase of the design. It is important to
consider the current rating of the caps, their ESR, and the capacitance rating. Be sure to consider the bias
voltage derating for the caps, as the CFLY caps are biased to half of the input voltage, and this will affect their
effective capacitance. An optimal system will have 3 22-µF caps per phase, for a total of 6 caps per device. It is
possible to use fewer caps if the board space is limited. Using fewer caps will result in higher voltage and current
ripple on the output, as well as lower efficiency.
The default switching frequency, fSW, for the power stage is 500 kHz. The switching frequency can be adjusted in
register 0x10h using the FSW_SET bits. It is recommended to select 500 kHz if IBATADC is not used and 375
kHz if IBATADC is used.
It is recommended to use 1-µF cap on VBUS, 10-µF cap on PMID and 22-µF cap on VOUT.
10.2.1.3 Application Curves
图10-3. Switched Cap Mode Power Up
图10-4. Bypass Mode Power Up
图10-5. Adapter Unplug in Switched Cap Mode
图10-6. Adapter Unplug in Bypass Mode
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图10-7. VBUSOVP in Switched Cap Mode
图10-8. VBUSOVP in Bypass Mode
图10-9. IBUSOCP in Switched Cap Mode
图10-10. IBUSOCP in Bypass Mode
图10-11. VBATOVP in Switched Cap Mode
图10-12. VBATOVP in Bypass Mode
图10-13. IBATOCP in Switched Cap Mode
图10-14. IBATOCP in Bypass Mode
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VAC1 and VAC2 short to VBUS, ACDRV1 and ACDRV2 short
to ground
VAC1 connected to input source, VAC2 short to VBUS,
ACDRV1 active, ACDRV2 short to ground
图10-15. Power Up without AC-RFFET
图10-16. Power Up from VAC1 with Single ACFET1
VAC1 connected to input source 1, VBUS connected to input
source 2, VAC2 short to VBUS, ACDRV1 active, ACDRV2
short to ground
VAC1 connected to input source 1, VBUS connected to input
source 2, VAC2 short to VBUS, ACDRV1 active, ACDRV2
short to ground
图10-17. Power Up from VAC1 with ACFET1-
图10-18. Plugin VAC1 When Device is Power Up
RBFET1
From VBUS with ACFET1-RBFET1
VAC1 connected to input source 1, VAC2 connected to input
source 2, ACDRV1 and ACDRV2 active
VAC1 connected to input source 1, VAC2 connected to input
source 2, ACDRV1 and ACumDRV2 active
图10-19. Power Up from VAC1 with ACFET1-
图10-20. Power Up from VAC2 with ACFET1-
RBFET1 and ACFET2-RBFET2
RBFET1 and ACFET2-RBFET2
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11 Power Supply Recommendations
The BQ25960 can be powered by a standard power supply capable of meeting the input voltage and current
requirements for evaluation. In the actual application, it must be used with a wall adapter that supports USB
Power Delivery (PD) Programmable Power Supply (PPS) specifications.
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12 Layout
12.1 Layout Guidelines
Layout is very important to maximize the electrical and thermal performance of the total system. General
guidelines are provided, but the form factor, board stack-up, and proximity of other components also need to be
considered to maximize the performance.
1. VBUS and VOUT traces should be as short and wide as possible to accommodate for high current.
2. Copper trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP
ball array) before making turns.
3. CFLY caps should be placed as close as possible to the device and CFLY trace should be as wide as
possible until close to the IC.
4. CLFY pours should be as symmetrical between CFH pads and CFL pads as possible.
5. Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be placed as
close to the device pins as possible.
6. The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the
device, as these are switching pins and this will help reduce EMI.
7. Do not route so the power planes are interrupted by signal traces.
Refer to the EVM design and more information in the BQ25960EVM (BMS041) Evaluation Module User's Guide
for the recommended component placement with trace and via locations.
12.2 Layout Example
CFLY1
CFLY2
0603
0603
CFLY1
CFLY2
0603
0603
1
2
3
4
5
6
Blind via
PMID
GND
CFL1
VOUT
CFH1
VBUS
A
Top Layer
Bottom Layer
CFH1
CFH2
PMID
PMID
GND
GND
CFL1
CFL2
VOUT
VOUT
VOUT
VBUS
VBUS
SRN
B
C
D
E
F
Mid Layer_1
Mid Layer_2
/INT
SCL
SDA
CDRVH
CDRVL
REGN
CFL2
CFH2
SRP_
BATN
VAC2
TSBAT
TSBUS
VAC1
ACDRV1
BATP
ACDRV2
图12-1. BQ25960 Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• BQ25960EVM (BMS041) Evaluation Module User's Guide
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25960YBGR
ACTIVE
DSBGA
YBG
36
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25960
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
YBG0036
DSBGA - 0.5 mm max height
SCALE 6.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.05 C
0.20
0.14
BALL TYP
2 TYP
SYMM
F
E
D
C
2
TYP
SYMM
D: Max = 2.542 mm, Min =2.482 mm
E: Max = 2.542 mm, Min =2.482 mm
B
A
0.4 TYP
0.27
2
1
4
5
6
3
36X
0.23
0.015
C A B
0.4 TYP
4224846/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YBG0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
36X ( 0.23)
2
1
4
5
6
A
(0.4) TYP
B
C
SYMM
D
E
F
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224846/A 03/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBG0036
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
36X ( 0.25)
(0.4) TYP
(R0.05) TYP
6
2
1
4
5
A
B
C
SYMM
METAL
TYP
D
E
F
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 30X
4224846/A 03/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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