BQ27320YZFR [TI]
单节电池组/系统侧 CEDV 电池电量监测计 | YZF | 15 | -40 to 85;
| 型号： | BQ27320YZFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单节电池组/系统侧 CEDV 电池电量监测计 | YZF | 15 | -40 to 85 电池 |
| 文件： | 总33页 (文件大小：1371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
bq27320 单节 CEDV 电量监测计
1 特性
3 说明
1
•
•
用于系统/电池组端配置的电池电量监测计
补偿放电终点电压 (CEDV) 电量监测技术
德州仪器 (TI) 的 bq27320 单节电池电量监测计只需进
行极少的配置和系统微控制器固件开发工作，有助于实
现快速系统调通。bq27320 采用补偿放电终点电压
(CEDV) 电量监测算法进行电量检测，可提供诸如剩余
电量 (mAh)、充电状态 (%)、续航时间（分钟）、电池
电压 (mV)、温度 (°C) 和健康状况 (%) 等信息。
–
针对电池老化、自放电、温度和速率变化进行调
节
–
可报告剩余电量、充电状态 (SOC) 和续航时
间，具有平滑滤波器
–
–
电池健康状况估计
TI 客户可使用 TI 基于网络的工具 GAUGEPARCAL 调
整化学参数。
支持 100mAhr 至 14,500mAhr 容量范围内的嵌
入式或可拆卸电池组
–
具有多达 4 种单独的电池配置文件，能够适应
电池组交换
可配置中断有助于节省系统功耗，释放主机使其停止继
续轮询。外部热敏电阻为精确温度感测提供支持。
–
支持原始库仑计数器，用以提供电量变化信息
通过 bq27320 进行电池电量监测时，只需将 PACK+
(P+)、PACK- (P-) 以及选装的热敏电阻 (T) 连接至一
个可拆卸电池组或嵌入式电池电路即可。此器件使用一
个 15 焊球 NanoFree™（芯片尺寸球栅阵列
•
微控制器外设支持：
–
用于身份验证 ID 的
SDQ 通信接口
400kHz I2C™用于高速通信的串行接口
–
–
(DSBGA)）封装, 是空间受限类应用的 理想选择。
32 字节高速暂存存储器闪存非易失性内存
(NVM)
器件信息(1)
–
–
–
电池低电平数字输出警告
器件型号
bq27320
封装
封装尺寸（标称值）
可配置 SOC 中断
1.375mm x 2.75mm
x 1.75mm
YZF (15)
外部热敏电阻、内部传感器或主机温度报告选项
•
15 引脚 1.375mm x 2.75mm x 1.75mm（间距）
NanoFree™(DSBGA) 封装
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
2 应用
Host System
Single Cell Li-lon
Battery Pack
•
•
•
•
•
•
智能手机、功能型手机和平板电脑
VCC
LDO
PACK+
可穿戴产品
CE
PROTECTION
IC
Voltage
Sense
SDQ
楼宇自动化
Temp
Sense
I2C
DATA
便携式医疗/工业手持终端
便携式音频设备
游戏机
Power
Management
Controller
T
CHG
DSG
FETs
BAT_GD
PACK-
Current
Sense
SOC_INT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCG9
bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
目录
7.14 SDQ Switching Characteristics ............................... 7
7.15 Typical Characteristics............................................ 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Applications ................................................ 19
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Supply Current .......................................................... 5
7.6 Digital Input and Output DC Characteristics............. 5
7.7 Power-On Reset........................................................ 5
7.8 2.5-V LDO Regulator ................................................ 5
7.9 Internal Clock Oscillators .......................................... 5
8
9
10 Power Supply Recommendations ..................... 23
10.1 Power Supply Decoupling..................................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 文档支持................................................................ 25
12.2 社区资源................................................................ 25
12.3 商标....................................................................... 25
12.4 静电放电警告......................................................... 25
12.5 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
7.10 ADC (Temperature and Cell Measurement)
Characteristics ........................................................... 6
7.11 Integrating ADC (Coulomb Counter)
Characteristics ........................................................... 6
7.12 Data Flash Memory Characteristics........................ 6
7.13 I2C-Compatible Interface Communication Timing
Characteristics ........................................................... 7
4 修订历史记录
日期
修订版本
注释
2016 年 3 月
A
产品预览至量产数据
2
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
5 Device Comparison Table
ORDER NUMBER
bq27320YZFT
PACKAGE
YZF
PACKAGE QUANTITY
BODY SIZE
250
1.375 mm x 2.75 mm x 1.75 mm
bq27320YZFR
3000
6 Pin Configuration and Functions
1
2
3
E
D
C
B
A
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
SRP
NUMBER
Analog input pin connected to the internal coulomb counter with a Kelvin connection where SRP is nearest the
PACK– connection. Connect to 5-mΩ to 20-mΩ sense resistor.
A1
IA(1)
IA
Analog input pin connected to the internal coulomb counter with a Kelvin connection where SRN is nearest the Vss
connection. Connect to 5-mΩ to 20-mΩ sense resistor.
SRN
B1
VSS
C1, C2
D1
P
P
P
O
Device ground
VCC
Regulator output and bq27320 processor power. Decouple with 1-μF ceramic capacitor to Vss.
REGIN
SOC_INT
E1
Regulator input. Decouple with 0.1-μF ceramic capacitor to VSS.
SOC state interrupts output. Generates a pulse under the conditions specified by (1). Open drain output
A2
Battery Good push-pull indicator output. Active-low and output disabled by default. Polarity is configured via Op
Config [BATG_POL] and the output is enabled via OpConfig C [BATGSPUEN].
BAT_GD
B2
O
Chip Enable. Internal LDO is disconnected from REGIN when driven low. Note: CE has an internal ESD protection
diode connected to REGIN. Recommend maintaining VCE ≤ VREGIN under all conditions.
CE
D2
E2
A3
I
I
I
BAT
SCL
Cell-voltage measurement input. ADC input. Recommend 4.8V maximum for conversion accuracy.
Slave I2C serial communications clock input line for communication with system (Master). Open-drain I/O. Use with
10-kΩ pull-up resistor (typical).
Slave I2C serial communications data line for communication with system (Master). Open-drain I/O. Use with 10-kΩ
pull-up resistor (typical).
SDA
B3
I/O
SDQ
TS
C3
D3
O
Communication interface to Authentication ID IC, using the SDQ protocol
Pack thermistor voltage sense (use 103AT-type thermistor). ADC input
IA
Battery-insertion detection input. Power pin for pack thermistor network. Thermistor-multiplexer control pin. Use with
pull-up resistor >1MΩ (1.8 MΩ typical).
BI/TOUT
E3
I/O
(1) I/O = Digital input/output, IA = Analog input, P = Power connection
Copyright © 2016, Texas Instruments Incorporated
3
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ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
5.5
(2)
VREGIN
Regulator input range
6.0
VREGIN + 0.3
2.75
V
VCE
VCC
VIOD
CE input pin
V
Supply voltage range
V
Open-drain I/O pins (SDA, SCL, SOC_INT)
5.5
V
5.5
V
VBAT
VI
BAT input pin
(2)
6.0
V
Input voltage range to all other pins
(BI/TOUT, TS, SRP, SRN, SDQ, BAT_GD)
–0.3
VCC + 0.3
V
TA
Operating free-air temperature range
Functional Temperature
–40
–40
–65
85
°C
°C
°C
TFUNC
TSTG
110
150
Storage temperature range
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Condition not to exceed 100 hours at 25°C lifetime.
7.2 ESD Ratings
VALUE
1500
2000
500
UNIT
V
Human body model (HBM) ESD stress voltage(1), BAT pin
Electrostatic Discharge Human-body model (HBM), all other pins
Charged-device model (CDM) ESD stress voltage(1)
V(ESD)
V
(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
TA = -40°C to 85°C, VREGIN = VBAT = 3.6 V (unless otherwise noted)
MIN
2.8
NOM
MAX
UNIT
No operating restrictions
No FLASH writes
4.5
2.8
VREGIN
Supply voltage
V
2.45
External input capacitor for internal
LDO between REGIN and VSS
CREGIN
CLDO25
tPUCD
0.1
1
μF
Nominal capacitor values specified.
Recommend a 5% ceramic X5R type
capacitor located close to the device.
External output capacitor for internal
LDO between VCC and VSS
0.47
μF
Power-up communication delay
250
ms
7.4 Thermal Information
bq27320
THERMAL METRIC(1)
YZF (DSBGA)
UNIT
15 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
70
17
20
1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
18
n/a
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
4
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
7.5 Supply Current
TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fuel gauge in NORMAL mode
ILOAD > Sleep Current
(1)
ICC
Normal operating-mode current
118
μA
Fuel gauge in SNOOZE mode
ILOAD < Sleep Current
(1)
ISNOOZE
Sleep+ operating mode current
Low-power storage-mode current
Hibernate operating-mode current
SHUTDOWN mode current
62
23
8
μA
μA
μA
μA
Fuel gauge in SLEEP mode
ILOAD < Sleep Current
(1)
ISLP
Fuel gauge in HIBERNATE mode
ILOAD < Hibernate Current
(1)
IHIB
Fuel gauge in SHUTDOWN mode
CE Pin < VIL(CE) max.
(1)
ISHD
1
(1) Specified by design. Not production tested.
7.6 Digital Input and Output DC Characteristics
TA = –40°C to 85°C, typical values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 3 mA
IOH = –1 mA
MIN
TYP
MAX
UNIT
Output voltage, low (SCL, SDA,
SOC_INT, SDQ, BAT_GD)
VOL
0.4
V
VOH(PP)
Output voltage, high (SDQ,
BAT_GD)
VCC – 0.5
VCC – 0.5
V
Output voltage, high (SDA, SCL, External pullup resistor connected to
SOC_INT)
VOH(OD)
VIL
VCC
Input voltage, low (SDA, SCL)
Input voltage, low (BI/TOUT)
Input voltage, high (SDA, SCL)
Input voltage, high (BI/TOUT)
Input voltage, low (CE)
–0.3
–0.3
1.2
0.6
0.6
V
V
BAT INSERT CHECK mode active
VIH
BAT INSERT CHECK mode active
VREGIN = 2.8 to 4.5 V
1.2
VCC + 0.3
0.8
VIL(CE)
VIH(CE)
V
Input voltage, high (CE)
Input leakage current (I/O pins)
2.65
(1)
Ilkg
0.3
μA
(1) Specified by design. Not production tested.
7.7 Power-On Reset
TA = –40°C to 85°C, typical values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIT+
Positive-going battery voltage
input at VCC
2.05
2.15
115
2.20
VHYS
Power-on reset hysteresis
mV
7.8 2.5-V LDO Regulator
TA = –40°C to 85°C, CLDO25 = 1μF, VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
2.8 V ≤ VREGIN ≤ 4.5V, IOUT ≤ 16 mA(1)
2.3
2.5
2.6
V
VREG25
Regulator output voltage (VCC)
2.45 V ≤ VREGIN < 2.8V (low battery),
2.3
V
IOUT ≤ 3 mA
(1) LDO output current, IOUT, is the total load current. LDO regulator should be used to power internal fuel gauge only.
7.9 Internal Clock Oscillators
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOSC
High Frequency Oscillator
8.389
MHz
Copyright © 2016, Texas Instruments Incorporated
5
bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
Internal Clock Oscillators (continued)
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fLOSC
Low Frequency Oscillator
32.768
kHz
7.10 ADC (Temperature and Cell Measurement) Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSS
0.125
–
VADC1
Input voltage range (TS)
2
V
VSS
0.125
–
VADC2
Input voltage range (BAT)
Input voltage range
5
1
V
V
VIN(ADC)
GTEMP
0.05
Internal temperature sensor
voltage gain
–2
mV/°C
Conversion time
Resolution
125
15
ms
bits
mV
MΩ
MΩ
kΩ
tADC_CONV
VOS(ADC)
14
Input offset
1
(1)
ZADC1
Effective input resistance (TS)
8
8
bq27320 not measuring cell voltage
bq27320 measuring cell voltage
(1)
ZADC2
Effective input resistance (BAT)
Input leakage current
100
(1)
Ilkg(ADC)
0.3
μA
(1) Specified by design. Not tested in production.
7.11 Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSR = V(SRP) – V(SRN)
Single conversion
MIN
TYP
MAX
UNIT
VSR
Input voltage range,
V(SRP) and V(SRN)
–0.125
0.125
V
tSR_CONV
Conversion time
1
s
Resolution
14
15
bits
μV
VOS(SR)
INL
Input offset
10
Integral nonlinearity error
Effective input resistance
Input leakage current
±0.007% ±0.034%
0.3
FSR
MΩ
μA
(1)
ZIN(SR)
2.5
(1)
Ilkg(SR)
(1) Specified by design. Not tested in production.
7.12 Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Data retention
10
Years
(1)
tDR
Flash-programming write
cycles(1)
20,000
Cycles
(1)
tWORDPROG
Word programming time
Flash-write supply current
Data flash master erase time
2
ms
mA
ms
(1)
ICCPROG
5
10
(1)
tDFERASE
200
200
20
Instruction flash master erase
time
(1)
tIFERASE
ms
ms
(1)
tPGERASE
Flash page erase time
(1) Specified by design. Not production tested
6
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
7.13 I2C-Compatible Interface Communication Timing Characteristics
TA = –40°C to 85°C, 2.4 V < VCC < 2.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
300
UNIT
ns
tr
SCL/SDA rise time
SCL/SDA fall time
tf
300
ns
tw(H)
SCL pulse duration (high)
SCL pulse duration (low)
Setup for repeated start
Start to first falling edge of SCL
Data setup time
600
1.3
600
600
100
0
ns
tw(L)
μs
tsu(STA)
td(STA)
tsu(DAT)
th(DAT)
tsu(STOP)
t(BUF)
ns
ns
ns
Data hold time
ns
Setup time for stop
600
ns
Bus free time between stop and
start
66
μs
fSCL
Clock frequency(1)
400
kHz
(1) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at
400 kHz. (Refer to I2C Interface and I2C Command Waiting Time)
7.14 SDQ Switching Characteristics
TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
120
15
UNIT
μs
(1)
tc
Bit cycle time
60
(1)
tWSTRB
tWDSU
tWDH
Write start cycle
1
tWSTRB
60
μs
(1)
Write data setup
15
μs
(1) (2)
Write data hold
tc
μs
1
(1)
trec
Recovery time
μs
For memory command only
5
(1)
tRSTRB
tODD
tODHO
tRST
Read start cycle
1
13
13
60
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
(1)
Output data delay
tRSTRB
17
(1)
Output data hold
(1)
Reset time
480
15
(1)
tPPD
Presence pulse delay
60
(1)
tPP
Presence pulse
60
240
tEPROG
tPSU
tPREC
tPRE
EPROM programming time
Program setup time
2500
5
Program recovery time
Program rising-edge time
Program falling-edge time
5
5
5
tPFE
tRSTREC
480
(1) 5-kΩ series resistor between SDQ pin and VPU
.
(2) tWDH must be less than tc to account for recovery.
Copyright © 2016, Texas Instruments Incorporated
7
bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
Figure 1. I2C-Compatible Interface Timing Diagrams
7.15 Typical Characteristics
2.65
2.6
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
VREGIN = 2.7 V
VREGIN = 4.5 V
2.55
2.5
2.45
2.4
2.35
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D001
D002
Figure 2. Regulator Output Voltage vs. Temperature
Figure 3. High-Frequency Oscillator Frequency vs.
Temperature
34
5
4
33.5
33
3
2
32.5
32
1
0
-1
-2
-3
-4
-5
31.5
31
30.5
30
-40
-20
0
20
40
60
80
100
-30
-20
-10
0
10
20
30
40
50
60
Temperature (èC)
Temperature (èC)
D003
D004
Figure 4. Low-Frequency Oscillator Frequency vs.
Temperature
Figure 5. Reported Internal Temperature Measurement vs.
Temperature
8
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
8 Detailed Description
8.1 Overview
The bq27320 measures the voltage, temperature, and current to determine battery capacity and state of charge
(SOC). The bq27320 monitors charge and discharge activity by sensing the voltage across a small-value resistor
(5 mΩ to 20 mΩ typical) between the SRP and SRN pins and in series with the battery. By integrating charge
passing through the battery, the battery’s SOC is adjusted during battery charge or discharge.
Measurements of OCV and charge integration determine chemical state of charge. The Qmax values are taken
from a cell manufacturers' data sheet multiplied by the number of parallel cells. It is also used for the value in
Design Capacity. It uses the OCV and Qmax value to determine StateOfCharge() on battery insertion, device
reset, or on command. The FullChargeCapacity() is reported as the learned capacity available from full charge
until Voltage() reaches the EDV0 threshold.
As Voltage() falls below the SysDown Set Volt Threshold, the Flags() [SYSDOWN] bit is set and SOC_INT will
toggle once to provide a final warning to shut down the system. As Voltage() rises above SysDown Clear
Voltage the [SYSDOWN] bit is cleared.
Additional details are found in the bq27320 Technical Reference Manual (SLUUBE6).
The fuel gauging is derived from the Compensated End of Discharge Voltage (CEDV) method, which uses a
mathematical model to correlate remaining state of charge (RSOC) and voltage near to the end of discharge
state. This requires a full discharge cycle for a single point FCC update. The implementation models cell voltage
(OCV) as a function of battery state of charge (SOC), temperature, and current. The impedance is also a function
of SOC and temperature, all of which can be satisfied by using seven parameters: EMF, C0, R0, T0, R1, TC, C1.
For more detailed information, contact TI Applications Support at http://www-k.ext.ti.com/sc/technical-
support/email-tech-support.asp?AAP.
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8.2 Functional Block Diagram
CE
LDO
POR
REGIN
2.5 V
VCC
HFO
BAT
SRN
CC
HFO
LFO
HFO/128
4R
HFO/128
SRP
MUX
ADC
R
Wake
Comparator
TS
Internal
Temp
Sensor
BI/TOUT
SOCINT
HFO/4
SDA
22
Instruction
ROM
I2C Slave
Engine
22
CPU
VSS
SDQ
SCL
I/O
Controller
Instruction
FLASH
BAT_LOW
BAT_GD
8
8
Wake
and
GP Timer
and
PWM
Data
SRAM
Data
FLASH
Watchdog
Timer
8.3 Feature Description
The bq27320 accurately predicts the battery capacity and other operational characteristics of a single Li-based
rechargeable cell. It can be interrogated by a system processor to provide cell information, such as time-to-empty
(TTE) and state-of-charge (SOC) as well as SOC interrupt signal to the host.
10
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Feature Description (continued)
Information is accessed through a series of commands, called Standard Commands. Further capabilities are
provided by the additional Manufacturer Access Control subcommand set. Both sets of commands, indicated by
the general format Command(), are used to read and write information contained within the device control and
status registers, as well as its data flash locations. Commands are sent from system to gauge using the bq27320
device’s I2C serial communications engine, and can be executed during application development, system
manufacture, or end-equipment operation.
Cell information is stored in the device in non-volatile flash memory. Many of these data flash locations are
accessible during application development. They cannot, generally, be accessed directly during end-equipment
operation. Access to these locations is achieved by either use of the bq27320 device’s companion evaluation
software, through individual commands, or through a sequence of data-flash-access commands. To access a
desired data flash location, the correct data flash address must be known.
The key to the bq27320 device’s high-accuracy gas gauging prediction is Texas Instruments CEDV algorithm.
This algorithm uses cell measurements, characteristics, and properties to create state-of-charge predictions
across a wide variety of operating conditions and over the lifetime of the battery.
The device measures charge and discharge activity by monitoring the voltage across a small-value series sense
resistor (5 mΩ to 20 mΩ typical) located between the system’s VSS and the battery’s PACK– pin. When a cell is
attached to the device, FCC is learned based on cell current and on cell voltage under-loading conditions when
the EDV2 threshold is reached.
The device external temperature sensing is optimized with the use of a high accuracy negative temperature
coefficient (NTC) thermistor with R25 = 10.0 kΩ ±1%. B25/85 = 3435K ± 1% (such as Semitec NTC 103AT).
Alternatively, the bq27320 can also be configured to use its internal temperature sensor or receive temperature
data from the host processor. When an external thermistor is used, a 18.2-kΩ pull-up resistor between BI/TOUT
and TS pins is also required. The bq27320 uses temperature to monitor the battery-pack environment, which is
used for fuel gauging and cell protection functionality.
To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP,
HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending
upon the occurrence of specific events, though a system processor can initiate some of these modes directly.
For complete operational details, refer to the bq27320 Technical Reference Manual (SLUUBE6).
NOTE
Formatting Conventions in this Document:
Commands: italics with parentheses() and no breaking spaces; for example,
RemainingCapacity()
Data Flash: italics, bold, and breaking spaces; for example, Design Capacity
Register bits and flags: italics with brackets [ ]; for example, [TDA]
Data flash bits: italics, bold, and brackets [ ]; for example, [LED1]
Modes and states: ALL CAPITALS, for example; UNSEALED mode
8.3.1 Data Commands
8.3.1.1 Standard Data Commands
The bq27320 uses a series of 2-byte standard commands to enable system reading and writing of battery
information. Each standard command has an associated command-code pair, as indicated in Table 1 (see the
bq27320 Technical Reference Manual [SLUUBE6]). Because each command consists of two bytes of data, two
consecutive I2C transmissions must be executed both to initiate the command function, and to read or write the
corresponding two bytes of data.
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Feature Description (continued)
Table 1. Standard Commands
SEALED
ACCESS
NAME
COMMAND CODE
UNIT
Control() / CONTROL_STATUS()
AtRate()
CNTL
AR
0x00 and 0x01
0x02 and 0x03
0x04 and 0x05
0x06 and 0x07
0x08 and 0x09
0x0A and 0x0B
0x0C and 0x0D
0x10 and 0x11
0x12 and 0x13
0x14 and 0x15
0x16 and 0x17
0x18 and 0x19
0x1A and 0x1B
0x1C and 0x1D
0x1E and 0x1F
0x20 and 0x21
0x24 and 0x25
0x28 and 0x29
0x2A and 0x2B
0x2C and 0x2D
0x2E and 0x2F
0x30 and 0x31
0x32 and 0x33
0x34 and 0x35
0x36 and 0x37
0x3A and 0x3B
0x3C and 0x3D
0x3E and 0x3F
0x40 through 0x5F
0x60
NA
mA
RW
RW
R
AtRateTimeToEmpty()
Temperature()
ARTTE
TEMP
VOLT
Flags()
Minutes
0.1°K
mV
RW
R
Voltage()
BatteryStatus()
NA
R
Current()
Current()
RM
mAh
mAh
mAh
mA
R
RemainingCapacity()
FullChargeCapacity()
AverageCurrent()
TimeToEmpty()
TimeToFull()
R
FCC
AI
R
R
TTE
TTF
Minutes
Minutes
mA
R
R
StandbyCurrent()
StandbyTimeToEmpty()
MaxLoadCurrent()
MaxLoadTimeToEmpty()
AveragePower()
InternalTemperature()
CycleCount()
SI
R
STTE
MLI
Minutes
mA
R
R
MLTTE
AP
min
R
mW
R
INTTEMP
CC
0.1°K
num
—
R
R
StateOfCharge()
StateOfHealth()
ChargeVoltage()
ChargeCurrent()
BTPDischargeSet()
BTPChargeSet()
OperationStatus()
DesignCapacity()
ManufacturerAccessControl()
MACData()
SOC
SOH
CV
R
num
mV
R
R
CC
mA
R
mAh
mAh
NA
R
R
R
Design Cap
MAC
mAh
R
MACDataSum()
MACDataLen()
0x61
AnalogCount()
0x79
RawCurrent()
0x7A and 0x7B
0x7C and 0x7D
0x7E and 0x7F
0x80 and 0x81
RawVoltage()
RawIntTemp()
RawExtTemp()
8.3.1.1.1 Control(): 0x00/0x01
Issuing a Control() (Manufacturer Access Control or MAC) command requires a 2-byte subcommand. The
subcommand specifies the particular MAC function desired. The Control() command allows the system to control
specific features of the gas gauge during normal operation and additional features when the device is in different
access modes, as described in the bq27320 Technical Reference Manual (SLUUBE6).
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Table 2. Control() MAC Subcommands
SUBCOMMAND
CODE
SEALED
ACCESS?
CNTL / MAC FUNCTION
DESCRIPTION
Ignored by gauge (in previous devices would enable
CONTROL_STATUS() read).
CONTROL_STATUS
0x0000
Yes
DEVICE_TYPE
FW_VERSION
HW_VERSION
IF_SUM
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Reports the device type (for example: 0x0320)
Reports the firmware version block (device, version, build, and so on)
Reports the hardware version of the device
Reports Instruction flash checksum
STATIC_DF_SUM
CHEM_ID
Reports the static data flash checksum
Reports the chemical identifier of the CEDV configuration
Returns previous Control() subcommand code
Returns the chem ID checksum
PREV_MACWRITE
STATIC_CHEM_DF_SUM
BOARD_OFFSET
CC_OFFSET
Invokes the board offset correction
Invokes the CC offset correction
CC_OFFSET_SAVE
OCV_CMD
Saves the results of the offset calibration process
Requests the gas gauge to take an OCV measurement
Forces BatteryStatus()[BATTPRES] bit set when Operation Config B
[BIEnable] bit = 0
BAT_INSERT
0x000D
0x000E
Yes
Yes
Forces BatteryStatus()[BATTPRES] bit clear when Operation Config B
[BIEnable] bit = 0
BAT_REMOVE
ALL_DF_SUM
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x002D
0x0030
0x0035
0x0041
0x004a
0x0054
0x0056
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Returns the checksum of the entire data flash except for calibration data
Forces CONTROL_STATUS()[HIBERNATE] bit to 1
Forces CONTROL_STATUS()[HIBERNATE] bit to 0
Forces CONTROL_STATUS()[SNOOZE] bit to 1
Forces CONTROL_STATUS()[SNOOZE] bit to 0
Select Battery Profile 0
SET_HIBERNATE
CLEAR_HIBERNATE
SET_SNOOZE
CLEAR_SNOOZE
BATT_SELECT_0
BATT_SELECT_1
BATT_SELECT_2
BATT_SELECT_3
CAL_MODE
Select Battery Profile 1
Select Battery Profile 2
Select Battery Profile 3
Toggles OperationStatus()[CALMD]
SEALED
No
Places the gas gauge in SEALED access mode
Read and Write Security Keys
SECURITY_KEYS
RESET
No
No
Resets device
DEVICE_NAME
OPERATION_STATUS
GaugingStatus
Yes
Yes
Yes
Returns the device name
This returns the same value as the OperationStatus() register.
Returns the information of CEDV gauge module status register
Returns the manufacturer info A block. This can be written directly when
unsealed
MANU_DATA
0x0070
Yes
GGSTATUS1
GGSTATUS2
GGSTATUS3
GGSTATUS4
EXIT_CAL
0x0073
0x0074
0x0075
0x0076
0x0080
0x0081
0xF00
Yes
Yes
Yes
Yes
No
Returns internal gauge debug data block 1
Returns internal gauge debug data block 2
Returns internal gauge debug data block 3
Returns internal gauge debug data block 4
Instructs the fuel gauge to exit calibration mode
Instructs the fuel gauge to enter calibration mode
Places the device in ROM mode
ENTER_CAL
No
RETURN_TO_ROM
DF_ADDR_START
DF_ADDR_END
No
0x4000
0x43FF
No
Direct DF read write access boundary
DF read write access boundary
No
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8.3.2 SDQ Signaling
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 6 shows the initialization timing, whereas Figure 7 and Figure 8
show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq27320 responds during a
READ.
8.3.3 Reset and Presence Pulse
If the DATA bus is driven low for more than 120 μs, the bq27320 may be reset. Figure 6 shows that if the DATA
bus is driven low for more than 480 μs, the bq27320 resets and indicates that it is ready by responding with a
PRESENCE PULSE.
RESET
(Sent by Host)
Presence Pulse
(Sent by bq2022A)
V
PU
V
IH
V
IL
t
t
PPD
PP
t
RST
t
RSTREC
Figure 6. Reset Timing Diagram
8.3.4 WRITE
The WRITE bit timing diagram in Figure 7 shows that the host initiates the transmission by issuing the tWSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
Write ”1”
Write ”0”
V
PU
V
V
IH
IL
t
t
rec
WSTRB
t
WDSU
t
WDH
Figure 7. Write Bit Timing Diagram
8.3.5 READ
The READ bit timing diagram in Figure 8 shows that the host initiates the transmission of the bit by issuing the
tRSTRB portion of the bit. The bq27320 then responds by either driving the DATA bus low to transmit a READ 0 or
releasing the DATA bus to transmit a READ 1.
Read ”1”
Read ”0”
V
PU
V
V
IH
IL
t
RSTRB
t
t
REC
ODD
t
ODHO
Figure 8. Read Bit Timing Diagram
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8.3.6 Program Pulse
V
PP
PU
V
t
t
t
t
PRE
PFE
PREC
PSU
t
EPROG
V
SS
Figure 9. Program Pulse Timing Diagram
8.3.7 IDLE
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in
IDLE. Bus transactions can resume at any time from the IDLE state.
8.3.8 CRC Generation
The bq27320 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can
compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the
bq27320 to determine if the ROM data has been received error-free by the bus master. The equivalent
polynomial function of this CRC is: X8 + X5 + X4 +1.
Under certain conditions, the bq27320 also generates an 8-bit CRC value using the same polynomial function
shown and provides this value to the bus master to validate the transfer of command, address, and data bytes
from the bus master to the bq27320. The bq27320 computes an 8-bit CRC for the command, address, and data
bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the
bus master to confirm proper transfer. Similarly, the bq27320 computes an 8-bit CRC for the command and
address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ
DATA/GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC
generator on the bq27320 is also used to provide verification of error-free data transfer as each page of data
from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command,
and for the eight bytes of information in the status memory field.
In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using
the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in
the 64-bit ROM portion of the bq27320 (for ROM reads) or the 8-bit CRC value computed within the bq27320.
The comparison of CRC values and decision to continue with an operation are determined entirely by the bus
master. No circuitry on the bq27320 prevents a command sequence from proceeding if the CRC stored in or
calculated by the bq27320 does not match the value generated by the bus master. Proper use of the CRC can
result in a communication channel with a high level of integrity.
CLK
DAT
Q
D
Q
D
Q
D
Q
D
+
Q
D
+
Q
D
Q
D
Q
D
+
R
R
R
R
R
R
R
R
UDG-02065
Figure 10. 8-Bit CRC Generator Circuit (X8 + X5 + X4 + 1)
8.3.9 Communications
8.3.9.1 I2C Interface
The bq27320 supports the standard I2C read, incremental read, quick read, one-byte write, and incremental write
functions. The 7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The first 8 bits of the I2C protocol are, therefore, 0xAA or 0xAB for write or read, respectively.
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Host generated
ADDR[6:0] 0 A
Gauge generated
S
CMD[7:0]
(a) 1-byte write
A
DATA [7:0]
A
P
S
ADDR[6:0]
1
A
DATA [7:0]
(b) quick read
DATA [7:0]
N P
S
ADDR[6:0] 0 A
CMD[7:0]
A
Sr
ADDR[6:0]
1
A
N P
(c) 1- byte read
S
ADDR[6:0] 0 A
CMD[7:0]
A
Sr
ADDR[6:0]
1
A
DATA [7:0]
A
A
. . .
DATA [7:0]
A . . . A P
N P
(d) incremental read
S
ADDR[6:0] 0 A
CMD[7:0]
A
DATA [7:0]
DATA [7:0]
(e) incremental write
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge , and P = Stop).
The quick read returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I2C communication engine, increments whenever data is acknowledged by the bq27320 or the I2C
master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data).
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x6B (NACK command):
8.3.9.2 I2C Time Out
The I2C engine releases both SDA and SCL if the I2C bus is held low for 2 seconds. If the bq27320 is holding the
lines, releasing them frees them for the master to drive the lines. If an external condition is holding either of the
lines low, the I2C engine enters the low-power sleep mode.
8.3.9.3 I2C Command Waiting Time
To ensure proper operation at 400 kHz, a t(BUF) ≥ 66 μs bus-free waiting time must be inserted between all
packets addressed to the bq27320. In addition, if the SCL clock frequency (fSCL) is > 100 kHz, use individual 1-
byte write commands for proper data flow control. The following diagram shows the standard waiting time
required between issuing the control subcommand the reading the status result. For read-write standard
command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands,
there is no waiting time required, but the host must not issue any standard command more than two times per
second. Otherwise, the gauge could result in a reset issue due to the expiration of the watchdog timer.
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S
S
S
ADDR [6:0] 0 A
CMD [7:0]
CMD [7:0]
CMD [7:0]
A
A
A
DATA [7:0]
DATA [7:0]
ADDR [6:0]
A
A
P
P
66ms
66ms
ADDR [6:0] 0 A
ADDR [6:0] 0 A
Sr
1
A
DATA [7:0]
A
DATA [7:0]
N P
66ms
Waiting time inserted between two 1-byte write packets for a subcommand and reading results
(required for 100 kHz < fSCL £ 400 kHz)
S
S
ADDR [6:0] 0 A
ADDR [6:0] 0 A
CMD [7:0]
CMD [7:0]
A
A
DATA [7:0]
ADDR [6:0]
A
DATA [7:0]
DATA [7:0]
A
P
66ms
DATA [7:0]
Sr
1
A
A
N P
66ms
Waiting time inserted between incremental 2-byte write packet for a subcommand and reading results
(acceptable for fSCL £ 100 kHz)
S
ADDR [6:0] 0 A
DATA [7:0]
CMD [7:0]
DATA [7:0]
A
Sr
ADDR [6:0]
66ms
1
A
DATA [7:0]
A
DATA [7:0]
A
A
N P
Waiting time inserted after incremental read
8.3.9.4 I2C Clock Stretching
A clock stretch can occur during all modes of fuel gauge operation. In SNOOZE and HIBERNATE modes, a short
clock stretch occurs on all I2C traffic as the device must wake-up to process the packet. In the other modes (BAT
INSERT CHECK, NORMAL) clock stretching only occurs for packets addressed for the fuel gauge. The majority
of clock stretch periods are small as the I2C interface performs normal data flow control. However, less frequent
yet more significant clock stretch periods may occur as blocks of data flash are updated. The following table
summarizes the approximate clock stretch duration for various fuel gauge operating conditions.
Approximate
Duration
Gauging Mode
Operating Condition/Comment
SLEEP
HIBERNATE
Clock stretch occurs at the beginning of all traffic as the device wakes up.
≤ 4 ms
Clock stretch occurs within the packet for flow control (after a start bit, ACK or first data bit).
Data flash block writes.
≤ 4 ms
72 ms
BAT INSERT
CHECK
NORMAL
Restored data flash block write after loss of power.
116 ms
8.4 Device Functional Modes
To minimize power consumption, the device has different power modes: NORMAL, SNOOZE, SLEEP,
HIBERNATE, and BAT INSERT CHECK. The bq27320 passes automatically between these modes, depending
upon the occurrence of specific events, though a system processor can initiate some of these modes directly.
•
•
In NORMAL mode, the gas gauge is fully powered and can execute any allowable task.
In SNOOZE mode, low-frequency and high-frequency oscillators are active. Although the SNOOZE mode has
higher current consumption than the SLEEP mode, it is also a reduced power mode.
•
•
•
In SLEEP mode, the gas gauge turns off the high-frequency oscillator and exists in a reduced-power state,
periodically taking measurements and performing calculations.
In HIBERNATE mode, the gas gauge is in a low-power state, but can be woken up by communication or
certain IO activity.
BAT INSERT CHECK mode is a powered up, but low-power halted, state, where the gas gauge resides when
no battery is inserted into the system.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq27320 system-side Li-Ion battery fuel gauge is a microcontroller peripheral that provides fuel gauging for
single-cell Li-Ion battery packs. The device requires little system microcontroller firmware development.
The fuel resides on the main board of the system and manages an embedded battery (non-removable) or
removable battery pack. To allow for optimal performance in the end application, special considerations must be
taken to ensure minimization of measurement error through proper printed circuit board (PCB) board layout.
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9.2 Typical Applications
Figure 11. Schematic
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9.2.1 Design Requirements
Several key parameters must be updated to align with a given application's battery characteristics. For highest
accuracy gauging, it is important to follow-up this initial configuration with a learning cycle to optimize resistance
and maximum chemical capacity (Qmax) values prior to sealing and shipping systems to the field. Successful
and accurate configuration of the fuel gauge for a target application can be used as the basis for creating a
"golden" gas gauge (.fs) file that can be written to all gauges, assuming identical pack design and Li-ion cell
origin (chemistry, lot, and so on). Calibration data is included as part of this golden GG file to cut down on
system production time. If going this route, it is recommended to average the voltage and current measurement
calibration data from a large sample size and use these in the golden file. Table 3, Key Data Flash Parameters
for Configuration, shows the items that should be configured to achieve reliable protection and accurate gauging
with minimal initial configuration.
Table 3. Key Data Flash Parameters for Configuration
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Set based on the nominal pack capacity as interpreted from cell manufacturer's
datasheet. If multiple parallel cells are used, should be set to N × Cell Capacity.
Design Capacity
1000
mAh
Set to 10 to convert all power values to cWh or to 1 for mWh. Design Energy
is divided by this value.
Design Energy Scale
Reserve Capacity-mAh
1
0
—
Set to desired runtime remaining (in seconds / 3600) × typical applied load
between reporting 0% SOC and reaching Terminate Voltage, if needed.
mAh
Should be configured using TI-supplied Battery Management Studio software.
Default open-circuit voltage and resistance tables are also updated in
conjunction with this step. Do not attempt to manually update reported Device
Chemistry as this does not change all chemistry information! Always update
chemistry using the appropriate software tool (that is, bqStudio).
Chem ID
0100
hex
Load Mode
Load Select
1
1
—
—
Set to applicable load model, 0 for constant current or 1 for constant power.
Set to load profile which most closely matches typical system load.
Set to initial configured value for Design Capacity. The gauge will update this
parameter automatically after the optimization cycle and for every regular
Qmax update thereafter.
Qmax Cell 0
1000
4200
mAh
mV
Set to nominal cell voltage for a fully charged cell. The gauge will update this
parameter automatically each time full charge termination is detected.
Cell0 V at Chg Term
Set to empty point reference of battery based on system needs. Typical is
between 3000 and 3200 mV.
Terminate Voltage
Ra Max Delta
3200
44
mV
mΩ
Set to 15% of Cell0 R_a 4 resistance after an optimization cycle is completed.
Set based on nominal charge voltage for the battery in normal conditions
(25°C, etc). Used as the reference point for offsetting by Taper Voltage for full
charge termination detection.
Charging Voltage
Taper Current
4200
100
100
60
mV
mA
mV
mA
mA
mA
mA
Set to the nominal taper current of the charger + taper current tolerance to
ensure that the gauge will reliably detect charge termination.
Sets the voltage window for qualifying full charge termination. Can be set
tighter to avoid or wider to ensure possibility of reporting 100% SOC in outer
JEITA temperature ranges that use derated charging voltage.
Taper Voltage
Sets threshold for gauge detecting battery discharge. Should be set lower than
minimal system load expected in the application and higher than Quit Current.
Dsg Current Threshold
Chg Current Threshold
Quit Current
Sets the threshold for detecting battery charge. Can be set higher or lower
depending on typical trickle charge current used. Also should be set higher
than Quit Current.
75
Sets threshold for gauge detecting battery relaxation. Can be set higher or
lower depending on typical standby current and exhibited in the end system.
40
Current profile used in capacity simulations at onset of discharge or at all times
if Load Select = 0. Should be set to nominal system load. Is automatically
updated by the gauge every cycle.
Avg I Last Run
–299
Power profile used in capacity simulations at onset of discharge or at all times
if Load Select = 0. Should be set to nominal system power. Is automatically
updated by the gauge every cycle.
Avg P Last Run
Sleep Current
–1131
15
mW
mA
Sets the threshold at which the fuel gauge enters SLEEP mode. Take care in
setting above typical standby currents else entry to SLEEP may be
unintentionally blocked.
20
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
Table 3. Key Data Flash Parameters for Configuration (continued)
NAME
DEFAULT
UNIT
RECOMMENDED SETTING
Calibrate this parameter using TI-supplied bqStudio software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to current.
CC Gain
CC Delta
10
mΩ
Calibrate this parameter using TI-supplied bqStudio software and calibration
procedure in the TRM. Determines conversion of coulomb counter measured
sense resistor voltage to passed charge.
10
–1418
0
mΩ
Calibrate this parameter using TI-supplied bqStudio software and calibration
procedure in the TRM. Determines native offset of coulomb counter hardware
that should be removed from conversions.
CC Offset
Board Offset
Counts
Counts
Calibrate this parameter using TI-supplied bqStudio software and calibration
procedure in the TRM. Determines native offset of the printed circuit board
parasitics that should be removed from conversions.
Calibrate this parameter using TI-supplied bqStudio software and calibration
procedure in the TRM. Determines voltage offset between cell tab and ADC
input node to incorporate back into or remove from measurement, depending
on polarity.
Pack V Offset
0
mV
9.2.2 Detailed Design Procedure
9.2.2.1 BAT Voltage Sense Input
A ceramic capacitor at the input to the BAT pin is used to bypass AC voltage ripple to ground, greatly reducing
its influence on battery voltage measurements. It proves most effective in applications with load profiles that
exhibit high-frequency current pulses (that is, cell phones) but is recommended for use in all applications to
reduce noise on this sensitive high-impedance measurement node.
9.2.2.2 SRP and SRN Current Sense Inputs
The filter network at the input to the coulomb counter is intended to improve differential mode rejection of voltage
measured across the sense resistor. These components should be placed as close as possible to the coulomb
counter inputs and the routing of the differential traces length-matched to best minimize impedance mismatch-
induced measurement errors.
9.2.2.3 Sense Resistor Selection
Any variation encountered in the resistance present between the SRP and SRN pins of the fuel gauge will affect
the resulting differential voltage, and derived current, it senses. As such, it is recommended to select a sense
resistor with minimal tolerance and temperature coefficient of resistance (TCR) characteristics. The standard
recommendation based on best compromise between performance and price is a 1% tolerance, 100-ppm drift
sense resistor with a 1-W power rating.
9.2.2.4 TS Temperature Sense Input
Similar to the BAT pin, a ceramic decoupling capacitor for the TS pin is used to bypass AC voltage ripple away
from the high-impedance ADC input, minimizing measurement error. Another helpful advantage is that the
capacitor provides additional ESD protection since the TS input to system may be accessible in systems that use
removable battery packs. It should be placed as close as possible to the respective input pin for optimal filtering
performance.
9.2.2.5 Thermistor Selection
The fuel gauge temperature sensing circuitry is designed to work with a negative temperature coefficient-type
(NTC) thermistor with a characteristic 10-kΩ resistance at room temperature (25°C). The default curve-fitting
coefficients configured in the fuel gauge specifically assume a 103AT-2 type thermistor profile and so that is the
default recommendation for thermistor selection purposes. Moving to a separate thermistor resistance profile (for
example, JT-2 or others) requires an update to the default thermistor coefficients in data flash to ensure highest
accuracy temperature measurement performance.
Copyright © 2016, Texas Instruments Incorporated
21
bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
9.2.2.6 REGIN Power Supply Input Filtering
A ceramic capacitor is placed at the input to the fuel gauge internal LDO to increase power supply rejection
(PSR) and improve effective line regulation. It ensures that voltage ripple is rejected to ground instead of
coupling into the internal supply rails of the fuel gauge.
9.2.2.7 VCC LDO Output Filtering
A ceramic capacitor is also needed at the output of the internal LDO to provide a current reservoir for fuel gauge
load peaks during high peripheral utilization. It acts to stabilize the regulator output and reduce core voltage
ripple inside of the fuel gauge.
9.2.3 Application Curves
2.65
2.6
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
VREGIN = 2.7 V
VREGIN = 4.5 V
2.55
2.5
2.45
2.4
2.35
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D001
D002
Figure 12. Regulator Output Voltage vs. Temperature
Figure 13. High-Frequency Oscillator Frequency vs.
Temperature
34
5
4
33.5
33
3
2
32.5
32
1
0
-1
-2
-3
-4
-5
31.5
31
30.5
30
-40
-20
0
20
40
60
80
100
-30
-20
-10
0
10
20
30
40
50
60
Temperature (èC)
Temperature (èC)
D003
D004
Figure 14. Low-Frequency Oscillator Frequency vs.
Temperature
Figure 15. Reported Internal Temperature Measurement
vs. Temperature
22
Copyright © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
10 Power Supply Recommendations
10.1 Power Supply Decoupling
Both the REGIN input pin and the VCC output pin require low equivalent series resistance (ESR) ceramic
capacitors placed as closely as possible to the respective pins to optimize ripple rejection and provide a stable
and dependable power rail that is resilient to line transients. A 0.1-µF capacitor at the REGIN and a 1-µF
capacitor at VCC will suffice for satisfactory device performance.
11 Layout
11.1 Layout Guidelines
11.1.1 Sense Resistor Connections
Kelvin connections at the sense resistor are just as critical as those for the battery terminals themselves. The
differential traces should be connected at the inside of the sense resistor pads and not anywhere along the high-
current trace path to prevent false increases to measured current that could result when measuring between the
sum of the sense resistor and trace resistance between the tap points. In addition, the routing of these leads
from the sense resistor to the input filter network and finally into the SRP and SRN pins needs to be as closely
matched in length as possible else additional measurement offset could occur. It is further recommended to add
copper trace or pour-based "guard rings" around the perimeter of the filter network and coulomb counter inputs to
shield these sensitive pins from radiated EMI into the sense nodes. This prevents differential voltage shifts that
could be interpreted as real current change to the fuel gauge. All of the filter components need to be placed as
close as possible to the coulomb counter input pins.
11.1.2 Thermistor Connections
The thermistor sense input should include a ceramic bypass capacitor placed as close to the TS input pin as
possible. The capacitor helps to filter measurements of any stray transients as the voltage bias circuit pulses
periodically during temperature sensing windows.
11.1.3 High-Current and Low-Current Path Separation
For best possible noise performance, it is extremely important to separate the low-current and high-current loops
to different areas of the board layout. The fuel gauge and all support components should be situated on one side
of the boards and tap off of the high-current loop (for measurement purposes) at the sense resistor. Routing the
low-current ground around instead of under high-current traces will further help to improve noise rejection.
Copyright © 2016, Texas Instruments Incorporated
23
bq27320
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
www.ti.com.cn
11.2 Layout Example
Battery power
connection to
system
Use copper
pours for battery
power path to
minimize IR
losses
SCL
SDA
To system host
processor
BAT_LOW
BAT_GD
BATTERY PACK
CONNECTOR
C1
PACK+
Kelvin connect the
BAT sense line right
at positive terminal to
battery pack
C2
C3
REGIN
BAT
BI/TOUT
CE
THERM
TS
VCC
VSS
SRN
BAT_LOW
VSS
SOC_INT
SDA
BAT_GD
SOC_INT
SCL
SRP
Ground return to
system
PACK–
10 mΩ 1%
Kelvin connect SRP
and SRN
Via connects to Power Ground
connections right at
Rsense terminals
Figure 16. Layout Recommendation
24
版权 © 2016, Texas Instruments Incorporated
bq27320
www.ti.com.cn
ZHCSEV6A –FEBRUARY 2016–REVISED MARCH 2016
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：《bq27320 技术参考手册》（文献编号：SLUUAN6）
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
NanoFree, E2E are trademarks of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ27320YZFR
BQ27320YZFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YZF
YZF
15
15
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ27320
BQ27320
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ27320YZFR
BQ27320YZFT
DSBGA
DSBGA
YZF
YZF
15
15
3000
250
180.0
180.0
8.4
8.4
2.1
2.1
2.76
2.76
0.81
0.81
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ27320YZFR
BQ27320YZFT
DSBGA
DSBGA
YZF
YZF
15
15
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0015
DSBGA - 0.625 mm max height
SCALE 6.500
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
0.35
0.15
BALL TYP
1 TYP
SYMM
E
D
SYMM
2
TYP
C
B
D: Max = 2.64 mm, Min = 2.58 mm
E: Max = 1.986 mm, Min =1.926 mm
0.5
TYP
A
1
2
3
0.35
0.25
C A B
15X
0.5 TYP
0.015
4219381/A 02/2017
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
15X ( 0.245)
(0.5) TYP
1
3
2
A
B
SYMM
C
D
E
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MAX
0.05 MIN
(
0.245)
METAL
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
(
0.245)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219381/A 02/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0015
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
15X ( 0.25)
1
2
3
A
B
(0.5)
TYP
METAL
TYP
SYMM
C
D
E
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219381/A 02/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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