BQ28Z610DRZT-R1 [TI]
适用于 1-2 节串联电池组并具有集成保护器的电池电量监测计 | DRZ | 12 | -40 to 85;
| 型号： | BQ28Z610DRZT-R1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 1-2 节串联电池组并具有集成保护器的电池电量监测计 | DRZ | 12 | -40 to 85 电池 |
| 文件： | 总39页 (文件大小：1998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ28Z610-R1
ZHCSKR6B –JANUARY 2020 –REVISED JANUARY 2022
BQ28Z610-R1 适用于1-2 芯串联锂离子电池组的
Impedance Track™ 电量监测计和保护解决方案
1 特性
3 说明
• 采用专用主模式I2C 接口实现自主电池充电控制
• 采用内部旁路实现电芯均衡，优化电池运行状况
• 高侧保护N 沟道FET 驱动器可在故障期间实现串
行总线通信
• 适用于电压、电流和温度的可编程保护等级
• 具备两个独立ADC 的模拟前端
德州仪器 (TI) 的 BQ28Z610-R1 器件是一款高度集成
的高精度1-2 芯串联电池电量监测计和保护解决方案，
可实现自主的电荷控制和电芯均衡。
BQ28Z610-R1 器件通过主模式 I2C 广播充电电流和电
压信息，可实现自主电荷控制，从而消除通常由系统主
机控制器产生的软件开销。
– 支持电流和电压同步采样
– 高精度库伦计数器，输入失调电压误差< 1µV
（典型值）
BQ28Z610-R1 器件提供了一个基于电池组的全集成解
决方案，该解决方案具备闪存可编程的定制精简指令集
CPU (RISC)、安全保护以及认证功能，适用于 1-2 芯
串联锂离子和锂聚合物电池组。
• 支持低至1mΩ的电流感应电阻器，同时支持1mA
电流测量
• 支持电池跳变点(BTP) 功能，用于Windows® 集成
• SHA-1 认证响应器，用于提高电池组安全性
• 适用于高速编程和数据访问的400kHz I2C 总线通
信接口
BQ28Z610-R1 电量监测计通过 I2C 兼容接口进行通
信，并将超低功耗的高速 TI BQBMP 处理器、高精度
模拟测量功能、集成闪存、大量的外设和通信端口、N
沟道FET 驱动器以及SHA-1 认证转换响应器融合于一
套完整的高性能电池管理解决方案。
• 紧凑型12 引脚VSON 封装(DRZ)
2 应用
器件信息
器件型号(1)
封装尺寸（标称值）
封装
VSON (12)
• 平板电脑计算
• 便携式和可佩戴式健康设备
• 便携式音频设备
BQ28Z610-R1
4mm x 2.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 无线(Bluetooth®) 扬声器
Pack
+
10 M
10 M
Audio
Power Amp
Fuse
Boost Converter
Battery
13
100
1 µF
5
1
2
3
VC1 12
VSS
SRN
PWPD
2 s
0.1
µF
Gauge
Charger
1 s
11
VC2
0.1 µF
5.1 k
5.1 k
SRP
TS1
10
9
PBI
Audio Processor
MCU
2.2 µF
Battery
cells
4
5
CHG
10k
10
100
100
100
PACK
8
Pack Side
System Side
SCL
SDA
2
I
C
Comm
Bus
MM3Z5V6C
100
6
7
DSG
Power
Copyright
© 2017, Texas Instruments Incorporated
MM3Z5V6C
100
100
无线(Bluetooth®) 扬声器应用
方框图
Pack–
Copyright © 2016 Texas Instruments Incorporated
,
1 to10 mΩ
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSE07
BQ28Z610-R1
ZHCSKR6B –JANUARY 2020 –REVISED JANUARY 2022
www.ti.com.cn
Table of Contents
7.23 Current Protection Thresholds................................10
7.24 Current Protection Timing....................................... 11
7.25 N-CH FET Drive (CHG, DSG).................................12
7.26 I2C Interface I/O...................................................... 12
7.27 I2C Interface Timing ............................................... 12
7.28 Typical Characteristics............................................14
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................22
9 Applications and Implementation................................24
9.1 Application Information............................................. 24
9.2 Typical Applications.................................................. 24
10 Power Supply Recommendations..............................27
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 第三方产品免责声明................................................30
12.2 Documentation Support.......................................... 30
12.3 接收文档更新通知................................................... 30
12.4 支持资源..................................................................30
12.5 Trademarks.............................................................30
12.6 Electrostatic Discharge Caution..............................30
12.7 术语表..................................................................... 30
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Supply Current............................................................5
7.6 Power Supply Control................................................. 5
7.7 Low-Voltage General Purpose I/O, TS1......................6
7.8 Power-On Reset (POR).............................................. 6
7.9 Internal 1.8-V LDO......................................................6
7.10 Current Wake Comparator........................................7
7.11 Coulomb Counter......................................................7
7.12 ADC Digital Filter...................................................... 7
7.13 ADC Multiplexer........................................................8
7.14 Cell Balancing Support............................................. 8
7.15 Internal Temperature Sensor.................................... 8
7.16 NTC Thermistor Measurement Support....................8
7.17 High-Frequency Oscillator........................................ 8
7.18 Low-Frequency Oscillator......................................... 9
7.19 Voltage Reference 1................................................. 9
7.20 Voltage Reference 2................................................. 9
7.21 Instruction Flash........................................................9
7.22 Data Flash...............................................................10
Information.................................................................... 30
4 Revision History
Changes from Revision A (February 2020) to Revision B (January 2022)
Page
• Changed Absolute Maximum Ratings ............................................................................................................... 4
Changes from Revision * (February 2020) to Revision A (February 2020)
Page
• Changed I2C Interface I/O ............................................................................................................................... 12
5 说明（续）
BQ28Z610-R1 器件提供大量的电池和系统安全功能，其中包括对电池提供放电过流、充电短路和放电短路保护，
对N 沟道FET 提供FET 保护，内部AFE 看门狗以及电芯均衡功能。该器件可通过固件添加更多保护特性，例如
过压、欠压、过热等。
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6 Pin Configuration and Functions
VSS
SRN
SRP
TS1
SCL
SDA
1
2
3
4
5
6
12
11
10
9
VC1
VC2
PBI
Thermal
Pad
CHG
PACK
DSG
8
7
Not to scale
图6-1. DRZ Package 12-Pin VSON Top View
表6-1. Pin Functions
PIN NUMBER PIN NAME
TYPE
DESCRIPTION
1
2
VSS
SRN
P(1)
Device ground
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
AI
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
3
4
SRP
TS1
AI
AI
Temperature input for ADC to the oversampled ADC channel, and optional Battery Trip
Point (BTP) output
5
6
SCL
SDA
DSG
PACK
CHG
PBI
I/O
I/O
O
Serial Clock for I2C interface; requires external pullup when used
Serial Data for I2C interface; requires external pullup
N-CH FET drive output pin
7
8
AI, P
O
Pack sense input pin
9
N-CH FET drive output pin
10
P
Power supply backup input pin
Sense voltage input pin for most positive cell, balance current input for most positive cell.
Primary power supply input and battery stack measurement input (BAT)
11
12
VC2
AI, P
VC1
AI
Sense voltage input pin for least positive cell, balance current input for least positive cell
Exposed Pad, electrically connected to VSS (external trace)
PWPD
—
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/O = Digital Input/Output
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
30
UNIT
Supply voltage range, VCC
Input voltage range, VIN
VC2, PBI
PACK
V
V
V
V
–0.3
–0.3
–0.3
–0.3
30
TS
VREG + 0.3
VREG + 0.3
SRP, SRN
VC1 + 8.5 or
VSS + 30
VC2
VC1
V
V
VC1 –0.3
VSS –0.3
VSS + 8.5 or
VSS + 30
Communication Interface
Output voltage range, VO
Maximum VSS current, ISS
Functional Temperature, TFUNC
SDA, SCL
CHG, DSG
6
V
V
–0.3
–0.3
32
±50
110
±300
150
mA
°C
°C
°C
–40
–65
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature range, TSTG
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
2.2
NOM
MAX UNIT
VCC
Supply voltage
Shutdown voltage
Start-up voltage
VC2, PBI
26
2.2
V
VSHUTDOWN–
VSHUTDOWN+
VPACK < VSHUTDOWN –
VPACK > VSHUTDOWN– + VHYS
1.8
2.0
V
V
2.05
2.25
2.45
Shutdown voltage
hysteresis
VHYS
250
mV
V
V
SHUTDOWN+ –VSHUTDOWN–
SDA, SCL
TS1
5.5
VREG
0.2
SRP, SRN
VC2
–0.2
VVC1
VVSS
VIN
Input voltage range
VVC1 + 5
VVSS + 5
26
VC1
PACK
VO
Output voltage range
External PBI capacitor
CHG, DSG
26
V
CPBI
2.2
µF
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7.3 Recommended Operating Conditions (continued)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX UNIT
85 °C
TOPR
Operating temperature
–40
7.4 Thermal Information
BQ28Z610-R1
DRZ
THERMAL METRIC(1)
UNIT
12 PINS
186.4
90.4
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
110.7
96.7
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJT
90
ψJB
RθJC(bottom)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report (SPRA953).
7.5 Supply Current
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
(1)
INORMAL
NORMAL mode
SLEEP mode
CHG = ON, DSG = ON, No Flash Write
250
µA
CHG = OFF, DSG = OFF, No Communication on
Bus
(1)
ISLEEP
100
0.5
ISHUTDOWN
SHUTDOWN mode
2
µA
(1) Dependent on the use of the correct firmware (FW) configuration
7.6 Power Supply Control
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VVC2 < VSWITCHOVER–
VVC2 > VSWITCHOVER– + VHYS
SWITCHOVER+ –VSWITCHOVER–
MIN
TYP
MAX
UNIT
VC2 to PACK
VSWITCHOVER–
VSWITCHOVER+
VHYS
2.0
2.1
2.2
V
switchover voltage
PACK to VC2
3.0
3.1
3.2
V
switchover voltage
Switchover voltage
hysteresis
1000
mV
V
VC2 pin, VC2 = 0 V, PACK = 25 V
PACK pin, VC2 = 25 V, PACK = 0 V
1
1
Input Leakage
current
ILKG
µA
VC2 and PACK pins, VC2 = 0 V, PACK = 0 V,
PBI = 25 V
1
Internal pulldown
resistance
RPACK(PD)
PACK
30
40
50
kΩ
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7.7 Low-Voltage General Purpose I/O, TS1
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
0.35 x VREG
0.2 x VREG
UNIT
V
VIH
VIL
High-level input
0.65 x VREG
Low-level input
V
VOH
VOL
CIN
Output voltage high
0.75 x VREG
V
IOH = –1.0 mA
Output voltage low IOL = 1.0 mA
Input capacitance
V
5
pF
Input leakage
current
ILKG
1
µA
7.8 Power-On Reset (POR)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Negative-going voltage
input
VREGIT–
VREG
REGIT+ –VREGIT–
1.51
1.55
1.59
V
Power-on reset
hysteresis
VHYS
tRST
70
100
300
130
400
mV
µs
V
Power-on reset time
200
7.9 Internal 1.8-V LDO
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VREG
Regulator voltage
1.6
1.8
2.0
V
Regulator output over
temperature
±0.25%
ΔVO(TEMP)
ΔVREG/ΔTA, IREG = 10 mA
Line regulation
Load regulation
0.5%
1.5%
ΔVO(LINE)
ΔVO(LOAD)
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6%
–1.5%
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
Regulator output
current limit
IREG
VREG = 0.9 x VREG(NOM), VIN > 2.2 V
VREG = 0 x VREG(NOM)
ΔVBAT/ΔVREG, IREG = 10 mA, VIN > 2.5 V, f = 10 Hz
20
25
mA
mA
dB
V
Regulator short-circuit
current limit
ISC
40
40
50
Power supply rejection
ratio
PSRRREG
VSLEW
Slew rate enhancement
voltage threshold
VREG
1.58
1.65
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7.10 Current Wake Comparator
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VWAKE = VSRP –VSRN WAKE_CONTROL[WK1,
WK0] = 0,0
±0.3
±0.625
±0.9
±1.8
±3.6
±7.2
mV
VWAKE = VSRP –VSRN WAKE_CONTROL[WK1,
WK0] = 0,1
±0.6
±1.2
±2.4
±1.25
±2.5
±5.0
0.5%
0.25
250
mV
mV
mV
°C
Wake voltage
threshold
VWAKE
VWAKE = VSRP –VSRN WAKE_CONTROL[WK1,
WK0] = 1,0
VWAKE = VSRP –VSRN WAKE_CONTROL[WK1,
WK0] = 1,1
Temperature drift of
VWAKE accuracy
VWAKE(DRIFT)
Time from application
of current to wake
tWAKE
0.5
ms
µs
Wake up comparator
startup time
[WKCHGEN] = 0 and [WKDSGEN] = 0 to
[WKCHGEN] = 1 and [WKDSGEN] = 1
tWAKE(SU)
640
7.11 Coulomb Counter
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
–100
TYP
MAX UNIT
Input voltage range
Full scale range
Differential nonlinearity
Integral nonlinearity
Offset error
100
+VREF1/10
±1
mV
mV
LSB
LSB
LSB
–VREF1/10
16-bit, no missing codes
16-bit, best fit over input voltage range
16-bit, post-calibration
±5.2
±1.3
0.04
±131
4.3
±22.3
±2.6
Offset error drift
Gain error
15-bit + sign, post-calibration
15-bit + sign, over input voltage range
15-bit + sign, over input voltage range
0.07 LSB/°C
±492 LSB
Gain error drift
9.8 LSB/°C
Effective input resistance
2.5
MΩ
7.12 ADC Digital Filter
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2
V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
31.25
15.63
7.81
MAX UNIT
ADCTL[SPEED1, SPEED0] = 0, 0
ADCTL[SPEED1, SPEED0] = 0, 1
ADCTL[SPEED1, SPEED0] = 1, 0
ADCTL[SPEED1, SPEED0] = 1, 1
tCONV
ms
1.95
No missing codes, ADCTL[SPEED1, SPEED0] =
0, 0
Resolution
16
Bits
Bits
With sign, ADCTL[SPEED1, SPEED0] = 0, 0
With sign, ADCTL[SPEED1, SPEED0] = 0, 1
With sign, ADCTL[SPEED1, SPEED0] = 1, 0
With sign, ADCTL[SPEED1, SPEED0] = 1, 1
14
13
11
9
15
14
12
10
Effective resolution
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7.13 ADC Multiplexer
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2
V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
VC1–VSS, VC2–VC1
VC2–VSS, PACK–VSS
VREF1/2
MIN
0.1980
0.0485
0.490
–0.2
TYP
0.2000
0.050
MAX UNIT
0.2020
K
Scaling factor
0.051
0.510
—
0.500
20
VC2–VSS, PACK–VSS
TS1
VIN
Input voltage range
Input leakage current
0.8 × VREF1
0.8 × VREG
V
–0.2
TS1
–0.2
VC1, VC2 cell balancing off, cell detach detection off,
ADC multiplexer off
ILKG
1
µA
7.14 Cell Balancing Support
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
Internal cell balance
resistance
TEST CONDITION
MIN
TYP
MAX UNIT
200
RCB
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
Ω
7.15 Internal Temperature Sensor
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
–1.9
0.177
TYP
–2.0
0.178
MAX UNIT
VTEMPP
–2.1
Internal temperature
VTEMP
mV/°C
sensor voltage drift
(1)
0.179
V
TEMPP –VTEMPN
(1) Assured by design
7.16 NTC Thermistor Measurement Support
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Internal pull-up
resistance
RNTC(PU)
TS1
14.4
18
21.6
kΩ
Resistance drift over
temperature
RNTC(DRIFT)
TS1
PPM/°C
–360
–280
–200
7.17 High-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
16.78
MAX UNIT
MHz
fHFO
Operating frequency
±0.25%
±0.25%
2.5%
3.5%
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–2.5%
–3.5%
fHFO(ERR)
Frequency error
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7.17 High-Frequency Oscillator (continued)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
TA = –20°C to 85°C, Oscillator frequency within +/–
3% of nominal, CLKCTL[HFRAMP] = 1
4
ms
µs
tHFO(SU)
Start-up time
Oscillator frequency within +/–3% of nominal,
CLKCTL[HFRAMP] = 0
100
7.18 Low-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
fLFO
Operating frequency
262.144
kHz
kHz
Operating frequency in
low power mode
fLFO(LP)
247
±0.25%
±0.25%
1.5%
2.5%
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–1.5%
–2.5%
fLFO(ERR)
Frequency error
Frequency error in low
power mode
fLFO(LPERR)
5%
–5%
Failure detection
frequency
fLFO(FAIL)
30
80
100
kHz
7.19 Voltage Reference 1
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF1
TA = 25°C, after trim
1.215
1.220
1.225
V
TA = 0°C to 60°C, after trim
±50
±80
Internal reference
voltage drift
VREF1(DRIFT)
PPM/°C
TA = –40°C to 85°C, after trim
7.20 Voltage Reference 2
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Internal reference
voltage
VREF2
TA = 25°C, after trim
1.215
1.220
1.225
V
TA = 0°C to 60°C, after trim
±50
±80
Internal reference
voltage drift
VREF2(DRIFT)
PPM/°C
TA = –40°C to 85°C, after trim
7.21 Instruction Flash
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Years
Data retention
10
Flash programming
write cycles
1000
Cycles
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7.21 Instruction Flash (continued)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
Word programming
time
TEST CONDITION
MIN
TYP
MAX UNIT
tPROGWORD
40
µs
TA = –40°C to 85°C
tMASSERASE Mass-erase time
tPAGEERASE Page-erase time
IFLASHREAD Flash-read current
IFLASHWRITE Flash-write current
IFLASHERASE Flash-erase current
40
40
2
ms
ms
mA
mA
mA
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
5
15
7.22 Data Flash
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
Years
Data retention
10
Flash programming
write cycles
20000
Cycles
µs
Word programming
time
tPROGWORD
40
TA = –40°C to 85°C
tMASSERASE Mass-erase time
tPAGEERASE Page-erase time
IFLASHREAD Flash-read current
IFLASHWRITE Flash-write current
IFLASHERASE Flash-erase current
40
40
1
ms
ms
mA
mA
mA
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
5
15
7.23 Current Protection Thresholds
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VOCD = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–16.6
–100
OCD detection threshold
voltage range
VOCD
mV
VOCD = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
–8.3
–50
VOCD = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–5.56
–2.78
OCD detection threshold
voltage program step
mV
mV
mV
ΔVOCD
ΔVSCC
ΔVSCC
VOCD = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCC = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
44.4
22.2
200
100
SCC detection threshold
voltage range
VSCC = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCC = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
22.2
11.1
SCC detection threshold
voltage program step
VSCC = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
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7.23 Current Protection Thresholds (continued)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VSCD1 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–44.4
–200
SCD1 detection threshold
voltage range
VSCD1
mV
VSCD1 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
–22.2
–100
VSCD1 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–22.2
–11.1
SCD1 detection threshold
voltage program step
mV
mV
mV
ΔVSCD1
VSCD1 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–44.4
–22.2
–200
–100
SCD2 detection threshold
voltage range
VSCD2
VSCD2 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
VSCD2 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 1
–22.2
–11.1
SCD2 detection threshold
voltage program step
ΔVSCD2
VSCD2 = VSRP –VSRN,
PROTECTION_CONTROL[RSNS] = 0
7.24 Current Protection Timing
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX UNIT
OCD detection delay
time
tOCD
1
31
ms
ms
µs
OCD detection delay
time program step
2
ΔtOCD
tSCC
SCC detection delay
time
0
915
SCC detection delay
time program step
61
µs
ΔtSCC
PROTECTION_CONTROL[SCDDx2] = 0
0
0
915
SCD1 detection delay
time
tSCD1
µs
µs
µs
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
PROTECTION_CONTROL[SCDDx2] = 0
PROTECTION_CONTROL[SCDDx2] = 1
1850
61
SCD1 detection delay
time program step
ΔtSCD1
121
0
0
458
915
SCD2 detection delay
time
tSCD2
30.5
61
SCD2 detection delay
time program step
µs
µs
ΔtSCD2
V
V
SRP –VSRN = VT –3 mV for OCD, SCD1, and SC2,
SRP –VSRN = VT + 3 mV for SCC
tDETECT
tACC
Current fault detect time
160
Current fault delay time
accuracy
Max delay setting
10%
–10%
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7.25 N-CH FET Drive (CHG, DSG)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
RatioDSG = (VDSG –VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V,
10 MΩbetween PACK and DSG
2.133
2.333
2.467
Output voltage ratio
—
RatioCHG = (VCHG –VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V,
10 MΩbetween BAT and CHG
2.133
8.75
2.333
9.5
2.467
10.25
10.25
0.4
VDSG(ON) = VDSG –VVC2, 4.07 V ≤VVC2 ≤18 V, 10 MΩ
between PACK and DSG
Output voltage,
CHG and DSG on
V(FETON)
V
V
VCHG(ON) = VCHG –VVC2, 4.07 V ≤VVC2 ≤18 V, 10 MΩ
between VC2 and CHG
8.75
9.5
VDSG(OFF) = VDSG –VPACK, 10 MΩbetween PACK and
DSG
–0.4
–0.4
Output voltage,
CHG and DSG off
V(FETOFF)
VCHG(OFF) = VCHG –VBAT, 10 MΩbetween VC2 and
CHG
0.4
VDSG from 0% to 35% VDSG (ON)(TYP), VBAT ≥2.2 V, CL =
4.7 nF between DSG and PACK, 5.1 kΩbetween DSG
and CL, 10 MΩbetween PACK and DSG
200
200
40
500
500
300
200
tR
Rise time
µs
µs
VCHG from 0% to 35% VCHG (ON)(TYP), VVC2 ≥2.2 V, CL =
4.7 nF between CHG and VC2, 5.1 kΩbetween CHG and
CL, 10 MΩbetween VC2 and CHG
VDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩbetween DSG and CL,
10 MΩbetween PACK and DSG
tF
Fall time
VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥2.2 V, CL = 4.7 nF
between CHG and VC2, 5.1 kΩbetween CHG and CL, 10
MΩbetween VC2 and CHG
40
7.26 I2C Interface I/O
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
0.7 × VREG
–0.5
TYP
MAX UNIT
VIH
VIL
Input voltage high
SCL, SDA (STANDARD and FAST modes)
SCL, SDA (STANDARD and FAST modes)
SCL, SDA, IOL = 1 mA (STANDARD and FAST modes)
V
Input voltage low
Output low voltage
Input capacitance
0.3 × VREG
0.2 × VREG
10
V
V
VOL
CIN
pF
Input leakage
current
ILKG
RPD
1
µA
Pull-down resistance
3.3
kΩ
7.27 I2C Interface Timing
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
Clock rise time
Clock fall time
Clock high period
Clock low period
TEST CONDITION
MIN
NOM
MAX
300
UNIT
ns
tR
10% to 90%
90% to 10%
tF
300
ns
tHIGH
tLOW
600
1.3
ns
µs
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7.27 I2C Interface Timing (continued)
Typical values stated where TA = 25°C and VCC = 7.2 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 7.6 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
Repeated start setup
time
tSU(START)
td(START)
600
ns
Start for first falling
edge to SCL
600
ns
tSU(DATA)
tHD(DATA)
tSU(STOP)
Data setup time
Data hold time
Stop setup time
100
0
ns
µs
ns
600
Bus free time
between stop and
start
tBUF
1.3
µs
Clock operating
frequency
fSW
SLAVE mode, SCL 50% duty cycle
400
kHz
t
t
t
t
t
f
t
w(L)
r
(BUF)
SU(STA)
w(H)
SCL
SDA
t
t
t
d(STA)
su(STOP)
f
t
r
t
t
su(DAT)
h(DAT)
REPEATED
START
STOP
START
图7-1. I2C Timing
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7.28 Typical Characteristics
±8.
ꢀ8.
0.15
Max CC Offset Error
Min CC Offset Error
0.10
0.05
ꢁ8.
ꢂ8.
0.00
.8.
±ꢂ8.
±ꢁ8.
±ꢀ8.
±±8.
œ0.05
œ0.10
œ0.15
Max ADC Offset Error
Min ADC Offset Error
0
20
40
60
80
100
120
œ40
œ20
.
ꢂ.
ꢁ.
ꢀ.
±.
1..
1ꢂ.
±ꢁ.
±ꢂ.
Temperature (°C)
C001
Temperature (°C)
C..3
图7-2. CC Offset Error vs Temperature
图7-3. ADC Offset Error vs Temperature
1.24
1.23
1.22
1.21
1.20
264
262
260
258
256
254
252
250
0
20
40
60
80
100
0
20
40
60
80
100
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C006
C007
图7-4. Reference Voltage vs Temperature
图7-5. Low-Frequency Oscillator vs Temperature
16.9
16.8
16.7
16.6
–24.6
–24.8
–25.0
–25.2
–25.4
–25.6
–25.8
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
–40
–20
Temperature (°C)
Temperature (°C)
C008
C009
图7-6. High-Frequency Oscillator vs Temperature
Threshold setting is 25 mV.
图7-7. Overcurrent Discharge Protection Threshold vs
Temperature
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7.28 Typical Characteristics (continued)
87.4
87.2
87.0
86.8
86.6
86.4
86.2
œ86.0
œ86.2
œ86.4
œ86.6
œ86.8
œ87.0
œ87.2
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C010
C011
Threshold setting is 88.8 mV.
Threshold setting is –88.8 mV.
图7-8. Short Circuit Charge Protection Threshold vs
图7-9. Short Circuit Discharge 1 Protection Threshold vs
Temperature
Temperature
11.00
10.95
10.90
10.85
10.80
10.75
10.70
œ172.9
œ173.0
œ173.1
œ173.2
œ173.3
œ173.4
œ173.5
œ173.6
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C012
C013
Threshold setting is 11 ms.
Threshold setting is –177.7 mV.
图7-11. Overcurrent Delay Time vs Temperature
图7-10. Short Circuit Discharge 2 Protection Threshold vs
Temperature
452
450
448
446
444
442
440
438
436
434
432
480
460
440
420
400
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C014
C015
Threshold setting is 465 µs.
Threshold setting is 465 µs (including internal delay).
图7-12. Short Circuit Charge Current Delay Time vs
图7-13. Short Circuit Discharge 1 Delay Time vs Temperature
Temperature
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7.28 Typical Characteristics (continued)
2.4984
2.49835
2.4983
2.49825
2.4982
2.49815
2.4981
2.49805
2.498
3.49825
3.4982
3.49815
3.4981
3.49805
3.498
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Temperature (°C)
Temperature (°C)
C017
C016
图7-14. VCELL Measurement at 2.5-V vs Temperature
This is the VCELL average for single cell.
图7-15. VCELL Measurement at 3.5-V vs Temperature
4.24805
4.248
99.25
99.20
99.15
99.10
99.05
99.00
4.24795
4.2479
4.24785
4.2478
0
20
40
60
80
100
120
œ40
œ20
0
20
40
60
80
100
120
œ40
œ20
Temperature (°C)
Temperature (°C)
C018
C019
A.
This is the VCELL average for single cell.
ISET = 100 mA, RSNS= 1 Ω
图7-17. I Measured vs Temperature
图7-16. VCELL Measurement at 4.25-V vs Temperature
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8 Detailed Description
8.1 Overview
The BQ28Z610-R1 gas gauge is a fully integrated battery manager that employs flash-based firmware and
integrated hardware protection to provide a complete solution for battery-stack architectures composed of 1- to
2-series cells. The BQ28Z610-R1 device interfaces with a host system via an I2C protocol. High-performance,
integrated analog peripherals enable support for a sense resistor down to 1 mΩ and simultaneous current/
voltage data conversion for instant power calculations. The following sections detail all of the major component
blocks included as part of the BQ28Z610-R1 device.
8.2 Functional Block Diagram
The Functional Block Diagram depicts the analog (AFE) and digital (AGG) peripheral content in the BQ28Z610-
R1 device.
High Side
N-CH FET
Drive
Cell, Stack,
Pack
Voltage
Cell
Balancing
Cell Detach
Detection
Power Mode
Control
Zero Volt
Charge
Control
Wake
Comparator
Power On
Reset
Short Circuit
Comparator
Over
Current
Comparator
Voltage
Reference2
Watchdog
Timer
Interrupt
NTC Bias
Internal
Temp
Sensor
(
AD0/RC0 TS1
)
Internal
Reset
Voltage
Reference1
ADC MUX
AFE Control
Low
Frequency
Oscillator
ADC/CC
FRONTEND
AFE COM
Engine
1.8V LDO
Regulator
SRP
SRN
SDA
SCL
High
Frequency
Oscillator
Low Voltage
I/O
I/O &
Interrupt
Controller
In-Circuit
Emulator
ADC/CC
Digital Filter
Timers&
PWM
AFE COM
Engine
COM
Engine
Data (8bit)
DMAddr (16bit)
bqBMP
CPU
PMInstr
(8bit)
PMAddr
(16bit)
Program
Flash
EEPROM
Data Flash
EEPROM
Data
SRAM
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8.3 Feature Description
8.3.1 Battery Parameter Measurements
The BQ28Z610-R1 device measures cell voltage and current simultaneously, and measures temperature to
calculate the information related to remaining capacity, full charge capacity, state-of-health, and other gauging
parameters.
8.3.1.1 BQ28Z610-R1 Processor
The BQ28Z610-R1 device uses a custom TI-proprietary processor design that features a Harvard architecture
and operates at frequencies up to 4.2 MHz. Using an adaptive, three-stage instruction pipeline, the BQ28Z610-
R1 processor supports variable instruction length of 8, 16, or 24 bits.
8.3.2 Coulomb Counter (CC)
The first ADC is an integrating converter designed specifically for coulomb counting. The converter resolution is
a function of its full-scale range and number of bits, yielding a 3.74-µV resolution.
8.3.3 CC Digital Filter
The CC digital filter generates a 16-bit conversion value from the delta-sigma CC front-end. Its FIR filter uses the
LFO clock output, which allows it to stop the HFO clock during conversions. New conversions are available
every 250 ms while CCTL[CC_ON] = 1. Proper use of this peripheral requires turning on the CC modulator in the
AFE.
8.3.4 ADC Multiplexer
The ADC multiplexer provides selectable connections to the VCx inputs, TS1 inputs, internal temperature
sensor, internal reference voltages, internal 1.8-V regulator, PACK input, and VSS ground reference input. In
addition, the multiplexer can independently enable the TS1 input connection to the internal thermistor biasing
circuitry, and enables the user to short the multiplexer inputs for test and calibration purposes.
8.3.5 Analog-to-Digital Converter (ADC)
The second ADC is a 16-bit delta-sigma converter designed for general-purpose measurements. The ADC
automatically scales the input voltage range during sampling based on channel selection. The converter
resolution is a function of its full-scale range and number of bits, yielding a 38-µV resolution. The default
conversion time of the ADC is 31.25 ms, but is user-configurable down to 1.95 ms. Decreasing the conversion
time presents a tradeoff between conversion speed and accuracy, as the resolution decreases for faster
conversion times.
8.3.6 ADC Digital Filter
The ADC digital filter generates a 24-bit conversion result from the delta-sigma ADC front end. Its FIR filter uses
the LFO clock, which allows it to stop the HFO clock during conversions. The ADC digital filter is capable of
providing two 24-bit results: one result from the delta-sigma ADC front-end and a second synchronous result
from the delta-sigma CC front-end.
8.3.7 Internal Temperature Sensor
An internal temperature sensor is available on the BQ28Z610-R1 device to reduce the cost, power, and size of
the external components necessary to measure temperature. It is available for connection to the ADC using the
multiplexer, and is ideal for quickly determining pack temperature under a variety of operating conditions.
8.3.8 External Temperature Sensor Support
The TS1 input is enabled with an internal 18-kΩ (Typ.) linearization pull-up resistor to support the use of a 10-
kΩ (25°C) NTC external thermistor, such as the Semitec 103AT-2. The NTC thermistor should be connected
between VSS and the individual TS1 pin. The analog measurement is then taken via the ADC through its input
multiplexer. If a different thermistor type is required, then changes to configurations may be required.
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VREG
RNTC
ADx
NTC
图8-1. External Thermistor Biasing
8.3.9 Power Supply Control
The BQ28Z610-R1 device manages its supply voltage dynamically according to operating conditions. When
VVC2 > VSWITCHOVER– + VHYS, the AFE connects an internal switch to BAT and uses this pin to supply power to
its internal 1.8-V LDO, which subsequently powers all device logic and flash operations. Once VC2 decreases to
VVC2 < VSWITCHOVER–, the AFE disconnects its internal switch from VC2 and connects another switch to PACK,
allowing sourcing of power from a charger (if present). An external capacitor connected to PBI provides a
momentary supply voltage to help guard against system brownouts due to transient short-circuit or overload
events that pull VC2 below VSWITCHOVER–
.
8.3.10 Power-On Reset
In the event of a power-cycle, the BQ28Z610-R1 AFE holds its internal RESET output pin high for tRST duration
to allow its internal 1.8-V LDO and LFO to stabilize before running the AGG. The AFE enters power-on reset
when the voltage at VREG falls below VREGIT– and exits reset when VREG rises above VREGIT– + VHYS for tRST
time. After tRST, the BQ28Z610-R1 AGG will write its trim values to the AFE.
tRST
normal operation
(untrimmed)
normal operation
(trimmed)
tOSU
VIT+
1.8-V Regulator
LFO
VIT–
AFE RESET
AGG writes trim values to
AFE
图8-2. POR Timing Diagram
8.3.11 Bus Communication Interface
The BQ28Z610-R1 device has an I2C bus communication interface. This device has the option to broadcast
information to a smart charger to provide key information to adjust the charging current and charging voltage
based on the temperature or individual cell voltages.
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CAUTION
If the device is configured as a single-master architecture (an application processor) and an
occasional NACK is detected in the operation, the master can resend the transaction. However, in a
multi-master architecture, an incorrect ACK leading to accidental loss of bus arbitration can cause a
master to wait incorrectly for another master to clear the bus. If this master does not get a bus-free
signal, then it must have in place a method to look for the bus and assume it is free after some
period of time. Also, if possible, set the clock speed to be 100 kHz or less to significantly reduce the
issue described above for multi-mode operation.
8.3.12 I2C Timeout
The I2C engine will release both SDA and SCL if the I2C bus is held low for ~2 seconds. If the BQ28Z610-R1
device were holding the lines, releasing them frees the master to drive the lines. Note: that the low time setting
can be under firmware control but the HW default is 2 seconds.
8.3.13 Cell Balancing Support
The integrated cell balancing FETs included in the BQ28Z610-R1 device enable the AFE to bypass cell current
around a given cell or numerous cells to effectively balance the entire battery stack. External series resistors
placed between the cell connections and the VCx input pins set the balancing current magnitude. The cell
balancing circuitry can be enabled or disabled via the CELL_BAL_DET[CB2, CB1] control register. Series input
resistors between 100 Ωand 1 kΩare recommended for effective cell balancing.
VC2
VC1
VSS
图8-3. Internal Cell Balancing
8.3.14 N-Channel Protection FET Drive
The BQ28Z610-R1 device controls two external N-Channel MOSFETs in a back-to-back configuration for battery
protection. The charge (CHG) and discharge (DSG) FETs are automatically disabled if a safety fault (AOLD,
ASSC, ASCD, SOV) is detected, and can also be manually turned off using AFE_CONTROL[CHGEN, DSGEN]
= 0, 0. When the gate drive is disabled, an internal circuit discharges CHG to VC2 and DSG to PACK.
8.3.15 Low Frequency Oscillator
The BQ28Z610-R1 AFE includes a low frequency oscillator (LFO) running at 262.144 kHz. The AFE monitors
the LFO frequency and indicates a failure via LATCH_STATUS[LFO] if the output frequency is much lower than
normal.
8.3.16 High Frequency Oscillator
The BQ28Z610-R1 AGG includes a high frequency oscillator (HFO) running at 16.78 MHz. It is synthesized from
the LFO output and scaled down to 8.388 MHz with 50% duty cycle.
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8.3.17 1.8-V Low Dropout Regulator
The BQ28Z610-R1 AFE contains an integrated 1.8-V LDO that provides regulated supply voltage for the device
CPU and internal digital logic.
8.3.18 Internal Voltage References
The BQ28Z610-R1 AFE provides two internal voltage references with VREF1, used by the ADC and CC, while
VREF2 is used by the LDO, LFO, current wake comparator, and OCD/SCC/SCD1/SCD2 current protection
circuitry.
8.3.19 Overcurrent in Discharge Protection
The overcurrent in discharge (OCD) function detects abnormally high current in the discharge direction. The
overload in discharge threshold and delay time are configurable via the OCD_CONTROL register. The
thresholds and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider
tolerance via the PROTECTION_CONTROL register. The detection circuit also incorporates a filtered delay
before disabling the CHG and DSG FETs. When an OCD event occurs, the LATCH_STATUS[OCD] bit is set to
1 and is latched until it is cleared and the fault condition has been removed.
8.3.20 Short-Circuit Current in Charge Protection
The short-circuit current in charge (SCC) function detects catastrophic current conditions in the charge direction.
The short-circuit in charge threshold and delay time are configurable via the SCC_CONTROL register. The
thresholds and timing can be fine-tuned even further based on a sense resistor with lower resistance or wider
tolerance via the PROTECTION_CONTROL register. The detection circuit also incorporates a blanking delay
before disabling the CHG and DSG FETs. When an SCC event occurs, the LATCH_STATUS[SCC] bit is set to 1
and is latched until it is cleared and the fault condition has been removed.
8.3.21 Short-Circuit Current in Discharge 1 and 2 Protection
The short-circuit current in discharge (SCD) function detects catastrophic current conditions in the discharge
direction. The short-circuit in discharge thresholds and delay times are configurable via the SCD1_CONTROL
and SCD2_CONTROL registers. The thresholds and timing can be fine-tuned even further based on a sense
resistor with lower resistance or wider tolerance via the PROTECTION_CONTROL register. The detection circuit
also incorporates a blanking delay before disabling the CHG and DSG FETs. When an SCD event occurs, the
LATCH_STATUS[SCD1] or LATCH_STATUS[SCD2] bit is set to 1 and is latched until it is cleared and the fault
condition has been removed.
8.3.22 Primary Protection Features
The BQ28Z610-R1 gas gauge supports the following battery and system level protection features, which can be
configured using firmware:
• Cell Undervoltage Protection
• Cell Overvoltage Protection
• Overcurrent in CHARGE Mode Protection
• Overcurrent in DISCHARGE Mode Protection
• Overload in DISCHARGE Mode Protection
• Short Circuit in CHARGE Mode Protection
• Overtemperature in CHARGE Mode Protection
• Overtemperature in DISCHARGE Mode Protection
• Precharge Timeout Protection
• Fast Charge Timeout Protection
8.3.23 Gas Gauging
This device uses the Impedance Track™ technology to measure and determine the available charge in battery
cells. The accuracy achieved using this method is better than 1% error over the lifetime of the battery. There is
no full charge/discharge learning cycle required. See the Theory and Implementation of Impedance Track
Battery Fuel-Gauging Algorithm Application Report for further details.
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8.3.24 Charge Control Features
This device supports charge control features, such as:
• Reports charging voltage and charging current based on the active temperature range—JEITA temperature
ranges T1, T2, T3, T4, T5, and T6
• Provides more complex charging profiles, including sub-ranges within a standard temperature range
• Reports the appropriate charging current required for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger, using the bus communication interface
• Selects the chemical state-of-charge of each battery cell using the Impedance Track method, and reduces
the voltage difference between cells when cell balancing multiple cells in a series
• Provides pre-charging/zero-volt charging
• Employs charge inhibit and charge suspend if battery pack temperature is out of programmed range
• Reports charging faults and indicates charge status via charge and discharge alarms
8.3.25 Authentication
This device supports security by:
• Authentication by the host using the SHA-1 method
• The gas gauge requires SHA-1 authentication before the device can be unsealed or allow full access.
8.4 Device Functional Modes
This device supports three modes, but the current consumption varies, based on firmware control of certain
functions and modes of operation:
• NORMAL mode: In this mode, the device performs measurements, calculations, protections, and data
updates every 250-ms intervals. Between these intervals, the device is operating in a reduced power stage to
minimize total average current consumption.
• SLEEP mode: In this mode, the device performs measurements, calculations, protections, and data updates
in adjustable time intervals. Between these intervals, the device is operating in a reduced power stage to
minimize total average current consumption.
• SHUTDOWN mode: The device is completely disabled.
8.4.1 Lifetime Logging Features
The device supports data logging of several key parameters for warranty and analysis:
• Maximum and minimum cell temperature
• Maximum current in CHARGE or DISCHARGE mode
• Maximum and minimum cell voltages
8.4.2 Configuration
The device supports accurate data measurements and data logging of several key parameters.
8.4.2.1 Coulomb Counting
The device uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement. The ADC
measures charge/discharge flow of the battery by measuring the voltage across a very small external sense
resistor. The integrating ADC measures a bipolar signal from a range of –100 mV to 100 mV, with a positive
value when V(SRP) – V(SRN), indicating charge current and a negative value indicating discharge current. The
integration method uses a continuous timer and internal counter, which has a rate of 0.65 nVh.
8.4.2.2 Cell Voltage Measurements
The BQ28Z610-R1 measures the individual cell voltages at 250-ms intervals using an ADC. This measured
value is internally scaled for the ADC and is calibrated to reduce any errors due to offsets. This data is also used
for calculating the impedance of the individual cell for Impedance Track gas gauging.
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8.4.2.3 Current Measurements
The current measurement is performed by measuring the voltage drop across the external sense resistor (1 mΩ
to 3 mΩ) and the polarity of the differential voltage determines if the cell is in the CHARGE or DISCHARGE
mode.
8.4.2.4 Auto Calibration
The auto-calibration feature helps to cancel any voltage offset across the SRP and SRN pins for accurate
measurement of the cell voltage, charge/discharge current, and thermistor temperature. The auto-calibration is
performed when there is no communication activity for a minimum of 5 s on the bus lines.
8.4.2.5 Temperature Measurements
This device has an internal sensor for on-die temperature measurements, and the ability to support external
temperature measurements via the external NTC on the TS1 pin. These two measurements are individually
enabled and configured.
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9 Applications and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The BQ28Z610-R1 gas gauge is a primary protection device that can be used with a 1- to 2-series Li-ion/Li-
polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery pack,
the user needs Battery Management Studio (BQSTUDIO), which is a graphical user-interface tool installed on a
PC during development. The firmware installed in the product has default values, which are summarized in the
BQ28Z610-R1 Technical Reference Manual (SLUUC81) for this product. Using the BQSTUDIO tool, these
default values can be changed to cater to specific application requirements during development once the system
parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,
configuration of cells, chemistry that best matches the cell used, and more are known. This data can be referred
to as the "golden image."
9.2 Typical Applications
图 9-1 shows the BQ28Z610-R1 application schematic for the 2-series configuration. 图 9-2 shows a wireless
(Bluetooth) speaker application block diagram.
0.1
0.1
µF
µF
2N7002K
10 M
10 M
10 k
Fuse
13
100
1
12
VC1
VSS
SRN
0.1 µF
0.1 µF
PWPD
2 s
1s
0.1µF
1 µF
11
10
9
2
3
4
5
6
VC2
PBI
5
0.1 µF
0.1 µF
0.1 µF
5.1 k
5.1 k
SRP
TS1
SCL
SDA
µF
2.2
PACK+
CHG
10 k
100
10
100
100
8
SCL
SDA
PACK
DSG
MM3Z5V6C
100
7
MM3Z5V6C
–
PACK
100
100
1 to 3 mΩ
Note:
The input filter capacitors of 0.1 µF for the SRN and SRP pins must be located near the pins of
the device.
图9-1. BQ28Z610-R1 2-Series Cell Typical Implementation
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Audio
Power Amp
Boost Converter
Battery
Gauge
Charger
Audio Processor
MCU
System Side
Pack Side
2
I C
Power
Copyright © 2017, Texas Instruments Incorporated
图9-2. Wireless (Bluetooth) Speaker Application Block Diagram
9.2.1 Design Requirements (Default)
DESIGN PARAMETER
Cell Configuration
EXAMPLE
2s1p (2-series with 1 parallel)
Design Capacity
4400 mAh
Device Chemistry
100 (LiCoO2/graphitized carbon)
Cell Overvoltage at Standard Temperature
Cell Undervoltage
4300 mV
2500 mV
Shutdown Voltage
2300 mV
Overcurrent in CHARGE Mode
Overcurrent in DISCHARGE Mode
Short Circuit in CHARGE Mode
Short Circuit in DISCHARGE 1 Mode
Safety Over Voltage
6000 mA
–6000 mA
0.1 V/Rsense across SRP, SRN
–0.1 V/Rsense across SRP, SRN
4500 mV
Disabled
Enabled
0°C
Cell Balancing
Internal and External Temperature Sensor
Under Temperature Charging
Under Temperature Discharging
BROADCAST Mode
0°C
Enabled
9.2.2 Detailed Design Procedure
9.2.2.1 Setting Design Parameters
For the firmware settings needed for the design requirements, refer to the BQ28Z610-R1 Technical Reference
Manual.
• To set the 2s1p battery pack, go to data flash Configuration: DA Configuration register's bit 0 (CC0) = 1.
• To set design capacity, set the data flash value to 4400 in the Gas Gauging: Design: Design Capacity
register.
• To set device chemistry, go to data flash SBS Configuration: Data: Device Chemistry. The BQSTUDIO
software automatically populates the correct chemistry identification. This selection is derived from using the
BQCHEM feature in the tools and choosing the option that matches the device chemistry from the list.
• To protect against cell overvoltage, set the data flash value to 4300 in Protections: COV: Standard Temp.
• To protect against cell undervoltage, set the data flash value to 2500 in the Protections: CUV register.
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• To set the shutdown voltage to prevent further pack depletion due to low pack voltage, program Power:
Shutdown: Shutdown voltage = 2300.
• To protect against large charging currents when the AC adapter is attached, set the data flash value to 6000
in the Protections: OCC: Threshold register.
• To protect against large discharging currents when heavy loads are attached, set the data flash value to –
6000 in the Protections: OCD: Threshold register.
• Program a short circuit delay timer and threshold setting to enable the operating the system for large short
transient current pulses. These two parameters are under Protections: ASCC: Threshold = 100 for
charging current. The discharge current setting is Protections: ASCD:Threshold = –100 mV.
• To prevent the cells from overcharging and adding a second level of safety, there is a register setting that will
shut down the device if any of the cells voltage measurement is greater than the Safety Over Voltage setting
for greater than the delay time. Set this data flash value to 4500 in Permanent Fail: SOV: Threshold.
• To disable the cell balancing feature, set the data flash value to 0 in Settings: Configuration: Balancing
Configuration: bit 0 (CB).
• To enable the internal temperature and the external temperature sensors: Set Settings:Configuration:
Temperature Enable: Bit 0 (TSInt) = 1 for the internal sensor; set Bit 1 (TS1) = 1 for the external sensor.
• To prevent charging of the battery pack if the temperature falls below 0°C, set Protections: UTC:Threshold
= 0.
• To prevent discharging of the battery pack if the temperature falls below 0°C, set Protections:
UTD:Threshold = 0.
• To provide required information to the smart chargers, the gas gauge must operate in BROADCAST mode.
To enable this, set the [BCAST] bit in Configuration: SBS Configuration 2: Bit 0 [BCAST] = 1.
Each parameter listed for fault trigger thresholds has a delay timer setting associated for any noise filtering.
These values, along with the trigger thresholds for fault detection, may be changed based upon the application
requirements using the data flash settings in the appropriate register stated in the BQ28Z610-R1 Technical
Reference Manual.
9.2.2.2 Calibration Process
The calibration of current, voltage, and temperature readings is accessible by writing 0xF081 or 0xF082 to
ManufacturerAccess(). A detailed procedure is included in the BQ28Z610-R1 Technical Reference Manual in the
Calibration section. The description allows for calibration of cell voltage measurement offset, battery voltage,
pack voltage, current calibration, coulomb counter offset, PCB offset, CC gain/capacity gain, and temperature
measurement for both internal and external sensors.
9.2.2.3 Gauging Data Updates
When a battery pack enabled with the BQ28Z610-R1 device is first cycled, the value of FullChargeCapacity()
updates several times. 图 9-3 shows RemainingCapacity() and FullChargeCapacity(), and where those updates
occur. As part of the Impedance Track algorithm, it is expected that FullChargeCapacity() may update at the end
of charge, at the end of discharge, and at rest.
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9.2.3 Application Curve
图9-3. Elapsed Time(s)
10 Power Supply Recommendations
There are two inputs for this device, the PACK input and VC2. The PACK input can be an unregulated input from
a typical AC adapter. This input should always be greater than the maximum voltage associated with the number
of series cells configured. The input voltage for the VC2 pin will have a minimum of 2.2 V to a maximum of 26 V
with the recommended external RC filter.
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11 Layout
11.1 Layout Guidelines
• The layout for the high-current path begins at the PACK+ pin of the battery pack. As charge current travels
through the pack, it finds its way through protection FETs, a chemical fuse, the Li-ion cells and cell
connections, and the sense resistor, and then returns to the PACK–pin. In addition, some components are
placed across the PACK+ and PACK–pins to reduce effects from electrostatic discharge.
• The N-channel charge and discharge FETs must be selected for a given application. Most portable battery
applications are a good option for the CSD16412Q5A. These FETs are rated at 14-A, 25-V device with
Rds(on) of 11 mΩwhen the gate drive voltage is 10 V. The gates of all protection FETs are pulled to the
source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive
is open. The capacitors (both 0.1 µF values) placed across the FETs are to help protect the FETs during an
ESD event. The use of two devices ensures normal operation if one of them becomes shorted. For effective
ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide
as possible. Ensure that the voltage rating of both these capacitors is adequate to hold off the applied voltage
if one of the capacitors becomes shorted.
• The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a
temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with
temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-
circuit ranges of the BQ28Z610-R1. Select the smallest value possible in order to minimize the negative
voltage generated on the BQ28Z610-R1 VSS node(s) during a short circuit. This pin has an absolute
minimum of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is
designed to support a 1-mΩto 3-mΩsense resistor.
• A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK–pins to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the
pack if one of the capacitors becomes shorted. Optionally, a transorb such as the SMBJ2A can be placed
across the pins to further improve ESD immunity.
• In reference to the gas gauge circuit the following features require attention for component placement and
layout: Differential Low-Pass Filter, I2C communication, and PBI (Power Backup Input).
• The BQ28Z610-R1 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ωresistor
from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-μF filter capacitor across the
SRP and SRN inputs. Optional 0.1-μF filter capacitors can be added for additional noise filtering for each
sense input pin to ground, if required for your circuit. Place all filter components as close as possible to the
device. Route the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around
the filter network can add additional noise immunity.
0.1 µF
0.1 µF
0.1 µF
100
100
0.001, 50 ppm
Filter Circuit
Sense
Ground
Shield
resistor
图11-1. BQ28Z610-R1 Differential Filter
• The BQ28Z610-R1 has an internal LDO that is internally compensated and does not require an external
decoupling capacitor. The PBI pin is used as a power supply backup input pin, providing power during brief
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transient power outages. A standard 2.2-μF ceramic capacitor is connected from the PBI pin to ground, as
shown in application example.
• The I2C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener
diode and series resistor provides more robust ESD performance. The I2C clock and data lines have an
internal pull-down. When the gas gauge senses that both lines are low (such as during removal of the pack),
the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.
11.2 Layout Example
CSD16412Q5A
CSD16412Q5A
D
G
D
G
D
S
D
S
D
S
D
S
D
S
D
S
Power Trace Line
PACK+
PACK–
Reverse Polarity
Portection
Fuse
Input filters
13
1
VSS
12
11
10
9
VC1
VC2
PBI
PWPD
2 s
1 s
2
3
SRN
SRP
TS1
SCL
Differential Input well
matched for accuracy
Thermistor
CHG
4
5
8
7
PACK
DSG
SCL
SDA
Bus
Communication
Power Ground Trace
6
SDA
Exposed Thermal Pad
Via connects to Power Ground
Via connects between two layers
图11-2. BQ28Z610-R1 Board Layout
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12 Device and Documentation Support
12.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
• BQ28Z610-R1 Technical Reference Manual
• Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm Application Report
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
Impedance Track™ and TI E2E™ are trademarks of Texas Instruments.
Windows® is a registered trademark of Microsoft.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: BQ28Z610-R1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ28Z610DRZR-R1
BQ28Z610DRZT-R1
ACTIVE
SON
SON
DRZ
12
12
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
28Z6
10R1
ACTIVE
DRZ
NIPDAU
28Z6
10R1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jun-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ28Z610DRZR-R1
BQ28Z610DRZT-R1
SON
SON
DRZ
DRZ
12
12
3000
250
330.0
180.0
12.4
12.4
2.8
2.8
4.3
4.3
1.2
1.2
4.0
4.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ28Z610DRZR-R1
BQ28Z610DRZT-R1
SON
SON
DRZ
DRZ
12
12
3000
250
552.0
552.0
346.0
185.0
36.0
36.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
BQ28Z610DRZR-R1
BQ28Z610DRZT-R1
DRZ
DRZ
VSON
VSON
12
12
3000
250
381.51
381.51
4.22
4.22
2286
2286
0
0
Pack Materials-Page 3
PACKAGE OUTLINE
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
4.15
3.85
B
A
PIN 1 INDEX AREA
2.65
2.35
1
0.8
C
SEATING PLANE
0.08 C
0.05
0
2.55
2.35
(0.2) TYP
2X (0.2)
6
7
SYMM
13
2.05
1.85
2X
2
10X 0.4
1
12
SYMM
0.3
12X
PIN 1 ID
(OPTIONAL)
0.1
0.1
C A B
C
0.5
0.3
12X
0.05
4218895/B 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
2X (2.25)
2X (0.975)
12X (0.6)
12X (0.2)
1
12
(1.95)
10X (0.4)
13
SYMM
2X (2)
(2.9)
2X (0.725)
(Ø0.2) VIA
TYP
6
7
(R0.05) TYP
4X (0.2)
SYMM
(2.45)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218895/B 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRZ0012A
PLASTIC QUAD FLATPACK- NO LEAD
2X (1.08)
4X (1.2625)
2X (0.64)
12X (0.6)
12X (0.2)
1
7
10X (0.4)
SYMM
13
2X (1.75)
(0.05) TYP
12
6
SYMM
4X (0.375)
METAL TYP
4X (0.2)
2X (2.25)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
79% PRINTED COVERAGE BY AREA
SCALE: 20X
4218895/B 03/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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