BQ294712 [TI]
BQ2947 Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries with External Delay Capacitor;
| 型号： | BQ294712 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BQ2947 Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries with External Delay Capacitor |
| 文件： | 总28页 (文件大小：2376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ2947
SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021
BQ2947 Overvoltage Protection for 2-Series to 4-Series Cell Li-Ion Batteries
with External Delay Capacitor
1 Features
3 Description
•
•
•
2-, 3-, and 4-series cell overvoltage protection
External capacitor-programmed delay timer
Factory programmed OVP threshold (threshold
range 3.85 V to 4.6 V)
The BQ2947 family is an overvoltage monitor and
protector for Li-Ion battery pack systems. Each cell is
monitored independently for an overvoltage condition.
In the BQ2947 device, an external delay timer is
initiated upon detection of an overvoltage condition on
any cell. Upon expiration of the delay timer, the output
is triggered into its active state (either high or low,
depending on the configuration). The external delay
timer feature also includes the ability to detect an
open or shorted delay capacitor on the CD pin, which
will similarly trigger the output driver in an overvoltage
condition.
•
Output options: active high or open drain active
low
High-accuracy overvoltage protection: ±10 mV
Low power consumption ICC ≈ 1 µA
•
•
(VCELL(ALL) < VPROTECT
)
•
•
Low leakage current per cell input < 100 nA
Small package footprint
– 8-pin WSON (2.00 mm x 2.00 mm)
2 Applications
For quicker production-line testing, the BQ2947
device provides a Customer Test Mode with 67
reduced delay time.
•
•
Notebooks
UPS battery backup
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
BQ294700
WSON (8)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pack
+
100 Ω
OUT
CD
VDD
V4
1k
1k
1k
1k
VCELL4
VCELL3
VCELL2
VCELL1
0.1µF
0.1µF
V3
V2
VSS
V1
0.1µF
PWPD
0.1 µF
0.1 µF
0.1µF
–
Pack
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ2947
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SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Applications.................................................. 13
10 Power Supply Recommendations..............................16
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Third-Party Products Disclaimer............................. 17
12.2 Documentation Support.......................................... 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks.............................................................17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
Changes from Revision I (June 2018) to Revision J (May 2021)
Page
•
Updated the BQ294712 and BQ294713 devices in the Device Options table ...................................................3
Changes from Revision H (February 2018) to Revision I (June 2018)
Page
•
•
Added BQ294713 to the Device Options table ..................................................................................................3
Added BQ294713 to the Electrical Characteristics ............................................................................................6
Changes from Revision G (November 2017) to Revision H (February 2018)
Page
•
Changed BQ294712 to Production Data in the Device Options table ............................................................... 3
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5 Device Comparison Table
PART NUMBER
BQ294700
BQ294701
BQ294702
BQ294703
BQ294704
BQ294705
BQ294706
BQ294707
BQ294708
BQ294711
BQ294712
BQ294713
BQ2947
OVP (V)
4.350
OV HYSTERESIS
0.300
OUTPUT DRIVE
CMOS Active High
4.250
0.300
CMOS Active High
4.300
0.300
CMOS Active High
4.325
0.300
CMOS Active High
4.400
0.300
CMOS Active High
4.450
0.300
CMOS Active High
4.550
0.300
CMOS Active High
4.225
0.050
NCH Open Drain Active Low
CMOS Active High
4.500
0.300
4.220
0.300
CMOS Active High
4.125
0.300
CMOS Active High
4.600
0.300
CMOS Active High
3.850–4.60
0–0.300
CMOS Active High or Open Drain Active Low
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6 Pin Configuration and Functions
VDD
V4
1
2
3
4
8
7
6
5
OUT
CD
Thermal
Pad
V3
VSS
V1
V2
Not to scale
Figure 6-1. DSG Package 8-Pin WSON Top View
Table 6-1. Pin Functions
NUMBER
NAME
VDD
TYPE(1)
DESCRIPTION
1
2
3
4
5
6
7
8
P
IA
IA
IA
IA
P
Power supply input
V4
V3
Sense input for positive voltage of the fourth cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the lowest cell in the stack
V2
V1
VSS
CD
OUT
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
External capacitor connection for delay timer
OA
OA
P
Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low
TI recommends connecting the exposed pad to VSS on the PCB.
PowerPAD™
(1) IA = Input Analog, OA = Output Analog, P = Power Connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
30
UNIT
Supply voltage
Input voltage
Output voltage
VDD–VSS
V
V
V
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
OUT–VSS
30
30
Continuous total power dissipation, PTOT
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
See Section 7.4
300
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over-operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
V
Supply voltage, VDD
Input voltage range
20
5
V4–V3, V3–V2, V2–V1, V1–VSS, or CD–VSS
0
V
Operating ambient temperature range, TA
–40
110
°C
7.4 Thermal Information
BQ2947
WSON
8 PINS
62
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
72
32.5
1.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
33
RθJC(bottom)
10
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOLTAGE PROTECTION THRESHOLDS
BQ294700, RIN = 1 kΩ
BQ294701, RIN = 1 kΩ
BQ294702, RIN = 1 kΩ
BQ294703, RIN = 1 kΩ
BQ294704, RIN = 1 kΩ
BQ294705, RIN = 1 kΩ
BQ294706, RIN = 1 kΩ
BQ294707, RIN = 1 kΩ
BQ294708, RIN = 1 kΩ
BQ294711, RIN = 1 kΩ
BQ294712, RIN = 1 kΩ
BQ294713, RIN = 1 kΩ
4.350
4.250
4.300
4.325
4.400
4.450
4.550
4.225
4.500
4.220
4.125
4.600
300
V
V
V
V
V
V
V(PROTECT) Overvoltage
Detection
VOV
V
V
V
V
V
V
VHYS
VOA
OV Detection Hysteresis BQ2947(1)
250
–10
–40
–20
–24
–54
400
10
40
20
24
54
mV
mV
mV
mV
mV
mV
OV Detection Accuracy TA = 25°C
TA = –40°C
TA = 0°C
OV Detection Accuracy
Across Temperature
VOADRIFT
TA = 60°C
TA = 110°C
SUPPLY AND LEAKAGE CURRENT
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 8-4.)
IDD
IIN
Supply Current
1
2
µA
µA
(V4–V3) = (V3–V2) = (V2–V1) = (V1–VSS) = 4.0 V
at TA = 25°C (See Figure 8-4.)
Input Current at Vx Pins
–0.1
0.1
Current Consumption at Power down, (V4–V3) =
Input Current (ALL Vx
and VDD Input Pins)
ICELL
(V3–V2) = (V2–V1) = (V1–VSS) = 2.30 V at TA
25°C
=
1.1
µA
OUTPUT DRIVE OUT, CMOS ACTIVE HIGH VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV
VDD = 14.4 V, IOH = 100 µA
,
6
V
V
If three of four cells are short circuited, only one
cell remains powered and > VOV, VDD = Vx (cell
voltage), IOH = 100 µA
Output Drive Voltage,
Active High
VDD – 0.3
250
VOUT
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
,
,
400
4.5
mV
mA
(V4–V3), (V3–V2), (V2–V1), or (V1–VSS) > VOV
VDD = 14.4 V,
OUT = 0 V, measured out of OUT pin.
,
OUT Source Current
(during OV)
IOUTH
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
OUT = VDD, measured into OUT pin .Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
OUT Sink Current (no
OV)
IOUTL
0.5
14
mA
mV
OUTPUT DRIVE OUT, CMOS OPEN DRAIN ACTIVE LOW VERSIONS ONLY
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
Output Drive Voltage,
,
VOUT
VDD = 14.4 V, IOL = 100 µA measured into OUT
pin.
250
400
Active High
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7.5 Electrical Characteristics (continued)
Typical values stated where TA = 25°C and VDD = 14.4V, MIN/MAX values stated where TA = –40°C to +110°C and VDD = 3
V to 20 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
OUT = VDD, measured into OUT pin. Pull resistor
RPU = 5 kΩ to VDD = 14.4 V
,
OUT Sink Current (no
OV)
IOUTL
0.5
14
mA
(V4–V3), (V3–V2), (V2–V1), and (V1–VSS) < VOV
VDD = 14.4 V,
,
IOUTLK
OUT pin leakage
100
nA
OUT = VDD, measured into OUT pin.
DELAY TIMER
tCD
OV Delay Time
CCD = 0.1 µF (see External Delay Capacitor, CD)
1
1.5
2
s
OV Delay Time with CD Delay due to CCD capacitor shorted to ground for
pin = 0 V Customer Test Mode
tCD_GND
20
170
ms
(1) Future option, contact TI.
7.6 Typical Characteristics
Figure 7-1. Overvoltage Threshold (Nominal = 4.35
V) vs. Temperature
Figure 7-2. Hysteresis VHYS vs. Temperature
Figure 7-3. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 7-4. ICELL vs. Temperature
at VCELL= 9.2 V
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Figure 7-5. Output Current IOUT vs.
Temperature
Figure 7-6. VOUT vs. VDD
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8 Detailed Description
8.1 Overview
The BQ2947 is a second level overvoltage (OV) protector. Each cell is monitored independently by comparing
the actual cell voltage to a protection voltage threshold, VOV. The protection threshold is preprogrammed at the
factory with a range between 3.85 V and 4.65 V.
8.2 Functional Block Diagram
The Functional Block Diagram shows a CMOS Active High configuration.
PACK+
R
VD
C
VD
VDD
1
R
R
R
R
V4
V3
V2
IN
IN
IN
IN
2
3
4
5
6
C
IN
V
OV
C
IN
Enable
OUT
Active
Delay Charge
/
Discharge Circuit
8
C
IN
V1
C
IN
VSS
9
7
PWPD
CD
C
CD
PACK–
Note
In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the
OUT terminal.
8.3 Feature Description
In the BQ2947 family of devices, if any cell voltage exceeds the programmed OV value, a timer circuit is
activated. This timer circuit charges the CD pin to a nominal value, then slowly discharges it with a fixed current
back down to VSS. When the CD pin falls below a nominal threshold near VSS, the OUT terminal goes from
inactive to active state. Additionally, a timeout detection circuit checks to ensure that the CD pin successfully
begins charging to above VSS and subsequently drops back down to VSS, and if a timeout error is detected in
either direction, it will similarly trigger the OUT pin to become active. See Figure 8-2 for details on CD and OUT
pin behavior during an overvoltage event.
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For an NCH Open Drain Active Low configuration, the OUT pin pulls down to VSS when active (OV present) and
is high impedance when inactive (no OV).
VOV
VOV–VHYS
tCD
OUT (V)
Figure 8-1. Timing for Overvoltage Sensing (OUT Pin Is Active High)
Figure 8-2 shows the behavior of CD pin during an OV sequence.
Fault condition
present
Fault response
becomes active
VCD
V(CD)
tCHGDELAY
tCD
V
OUT1
V(OUT)
Note: Active High OUT version shown
Figure 8-2. CD Pin Mechanism (OUT Pin Is Active High)
Note
In the case of an Open Drain Active Low version, the VOUT signal will be high and transition to low
state when the voltage on the VCD capacitor discharges to the set level based on the tCD timer.
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8.3.1 Pin Details
8.3.1.1 Input Sense Voltage, Vx
These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is
required for noise filtering and stable voltage monitoring.
8.3.1.2 Output Drive, OUT
This terminal serves as the fault signal output, and may be ordered in either Active High or Open Drain Active
Low options.
8.3.1.3 Supply Input, VDD
This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,
and a capacitor is connected to ground for noise filtering.
8.3.1.4 External Delay Capacitor, CD
This terminal is connected to an external capacitor that sets the delay timer during an overvoltage fault event.
The CD pin includes a timeout detection circuit to ensure that the output drives active even with a shorted or
open capacitor during an overvoltage event.
The capacitor connected on the CD pin rapidly charges to a voltage if any one of the cell inputs exceeds the
OV threshold. Then the delay circuit gradually discharges the capacitor on the CD pin. Once this capacitor
discharges below a set voltage, the OUT transitions from an inactive to active state.
To calculate the delay, use the following equation:
tCD (sec) = K × CCD (µF), where K = 10 to 20 range.
(1)
Example: If CCD= 0.1 µF (typical), then the delay timer range is
tCD (s) = 10 × 0.1 = 1 s (Minimum)
tCD (s) = 20 × 0.1 = 2 s (Maximum)
Note
The tolerance on the capacitor used for CCD increases the range of the tCD timer.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–V2), and (V4–V3).
The OUT pin is inactive, and is low if configured active high, or, if configured active low, is an open drain being
externally pulled up.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltage exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally if configured
as active low. An external FET is then turned on, shorting the fuse to ground, which allows the battery and/or
charger power to blow the fuse. When all of the cell voltages fall below the (VOV–VHYS), the device returns to
NORMAL mode.
8.4.3 Customer Test Mode
It is possible to reduce test time for checking the overvoltage function by simply shorting the external CD
capacitor to VSS. In this case, the OV delay would be reduced to the t(CD_GND) value, which has a maximum of
170 ms.
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Figure 8-3 shows the timing for the Customer Test Mode.
OV Condition
V(VCELL)
≤ 170 ms
V(
V(
)
OUT
CD pin held low
)
CD
Figure 8-3. Timing for Customer Test Mode
Figure 8-4 shows the measurement for current consumption of the product for both VDD and Vx.
IDD
1
2
3
4
8
7
6
5
VDD
V4
OUT
CD
IIN4
IIN3
VSS
V3
V2
ICELL
IIN2
V1
IIN1
ICELL = IDD + IIN1 + IIN2 + IIN3 + IIN4
Figure 8-4. Configuration for IC Current Consumption Test
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The BQ2947 devices are a family of second-level protectors used for overvoltage protection of the battery pack
in the application. The device, when configuring the OUT pin with active high, drives a NMOS FET that connects
the fuse to ground in the event of a fault condition. This provides a shorted path to use the battery and/or charger
power to blow the fuse and cut the power path. The OUT pin, when configured as active low, can be used to
drive a PMOS FET to connect the fuse to ground instead.
9.2 Typical Applications
9.2.1 Application Configuration for Active High
Figure 9-1 shows the recommended reference design components.
Pack
+
100 Ω
OUT
CD
VDD
V4
1k
VCELL4
VCELL3
VCELL2
VCELL1
0.1µF
0.1µF
0.1µF
1k
1k
1k
V3
V2
VSS
V1
PWPD
0.1 µF
0.1 µF
0.1µF
–
Pack
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Figure 9-1. Application Configuration for Active High
9.2.1.1 Design Requirements
Note
In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the
OUT terminal.
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements.
Table 9-1. Parameters
PARAMETER
Voltage monitor filter resistance
EXTERNAL COMPONENT
MIN
900
0.01
100
NOM
1000
0.1
MAX UNIT
4700
1.0
RIN
CIN
Ω
µF
Ω
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
CD external delay capacitance
RVD
CVD
CCD
1000
1.0
0.1
0.1
µF
µF
1.0
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Note
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
9.2.1.2 Detailed Design Procedure
1. Determine the number of cell in series.
The device supports 2-S to 4-S cell configuration. For 2S and 3S, the top unused pin(s) should be shorted as
shown in Figure 9-2 and Figure 9-3.
2. Determine the overvoltage protection delay.
Follow the calculation example described in CD pin description. Select the right capacitor to connect to the
CD pin.
3. Follow the application schematic to connect the device. If the OUT pin is configured to open drain, an
external pull up resistor should be used.
Pack
+
100 Ω
VDD
V4
OUT
CD
V3
V2
VSS
V1
0.1µF
1k
1k
VCELL2
VCELL1
0.1µF
PWPD
0.1µF
0.1µF
0.1µF
–
Pack
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Figure 9-2. 2-Series Cell Configuration
Pack
+
100 Ω
OUT
CD
VDD
V4
1k
V3
V2
VSS
V1
0.1µF
VCELL3
1k
1k
0.1µF
VCELL2
VCELL1
PWPD
0.1µF
0.1µF
0.1µF
–
Pack
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Figure 9-3. 3-Series Cell Configuration
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www.ti.com
SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021
9.2.1.3 Application Curves
Figure 9-4. Overvoltage Threshold (OVT) vs.
Temperature
Figure 9-5. Hysteresis VHYS vs. Temperature
Figure 9-6. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 9-7. VOUT vs. VDD
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: BQ2947
BQ2947
www.ti.com
SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021
10 Power Supply Recommendations
The maximum power of this device is 20 V on VDD
.
11 Layout
11.1 Layout Guidelines
1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,
reducing the tracing loop area.
2. The capacitor for CD should be placed close to the IC terminals.
3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand
the current during fuse blown event.
11.2 Layout Example
Place the RC filters close to the
Power Trace Line
device terminals
Pack +
Pack -
VDD
V4
OUT
CD
V3
V2
VSS
V1
VCELL3
VCELL2
VCELL1
PWPD
Ensure trace can support sufficient current
flow for fuse blow
Figure 11-1. Layout Example
Copyright © 2021 Texas Instruments Incorporated
16
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Product Folder Links: BQ2947
BQ2947
www.ti.com
SLUSB15J – SEPTEMBER 2012 – REVISED MAY 2021
12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see BQ2945xy and BQ2947xy Cascade Voltage Monitoring (SLUA662).
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: BQ2947
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
BQ294706DSGR
BQ294706DSGT
BQ294707DSGR
BQ294707DSGT
BQ294708DSGR
BQ294708DSGT
BQ294711DSGR
BQ294711DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
700
700
701
701
702
702
703
703
704
704
705
705
706
706
707
707
708
708
711
711
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI | NIPDAU
Call TI | NIPDAU
NIPDAU
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ294712DSGR
BQ294712DSGT
BQ294713DSGR
BQ294713DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 110
-40 to 110
-40 to 110
-40 to 110
712
712
713
713
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
BQ294706DSGR
BQ294706DSGT
BQ294707DSGR
BQ294707DSGT
BQ294708DSGR
BQ294708DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ294711DSGR
BQ294711DSGT
BQ294712DSGR
BQ294712DSGR
BQ294712DSGT
BQ294712DSGT
BQ294713DSGR
BQ294713DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
250
3000
250
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ294700DSGR
BQ294700DSGT
BQ294701DSGR
BQ294701DSGT
BQ294702DSGR
BQ294702DSGT
BQ294703DSGR
BQ294703DSGT
BQ294704DSGR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ294704DSGT
BQ294705DSGR
BQ294705DSGT
BQ294706DSGR
BQ294706DSGT
BQ294707DSGR
BQ294707DSGT
BQ294708DSGR
BQ294708DSGT
BQ294711DSGR
BQ294711DSGT
BQ294712DSGR
BQ294712DSGR
BQ294712DSGT
BQ294712DSGT
BQ294713DSGR
BQ294713DSGT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
DSG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
250
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
3000
250
250
3000
250
Pack Materials-Page 3
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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