BQ296213DSGR [TI]

适用于 2 节、3 节和 4 节串联锂离子电池的过压保护 | DSG | 8 | -40 to 110;


型号：	BQ296213DSGR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 2 节、3 节和 4 节串联锂离子电池的过压保护 \| DSG \| 8 \| -40 to 110 电池光电二极管
文件：	总31页 (文件大小：2647K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ2961, BQ2962

SLUSBU5P – NOVEMBER 2013 – REVISED AUGUST 2021

BQ296xxx Overvoltage Protection for 2-Series, 3-Series, and 4-Series Cell

Li-Ion Batteries with Regulated Output Supply

1 Features

3 Description

•

2-series, 3-series, and 4-series cell overvoltage

protection (OVP)

Fixed delay timer to trigger FET drive output

(3-s, 4-s, 5.5-s, or 6.5-s options)

Factory programmed OVP threshold (threshold

range 3.85 V to 4.6 V)

Output options: active high

High-accuracy overvoltage protection:

±10 mV

The BQ296xxx family is a high-accuracy, low-power

overvoltage protector with a 2-mA regulated output

supply for Li-ion battery pack applications.

Each cell in a 2-series to 4-series cell stack is

individually monitored for an overvoltage condition. An

internally fixed-delay timer is initiated upon detection

of an overvoltage condition on any cell. Upon

expiration of the delay timer, an output pin is triggered

into an active state to indicate that an overvoltage

condition has occurred.

•

Regulated supply output with self-disable and/or

external enable/disable control

The regulated output supply delivers up to 2-mA

(max) output current to drive always-on circuits, such

as a real-time clock (RTC) oscillator. The BQ296xxx

family has a self-disable function to turn off the

regulated output if any cell voltage falls below a

certain threshold, thereby preventing drain on the

battery, and provides an external control to enable or

disable the regulated output.

– Options: 3.3 V, 2.5 V, and 1.8 V (BQ2961)

– Options: 3.3 V, 3.15 V, 3.0 V (BQ2962)

Low power consumption I_CC~ 4 µA

•

(V_CELL(ALL)< V_PROTECT

)

Extra low power consumption with reg output

disabled, I_CC~ 1.2 µA

Low leakage current per cell input < 100 nA

Small package footprint

•

– 8-Pin WSON (2 mm × 2 mm)

Device Information

PART NUMBER⁽¹⁾

BQ2961

PACKAGE

BODY SIZE (NOM)

2 Applications

•

Notebook PC

Ultrabooks

Medical

WSON (8)

2.00 mm × 2.00 mm

BQ2962

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

UPS battery backup

Pack +

Protector

FETs

100 Ω

OUT

REG

VDD

External

Circuit

e.g., RTC

1 kΩ

5 ꢀ (*)

0.1µF

VCELL4

VCELL3

1 kΩ

VSS

* can be removed if Vss will be

connected first during cell

connection

PWPD

VCELL2

VCELL1

1 kΩ

0.1µF

0.47 µF

0.1µF

Pack œ

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

BQ2961, BQ2962

SLUSBU5P – NOVEMBER 2013 – REVISED AUGUST 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................5

7.5 Electrical Characteristics.............................................6

7.6 Typical Characteristics................................................8

8 Detailed Description........................................................9

8.1 Overview.....................................................................9

8.2 Functional Block Diagram.........................................10

8.3 Feature Description...................................................10

8.4 Device Functional Modes..........................................11

9 Application and Implementation..................................13

9.1 Application Information............................................. 13

9.2 Typical Application.................................................... 13

10 Power Supply Recommendations..............................15

11 Layout...........................................................................16

11.1 Layout Guidelines................................................... 16

11.2 Layout Example...................................................... 16

12 Device and Documentation Support..........................16

12.1 Third-Party Products Disclaimer............................. 16

12.2 Receiving Notification of Documentation Updates..16

12.3 Support Resources................................................. 16

12.4 Trademarks.............................................................16

12.5 Electrostatic Discharge Caution..............................17

12.6 Glossary..................................................................17

13 Mechanical, Packaging, and Orderable

Information.................................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision O (July 2021) to Revision P (August 2021)

Page

•

Changed the BQ296227 and BQ296233 devices to Production Data in the Device Comparison Table ...........3

Changes from Revision N (June 2021) to Revision O (July 2021)

Page

•

Changed the BQ296115 device to Production Data in the Device Comparison Table ...................................... 3

Changes from Revision M (June 2021) to Revision N (June 2021)

Page

•

Added the BQ296227 and BQ296233 PRODUCT PREVIEW devices to the Device Comparison Table ......... 3

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5 Device Comparison Table

Table 5-1. BQ2961 Device Options

BQ2961

BQ296100

BQ296103

BQ296106

BQ296107

BQ296111

BQ296112

BQ296113

BQ296114

BQ296115

BQ296116⁽¹⁾

BQ2961

OVP (V)

OVP DELAY (s)

UV (V)

LDO (V)

4.35

6.5

2.5

3.3

4.50

6.5

2.5

4.45

6.5

2.8

3.3

4.50

6.5

2.8

3.3

4.45

4.0

2.5

3.3

4.50

3.0

2.5

3.3

4.35

3.0

2.5

3.3

4.50

4.0

2.5

3.3

4.25

4.50

6.5

2.0

2.5

1.8

3.85 V–4.60 V (50-mV step)

3.0, 4.0, 5.5, 6.5

2.0 V–2.8 V (50-mV step)

1.8, 2.5, 3.3

(1) PRODUCT PREVIEW. Contact TI for more information.

Table 5-2. BQ2962 Device Options

BQ2962

OVP (V)

4.45

4.50

4.35

4.50

4.55

4.50

4.5

OVP DELAY (s)

UV (V)

LDO (V)

3.3

BQ296202

BQ296203

BQ296212

BQ296213

BQ296215

BQ296216

BQ296217

BQ296221

BQ296222

BQ296223

BQ296224

BQ296226

BQ296227

BQ296228

bq296229

BQ296230

BQ296231

BQ296232

BQ296233

BQ2962

6.5

3.0

6.5

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.0

2.5

3.0

2.8

3.3

2.5

3.3

3.0

2.5

3.3

2.5

3.0

2.8

3.3

4.55

4.60

4.35

4.60

4.55

4.45

2.8

3.3

2.5

3.0

2.5

3.0

2.5

3.3

3.0

2.5

3.0

3.3

3.85 V–4.60 V (50-mV step)

3.0, 4.0, 5.5, 6.5

2.0 V–2.8 V (50-mV step)

3, 3.15, 3.3

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6 Pin Configuration and Functions

OUT

REG

VDD

VSS

Figure 6-1. 2-Series to 4-Series BQ2961 (Top View)

REG

OUT

VDD

VSS

Figure 6-2. 2-Series to 4-Series BQ2962 (Top View)

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

BQ2961

BQ2962

Analog output drive for an overvoltage fault signal; CMOS output high or open-

drain active low

OUT

PWPD

REG

TI recommends connecting the exposed pad to VSS on PCB.

Regulated supply output. Requires an external ceramic capacitor for stability

Regulated supply output enable. A "high" to enable REG output and "low" to

disable REG output

REG_EN

—

Sense input for positive voltage of the lowest cell from the bottom of the stack

Sense input for positive voltage of the second cell from the bottom of the stack

Sense input for positive voltage of the third cell from the bottom of the stack

Sense input for positive voltage of the fourth cell from the bottom of the stack

Power supply input

VDD

Electrically connected to integrated circuit ground and negative terminal of the

lowest cell in the stack

VSS

(1) IA = Analog input, OA = Analog Output, P = Power connection

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Supply voltage

Input voltage

VDD – VSS

–0.3

V4 – V3, V3 – V2, V2 – V1, V1 – VSS

REG – VSS

–0.3

3.6

REG_EN – VSS

OUT – VSS

–0.3

Output voltage

–0.3

See Section 7.4.

300

Continuous total power dissipation, P_TOT

Lead temperature (soldering, 10 s), T_SOLDER

Storage temperature, T_stg

300

150

°C

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

2000

500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN

NOM

MAX

UNIT

(1)

Supply voltage, V_DD

Supply voltage,

V_DD

(1)

Supply voltage, V_DDwith REG output on

V_n– V_n-1, V1 – VSS

Input voltage

range

REG_EN

Operating ambient temperature range, T_A

(1) See Section 9.2.

–40

110

°C

7.4 Thermal Information

BQ296xxx

THERMAL METRIC⁽¹⁾

DSG (WSON)

UNIT

8 PINS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

32.5

1.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics

Typical values stated where T_A= 25°C and VDD = 14.4 V, MIN/MAX values stated where T_A= –40°C to +110°C, and V_DD

3 V to 15 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Voltage Protection Thresholds

V_(PROTECT)Overvoltage

Detection

Applicable Voltage: 3.85 V to

4.6 V in 50-mV steps

V_OV

R_IN= 1 kΩ

V_HYS

V_OA

OV Detection Hysteresis

OV Detection Accuracy

250

–10

–40

–20

–24

–54

300

400

T_A= 25°C

T_A= –40°C

T_A= 0°C

OV Detection Accuracy

Across Temperature

V_OADRIFT

T_A= 60°C

T_A= 110°C

Supply and Leakage Current

(V_n– V_n-1) = 2 V to 4.15 V, n = T_A= 0°C to 60°C

Supply Current with REG 1 to 4, VDD = top V_nvoltage

µA

I_DD

(V1 – V_SS) > V_UVREG, I_REG= 0

mA,

T_A= –40°C to 110°C

(V_n– V_n-1) = 2 V to 4.15 V, n = T_A= 0°C to 60°C

1 to 4, VDD = top V_nvoltage

T_A= –40°C to 110°C

(V1 – V_SS) < V_UVREG

µA

Supply Current with REG

off

I_DD

(V_n– V_n-1) = (V1 – V_SS) = 3.8 V, VDD = top V_nvoltage,

T_A= 25°C

I_IN

Input Current at V_xPins

–0.1

0.1

µA

Output Drive OUT, CMOS Active High

(V_n– V_n-1) or (V1 – V_SS) > V_OV, I_OH= 100 µA, VDD =

top V_nvoltage

If three of four cells are short circuited, only one cell

remains powered and > V_OV, VDD = V_n(the remaining

cell voltage), I_OH= 100 µA

Output Drive Voltage,

Active High

VDD –

0.3

V_OUT

(V_n– V_n-1) and (V1 – V_SS) < V_OV, VDD = sum of the

cell stack voltage, I_OL= 100 µA measured into OUT pin

250

400

4.5

(V_n– V_n-1), (V3 – V2), or (V1 – V_SS) > V_OV, VDD = top

V_nvoltage,

OUT Source Current

(during OV)

I_OUTH

forced OUT = 0 V, measured out of OUT pin

(V_n– V_n-1) and (V1 – V_SS) < V_OV, VDD = top V_n

voltage, forced OUT = VDD, measured into OUT pin.

Pull-up resistor R_PU= 5 kΩ to VDD

OUT Sink Current (no

OV)

I_OUTL

0.5

Internal Fixed Delay Timer

Internal Fixed Delay, 3-s delay option

Internal Fixed Delay, 4-s delay option

Internal Fixed Delay, 5.5-s delay option

Internal Fixed Delay, 6.5-s delay option

2.4

3.2

4.4

5.2

3.6

4.8

6.6

7.8

t_DELAY

OV Delay Time⁽¹⁾

5.5

6.5

Fault Detection Delay

Time in Test Mode OV

Delay Time

t_{DELAY_CTM}

Internal Fixed Delay

OV delay timer count

reset time; t_DELAYresets

when the cell voltage

t_{DELAY_RESET}

Internal Fixed Delay

0.6

falls below V_OVfor

(1)

t_{DELAY_RESET}

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7.5 Electrical Characteristics (continued)

Typical values stated where T_A= 25°C and VDD = 14.4 V, MIN/MAX values stated where T_A= –40°C to +110°C, and V_DD

3 V to 15 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Regulated Supply Output, REG

V_REG= 3.3 V,

3.234

3.087

3.300

3.150

3.366

3.213

V_REG= 3.15 V,

BQ2962

V_REG= 3.0 V,

BQ2962

REG Supply at

500 µA load

VDD ≥ 4 V, I_REG= 500 µA,

C_REG= 0.47 µF

2.940

2.450

1.764

3.200

3.050

2.900

2.425

3.000

2.500

1.800

3.300

3.150

3.000

2.500

1.800

3.060

V_REG

V_REG= 2.5 V,

BQ2961

2.550

1.836

3.400

3.250

V_REG= 1.8 V,

BQ2961

V_REG= 3.3 V,

BQ2961, BQ2962

V_REG= 3.15 V,

BQ2962

VDD ≥ 4 V, I_REG= 0 µA to 2

mA,

C_REG= 0.47 µF

REG Supply from 0 to 2

mA load

V_REG= 3.0 V,

BQ2962

V_REG

3.100

2.575

V_REG= 2.5 V,

BQ2961

V_REG= 1.8 V,

BQ2961

1.746

1.854

I_REG

REG Current Output

VDD ≥ 4 V, C_REG= 0.47 µF

REG = V_SS, C_REG= 0.47 µF

REG is disabled.

kΩ

REG Output Short Circuit

Current Limit

I_{REG_ SC_Limit}

R_{REG_ PD}

REG pull-down resistor

Regulated Supply Output Enable, REG_EN

V_IH

V_IL

High-level Input

1.6

Low-level Input

0.4

0.1

I_LKG

Input Leakage Current

V_IH< 6 V

µA

Regulated Supply Undervoltage Self-Disable

Factory Configuration: 2.0 V to 2.8 V in 50 mV steps,

T_A= 25°C

V_UVREG

V_UVHYS

t_UVDELAY

V_UVQUAL

Undervoltage detection

–50

250

4.5

400

7.5

Undervoltage Detection

Hysteresis

300

Undervoltage Detection

Delay

Cell voltage to qualify for

UV detection

0.5

(1) Specified by design. Not 100% tested in production.

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7.6 Typical Characteristics

350

340

330

320

310

300

290

280

Mean

Min

Max

-5

-10

-15

-20

-25

Mean

Min

Max

-60

-40

-20

100 120

-60

-40

-20

100 120

Temperature (èC)

D002

D001

Figure 7-2. Hysteresis V_HYSvs. Temperature

Figure 7-1. Overvoltage Threshold (V_OV) vs.

Temperature

4.5

-5

3.5

-10

-15

Mean

Min

Max

Mean

Min

Max

2.5

-20

-60

-40

-20

100 120

-40

-20

100 120

Temperature (èC)

D003

D004

Figure 7-3. Undervoltage Accuracy

Figure 7-4. I_DDwith Regulator On

3.31

3.305

3.3

1.4

Mean

Min

Max

1.2

0.8

0.6

0.4

0.2

3.295

3.29

Mean

Min

Max

3.285

-60

-40

-20

100 120

-60

-40

-20

100 120

Temperature (èC)

D006

Temperature (èC)

D005

Figure 7-6. Regulator Output Without Load

Figure 7-5. I_DDwith Regulator Off

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-3.35

-3.4

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Mean

Min

Max

-3.45

-3.5

-3.55

-3.6

-3.65

-3.7

-60

-40

-20

100 120

Supply Voltage (V)

Temperature (èC)

D008

D009

Figure 7-7. I_OUTHvs Temperature

Figure 7-8. V_OUTvs V_DD

8 Detailed Description

8.1 Overview

The BQ2961 and BQ2962 devices are second-level overvoltage (OV) protectors with a regulated output. Each

cell is monitored independently by comparing the actual cell voltage to an overvoltage threshold V_OV. The

overvoltage threshold is preprogrammed at the factory with a range between 3.85 V to 4.65 V.

The regulated output is enabled unless any of the cell voltages fall below the V_UVREGthreshold. This threshold is

preprogrammed at the factory with a range between 2 V to 2.8 V.

Table 8-1. Programmable Parameters

OVERVOLTAGE RANGE (V)

OVERVOLTAGE DELAY (s)

UNDERVOLTAGE RANGE (V)

REGULATOR (V)

1.8, 2.5, 3.3 (BQ2961)

3.0, 3.15, 3.3 (BQ2962)

3.85 to 4.6 in 50-mV step

3, 4, 5.5, 6.5

2.0 to 2.8 in 50-mV step

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8.2 Functional Block Diagram

PACK+

VDD

Vref

Amp

Comp

UVP_Vref

REG

REG_EN

Programmable

setting

Enable

Active

OUT

Delay

Timer

Delay Charging/

Discharge circuit

REG_EN

VSS

PWPD

PACKœ

8.3 Feature Description

8.3.1 Pin Details

8.3.1.1 Input Sense Voltage, Vx

These inputs sense each battery cell voltage. A series resistor and a capacitor across the cell for each input is

required for noise filtering and stable voltage monitoring.

8.3.1.2 Output Drive, OUT

This terminal serves as the fault signal output in active high.

8.3.1.3 Supply Input, VDD

This terminal is the unregulated input power source for the device. A series resistor is connected to limit the

current, and a capacitor is connected to ground for noise filtering.

8.3.1.4 Regulated Supply Output, REG

This terminal is connected to an external capacitor and provides a regulated supply to power a circuit such as a

real-time clock integrated circuit, or functions requiring a well-regulated supply. Maximum current load on this pin

cannot exceed I_REGmA.

The REG output has protection for overcurrent, using a current limit protection circuit, and also detects and

protects for excessive power dissipation due to short circuit of the external load. This pin requires a ceramic 1-µF

capacitor connection to VSS for improved stability, noise immunity, and ESD performance of the supply output.

This capacitor must be placed close to the REG and VSS pins for connection.

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8.3.2 Overvoltage Sensing for OUT

In the BQ296xxx device, each cell is monitored independently. Overvoltage is detected by comparing the actual

cell voltage to a protection voltage reference, V_OV. If any cell voltage exceeds the programmed OV value, an

internal timer circuit is activated. This timer circuit causes a factory pre-programmed fixed delay before the OUT

terminal goes from inactive to active state.

VOV

VOV - VHYS

tDELAY

OUT (V)

Figure 8-1. Timing for Overvoltage Sensing for OUT

8.3.3 Regulated Output Voltage and REG_EN Pin

For BQ2961, there are three factory-preprogrammed options for the regulated output voltage, 3.3 V, 2.5 V, and

1.8 V. For BQ2962, the regulated output voltage options are 3.3 V, 3.15 V, and 3.0 V. Potentially, the BQ2962xy

device can provide other regulated voltage output between 3.3 V to 3.0 V. Contact Texas Instruments for details.

At power up, the regulated output is on by default. If any cell voltage is below V_UVREGat device power up, the

regulated output will remain on until the t_{UV_DELAY}time has passed, the regulated output turns off after the delay

time.

During discharge, if any cell voltage falls below the V_UVREGthreshold for t_{UV_DELAY}time, the regulated output is

self-disabled. The regulated output turns on again when all the cell voltages are above V_UVREG+ V_UVHYS

VUVREG + VUVHYS

VUVREG

tUVDELAY

REG (V)

Figure 8-2. REG Output Timing

8.4 Device Functional Modes

8.4.1 NORMAL Mode

When all of the cell voltages are below the V_OVthreshold AND above V_UVREGthreshold, the device operates

in NORMAL mode. The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1), (V3–

V2), and (V4–V3). The OUT pin is inactive in this mode. The regulated output is always enabled for BQ2961.

8.4.2 OVERVOLTAGE Mode

OVERVOLTAGE mode is detected if any of the cell voltages exceed the overvoltage threshold, V_OV, for a

configured OV delay time. The OUT pin is activated after a delay time preprogrammed at the factory. The OUT

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pin will pull high internally. Then an external FET is turned on, shorting the fuse to ground, which allows the

battery and/or charger power to blow the fuse. When all of the cell voltages fall below (V_OV– V_HYS), the device

returns to NORMAL mode. The regulated output (if enabled) remains on in this mode.

8.4.3 UNDERVOLTAGE Mode

The UNDERVOLTAGE mode is detected if any of the cell voltage across (V1–VSS), (V2–V1), (V3–V2), or (V4–

V3) is below the V_UVREGthreshold for t_{UV_DELAY}time. In this mode, the regulated output is disabled. To return to

the NORMAL mode, all the cell voltages must be above (V_UVREG+ V_UVHYS).

For a low cell configuration, V_npin can be shorted to the (V_{n – 1}) pin. The device ignores any differential cell

voltage below V_UVQUALthreshold for undervoltage detection.

8.4.4 CUSTOMER TEST MODE

The Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay-timer parameter

once the circuit is implemented into the battery pack. To enter CTM, the VDD pin should be set at least 10 V

higher than V3 (see Figure 8-3). The delay timer is greater than 10 ms, but considerably shorter than the timer

delay in normal operation. To exit CTM, remove the VDD to VC3 voltage differential of 10 V, so that the decrease

in the value automatically causes an exit.

CAUTION

Avoid exceeding any Absolute Maximum Voltages on any pins when placing the device into CTM.

Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (V3–V2), (V2–V1)

and (V1–VSS). Stressing the pins beyond the rated limits can cause permanent damage to the

device.

Figure 8-3 shows the timing for the Customer Test Mode.

VDD œ V3 = 10V

VDD

> 10ms

OUT (V)

Figure 8-3. Timing for Customer Test Mode

Figure 8-4 shows the measurement for current consumption of the product for both VDD and Vx.

I_CC

OUT 8

REG 7

VDD

I_IN

VDC

3.6 V

0.47 µF

I_IN

VSS

I_IN

REG_EN

Figure 8-4. Configuration for Integrated Circuit Current Consumption Test

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The BQ296xxx family of second-level protectors is used for overvoltage protection of the battery pack in the

application. A regulated output is available to drive a small circuit with maximum I_REGloading. The device OUT

pin is active high, which drives a NMOS FET that connects the fuse to ground in the event of a fault condition.

This provides a shorted path to use the battery and/or charger power to blow the fuse and cut the power path.

9.2 Typical Application

Application Schematic shows the recommended reference design components.

Pack +

Protector

FETs

100 Ω

OUT

REG

VDD

External

Circuit

e.g., RTC

1 kΩ

5 ꢀ (*)

0.1µF

VCELL4

VCELL3

VSS

* can be removed if Vss will be

connected first during cell

connection

PWPD

VCELL2

VCELL1

1 kΩ

0.1µF

0.47 µF

0.1µF

Pack œ

Figure 9-1. Application Schematic

Note

9.2.1 Design Requirements

Changes to the ranges shown in Table 9-1 will impact the accuracy of the cell measurements.

Table 9-1. Parameters

PARAMETER

Voltage monitor filter resistance

EXTERNAL COMPONENT

MIN

NOM

1000

MAX

4700

UNIT

R_IN

C_IN

900

0.01

0.1

Voltage monitor filter capacitance

Supply voltage filter resistance

Supply voltage filter capacitance

REG output capacitance

0.1

—

0.1

1.0

µF

KΩ

µF

R_VD

C_VD

C_REG

—

1.0

—

0.47

Note

The device is calibrated using an R_INvalue = 1 kΩ. Using a value other than the recommended value

changes the accuracy of the cell voltage measurements and V_OVtrigger level.

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9.2.2 Detailed Design Procedure

Note

The device VSS must be connected first during PCB test or cell attachment. Failure to do so can

damage the REG pin.

1. If the VSS pin cannot be connected first, it is required to add a resistor of a minimum of 5 Ω to a maximum of

10 Ω (a 5-Ω resistor is used in the reference schematic, Figure 9-2) in series with the REG capacitor. When

VSS is floating, the REG capacitor always charges up to the VDD voltage. When VSS is finally connected,

the REG capacitor will be discharged. Adding a small resistor in series reduces the current strength and

avoids any potential damage to the REG pin. The 5-Ω resistor can be placed in series with the REG connect

circuit (as shown in Figure 9-2) or in series of the REG capacitor (as shown in Figure 9-3). Placing the

resistor in series with the REG circuit results in a small drop of V_REG(for example: max loading of I_REGmA

with a 5-Ω resistor will drop 5 mV on V_REG), but such a connection can protect again rush current discharge

from a REG capacitor or an external filter capacitor connected to the REG pin. Placing the resistor in series

with the REG capacitor is an alternative to avoiding an additional drop in V_REGif the filter capacitor used by

the external circuit is much smaller than the REG capacitor.

2. After VSS is connected, the device allows a random cell connection to the Vx pin.

3. The cell should be connected to the lower V_npin; the unused V_npin should be shorted to the (V_n-1) pin. See

Figure 9-2 for details.

Pack +

Protector

FETs

100 Ω

OUT

REG

VDD

External

Circuit

e.g., RTC

5 Ω (*)

1 kΩ

0.1µF

bq2961

bq2962

VSS

VCELL3

VCELL2

1 kΩ

0.1µF

PWPD

0.1µF

0.47 µF

1 kΩ

0.1µF

VCELL1

Pack œ

Figure 9-2. 3-Series BQ2961 and BQ2962 Schematic

4. A Zener diode can be added to the REG pin to VSS, as shown in Figure 9-3. This is recommended to protect

the circuit connected to the REG pin if floating VSS in the field is a risk concern. When VSS is floating

(during cell connection when VSS is not connected first or in a system fault with a broken BAT– wire), the

REG voltage always pulls up to VDD. In a 4-series configuration, the REG voltage can reach approximately

16 V with VSS floating. Adding a Zener diode clamps the REG voltage to a safe level for the external circuits

connected to the REG pin. Having the Zener diode can also protect the external circuits if the REG pin is

shorted to the OUT pin or any other high-voltage output terminal. If a Zener diode is used, TI recommends

putting the diode on the battery side with the BQ296xxx device to allow protection on the REG pin, as well as

the circuit connected to REG under the floating VSS condition. The resistor in series with the REG pin is not

required in this case.

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REG

The 5-Ω resistor limits the rush current

discharge from the capacitor during cell

connection when Vss is not connected

first.

Loss of Vss connection or REG shorted to

high voltage can bring the REG above the

regulated range. This optional zener

clamp can protect the downstream circuit

under such an event.

5 Ω

0.47 µF

This resistor is not required if Vss is

connected first in the cell connection

sequence.

Figure 9-3. 5-V Zener Diode

9.2.3 Application Curves

Figure 9-5. Overvoltage Protection Release

Figure 9-4. Overvoltage Protection

Figure 9-7. Undervoltage Release to Switch On the

Regulator

Figure 9-6. Undervoltage Detection to Turn Off the

Regulator

10 Power Supply Recommendations

The maximum power is 20 V for BQ2961 and BQ2962 on VDD.

Note

Connect VSS first during power up.

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11 Layout

11.1 Layout Guidelines

Use the following layout guidelines:

1. Ensure the RC filters for the Vx pins and VDD pin are placed as close as possible to the target terminal,

reducing the tracing loop area.

2. The capacitor for REG should be placed close to the device terminals.

3. Ensure the trace connecting the fuse to the gate, source of the NFET to the Pack– is sufficient to withstand

the current during a fuse blown event.

11.2 Layout Example

Place the RC filters close

to device terminals

Power Trace Line

Pack +

VDD

OUT

REG

External

Circuit

e.g., RTC

5 ꢀ (*)

VSS

Pack œ

VCELL3

VCELL2

VCELL1

PWPD

* can be removed if Vss

will be connected first

during cell connection

Ensure trace can support sufficient

current flow for fuse blow

Figure 11-1. Layout Example

12 Device and Documentation Support

12.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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28-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ296100DSGR

BQ296100DSGT

BQ296103DSGR

BQ296103DSGT

BQ296106DSGR

BQ296106DSGT

BQ296107DSGR

BQ296107DSGT

BQ296111DSGR

BQ296111DSGT

BQ296112DSGR

BQ296112DSGT

BQ296113DSGR

BQ296113DSGT

BQ296114DSGR

BQ296114DSGT

BQ296115DSGR

BQ296202DSGR

BQ296202DSGT

BQ296203DSGR

ACTIVE

WSON

DSG

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 110

6100

6103

6106

6107

6111

6112

6113

6114

6115

6202

6203

NIPDAU

3000 RoHS & Green

250

RoHS & Green

3000 RoHS & Green

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ296203DSGT

BQ296212DSGR

BQ296212DSGT

BQ296213DSGR

BQ296213DSGT

BQ296215DSGR

BQ296215DSGT

BQ296216DSGR

BQ296216DSGT

BQ296217DSGR

BQ296217DSGT

BQ296221DSGR

BQ296221DSGT

BQ296222DSGR

BQ296222DSGT

BQ296223DSGR

BQ296223DSGT

BQ296224DSGR

BQ296224DSGT

BQ296226DSGR

BQ296226DSGT

ACTIVE

WSON

DSG

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

-40 to 110

6203

6212

6213

6215

6216

6217

6221

6222

6223

6224

6226

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

NIPDAU

250

RoHS & Green

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2021

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BQ296227DSGR

BQ296228DSGR

BQ296228DSGT

BQ296229DSGR

BQ296229DSGT

BQ296230DSGR

BQ296230DSGT

BQ296231DSGR

BQ296231DSGT

BQ296232DSGR

BQ296232DSGT

BQ296233DSGR

ACTIVE

WSON

DSG

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

-40 to 110

6227

6228

6229

6230

6231

6232

6233

NIPDAU

250

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

28-Sep-2021

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ296100DSGR

BQ296100DSGT

BQ296103DSGR

BQ296103DSGT

BQ296106DSGR

BQ296106DSGT

BQ296107DSGR

BQ296107DSGT

BQ296111DSGR

BQ296111DSGT

BQ296112DSGR

BQ296112DSGT

WSON

DSG

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ296113DSGR

BQ296113DSGT

BQ296114DSGR

BQ296114DSGT

BQ296115DSGR

BQ296202DSGR

BQ296202DSGT

BQ296203DSGR

BQ296203DSGT

BQ296212DSGR

BQ296212DSGT

BQ296213DSGR

BQ296213DSGT

BQ296215DSGR

BQ296215DSGT

BQ296216DSGR

BQ296216DSGT

BQ296217DSGR

BQ296217DSGT

BQ296221DSGR

BQ296221DSGT

BQ296222DSGR

BQ296222DSGT

BQ296223DSGR

BQ296223DSGT

BQ296224DSGR

BQ296224DSGT

BQ296226DSGR

BQ296226DSGT

BQ296227DSGR

BQ296228DSGR

BQ296228DSGT

BQ296229DSGR

BQ296229DSGT

BQ296230DSGR

WSON

DSG

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ296230DSGT

BQ296231DSGR

BQ296231DSGT

BQ296232DSGR

BQ296232DSGT

BQ296233DSGR

WSON

DSG

250

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

3000

250

3000

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ296100DSGR

BQ296100DSGT

BQ296103DSGR

BQ296103DSGT

BQ296106DSGR

BQ296106DSGT

BQ296107DSGR

WSON

DSG

3000

250

210.0

185.0

35.0

3000

250

3000

250

3000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ296107DSGR

BQ296107DSGT

BQ296111DSGR

BQ296111DSGT

BQ296112DSGR

BQ296112DSGT

BQ296113DSGR

BQ296113DSGT

BQ296114DSGR

BQ296114DSGT

BQ296115DSGR

BQ296202DSGR

BQ296202DSGT

BQ296203DSGR

BQ296203DSGT

BQ296212DSGR

BQ296212DSGT

BQ296213DSGR

BQ296213DSGT

BQ296215DSGR

BQ296215DSGT

BQ296216DSGR

BQ296216DSGT

BQ296217DSGR

BQ296217DSGT

BQ296221DSGR

BQ296221DSGT

BQ296222DSGR

BQ296222DSGT

BQ296223DSGR

BQ296223DSGT

BQ296224DSGR

BQ296224DSGT

BQ296226DSGR

BQ296226DSGT

WSON

DSG

3000

250

210.0

185.0

35.0

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

28-Oct-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ296227DSGR

BQ296228DSGR

BQ296228DSGT

BQ296229DSGR

BQ296229DSGT

BQ296230DSGR

BQ296230DSGT

BQ296231DSGR

BQ296231DSGT

BQ296232DSGR

BQ296232DSGT

BQ296233DSGR

WSON

DSG

3000

250

210.0

185.0

35.0

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 5

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

6X 0.5

1.5

1.6 0.1

0.32

0.18

0.4

0.2

PIN 1 ID

0.1

C A B

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

8X (0.25)

(0.55)

SYMM

(1.6)

6X (0.5)

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

SYMM

8X (0.25)

(0.45)

SYMM

(0.7)

6X (0.5)

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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