BQ29733 [TI]

BQ297xx Cost-Effective Voltage and Current Protection Integrated Circuit for Single-Cell Li-Ion and Li-Polymer Batteries;


型号：	BQ29733
厂家：	TEXAS INSTRUMENTS
描述：	BQ297xx Cost-Effective Voltage and Current Protection Integrated Circuit for Single-Cell Li-Ion and Li-Polymer Batteries
文件：	总32页 (文件大小：1964K)
中文：	中文翻译
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BQ2970, BQ2971, BQ2972, BQ2973

SLUSBU9G –MARCH 2014–REVISED JANUARY 2020

BQ297xx Cost-Effective Voltage and Current Protection Integrated Circuit for Single-Cell

Li-Ion and Li-Polymer Batteries

1 Features

2 Applications

•

Input voltage range pack+: VSS – 0.3 V to 12 V

FET drive:

•

Tablet PCs

Mobile handsets

Handheld data terminals

–

CHG and DSG FET drive output

•

Voltage sensing across external FETs for

overcurrent protection (OCP) is within ±5 mV

(typical)

3 Description

The BQ2970 battery cell protection device provides

an accurate monitor and trigger threshold for

overcurrent protection during high discharge/charge

current operation or battery overcharge conditions.

Fault detection

–

Overcharge detection (OVP)

Over-discharge detection (UVP)

Charge overcurrent detection (OCC)

Discharge overcurrent detection (OCD)

Load short-circuit detection (SCP)

The BQ2970 device provides the protection functions

for li-ion/li-polymer cells, and monitors across the

external power FETs for protection due to high

charge or discharge currents. In addition, there is

overcharge and depleted battery monitoring and

protection. These features are implemented with low

current consumption in NORMAL mode operation.

•

Zero voltage charging for depleted battery

Factory programmed fault protection thresholds

–

Fault detection voltage thresholds

Fault trigger timers

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

Fault recovery timers

BQ2970, BQ2971,

BQ2972, BQ2973⁽²⁾

WSON (6)

1.50 mm × 1.50 mm

•

Modes of operation without battery charger

enabled

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

NORMAL mode I_CC= 4 µA

Shutdown Iq = 100 nA

(2) For available released devices, see the Device Comparison

Table.

•

Operating temperature range T_A= –40°C to

+85°C

Package:

–

6-pin DSE (1.50 mm × 1.50 mm × 0.75 mm)

Simplified Schematic

OCD Detection Accuracy Versus Temperature

PACK+

0.0

œ0.5

œ1.0

œ1.5

œ2.0

œ2.5

œ3.0

œ3.5

œ4.0

V–

330

BAT

VSS

COUT

DOUT

CELLP

CELLN

2.2k

PACK–

CHG

DSG

100

120

œ40

œ20

Temperature (°C)

C012

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

BQ2970, BQ2971, BQ2972, BQ2973

SLUSBU9G –MARCH 2014–REVISED JANUARY 2020

www.ti.com

Table of Contents

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

6.1 Pin Descriptions ........................................................ 4

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 DC Characteristics .................................................... 5

7.6 Programmable Fault Detection Thresholds ............. 6

7.7 Programmable Fault Detection Timer Ranges ........ 6

7.8 Typical Characteristics.............................................. 7

Parameter Measurement Information ................ 10

8.1 Timing Charts.......................................................... 10

8.2 Test Circuits ............................................................ 12

8.3 Test Circuit Diagrams ............................................. 14

Detailed Description ............................................ 14

9.1 Overview ................................................................. 14

9.2 Functional Block Diagram ....................................... 15

9.3 Feature Description ................................................ 15

9.4 Device Functional Modes........................................ 15

10 Application and Implementation........................ 19

10.1 Application Information.......................................... 19

10.2 Typical Application ................................................ 19

11 Power Supply Recommendations ..................... 22

12 Layout................................................................... 22

12.1 Layout Guidelines ................................................ 22

12.2 Layout Example .................................................... 22

13 Device and Documentation Support ................. 23

13.1 Related Documentation......................................... 23

13.2 Related Links ........................................................ 23

13.3 Support Resources ............................................... 23

13.4 Trademarks........................................................... 23

13.5 Electrostatic Discharge Caution............................ 23

13.6 Glossary................................................................ 23

14 Mechanical, Packaging, and Orderable

Information ........................................................... 23

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (December 2018) to Revision G

Page

•

Changed the Device Comparison Table................................................................................................................................. 3

Changes from Revision E (May 2018) to Revision F

Page

•

Changed the BQ29728 device to Production Data ................................................................................................................ 3

Added the BQ29737 device.................................................................................................................................................... 3

Changes from Revision D (May 2016) to Revision E

Page

•

Changed 0-V Charging Function Enabled ........................................................................................................................... 17

Changed 0-V Charging Inhibit Function .............................................................................................................................. 17

Changes from Revision C (March 2016) to Revision D

Page

•

Changed BQ29733 to released in the Device Comparison Table. ........................................................................................ 3

Changes from Revision B (November, 2015) to Revision C

Page

•

Added the device numbers BQ2971, BQ2972, BQ2973. Changed document title to BQ297xx............................................ 1

Added BQ29708~BQ29733 to the Device Comparison Table. Clarified recovery delay and moved info to footnote 2 ........ 3

Changed UVP release voltage value based on 100-mV hysteresis from UVP threshold.................................................... 19

Added Related Links table.................................................................................................................................................... 23

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SLUSBU9G –MARCH 2014–REVISED JANUARY 2020

Changes from Revision A (June, 2014) to Revision B

Page

•

Changed the device number to BQ2970 ............................................................................................................................... 1

Deleted the Related Links table from the Device and Documentation Support section....................................................... 23

5 Device Comparison Table

UVP

DELAY

(ms)

OCC

DELAY

(ms)

OCD

DELAY

(ms)

PART

OVP

DELAY (s)

SCD DELAY

(µs)

OVP (V)

UVP (V)

OCC (V)

OCD (V)

SCD (V)

NUMBER⁽¹⁾

BQ29700

BQ29701

BQ29702

BQ29703

BQ29704

BQ29705

BQ29706

BQ29707

BQ29716

BQ29717

BQ29718

BQ29723

BQ29728⁽²⁾

BQ29729

BQ29732

BQ29733

BQ29737⁽²⁾

4.275

4.280

4.350

4.425

3.850

4.280

4.425

4.280

4.275

4.280

4.400

4.250

1.25

2.800

2.300

2.800

2.300

2.500

2.800

2.300

2.500

2.800

2.300

2.500

2.800

144

–0.100

–0.155

–0.100

–0.150

–0.090

–0.100

–0.060

–0.100

-0.050

0.100

0.125

0.160

0.125

0.150

0.200

0.090

0.165

0.130

0.100

0.150

0.130

0.190

0.120

0.100

0.5

0.3

0.5

0.6

0.3

0.5

0.3

0.5

0.3

250

1.25

144

1.25

144

0.25, 1,

1.25, 4.5

20, 96, 125, –0.045 to

144 –0.155

8, 16, 20,

0.3, 0.4,

0.5, 0.6

BQ297xy

3.85–4.6

2.0–2.8

4, 6, 8, 16

0.090–0.200

250

(1) All of the protections have a recovery delay time. The recovery timer starts as soon as the fault is triggered. The device starts to check

for a recovery condition only when the recovery timer expires. This is NOT a delay time between recovery condition to FETs recovery.

OVP recovery delay = 12 ms; UVP/OCC/OCD recovery delay = 8 ms.

(2) Contact TI for more information.

6 Pin Configuration and Functions

DSE Package

6-PIN WSON

Top View

COUT

DOUT

V–

BAT

VSS

Pin Functions

DESCRIPTION

VDD pin

TYPE

NAME

BAT

NO.

COUT

Gate Drive Output for Charge FET

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Pin Functions (continued)

TYPE

DESCRIPTION

NAME

DOUT

NO.

Gate Drive Output for Discharge FET

No Connection (electrically open, do not connect to BAT or VSS)

Ground pin

VSS

V–

I/O

Input pin for charger negative voltage

6.1 Pin Descriptions

6.1.1 Supply Input: BAT

This pin is the input supply for the device and is connected to the positive terminal of the battery pack. A 0.1-µF

input capacitor is connected to ground for filtering noise.

6.1.2 Cell Negative Connection: VSS

This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage

measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense

resistor sensing will be referenced to this node.

6.1.3 Voltage Sense Node: V–

This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or

overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the

differential measurement for the stated fault detection conditions. A 2.2-kΩ resistor is connected between this

input pin and Pack– terminal of the system in the application.

6.1.4 Discharge FET Gate Drive Output: DOUT

This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output transitions from high to low when a fault is detected, and requires the DSG FET to turn

OFF. A 5-MΩ high impedance resistor is connected from DOUT to VSS for gate capacitance discharge when the

FET is turned OFF.

6.1.5 Charge FET Gate Drive Output: COUT

This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn

OFF. A 5-MΩ high impedance resistor is connected from COUT to Pack– for gate capacitance discharge when

FET is turned OFF.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

UNIT

Input voltage: BAT

Supply control and input

V– pin(pack–)

BAT – 28

VSS – 0.3

BAT – 28

–40

BAT + 0.3

DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive)

FET drive and protection COUT (Charge FET Output), GCHG (Charge FET Gate Drive)

Operating temperature: T_FUNC

°C

Storage temperature, T_stg

–55

150

(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.

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SLUSBU9G –MARCH 2014–REVISED JANUARY 2020

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001, all pins⁽²⁾

±2000

Electrostatic

Discharge

(1)

V_ESD

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽³⁾

±500

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V

can have higher performance.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V

can have higher performance.

7.3 Recommended Operating Conditions⁽¹⁾

MIN

–0.3

MAX

UNIT

Positive input voltage: BAT

Supply control and

input

Negative input voltage: V–

BAT – 25

VSS

BAT

Discharge FET control: DOUT

Charge FET control: COUT

FET drive and

protection

BAT – 25

–40

Operating temperature: T_Amb

Storage temperature: T_S

°C

°C/W

–55

150

300

250

Temperature Ratings

Lead temperature (soldering 10 s)

Thermal resistance junction to ambient, θ_JA

(1)

(1) For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

BQ297xx

THERMAL METRIC⁽¹⁾

DSE (WSON)

12 PINS

190.5

UNIT

R_{θJA, High K}

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

94.9

149.3

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

6.4

ψ_JB

152.8

R_θJC(bottom)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 DC Characteristics

Typical Values stated where T_A= 25°C and BAT = 3.6 V. Min/Max values stated where T_A= –40°C to 85°C, and BAT = 3 V

to 4.2 V (unless otherwise noted)

PARAMETER

Current consumption

TEST CONDITIONS

MIN

TYP

MAX UNIT

BAT – VSS

BAT – V–

1.5

V_BAT

Device operating range

I_NORMAL

Current consumption in NORMAL mode

BAT = 3.8 V, V– = 0 V

5.5

0.1

µA

I_{Power_down}Current consumption in power down mode BAT = V– = 1.5 V

FET Output, DOUT and COUT

V_OL

V_OH

V_OL

V_OH

Charge FET low output

Charge FET high output

Discharge FET low output

Discharge FET high output

I_OL= 30 µA, BAT = 3.8 V

I_OH= –30 µA, BAT = 3.8 V

I_OL= 30 µA, BAT = 2 V

I_OH= –30 µA, BAT = 3.8 V

0.4

3.7

0.2

3.7

0.5

3.4

Pullup Internal Resistance on V–

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DC Characteristics (continued)

Typical Values stated where T_A= 25°C and BAT = 3.6 V. Min/Max values stated where T_A= –40°C to 85°C, and BAT = 3 V

to 4.2 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_BAT= 1.8 V, V– = 0 V

MIN

TYP

MAX UNIT

R_V–D

Resistance between V– and VBAT

100

300

550

kΩ

Current sink on V–

I_V–S

Current sink on V– to VSS

V_BAT= 3.8 V

µA

Load short detection on V–

V_BAT

1 V

–

V_short

Short detection voltage

V_BAT= 3.8 V and R_PackN= 2.2 kΩ

0-V battery charging function allowed

0-V battery charging function disallowed

0-V battery charge function

V_0CHG

0-V battery charging start voltage

1.7

0-V battery charge inhibit function

0-V battery charging inhibit voltage

threshold

V_0INH

0.75

7.6 Programmable Fault Detection Thresholds

PARAMETER

CONDITION

MIN

TYP

MAX UNIT

T_A= 25°C

–10

Factory Device Configuration: 3.85 V to

4.60 V in 50-mV steps

V_OVP

Overcharge detection voltage

T_A= 0°C to

60°C

–20

Overcharge release hysteresis 100 mV and (VSS – V–) > OCC (min) for release, T_A

V_OVP–Hys

V_UVP

–20

–50

voltage

25°C

Over-discharge detection

voltage

Factory Device Configuration: 2.00 V to 2.80 V in 50-mV

steps, T_A= 25°C

Over-discharge release

hysteresis voltage

V_UVP+Hys

100 mV and (BAT – V–) > 1 V for release, T_A= 25°C

–50

–10

–15

T_A= 25°C

Discharging overcurrent

detection voltage

Factory Device Configuration: 90 mV to

200 mV in 5-mV steps

V_OCD

T_A= –40°C to

85°C

Release when BAT – V– > 1 V

T_A= 25°C

Release of

V_OCD

Release of discharging

overcurrent detection voltage

–10

–15

Charging overcurrent detection Factory Device Configuration: –45 mV to

voltage

V_OCC

T_A= –40°C to

85°C

–155 mV in 5-mV steps

Release of

V_OCC

Release of overcurrent

detection voltage

Release when VSS – V– ≥ OCC (min)

Factory Device Configuration: 300 mV,

400 mV, 500 mV, 600 mV

V_SCC

Short Circuit detection voltage

T_A= 25°C

–100

100

Release of Short Circuit

detection voltage

V_SCCR

Release when BAT – V– ≥ 1 V

7.7 Programmable Fault Detection Timer Ranges

PARAMETER

CONDITION

MIN

TYP

MAX UNIT

t_OVPD

t_UVPD

Overcharge detection delay time Factory Device Configuration: 0.25 s, 1 s, 1.25 s, 4.5 s

–20%

20%

Over-discharge detection delay

time

Factory Device Configuration: 20 ms, 96 ms, 125 ms, 144

–20%

20%

Discharging overcurrent detection

delay time

t_OCDD

Factory Device Configuration: 8 ms, 16 ms, 20 ms, 48 ms –20%

20%

Charging overcurrent detection

delay time

t_OCCD

t_SCCD

Factory Device Configuration: 4 ms, 6 ms, 8 ms, 16 ms

–20%

–50%

20%

50%

µs

Short Circuit detection delay time 250 µs (fixed)

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7.8 Typical Characteristics

0.050

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0.000

100

120

œ40

œ20

100

120

œ40

œ20

Temperature (°C)

C002

C001

V_BAT= 3.9 V

V_BAT= 1.5 V

Figure 2. 3.9-V I_BATVersus Temperature

Figure 1. 1.5-V I_BATVersus Temperature

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

1.18

œ1.32

œ1.34

œ1.36

œ1.38

œ1.40

œ1.42

œ1.44

œ1.46

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C003

C004

F_OSC, Setting = 1.255 kHz

V_BAT, Setting = 0 V

Figure 3. Internal Oscillator Frequency Versus Temperature

Figure 4. 0-V Charging Allowed Versus Temperature

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

œ2

œ4

œ6

œ8

œ10

œ12

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C005

C006

OVP, Setting = 4.275 V

Figure 5. 0-V Charging Disallowed Versus Temperature

Figure 6. OVP Detection Accuracy Versus Temperature

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Typical Characteristics (continued)

1350

œ2

1300

1250

1200

1150

1100

œ4

œ6

œ8

œ10

œ12

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C007

C008

t_OVPD, Setting = 1.25 s

UVP, Setting = 2.800 V

Figure 7. OVP Detection Dely Time Versus Temperature

Figure 8. UVP Detection Accuracy Versus Temperature

160

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ1.2

œ1.4

œ1.6

œ1.8

155

150

145

140

135

130

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C009

C010

t_UVPD, Setting = 144 ms

V_OCC, Setting = –100 mV

Figure 9. UVP Detection Delay Time Versus Temperature

Figure 10. OCC Detection Accuracy Versus Temperature

8.6

0.0

8.4

8.2

8.0

7.8

7.6

7.4

7.2

7.0

œ0.5

œ1.0

œ1.5

œ2.0

œ2.5

œ3.0

œ3.5

œ4.0

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C011

C012

t_OCCD, Setting = 8 ms

V_OCD, Setting = 100 mV

Figure 11. OCC Detection Delay Time Versus Temperature

Figure 12. OCD Detection Accuracy Versus Temperature

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Typical Characteristics (continued)

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C013

C014

t_UVPD, Setting = 20 ms

V_SCC, Setting = 500 mV

Figure 13. OCD Detection Delay Time Versus Temperature

Figure 14. SCC Detection Accuracy Versus Temperature

1.24

3.795

1.22

1.20

1.18

1.16

1.14

1.12

1.10

3.790

3.785

3.780

3.775

3.770

3.765

100

120

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C015

C016

V_BAT, Setting = 3.9 V

Figure 15. Power On Reset Versus Temperature

Figure 16. COUT Versus Temperature with I_oh= –30 µA

3.7160

3.7155

3.7150

3.7145

3.7140

3.7135

100

120

œ40

œ20

Temperature (°C)

C017

V_BAT, Setting = 3.9 V

Figure 17. DOUT Versus Temperature with I_oh= –30 µA

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8 Parameter Measurement Information

8.1 Timing Charts

Over-

Discharge

Normal

Overcharge

Normal

OVP

OVP– Hys

UVP– Hys

UVP

BAT

PACK–

BAT

OCD

PACK–

UVPD

OVPD

Charger

Connected

Load

Connected

Charger

Connected

Figure 18. Overcharge Detection, Over-Discharge Detection

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Timing Charts (continued)

Normal

Discharge Overcurrent

Normal

Discharge Overcurrent

Normal

OVP

OVP–Hys

UVP+Hys

UVP

BAT

VSS

BAT

VSS

PACK–

BAT

SCC

OCD

VSS

OCDD

SCCD

Load

Connected

Load

Disconnected

Load Short-

Circuit

Figure 19. Discharge Overcurrent Detection

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8.2 Test Circuits

The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the

threshold voltage of the external logic level FETs and regarded as ON state. “L” is less than the turn ON

threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the

DOUT pin is with respect to VSS.

1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):

The overcharge detection voltage (V_OVP) is measured between the BAT and VSS pins, respectively. Once V1

is increased, the over-detection is triggered, and the delay timer expires. Then, COUT transitions from a high

to low state and reduces the V1 voltage to check for the overcharge hysteresis parameter (V_OVP-Hys). The

delta voltage between overcharge detection voltages (V_OVP) and the overcharge release occurs when the

CHG FET drive output goes from low to high.

2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):

Over-discharge detection (V_UVP) is defined as the voltage between BAT and VSS at which the DSG drive

output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is

set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the

DOUT drive output transition from low to high when V1 voltage is gradually increased from a V_UVPcondition.

The overcharge hysteresis voltage is defined as the delta voltage between V_UVPand the instance at which

the DOUT output drive goes from low to high.

3. Discharge overcurrent detection voltage (Test Circuit 2):

The discharge overcurrent detection voltage (V_OCD) is measured between V– and VSS pins and triggered

when the V2 voltage is increased above V_OCDthreshold with respect to VSS. This delta voltage once

satisfied will trigger an internal timer t_OCDDbefore the DOUT output drive transitions from high to low.

4. Load short circuit detection voltage (Test Circuit 2):

Load short-circuit detection voltage (V_SCC) is measured between V– and VSS pins and triggered when the V2

voltage is increased above V_SCCthreshold with respect to VSS within 10 µs. This delta voltage, once

satisfied, triggers an internal timer t_SCCDbefore the DOUT output drive transitions from high to low.

5. Charge overcurrent detection voltage (Test Circuit 2):

The charge overcurrent detection voltage (V_OCC) is measured between VSS and V– pins and triggered when

the V2 voltage is increased above V_OCCthreshold with respect to V–. This delta voltage, once satisfied,

triggers an internal timer t_OCCDbefore the COUT output drive transitions from high to low.

6. Operating current consumption (Test Circuit 2):

The operating current consumption I_BNORMALis the current measured going into the BAT pin under the

following conditions: V1 = 3.9 V and V2 = 0 V.

7. Power down current consumption (Test Circuit 2):

The operating current consumption I_{Power_down}is the current measured going into the BAT pin under the

following conditions: V1 = 1.5 V and V2 = 1.5 V.

8. Resistance between V– and BAT pin (Test Circuit 3):

Measure the resistance (R_{V_D}) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and

V2 = 0 V.

9. Current sink between V– and VSS (Test Circuit 3):

Measure the current sink I_V–Sbetween V– and VSS pins by setting the following condition: V1 = 4 V.

10. COUT current source when activated High (Test Circuit 4):

Measure I_COUTcurrent source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and

V3 = 3.4 V.

11. COUT current sink when activated Low (Test Circuit 4):

Measure I_COUTcurrent sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V, and V3 =

0.5 V.

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Test Circuits (continued)

12. DOUT current source when activated High (Test Circuit 4):

Measure I_DOUTcurrent source on DOUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V, and V3

= 3.4 V.

13. DOUT current sink when activated Low (Test Circuit 4):

Measure I_DOUTcurrent sink on DOUT pin by setting the following conditions: V1 = 2.0 V, V2 = 0 V, and V3 =

0.4 V.

14. Overcharge detection delay (Test Circuit 5):

The overcharge detection delay time t_OVPDis the time delay before the COUT drive output transitions from

high to low once the voltage on V1 exceeds the V_OVPthreshold. Set V2 = 0 V and then increase V1 until BAT

input exceeds the V_OVPthreshold, then check the time for when COUT goes from high to low.

15. Over-discharge detection delay (Test Circuit 5):

The over-discharge detection delay time t_UVPDis the time delay before the DOUT drive output transitions

from high to low once the voltage on V1 decreases to V_UVPthreshold. Set V2 = 0 V and then decrease V1

until BAT input reduces to the V_UVPthreshold, then check the time of when DOUT goes from high to low.

16. Discharge overcurrent detection delay (Test Circuit 5):

The discharge overcurrent detection delay time t_OCDDis the time for DOUT drive output to transition from

high to low after the voltage on V2 is increased from 0 V to 0.35 V. V1 = 3.5 V and V2 starts from 0 V and

increases to trigger threshold.

17. Load short circuit detection delay (Test Circuit 5):

The load short-circuit detection delay time t_SCCDis the time for DOUT drive output to transition from high to

low after the voltage on V2 is increased from 0 V to V1 – 1 V. V1 = 3.5 V and V2 starts from 0 V and

increases to trigger threshold.

18. Charge overcurrent detection delay (Test Circuit 5):

The charge overcurrent detection delay time t_OCCDis the time for COUT drive output to transition from high to

low after the voltage on V2 is decreased from 0 V to –0.3 V. V1 = 3.5 V and V2 starts from 0 V and

decreases to trigger threshold.

19. 0-V battery charge starting charger voltage (Test Circuit 2):

The 0-V charge for start charging voltage V_0CHAis defined as the voltage between BAT and V– pins at which

COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0 V.

20. 0-V battery charge inhibition battery voltage (Test Circuit 2):

The 0-V charge inhibit for charger voltage V_0INHis defined as the voltage between BAT and VSS pins at

which COUT should go low as V1 is gradually decreased from V1 = 2 V and V2 = –4 V.

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8.3 Test Circuit Diagrams

V-

BAT

220Ω

COUT

DOUT

BAT

VSS

COUT

DOUT

BAT

VSS

COUT

VCOUT V

DOUT

Figure 20. Test Circuit 1

Figure 21. Test Circuit 2

V-

COUT

BAT

COUT

DOUT

BAT

VSS

COUT

DOUT

BAT

VSS

DOUT

Figure 22. Test Circuit 3

Figure 23. Test Circuit 4

V-

Oscilloscope

COUT

DOUT

BAT

VSS

Figure 24. Test Circuit 5

9 Detailed Description

9.1 Overview

This BQ2970 device is a primary protector for a single-cell Li-Ion/Li-Polymer battery pack. The device uses a

minimum number of external components to protect for overcurrent conditions due to high discharge/charge

currents in the application. In addition, it monitors and helps to protect against battery pack overcharging or

depletion of energy in the pack. The BQ2970 device is capable of having an input voltage of 8 V from a charging

adapter and can tolerate a voltage of BAT – 25 V across the two input pins. In the condition when a fault is

triggered, there are timer delays before the appropriate action is taken to turn OFF either the CHG or DSG FETs.

The recovery period also has a timer delay once the threshold for recovery condition is satisfied. These

parameters are fixed once they are programmed. There is also a feature called zero voltage charging that

enables depleted cells to be charged to an acceptable level before the battery pack can be used for normal

operation. Zero voltage charging is allowed if the charger voltage is above 1.7 V. For Factory Programmable

Options, see Table 1.

Table 1. Factory Programmable Options

PARAMETER

FACTORY DEVICE CONFIGURATION

3.85 V to 4.60 V in 50-mV steps

V_OVP

V_UVP

V_OCD

V_OCC

V_SCC

t_OVPD

t_UVPD

t_OCDD

Overcharge detection voltage

Over-discharge detection voltage

Discharging overcurrent detection voltage

Charging overcurrent detection voltage

Short Circuit detection voltage

2.00 V to 2.80 V in 50-mV steps

90 mV to 200 mV in 5-mV steps

–45 mV to –155 mV in 5-mV steps

300 mV, 400 mV, 500 mV, 600 mV

0.25 s, 1.00 s, 1.25 s, 4.50 s

Overcharge detection delay time

Over-discharge detection delay time

Discharging overcurrent detection delay time

20 ms, 96 ms, 125 ms, 144 ms

8 ms, 16 ms, 20 ms, 48 ms

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Overview (continued)

Table 1. Factory Programmable Options (continued)

PARAMETER

FACTORY DEVICE CONFIGURATION

4 ms, 6 ms, 8 ms, 16 ms

250 µs (fixed)

t_OCCD

t_SCCD

Charging overcurrent detection delay time

Short Circuit detection delay time

For available released devices, see the Released Device Configurations table.

9.2 Functional Block Diagram

Charger

Detection

Circuit

Counter

Oscillator

Logic circuit

Overcharge

Comparator (OVP)

with Hys

BAT 5

COUT

Overcharge

Current

Comparator

Delay

Short Detect

Over-Discharge

Comparator (UVP)

with Hys

Logic circuit

DOUT

Over-Discharge

Current Comparator

BAT

V–D

6 V–

VSS

V–S

9.3 Feature Description

The BQ2970 family of devices measures voltage drops across several input pins for monitoring and detection of

the following faults: OCC, OCD, OVP, and UVP. An internal oscillator initiates a timer to the fixed delays

associated with each parameter once the fault is triggered. Once the timer expires due to a fault condition, the

appropriate FET drive output (COUT or DOUT) is activated to turn OFF the external FET. The same method is

applicable for the recovery feature once the system fault is removed and the recovery parameter is satisfied, then

the recovery timer is initiated. If there are no reoccurrences of this fault during this period, the appropriate gate

drive is activated to turn ON the appropriate external FET.

9.4 Device Functional Modes

9.4.1 Normal Operation

This device monitors the voltage of the battery connected between BAT pin and VSS pin and the differential

voltage between V– pin and VSS pin to control charging and discharging. The system is operating in NORMAL

mode when the battery voltage range is between the over-discharge detection threshold (V_UVP) and the

overcharge detection threshold (V_OVP), and the V– pin voltage is within the range for charge overcurrent

threshold (V_OCC) to over-discharge current threshold (V_OCD) when measured with respect to VSS. If these

conditions are satisfied, the device turns ON the drive for COUT and DOUT FET control.

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Device Functional Modes (continued)

CAUTION

When the battery is connected for the first time, the discharging circuit might not be

enabled. In this case, short the V– pin to the VSS pin.

Alternatively, connect the charger between the Pack+ and Pack– terminals in the

system.

9.4.2 Overcharge Status

This mode is detected when the battery voltage measured is higher than the overcharge detection threshold

(V_OVP) during charging. If this condition exists for a period greater than the overcharge detection delay (t_OVPD) or

longer, the COUT output signal is driven low to turn OFF the charging FET to prevent any further charging of the

battery.

The overcharge condition is released if one of the following conditions occurs:

•

If the V– pin is higher than the overcharge detection voltage (V_{OCC_Min}), the device releases the overcharge

status when the battery voltage drops below the overcharge release voltage (V_OVP-Hys).

•

If the V– pin is higher than or equal to the over-discharge detection voltage (V_OCD), the device releases the

overcharge status when the battery voltage drops below the overcharge detection voltage (V_OVP).

The discharge is initiated by connecting a load after the overcharge detection. The V– pin rises to a voltage

greater than VSS due to the parasitic diode of the charge FET conducting to support the load. If the V– pin

voltage is higher than or equal to the discharge overcurrent detection threshold (V_OCD), the overcurrent condition

status is released only if the battery voltage drops lower than or equal to the overcharge detection voltage (V_OVP).

CAUTION

1. If the battery is overcharged to a level greater than overcharge detection (V_OVP) and the

battery voltage does not drop below the overcharge detection voltage (V_OVP) with a heavy

load connected, the discharge overcurrent and load short-circuit detection features do not

function until the battery voltage drops below the overcharge detection voltage (V_OVP). The

internal impedance of a battery is in the order of tens of mΩ, so application of a heavy load

on the output should allow the battery voltage to drop immediately, enabling discharge

overcurrent detection and load short-circuit detection features after an overcharge release

delay.

2. When a charger is connected after an overcharge detection, the overcharge status does not

release even if the battery voltage drops below the overcharge release threshold. The

overcharge status is released when the V– pin voltage exceeds the overcurrent detection

voltage (V_OCD) by removing the charger.

9.4.3 Over-Discharge Status

If the battery voltage drops below the over-discharge detection voltage (V_UVP) for a time greater than (t_UVPD) the

discharge control output, DOUT is switched to a low state and the discharge FET is turned OFF to prevent

further discharging of the battery. This is referred to as an over-discharge detection status. In this condition, the

V– pin is internally pulled up to BAT by the resistor R_V–D. When this occurs, the voltage difference between V–

and BAT pins is 1.3 V or lower, and the current consumption of the device is reduced to power-down level

I_STANDBY. The current sink I_V–Sis not active in power-down state or over-discharge state. The power-down state is

released when a charger is connected and the voltage delta between V– and BAT pins is greater than 1.3 V.

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is lower than

–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the

discharge FET once the battery voltage exceeds over-discharge detection voltage (V_UVP).

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is higher than

–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the

discharge FET once the battery voltage exceeds over-discharge detection release hysteresis voltage (V_{UVP +Hys}).

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Device Functional Modes (continued)

9.4.4 Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)

When a battery is in normal operation and the V– pin is equal to or higher than the discharge overcurrent

threshold for a time greater than the discharge overcurrent detection delay, the DOUT pin is pulled low to turn

OFF the discharge FET and prevent further discharge of the battery. This is known as the discharge overcurrent

status. In the discharge overcurrent status, the V– and VSS pins are connected by a constant current sink I_V–S

When this occurs and a load is connected, the V– pin is at BAT potential. If the load is disconnected, the V– pin

goes to VSS (BAT/2) potential.

This device detects the status when the impedance between Pack+ and Pack– (see Figure 26) increases and is

equal to the impedance that enables the voltage at the V– pin to return to BAT – 1 V or lower. The discharge

overcurrent status is restored to the normal status.

Alternatively, by connecting the charger to the system, the device returns to normal status from discharge

overcurrent detection status, because the voltage at the V– pin drops to BAT – 1 V or lower.

The resistance R_V–Dbetween V– and BAT is not connected in the discharge overcurrent detection status.

9.4.5 Charge Overcurrent Status

When a battery is in normal operation status and the voltage at V– pin is lower than the charge overcurrent

detection due to high charge current for a time greater than charge overcurrent detection delay, the COUT pin is

pulled low to turn OFF the charge FET and prevent further charging to continue. This is known as charge

overcurrent status.

The device is restored to normal status from charge overcurrent status when the voltage at the V– pin returns to

charge overcurrent detection voltage or higher by removing the charger from the system.

The charge overcurrent detection feature does not work in the over-discharge status.

The resistance R_V–Dbetween V– and BAT and the current sink I_V–Sis not connected in the charge overcurrent

status.

9.4.6 0-V Charging Function Enabled

This feature enables recharging a connected battery that has very low voltage due to self-discharge. When the

charger applies a voltage greater than or equal to V_0CHGto Pack+ and Pack– connections, the COUT pin gate

drive is fixed by the BAT pin voltage.

Once the voltage between the gate and the source of the charging FET becomes equal to or greater than the

turn ON voltage due to the charger voltage, the charging FET is ON and the battery is charged with current flow

through the charging FET and the internal parasitic diode of the discharging FET. Once the battery voltage is

equal to or higher than the over-discharge release voltage, the device enters normal status.

CAUTION

1. Some battery providers do not recommend charging a depleted (self-discharged) battery.

Consult the battery supplier to determine whether to have the 0-V battery charger function.

2. The 0-V battery charge feature has a higher priority than the charge overcurrent detection

function. In this case, the 0-V charging will be allowed and the battery charges forcibly,

which results in charge overcurrent detection being disabled if the battery voltage is lower

than the over-discharge detection voltage.

9.4.7 0-V Charging Inhibit Function

This feature inhibits recharging a battery that has an internal short circuit of a 0-V battery. If the battery voltage is

below the charge inhibit voltage V_0INHor lower, the charge FET control gate is fixed to the Pack– voltage to

inhibit charging. When the battery is equal to V_0INHor higher, charging can be performed. The 0-V charge inhibit

function is available in all configurations of the BQ297xx device.

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Device Functional Modes (continued)

CAUTION

Some battery providers do not recommend charging a depleted (self-discharged)

battery. Consult the battery supplier to determine whether to enable or inhibit the 0-V

battery charger function.

9.4.8 Delay Circuit

The detection delay timers are based from an internal clock with a frequency of 10 kHz.

BAT

0 ≤ t ≤ t

SCCD

VSS

Time

t_D

OCDD

SCC

OCD

VSS

Time

Figure 25. Delay Circuit

If the over-discharge current is detected, but remains below the over-discharge short circuit detection threshold,

the over-discharge detection conditions must be valid for a time greater than or equal to over-discharge current

delay t_OCCDtime before the DOUT goes low to turn OFF the discharge FET. However, during any time the

discharge overcurrent detection exceeds the short circuit detection threshold for a time greater than or equal to

load circuit detection delay t_SCCD, the DOUT pin goes low in a faster delay for protection.

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The BQ2970 devices are a family of primary protectors used for protection of the battery pack in the application.

The application drives two low-side NMOS FETs that are controlled to provide energy to the system loads or

interrupt the power in the event of a fault condition.

10.2 Typical Application

PACK+

V–

330

BAT

VSS

COUT

DOUT

CELLP

CELLN

2.2k

PACK–

CHG

DSG

NOTE: The 5-M resistor for an external gate-source is optional.

Figure 26. Typical Application Schematic, BQ2970

10.2.1 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE at T_A= 25°C

4.5 V to 7 V

7 A

Maximum operating discharge current

Maximum Charge Current for battery pack

Overvoltage Protection (OVP)

4.5 A

4.275 V

1.2 s

Overvoltage detection delay timer

Overvoltage Protection (OVP) release voltage

Undervoltage Protection (UVP)

4.175 V

2.8 V

Undervoltage detection delay timer

150 ms

2.9 V

Undervoltage Protection (UVP) release voltage

Charge Overcurrent detection (OCC) voltage

Charge Overcurrent Detection (OCC) delay timer

Discharge Overcurrent Detection (OCD) voltage

Discharge Overcurrent Detection (OCD) delay timer

–70 mV

9 ms

100 mV

18 ms

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Typical Application (continued)

Table 2. Design Parameters (continued)

DESIGN PARAMETER

EXAMPLE VALUE at T_A= 25°C

Load Short Circuit Detection SCC) voltage, BAT to –V ≤ threshold

Load Short Circuit Detection (SCC) delay timer

500 mV

250 µs

1 V

Load Short Circuit release voltage, BAT to –V ≥ Threshold

10.2.2 Detailed Design Procedure

NOTE

The external FET selection is important to ensure the battery pack protection is sufficient

and complies to the requirements of the system.

•

FET Selection: Because the maximum desired discharge current is 7 A, ensure that the Discharge

Overcurrent circuit does not trigger until the discharge current is above this value.

•

The total resistance tolerated across the two external FETs (CHG + DSG) should be 100 mV/7 A = 14.3 mΩ.

Based on the information of the total ON resistance of the two switches, determine what would be the Charge

Overcurrent Detection threshold, 14.3 mΩ × 4.5 A = 65 mV. Selecting a device with a 70-mV trigger threshold

for Charge Overcurrent trigger is acceptable.

•

The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, de-rating due

to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the

FET choice should meet the following criteria:

Vdss = 25 V

Each FET Rds ON = 7.5 mΩ at Tj = 25°C and Vgs = 3.5 V

•

Imax > 50 A to allow for short Circuit Current condition for 350 µs (max delay timer). The only limiting factor

during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).

•

Use the CSD16406Q3 FET for the application.

An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative

transients. The 330-Ω resistor also limits the current during a reverse connection on the system.

•

TI recommends placing a high impedance 5-MΩ across the gate source of each external FET to deplete any

charge on the gate-source capacitance.

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10.2.3 Application Performance Plots

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output

Orange Line (Channel 1) = Power Down Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Date Drive Output

DOUT goes from low to high when UVP Recovery = UVP Set

Threshold +100 mV

DOUT goes from high to low when UVP threshold = UVP set

Threshold + set delay time

Figure 27. UVP Recovery

Figure 28. UVP Set Condition

Orange Line (Channel 1) = Power Up Ramp on BAT pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

Figure 29. Initial Power Up, DOUT

Figure 30. Initial Power Up, COUT

Orange Line (Channel 1) = Decrease Voltage on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = COUT Gate Drive Output

COUT goes from low to high when OVP Recovery = OVP Set

Threshold –100 mV

COUT goes from high to low when OVP threshold = OVP set

Threshold + set delay time

Figure 32. OVP Recovery Condition

Figure 31. OVP Set Condition

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11 Power Supply Recommendations

The recommended power supply for this device is a maximum 8-V operation on the BAT input pin.

12 Layout

12.1 Layout Guidelines

The following are the recommended layout guidelines:

1. Ensure the external power FETs are adequately compensated for heat dissipation with sufficient thermal

heat spreader based on worst-case power delivery.

2. The connection between the two external power FETs should be very close to ensure there is not an

additional drop for fault sensing.

3. The input RC filter on the BAT pin should be close to the terminal of the IC.

12.2 Layout Example

Power Trace Line

PACK+

V–

BAT

VSS

COUT

DOUT

–

PACK

Power Trace Line

CSD16406Q3

Power Trace

Via connects between two layers

Figure 33. BQ2970 Board Layout

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13 Device and Documentation Support

13.1 Related Documentation

BQ29700 Single-Cell Li-Ion Protector EVM User's Guide (SLUUAZ3)

13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

BQ2970

BQ2971

BQ2972

BQ2973

Click here

13.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Nov-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

DSE

Qty

3000

250

(1)

(2)

(3)

(4/5)

(6)

BQ29700DSER

BQ29700DSET

BQ29701DSER

BQ29701DSET

BQ29702DSER

BQ29702DSET

BQ29703DSER

BQ29703DSET

BQ29704DSER

BQ29704DSET

BQ29705DSER

BQ29705DSET

BQ29706DSER

BQ29706DSET

BQ29707DSER

BQ29707DSET

ACTIVE

WSON

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 85

ACTIVE

Green (RoHS

& no Sb/Br)

NIPDAU

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Nov-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

DSE

Qty

3000

250

(1)

(2)

(3)

(4/5)

(6)

BQ29716DSER

BQ29716DSET

BQ29717DSER

BQ29717DSET

BQ29718DSER

BQ29718DSET

BQ29723DSER

BQ29723DSET

BQ29729DSER

BQ29729DSET

BQ29732DSER

BQ29732DSET

BQ29733DSER

BQ29733DSET

BQ29739DSER

ACTIVE

WSON

Green (RoHS

& no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 85

ACTIVE

PREVIEW

Green (RoHS

& no Sb/Br)

NIPDAU

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

3000

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

11-Nov-2020

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Dec-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ29700DSER

BQ29700DSET

BQ29701DSER

BQ29701DSET

BQ29702DSER

BQ29702DSET

BQ29703DSER

BQ29703DSET

BQ29704DSER

BQ29704DSET

BQ29705DSER

BQ29705DSET

BQ29706DSER

BQ29706DSET

BQ29707DSER

BQ29707DSET

BQ29716DSER

BQ29716DSET

WSON

DSE

3000

250

180.0

8.4

1.75

1.0

4.0

8.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Dec-2019

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ29717DSER

BQ29717DSET

BQ29718DSER

BQ29718DSET

BQ29723DSER

BQ29723DSET

BQ29729DSER

BQ29729DSET

BQ29732DSER

BQ29732DSET

BQ29733DSER

BQ29733DSET

WSON

DSE

3000

250

180.0

8.4

1.75

1.0

4.0

8.0

3000

250

3000

250

3000

250

3000

250

3000

250

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ29700DSER

BQ29700DSET

BQ29701DSER

BQ29701DSET

BQ29702DSER

WSON

DSE

3000

250

182.0

20.0

3000

250

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Dec-2019

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ29702DSET

BQ29703DSER

BQ29703DSET

BQ29704DSER

BQ29704DSET

BQ29705DSER

BQ29705DSET

BQ29706DSER

BQ29706DSET

BQ29707DSER

BQ29707DSET

BQ29716DSER

BQ29716DSET

BQ29717DSER

BQ29717DSET

BQ29718DSER

BQ29718DSET

BQ29723DSER

BQ29723DSET

BQ29729DSER

BQ29729DSET

BQ29732DSER

BQ29732DSET

BQ29733DSER

BQ29733DSET

WSON

DSE

250

3000

250

182.0

20.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 3

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

BQ29733 [TI]

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