BQ298216RUGR [TI]
BQ298xyz Voltage, Current, Temperature Protectors with an Integrated High-Side NFET Driver for Fast/Flash Charging Single-Cell Li-Ion and Li-Polymer Batteries;
| 型号： | BQ298216RUGR |
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TEXAS INSTRUMENTS |
| 描述： | BQ298xyz Voltage, Current, Temperature Protectors with an Integrated High-Side NFET Driver for Fast/Flash Charging Single-Cell Li-Ion and Li-Polymer Batteries |
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BQ2980, BQ2982
SLUSCS3I – OCTOBER 2017 – REVISED NOVEMBER 2021
BQ298xyz Voltage, Current, Temperature Protectors with an Integrated High-Side
NFET Driver for Fast/Flash Charging Single-Cell Li-Ion and Li-Polymer Batteries
1 Features
3 Description
•
Voltage protection:
The BQ298xyz family of devices, featuring integrated
charge-pump FET drivers, provides high-side primary
battery cell protection for 1-series Li-ion and Li-
Polymer batteries, enabling consistent Rdson across
cell voltages. For better system thermal performance,
the BQ298x device's accuracy enables the use of a
sense resistor as low as 1 mΩ.
– Overvoltage (OV): ±10 mV
– Undervoltage (UV): ±20 mV
Current protection:
– Overcurrent in charge (OCC): ±1 mV
– Overcurrent in discharge (OCD): ±1 mV
– Short circuit in discharge (SCD): ±5 mV
Temperature protection:
– Overtemperature (OT)
Additional features:
– Supports as low as a 1-mΩ sense resistor
•
•
•
The CTR pin in the BQ298x device can be configured
to override the FET driver by host control to create a
system reset or shutdown function. Alternatively, the
CTR pin can be configured to connect an external
Positive Temperature Coefficient (PTC) thermistor for
FET OT protection in addition to the internal die
temperature sensor. The BQ2980xy devices support
zero-volt (0-V) charging, while the BQ2982xy devices
have this disabled.
(RSNS
)
– High-side protection
– High Vgs FET drive
– 0-V charging (only BQ2980)
– CTR pin for FET override control for system
reset/shutdown
– Configure CTR for second OT protection
through an external PTC thermistor
Current consumption:
– NORMAL mode: 4 µA
– SHUTDOWN mode: 0.1-µA maximum
Package:
Device Information
PART
PACKAGE
BODY SIZE (NOM)
NUMBER(1)
•
•
BQ2980xy
X2QFN
X2QFN
1.50 mm × 1.50 mm × 0.37 mm
1.50 mm × 1.50 mm × 0.37 mm
BQ2982xy
(1) For all available packages, see the orderable addendum and
Device Comparison Table.
– 8-pin X2QFN: 1.50 × 1.50 × 0.37 mm
PACK+
2 Applications
Option to configure for PTC protection
R
VDD
R
BAT
R
PACK
•
•
•
•
Smartphones
Tablets
Power bank
Wearables
CTR
VSS
BAT
CHG
VDD
VSS
CS
DSG
PACK
CTR
PACK–
R
CTR
System
Reset
C
VDD
Scale RC values for
system reset timing
PACK–
R
SNS
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ2980, BQ2982
SLUSCS3I – OCTOBER 2017 – REVISED NOVEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Applications.................................................. 17
10 Power Supply Recommendations..............................20
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 Third-Party Products Disclaimer............................. 21
12.2 Receiving Notification of Documentation Updates..21
12.3 Support Resources................................................. 21
12.4 Trademarks.............................................................21
12.5 Electrostatic Discharge Caution..............................21
12.6 Glossary..................................................................21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (July 2021) to Revision I (November 2021)
Page
•
Changed the Device Comparison Table ............................................................................................................ 3
Changes from Revision G (May 2021) to Revision H (July 2021)
Page
•
Changed the BQ298019 device from PRODUCT PREVIEW to Production Data in the Device Comparison
Table .................................................................................................................................................................. 3
Changes from Revision F (December 2020) to Revision G (May 2021)
Page
•
•
•
•
•
•
Removed "Product Preview" footnote from BQ2982 in Description .................................................................. 1
Changed the Device Comparison Table ............................................................................................................ 3
Removed PRODUCT PREVIEW footnote from BQ2982xy in Thermal Information ..........................................4
Clarified CHG driver at low VDD in Electrical Characteristics ........................................................................... 5
Clarified VDD condition in Charge and Discharge Driver .................................................................................11
Clarified ZVCHG in ZVCHG (0-V Charging) ....................................................................................................13
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5 Device Comparison Table
BQ298xyz Device Family (BQ2980xy with ZVCHG [0-V Charging] Enabled, BQ2982xy with ZVCHG Disabled)
OVP
OVP (V) DELAY
(s)
UVP
DELAY
(ms)
OCC
DELAY
(ms)
OCD
DELAY
(ms)
PART
NUMBER
UVP
(V)
OCC
(mV)
OCD
(mV)
SCD
SCD
CTR/
PTC Config
OT (°C)
UV_Shut
(mV) DELAY (µs)
BQ298000
BQ298006
BQ298009
BQ298010
BQ298012
BQ298015
BQ298018
BQ298019
BQ298215
BQ298216
4.475
4.475
4.500
4.500
4.300
4.440
4.400
4.425
4.440
4.300
1.25
1.00
1.00
1.00
1.00
1.25
1.00
1.25
1.25
1.00
2.600
2.500
2.900
2.900
2.750
2.800
2.700
2.800
2.800
2.500
144
20
–8
–12
–18
–10
–4
8
16
8
8
14
30
20
14
8
8
20
40
40
30
30
20
60
40
20
30
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
250 Fixed
85
75
CTR
CTR
CTR
CTR
CTR
CTR
CTR
CTR
CTR
CTR
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
16
16
16
20
8
20
Disable
Disable
Disable
85
20
8
144
144
144
144
144
144
8
–8
8
–8
8
20
8
48
48
8
85
–30
–8
48
8
85
8
85
–4
8
14
20
Disabled
6 Pin Configuration and Functions
BAT
VDD
VSS
1
2
3
7
6
5
DSG
PACK
CTR
Not to scale
Figure 6-1. RUG Package 8-Pin X2QFN Top View
Table 6-1. Pin Functions
NUMBER
NAME
BAT
TYPE
DESCRIPTION
BAT voltage sensing input (connected to the battery side)
Supply voltage
1
2
3
4
I(1)
VDD
VSS
CS
P
—
I
Device ground
Current sensing input (connect to PACK– side of the sense resistor)
Active high control pin to open FET drivers and shut down the device. It can be configured to
enable an internal pull-up and connect the CTR pin to an external PTC for OT protection.
5
6
CTR
I
I
Pack voltage sensing pin (connected to the charger side, typically referred to as PACK+ and
PACK–)
PACK
7
8
DSG
CHG
O
O
DSG FET driver
CHG FET driver
(1) I = input, O = output, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
MAX
6
UNIT
Supply voltage
Input voltage
VDD
PACK
BAT
V
24
6
V
CS
0.3
5
CTR
CHG
DSG
20
20
150
Output voltage
V
Storage temperature, Tstg
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.5
0
MAX
UNIT
Supply voltage
Input voltage
VDD
PACK
BAT
5.5
V
20
1.5
–0.25
0
5.5
V
CS
0.25
CTR
CHG
DSG
5
VSS
VSS
–40
VDD + VDD × AFETON
VDD + VDD × AFETON
85
Output voltage
V
Operating temperature, TA
°C
7.4 Thermal Information
BQ2980xy/BQ2982xy
THERMAL METRIC(1)
RUG (X2QFN)
8 PINS
171.8
75
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
94.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.5
ψJB
94.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Typical values stated at TA = 25°C and VDD = 3.6 V. MIN/MAX values stated with TA = –40°C to +85°C and VDD = 3 to 5 V
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY CURRENT CONSUMPTION
VCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA(1)),
VDD > 4.0 V
5
4
2
8
6
µA
µA
INORMAL
Normal mode supply current
VCHG and VDSG > 5 V, CLOAD = 8 nF (typical 20 nA(1)),
UVP < VDD < 3.9 V
Supply current with both
FET drivers off
IFETOFF
ISHUT
VCHG = VDSG ≤ 0.2 V
4
µA
µA
Shutdown current
VPACK < VBAT, VDD = 1.5 V
0.1
N-CH FET DRIVER, CHG and DSG
VCHG or VDSG = VDD + VDD × AFETON
UVP < VDD < 3.9 V
CLOAD = 8 nF
1.65
1.45
1.75
1.55
1.81
1.68
V/V
V/V
FET driver gain factor, the
AFETON
Vgs voltage to FET
VCHG or VDSG = VDD + VDD × AFETON
VDD > 4.0 V
CLOAD = 8 nF
VFETOFF = VCHG – VSS or VDSG – VSS
CLOAD = 8 nF
VFETOFF
FET driver off output voltage
0.2
2.1
V
V
FET driver charge pump
shut down voltage
Charge pump enabled when VDD rises to
VDRIVER_SHUT
VDRIVER_SHUT
1.95
2
FET driver charge pump
shut down voltage
hysteresis
VDRIVER_SHUT
Charge pump disabled when VDD falls to
VDRIVER_SHUT – VDRIVER_SHUT_HYS
50
mV
µs
_HYS
CLOAD = 8 nF,
VCHG or VDSG rises from VDD to (2 × VDD)
(2)
trise
FET driver rise time
400
50
800
CLOAD = 8 nF,
VCHG or VDSG fall to VFETOFF
tfall
FET driver fall time
200
10
µs
ILOAD
FET driver maximum loading
µA
VOLTAGE PROTECTION
VOVP
Overvoltage detection range Factory configured, 50-mV step
3750
–10
–15
–25
5200
10
mV
mV
TA = 25°C, CHG/DSG CLOAD < 1 µA
Overvoltage detection
accuracy
VOVP_ACC
TA = 0°C to 60°C, CHG/DSG CLOAD < 1 µA
TA = –40°C to +85°C, CHG/DSG CLOAD < 1 µA
15
25
Overvoltage release
hysteresis voltage
VOVP_HYS
VUVP
Fixed at 200 mV
150
200
250
mV
mV
Undervoltage detection
range
Factory configured, 50-mV step
2200
3000
TA = 25°C
–20
–30
–50
20
30
50
mV
mV
mV
Undervoltage detection
accuracy
VUVP_ACC
TA = 0°C to 60°C
TA = –40°C to +85°C
Undervoltage release
hysteresis voltage
VUVP_HYS
RPACK-VSS
Fixed at 200 mV
150
100
200
300
250
550
mV
kΩ
Resistance between PACK
and VSS during UV fault
CURRENT PROTECTION
Overcurrent in charge
Factory configured, 2-mV step. For OCC, the range is
negative (min = –64, max = –4).
VOC
(OCC) and discharge (OCD)
range
4
64
mV
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7.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 3.6 V. MIN/MAX values stated with TA = –40°C to +85°C and VDD = 3 to 5 V
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
10
20
30
Short circuit in discharge
threshold
VSCD
Factory configured
40
mV
60
120
200
< 20 mV
–1
–3
1
Overcurrent (OCC, OCD1,
OCD2, SCD) detection
accuracy
20 to approximately 55 mV
56 to approximately 100 mV
> 100 mV
2
3
VOC_ACC
mV
5
–5
–12
12
Current sink between PACK
and VDD during current
fault. Used for load removal
detection
IPACK-VDD
8
24
55
µA
OCD, SCD recovery
detection current
Sum of current from VDD and BAT during OCD or
SCD fault
IOCD_REC
VOC_REL
µA
mV
mV
OCC fault release threshold (VBAT – VPACK
)
)
100
OCD, SCD fault release
(VPACK – VBAT
–400
threshold
OVERTEMPERATURE PROTECTION(2)
75
85
Internal overtemperature
threshold
TOT
Factory configured
°C
Internal overtemperature
TOT_ACC
–10
8
10
22
°C
°C
detection accuracy
Internal overtemperature
TOT_HYS
15
hysteresis
PROTECTION DELAY(2)
0.2
0.8
0.25
1
0.3
1.2
tOVP
tUVP
tOC
Overvoltage detection delay Factory configured
s
1
1.25
4.5
20
1.5
3.6
5.4
16
24
76.8
100
115.2
5.6
96
115.2
150
172.8
10.5
19.6
24
Undervoltage detection
Factory configured
delay
ms
ms
125
144
8
12.4
16
16
Overcurrent (OCC, OCD)
Factory configured
detection delay
20
38.4
48
57.6
Short circuit discharge
Fixed configuration
detection delay
tSCD
tOT
125
3.6
250
4.5
375
5.4
µs
s
Overtemperature detection
Fixed configuration
delay
FET OVERRIDE/DEVICE SHUTDOWN CONTROL, CTR
VIH
High-level input
1
V
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7.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 3.6 V. MIN/MAX values stated with TA = –40°C to +85°C and VDD = 3 to 5 V
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIL
Low-level input
0.4
V
VHYS
Hysteresis for VIH and VIL
200
mV
1.5
5
Effective Internal pull-up
resistance (to use with
external PTC)
RPULL_UP
Factory configured if enabled
MΩ
8
ZVCHG (0-V Charging)
Charger voltage requires to
V0CHGR
2
V
V
BQ2980xy only (ZVCHG is disabled in BQ2982xy).
The CHG driver becomes high impedance when VDD
start 0-V charging
Battery voltage that inhibits
0-V charging
< V0INH
.
V0INH
1
(1) INORMAL is impacted by the efficiency of the charge pump driving the CHG and DSG FETs. An ultra-low-gate-leakage FET may be
required. INORMAL can be significantly higher with FETs with typical IGSS values of 10 µA. See Selection of Power FET for more details.
(2) Specified by design.
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7.6 Typical Characteristics
6
5
4
3
2
8
7.5
7
6.5
6
5.5
5
-40
-20
0
Normal at < 3.8V
Normal at > 3.9V
FETs off
25
60
85
1
0
4.5
4
-60
-40
-20
0
20
40
60
80
100
3
3.5
4
4.5
Temperature (èC)
VDD (V)
D002
S001
Figure 7-1. Normal and FET Off Current Across
Temperature
Figure 7-2. CHG and DSG Output (Loading with an
8-nF Capacitor on CHG and DSG) Across VDD
10
1
OCC (8 mV)
OCD (8 mV)
SCD (20 mV)
5
0.5
0
0
-5
-0.5
-1
OVP
UVP
-10
-60
-40
-20
0
20
40
60
80
100
-60
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D003
D004
Figure 7-3. Overvoltage and Undervoltage
Accuracy Across Temperature
Figure 7-4. Overcurrent Accuracy Across
Temperature
12
12
1.5 MW
5 MW
8 MW
1.5 MW
5 MW
8 MW
10
10
8
6
4
2
0
8
6
4
2
0
2
2.5
3
3.5
VDD (V)
4
4.5
5
-60
-40
-20
0
20
40
60
80
100
Temperature (èC)
D005
D006
Figure 7-5. CTR Internal Pull-Up Resistor (if
Configured) Across VDD
Figure 7-6. CTR Internal Pull-Up Resistor (if
Configured) Across Temperature (VDD at 3.6 V)
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8 Detailed Description
8.1 Overview
The BQ298xyz devices are high-side single-cell protectors designed to improve thermal performance by
reducing power dissipation across the protection FETs. This is achieved with high-side protection with a built-in
charge pump to provide higher Vgs to the FET gate voltage to reduce FET Rdson. Additionally, the device
supports as low as a 1-mΩ sense resistor with ±1-mV accuracy, resulting in lower heat dissipation at the sense
resistor without compromising current accuracy.
The BQ298x device implements a CTR pin that allows external control to open the power FETs, as well as shut
down the device for low power storage. Optionally, the CTR pin can be configured to connect to a PTC and be
used for overtemperature protection.
8.1.1 Device Configurability
Table 8-1 provides guidance on possible configurations of the BQ2980 and BQ2982 devices.
Note
Texas Instruments preprograms devices: Devices are not intended to be further customized by the
customer.
Table 8-1. Device Configuration Range
STEP
SIZE
DELAY
SELECTION
RECOVERY DESCRIPTION
(Non-Configurable)
FAULT
RANGE
UNIT
CHG, DSG STATUS
(200-mV hysteresis AND
charger removal) OR
(below OV threshold AND
discharge load is detected)
3750 –
5200
0.25, 1, 1.25,
4.5 s
OV
Overvoltage
50
mV
CHG OFF
(200-mV hysteresis AND
discharge load is removed
before device shuts down)
Option 1:
UV_SHUT enable
The device goes into OR
SHUTDOWN.
(above UV threshold AND
charger connection)
2200 –
3000
20, 96, 125,
144 ms
UV
Undervoltage
50
mV
Option 2:
UV_SHUT disable
DSG off, power
(200-mV hysteresis) OR
consumption drops (above UV threshold AND
to IFETOFF, and the
device does not shut
down.
charger connection)
Detect a charger removal
(VBAT – VPACK) > 100-mV
typical
OCC
OCD
SCD
Overcurrent in Charge
–64 – –4
4 – 64
2
2
mV
mV
mV
CHG OFF
8, 16, 20, 48
ms
Overcurrent in
Discharge
Detect a discharge load
removal
(VBAT – VPACK) < 400-mV
typical
DSG OFF
10, 20, 30,
40, 60, 120,
200
Short circuit in
discharge
—
Fixed 250 µs
Fixed 4.5 s
Overtemperature
(through internal
temperature sensor)
OT
75, 85
—
—
°C
CHG and DSG OFF Fixed 15°C hysteresis
Internal pull-up resistor
for OT with PTC
(through external PTC
on CTR pin)
OT
(PTC)
Voltage on CTR pin drops
CHG and DSG OFF
1.5, 5, 8
MΩ
—
below CTR VIL level
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8.2 Functional Block Diagram
BAT
VDD
PACK
0-V
Charging
(BQ2980)
I
PACK-VDD
Power
Module
R
PACK-VSS
CHG
DSG
Super
Comparator
Charge
Pump and
nFET Driver
Digital
Internal Temp Sensor
BATSNS Current Sensing
PACK
(OV, UV, OCC,
OCD, SCD, OT
BATSNS_Prot)
Internal
Temperature
Sensor
CS
VDD
CTR Logic
CTR
OTP
R
PULL_UP
VSS
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8.3 Feature Description
8.3.1 Overvoltage (OV) Status
The device detects an OV fault when VBAT > VOVP (OV threshold) during charging. If this condition exists for
longer than the OV delay (tOVP), the CHG output is driven to VFETOFF to turn off the CHG FET.
The OV status is released and the CHG output rises to HIGH, that is, VCHG = VDD × (1 + AFETON), if one of the
following conditions occurs:
•
•
When VBAT is < (VOVP – VOVP_HYS) and the charger is removed or
When VBAT is < VOVP and a discharge load is detected.
The device detects the charger is removed if (VPACK – VBAT) < 100-mv typical. To detect if a load is attached, the
device checks if (VBAT – VPACK) > 400-mv typical.
8.3.2 Undervoltage (UV) Status
The device detects a UV fault when the battery voltage measured is below the UV threshold (VUVP). If this
condition exists for longer than the UV delay (tUVP), the DSG output is driven to VFETOFF to turn off the DSG FET.
The device includes a UV_SHUT option which may be enabled during factory configuration. If this option
is enabled, during the UV fault state the device goes into SHUTDOWN mode to preserve the battery. In
SHUTDOWN mode, the BQ2980 will drive the CHG output to the PACK voltage, putting the device into ZVCHG
mode (the BQ2982 does not enable this ZVCHG mode). That means, the CHG FET can be turned on if a
charger is connected and both VDD and PACK meet the ZVCHG turn-on conditions (see Section 8.3.9 for more
details). The PACK pin is internally pulled to VSS through RPACK-VSS. This is to determine if the charger is
disconnected on the PACK+ terminal before shutting down the device. It is also to ensure the device does not
falsely wake up from SHUTDOWN mode due to noise.
The UV status is released and the DSG output rises to HIGH, that is, VDSG = VDD × (1 + AFETON), if one of the
following conditions occurs:
•
•
When VBAT is > (VUVP + VUVP_HYS) and the discharge load is removed or
When VBAT is > VUVP and a charger is connected.
The device detects that the charger is attached if (VPACK – VBAT) > 700-mV typical. To detect for load removal,
the device checks if (VBAT – VPACK) < 400-mV typical.
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If the UV_SHUT option is disabled, during a UV fault DSG is turned off and the device does not go into
SHUTDOWN. The power consumption is reduced to IFETOFF. The PACK pin is still internally pulled to VSS
through RPACK-VSS. To recover UV with this option, one of the following conditions must occur:
•
•
When VBAT is > (VUVP + VUVP_HYS) or
When VBAT is > VUVP and a charger is connected.
8.3.3 Overcurrent in Charge (OCC) Status
The BQ298xyz device detects a current fault by monitoring the voltage drop across an external sense resistor
(RSNS) between the CS and VSS pins. The device detects an OCC fault when (VCS – VSS) < OCC threshold
(–VOC). If this condition exists for longer than the OCC delay (tOC), the CHG output is driven to VFETOFF to turn
off the CHG FET.
The OCC status is released and the CHG output rises to HIGH, that is VCHG = VDD × (1 + AFETON), if (VBAT
VPACK) > 100 mV, indicating a charger is removed.
–
8.3.4 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) Status
The BQ298xyz device detects a current fault by monitoring the voltage drop across an external sense resistor
(RSNS) between the CS and VSS pins. The device applies the same method to detect OCD and SCD faults and
applies the same recovery scheme to release the OCD and SCD faults.
The device detects an OCD fault when (VCS – VSS) > OCD threshold (+VOC). If this condition exists for longer
than the OCD delay (tOC), the DSG output is driven to VFETOFF to turn off the DSG FET. The SCD detection is
similar to OCD, but uses the SCD threshold (VSCD) and SCD delay (tSCD) time.
During an OCD or SCD state, the device turns on the recovery detection circuit. An internal current sink
(IPACK – VDD) is connected between the PACK and VDD pins, and the device consumes IOC_REC during the OCD
and SCD fault until recovery is detected.
The OCD or SCD status is released and the DSG output rises to HIGH, that is VDSG = VDD × (1 + AFETON), if
(VBAT – VPACK) < 400 mV, indicating a discharge load is removed.
8.3.5 Overtemperature (OT) Status
The device has a built-in internal temperature sensor for OT protection. The sensor detects OT when the internal
temperature measurement is above the internal overtemperature threshold (TOT). If this condition exists for
longer than the OT delay (tOT), both CHG and DSG outputs are driven to VFETOFF to turn off the CHG and DSG
FETs.
The OT state is released and the CHG and DSG outputs rise to HIGH, that is VCHG and VDSG = VDD × (1 +
AFETON), if the internal temperature measurement falls below (TOT – TOT_HYS).
8.3.6 Charge and Discharge Driver
The device has a built-in charge pump to support high-side protection using an NFET. When the drivers are on,
the CHG and DSG pins are driven to the VDD × (1 + AFETON) voltage level. This means the Vgs across the CHG
or DSG FET is about (VDD × AFETON). When the drivers are turned off and VDD ≥ V0INH , the CHG and/or DSG
output is driven to VFETOFF
.
The charge pump requires VDD > VDRIVER_SHUT to operate. When VDD falls below VDRIVER_SHUT
-
VDRIVER_SHUT_HYS, the DSG output is off. The CHG output can be turned on in BQ2980 if the ZVCHG charging
condition is met. See Section 8.3.9 for more details.
8.3.7 CTR for FET Override and Device Shutdown
The CTR pin is an active-high input pin, which can be controlled by the host system to turn off both CHG and
DSG outputs momentarily to reset the system, shut down the system for low-power storage, or as a necessary
shutdown if the host detects a critical system error.
The CTR pin uses a 4.5-s timer (same specification tolerance as the tOVP delay 4.5-s option) to differentiate a
reset and shutdown signal. CHG and DSG are off when VCTR > CTR VIH for > 200 µs. Counting from the start of
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VCTR > VIH, if VCTR drops below VIL within 3.6 s, CHG and DSG simply turn back on. If CTR remains HIGH for >
5.4 s, the device enters SHUTDOWN mode.
With this timing control, the system designer can use an RC circuit to implement either a host-controlled
power-on-reset or a system shutdown.
On a rising direction of the CTR
On a falling direction of CTR signal,
CTR remains as “HIGH” when the
signal level is above(V – V ).
signal,
tobecome a “HIGH”.
CTR must be above V
IH
CTR V
IH
CTR V
IH
V
IH
HYS
CTR V
V
HYS
IH – HYS
On a rising direction of the CTR signal,
CTR remains as “LOW” when the
CTR V
CTR V
IL
IL
On a falling direction of the CTR
signal,
to become a “LOW”.
signal level is below V
.
IL
CTR must be below V
IL
Figure 8-1. CTR Level in Rising and Falling Direction
Note
•
•
CTR shuts down the device only when VCTR is HIGH for > 5.4 s AND when there is no OV or OT
fault present.
The CTR VIH level is the voltage level at which the CTR pin is considered HIGH in the positive
direction as voltage increases. There is a minimum hysteresis designed into the logic level;
therefore, as voltage decreases, CTR is considered HIGH at the (VIH – VHYS) level.
The FET override and the shutdown functions are not available if the CTR pull-up is enabled. See
Section 8.3.8 for details.
•
Host pulls up the
GPIO connecting
to CTR pin.
CHG/DSG are off ,
cutting off power to
the system.
Capacitor connects to CTR, depletes below
VIL level within 3.6 s.
-µs delay
200
Host keeps CRT low
during normal operation.
CTR VIH
CTR VIL
CTR
System host GPIO
CTR signal
CHG & DSG on
(assuming no fault is detected)
CHG &
DSG off
CHG & DSG on
(assuming no fault is detected )
Figure 8-2. System Reset Function Implementation
Can also implement the shutdown function
with RC circuit using RC constant > 5.4 s
Host signals a shutdown.
Pack-side gauge drives CRT high
200-µs
delay
Pack-side gauge continues to drive
the CTR signal high
> 5.4-s delay
Pack side gauge/
monitor
Host keeps CRT low
CTR V
IH
bq2980
CTR
during normal operation
CTR VHYS
System host
control
GPIO
GPIO
CTR signal
CHG and DSG on
(assuming no fault is detected)
CHG and DSG off
Device shuts down
Figure 8-3. Potential System- Controlled Shutdown Implementation
8.3.8 CTR for PTC Connection
If any of the CTR pull-up resistors are selected, the device assumes a PTC is connected to the CTR pin. There
are three internal pull-up options: 1.5 MΩ, 5 MΩ, or 8 MΩ. The internal pull-up allows a PTC to be connected
between the CTR pin and VSS. This turns the CTR pin to detect an overtemperature fault through an external
PTC, as shown in Figure 8-4.
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bq2980
VDD
RPULL_UP
CTR
PTC
VCTR
detection
circuit
Copyright © 2017, Texas Instruments Incorporated
Figure 8-4. Connecting PTC to CTR Pin for Overtemperature Protection
When any of the CTR internal pull-up resistors are selected (factory configured), an active-high signal (VCTR
CTR VIH) on CTR turns off both CHG and DSG outputs, but it does not shut down the device.
>
As temperature goes up, the PTC resistance increases and when the voltage divided by the internal RPULL_UP
and the RPTC is > CTR VIH, the CHG and DSG outputs are turned off. As temperature falls and the PTC
resistance decreases, the CHG and DSG outputs turn back on when (VCTR < CTR VIL).
8.3.9 ZVCHG (0-V Charging)
ZVCHG (0-V charging) is a special function that allows charging a severely depleted battery that is below
the FET driver charge pump shutdown voltage (VDRIVER_SHUT). The BQ2980 has ZVCHG enabled, while the
BQ2982 device has it disabled.
In BQ2980, if VBAT > V0INH and VDD < VDRIVER_SHUT-VDRIVER_SHUT_HYS and the charger voltage at PACK+ is >
V0CHGR, then the CHG output will be driven to the voltage of the PACK pin, allowing charging. ZVCHG mode
in the BQ2980 is exited when VBAT > VDRIVER_SHUT, at which point the charge pump is enabled, and CHG
transitions to being driven by the charge pump. In the BQ2982, ZVCHG is entirely disabled, so charging is
disabled whenever VDD < VDRIVER_SHUT –VDRIVER_SHUT_HYS
.
For BQ2980 and BQ2982, when the voltage on VDD is below V0INH, the CHG output becomes high impedance,
and any leakage current flowing through the CHG FET may cause this voltage to rise and reenable charging.
If this is undesired, a high impedance resistor can be included between the CHG FET gate and source to
overcome any leakage and ensure the FET remains disabled in this case. This resistance should be as high as
possible while still ensuring the FET is disabled, since it will increase the device operating current when the CHG
driver is enabled. Because gate leakage is typically extremely low, a gate-source resistance of 50 MΩ to 100 MΩ
may be sufficient to overcome the leakage.
8.4 Device Functional Modes
8.4.1 Power Modes
8.4.1.1 Power-On-Reset (POR)
The device powers up in SHUTDOWN mode, assuming a UV fault. To enter NORMAL mode, both VBAT and
VPACK must meet the UV recovery requirement. In summary, if UV_SHUT is enabled, (VBAT > VUVP) and VPACK
detecting a charger connection are required to enter NORMAL mode. If UV_SHUT is disabled, (VBAT > VUVP
)
and (VPACK > the minimum value of VDD) are required to enter NORMAL mode. See Section 8.4.1.4 for more
details.
During the ZVCHG operation mode (only available in BQ2980), the CHG pin is internally connected to PACK
when the device is in SHUTDOWN mode. If both VBAT and VPACK meet the ZVCHG condition (see Section 8.3.9
for details), CHG is on, even if UV recovery conditions are not met.
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8.4.1.2 NORMAL Mode
In NORMAL mode, all configured protections are active. No fault is detected, and both CHG and DSG drivers
are enabled. For the BQ298x device, if none of the internal CTR pull-up resistor options is selected, VCTR must
be < CTR VIL for CHG and DSG to be on.
8.4.1.3 FAULT Mode
If a protection fault is detected, the device enters FAULT mode. In this mode, the CHG or DSG driver is pulled to
VFETOFF to turn off the CHG or DSG FETs.
8.4.1.4 SHUTDOWN Mode
This mode is the lowest power-consumption state of the device, with both CHG and DSG turned off.
The two conditions to enter SHUTDOWN mode are as follows:
•
•
Undervoltage (UV): If the device is configured with UV_SHUT enabled, when UV protection is triggered, the
device enters SHUTDOWN mode. See Section 8.3.2 for details.
CTR control: When CTR is HIGH for > 5.4 s, the device enters SHUTDOWN mode. See Section 8.3.7 for
details.
Note
If the internal CTR pull-up is enabled, a HIGH at CTR does not activate the shutdown process. This is
because when the internal pull-up is enabled, the CTR pin is configured for use with an external PTC
for overtemperature protection, and the CTR functionality is disabled.
9 Application and Implementation
Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Test Circuits for Device Evaluation
1. Test Power Consumption (Test Circuit 1)
This setup is suitable to test for device power consumption at different power modes. VS1 is a voltage
source that simulates a battery cell. VS2 is used to simulate a charger and load under different power mode
conditions.
I1 is a current meter that monitors the device power consumption at different modes. I2 is a current meter
that monitors the PACK pin current. The IPACK current is insignificant in most operation modes. If a charger
is connected (VS2 has a positive voltage), but the device is still in SHUTDOWN mode, I2 reflects the IPACK
current drawing from the charger due to the internal RPACK-VSS resistor.
2. Test CHG and DSG Voltage and Status (Test Circuit 2)
This setup is suitable to test VCHG and VDSG levels or monitor the CHG and DSG status at different operation
modes. It is not suitable to measure power consumption of the device, because the meters (or scope
probes) connected to CHG and/or DSG increase the charge pump loading beyond the normal application
condition. Therefore, the current consumption of the device under this setup is greatly increased.
3. Test for Fault Protection (Test Circuit 3)
This setup is suitable to test OV, UV, OCD, OCD, and SCD protections.
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Voltage protection:
Adjust VS1 to simulation OV and UV. TI recommends having 0 V on VS3 during the voltage test to avoid
generating multiple faults. Adjust VS2 to simulate the charger/load connection or disconnection. Combine
with test circuit 1 to monitor power consumption, or combine with test circuit 2 to monitor CHG and DSG
status.
Test example for OV fault and OV recovery by charger removal:
a. Adjust both VS1 and VS2 > OVP threshold.
b. As the device triggers for OVP and CHG is open, VS2 can be set to a maximum expected charger
voltage as if in an actual application when CHG is open, and charger voltage may regulate to the
maximum setting.
c. To test for OV recovery, adjust VS1 below (VOVP – VOVP_Hys). Reduce the VS2 voltage so that (VS2 –
VS1) < 100 mV (to emulate removal of a charger).
Current protection:
Similar to the voltage protection test, adjust VS3 to simulate OCC, OCD, and SCD thresholds. Use VS2 to
simulate a charger/load status. TI recommends setting VS1 to the normal level to avoid triggering multiple
faults.
Note
It is normal to observe CHG or DSG flipping on and off if VS2 is not set up properly to simulate a
charger or load connection/disconnection, especially when the voltage source is used to simulate
fault conditions. It is because an improper VS2 setting may mislead the device to sense a
recovery condition immediately after a fault protection is triggered.
4. Test for CTR Control (Test Circuit 4)
This setup is suitable to test for CTR control. Adjust VS4 above or below the CTR VIH or VIL level. Combine
with test circuit 1 to observe the power consumption, or combine with test circuit 2 to observe the CHG and
DSG status.
9.1.2 Test Circuit Diagrams
R
VDD
R
VDD
8 nF
8 nF
BAT
CHG
BAT
CHG
I1
A
VDD
VSS
CS
DSG
PACK
CTR
VDD
VSS
CS
DSG
PACK
CTR
VS1
VS1
A
I2
V2
V1
C
VDD
C
V
V
VDD
VS2
VS2
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Test Circuit 1
Figure 9-2. Test Circuit 2
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R
VDD
R
VDD
8 nF
8 nF
8 nF
8 nF
BAT
CHG
BAT
CHG
VDD
VSS
CS
DSG
PACK
CTR
VDD
VSS
CS
DSG
PACK
CTR
VS1
VS1
C
VDD
C
VDD
VS2
VS2
VS4
VS3
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
Figure 9-3. Test Circuit 3
Figure 9-4. Test Circuit 4
9.1.3 Using CTR as FET Driver On/Off Control
Normally, CTR is not designed as a purely on/off control of the FET drivers, because there is a timing
constriction on the pin. The following is a list of workarounds to implement the CTR as an on/off switch to
the FET drivers.
1. Switching CTR from high to low with less than 3.6 s:
If the application only requires turning off the FET drivers in < 3.6 s, then the CTR pin can simply be viewed
as an on/off switch of the FET drivers. That means, after the CTR pin is pulled high, the application will pull
the CTR pin back low in < 3.6 s.
2. Applying a voltage on PACK to prevent the device from entering SHUTDOWN mode:
When the CTR pin is be pulled high for > 3.6 s, there is a chance the device may go into SHUTDOWN
mode. If the CTR pin is high for > 5.4 s, the device will be in SHUTDOWN mode. For applications that
may use the CTR to keep the FET drivers off for > 3.6 s, the workaround is to keep VPACK within the
VDD recommended operating range while the CTR is pulled high to prevent the device from entering
SHUTDOWN mode. The device is forced to stay in NORMAL mode with this method.
Because the PACK pin is also connected to the PACK terminal, the system designer should have a blocking
diode to protect the GPIO (that controls the CTR pin) from high voltage.
During the time CTR is high, voltage on PACK must be
applied. Otherwise, device will enter SHUTDOWN mode.
….
V
V
CTR > IH
V
V
V
V
CTR < IL
CTR < IL
CTR
….
> Min VDD
V
PACK
PACK
3.6 s
When CTR is pulled high (FETs off), the system ensures:
1. Voltage on PACK is applied before pulling CTR high or
2. Voltage on PACK is applied within 3.6 s after CTR is pulled high.
When CTR is pulled low (FET on), the system ensures:
Voltage on PACK is still applied before pulling CTR low.
Copyright ©2017, Texas Instruments Incorporated
Figure 9-5. PACK Voltage Timing with Switching CTR as On/Off Control of FET Drivers
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9.2 Typical Applications
9.2.1 BQ298x Configuration 1: System-Controlled Reset/Shutdown Function
CHG FET DSG FET
PACK+
R
R
BAT
VDD
R
PACK
BAT
CHG
VDD
VSS
CS
DSG
PACK
CTR
External
FET Override
Control
R
CTR
C
VDD
Scale RC values for
system reset timing
Configuration 1
PACKœ
R
SNS
Figure 9-6. BQ298x Reference Schematic Configuration 1
9.2.1.1 Design Requirements
For this design example, use the parameters listed Table 9-1.
Table 9-1. Recommended Component Selection
PARAMETER
TYP
MAX
UNIT
COMMENT
This resistor is used to protect the PACK pin from a
reserve charging current condition.
RPACK PACK resistor
—
2
kΩ
RVDD VDD filter resistor
CVDD VDD filter capacitor
—
300
1
Ω
0.1
µF
This resistor limits current if the BAT pin is shorted to
ground internally. BAT is used for voltage measurement
for OV and UV. A larger resistor value can impact the
voltage measurement accuracy.
BAT resistor (for safety. To limit
current if BAT pin is shorted
internally)
RBAT
20
—
—
Ω
Ω
This is optional for ESD protection and is highly
dependent on the PCB layout.
RCTR CTR resistor (optional for ESD)
100
9.2.1.2 Detailed Design Procedure
•
Determine if a CTR for FET override or an improved voltage measurement function is required in the battery
pack design.
•
•
•
See Figure 9-6 for the schematic design.
Check the cell specification and system requirement to determine OV and UV levels.
Define the sense resistor value and system requirement to determine OCC, OCD, and SCD levels. For
example, with a 1-mΩ sense resistor and OCC, OCD, and SCD, the requirement is 6 A, 8 A, and 20 A,
respectively. The OCC threshold should be set to 6 mV, the OCD threshold should be at 8 mV, and the SCD
threshold should be at 20 mV.
•
•
Determine the required OT protection threshold. The OT fault turns off the CHG and the DSG, so the
threshold must account for the highest allowable charge and discharge temperature range.
When a decision is made on the various thresholds, search for whether a device configuration is available or
contact the local sales office for more information.
9.2.1.3 Selection of Power FET
The high-side driver of the BQ298x device limits the Vgs below 8 V with a 4.4-V battery cell. This means the
device can work with a power FET with an absolute maximum rating as low as ±8 V Vgs, which is common in
smartphone applications.
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Additionally, TI highly recommends using a low gate leakage FET around 6-V to 7-V Vgs range. The power FET
on the BQ298x evaluation module has the following typical gate leakage. TI recommends selecting a similar gate
leakage FET for the design.
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
10
VGS (V)
D007
Figure 9-7. Power FET (on BQ2980 EVM) Gate Leakage Versus Vgs
9.2.1.4 Application Curves
DSG
After ~144ms UVP delay
Note: CHG and DSG voltages
increased because VBAT
Note: CHG and DSG voltages
DSG turned off
decreased because VBAT decreased
CHG
DSG
After ~1.25s OVP delay
CHG
BAT
CHG turned off too because device
went to Shutdown at UV protection
CHG turned off
Set VBAT below UVP
PACK
Set VBAT above OVP
BAT
PACK
PACK dropped to ground because internal
PACK pull-down resistor was connected
when device went into Shutdown
Figure 9-8. Overvoltage (OV) Protection
Figure 9-9. Undervoltage (UV) Protection
CHG
DSG
CTR voltage dropped
below VIL in < 3.6. both
FETs turned back on.
PACK+ voltage went
back up
Connect CTR to PACK+
(3.6V) for very short period
of time. FETs turned off
PACK+
CHG
After ~250s SCD delay
DSG turned off
PACK dropped because of
the load was connted
PACK
Current settled at
SCD threshold
CTR
Current
Current dropped to 0A
CTR cap started to deplete.
Both FETs remained off
PACK+ started falling to
ground
Figure 9-10. Short Circuit (SCD) Protection
The RC values used in this example are for reference only.
System designers should depend on their pull-up voltage
and RC tolerance to add any additional margin. TI also
recommends users keep the delay time below 3.6 s, if possible,
for the reset function.
Figure 9-11. Setup CTR for System Reset (Using 5
MΩ and 1 µF RC)
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Connect CTR to PACK+ (3.6V) for very
short period of time. FETs turned off
CTR cap started to deplete. FET reamined off.
The RC time kept the CTR voltage above VIH for
The RC values used in this example are for reference only. System designers should depend on their pull-up voltage and RC tolerance
to add any additional margin. TI also recommends users keep the delay time below 5.4 s, if possible, for the shutdown function.
Figure 9-12. Setup CTR for System Shutdown (Using 5 MΩ and 1 µF RC)
9.2.2 BQ298x Configuration 2: CTR Function Disabled
CHG FET DSG FET
PACK+
R
R
BAT
VDD
R
PACK
BAT
CHG
VDD
VSS
CS
DSG
PACK
CTR
No FET
Override
Function
C
VDD
Configuration 2
PACKœ
R
SNS
Figure 9-13. BQ298x Reference Schematic Configuration 2
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9.2.3 BQ298x Configuration 3: PTC Thermistor Protection
CHG FET DSG FET
PACK+
R
R
BAT
VDD
R
PACK
BAT
CHG
VDD
VSS
CS
DSG
PACK
CTR
2nd Overtemperature
protection level via PTC
C
VDD
Configuration 3
PACKœ
R
SNS
Figure 9-14. BQ298x Reference Schematic Configuration 3
10 Power Supply Recommendations
The device supports single-cell li-ion and li-polymer batteries of various chemistries with a maximum VDD below
5.5 V.
11 Layout
11.1 Layout Guidelines
1. Place the components to optimize the layout. For example, group the high-power components like cell pads,
PACK+ and PACK– pads, power FETs, and RSNS together, allowing the layout to optimize the power traces
for the best thermal heat spreading.
2. Separate the device's VSS and low-power components to a low-current ground plane. Both grounds can
meet at RSNS
.
3. Place the VDD RC filter close to the device's VDD pin.
11.2 Layout Example
High-current ground
plane
High-current traces
PACK+
Pad
PACK–
Pad
Connect low power
components (for example,
RC filter) close to the IC pin
and use a low current plane for
ground connection.
BAT–
Pad
bq298xy
RS
BAT+
Pad
FET
Low current (IC ground)
Group components along the high-current path together to
optimize layout.
Use Rs to connect the high-current
and low-current grounds.
Figure 11-1. Component Placement and Grounding Pattern Example
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: BQ2980 BQ2982
BQ2980, BQ2982
SLUSCS3I – OCTOBER 2017 – REVISED NOVEMBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: BQ2980 BQ2982
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ298000RUGR
BQ298000RUGT
BQ298006RUGR
ACTIVE
ACTIVE
ACTIVE
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
5I
5I
NIPDAU
NIPDAU
5I
06
BQ298006RUGT
BQ298009RUGR
BQ298009RUGT
BQ298010RUGR
BQ298010RUGT
BQ298012RUGR
BQ298012RUGT
BQ298015RUGR
BQ298015RUGT
BQ298018RUGR
BQ298019RUGR
BQ298215RUGR
BQ298216RUGR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
8
8
8
8
8
8
8
8
8
8
8
8
8
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
5I
06
5I
09
5I
09
5I
10
5I
10
5I
12
5I
12
5I
15
5I
15
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
5I
18
5I
19
82
15
82
16
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2021
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ298000RUGR
BQ298000RUGT
BQ298006RUGR
BQ298006RUGT
BQ298009RUGR
BQ298009RUGT
BQ298010RUGR
BQ298010RUGT
BQ298012RUGR
BQ298012RUGT
BQ298015RUGR
BQ298015RUGT
BQ298018RUGR
BQ298019RUGR
BQ298215RUGR
BQ298216RUGR
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
9.5
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
1.69
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
0.63
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
3000
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ298000RUGR
BQ298000RUGT
BQ298006RUGR
BQ298006RUGT
BQ298009RUGR
BQ298009RUGT
BQ298010RUGR
BQ298010RUGT
BQ298012RUGR
BQ298012RUGT
BQ298015RUGR
BQ298015RUGT
BQ298018RUGR
BQ298019RUGR
BQ298215RUGR
BQ298216RUGR
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
RUG
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
189.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
36.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
3000
3000
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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