BQ34Z100PWR-R2 [TI]
多化合物 Impedance Track™ 独立式电量监测计 | PW | 14 | -40 to 85;
| 型号： | BQ34Z100PWR-R2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 多化合物 Impedance Track™ 独立式电量监测计 | PW | 14 | -40 to 85 |
| 文件： | 总25页 (文件大小：1531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ34Z100-R2
ZHCSRC1 –DECEMBER 2022
BQ34Z100-R2 采用Impedance Track™ 技术的宽量程电量监测计
1 特性
2 应用
• 支持锂离子、磷酸铁锂、PbA、镍氢和镍镉化学物
质
• 轻型电动车辆
• 医疗仪器
• 移动无线电
• 电动工具
• 不间断电源(UPS)
• 对电压为3V 至
16.7 KV 的电池使用已获得专利的Impedance
Track™ 技术估算容量
– 老化补偿
– 自放电补偿
• 支持的电池容量高达7000Ah，并且提供标准配置
选项
• 支持的充电和放电电流高达8160 A，并且提供标准
配置选项
• 外部负温度系数(NTC) 热敏电阻支持
• 支持与主机系统的两线制I2C 和HDQ 单线制通信
接口
3 说明
BQ34Z100-R2 器件是适用于锂离子、铅酸、镍氢和镍
镉电池的Impedance Track™ 电量监测计，并且独立于
电池串联配置工作。通过外部电压转换电路可轻松支持
3V 至 16.7KV 的电池，此电路可通过自动控制来降低
系统功耗。
BQ34Z100-R2 器件提供多个接口选项，其中包括一个
I2C 外设接口、一个 HDQ 外设接口、一个或四个直接
LED 接口以及一个 ALERT 输出引脚。此外，
BQ34Z100-R2 还支持外部端口扩展器，连接四个以上
的LED。
• SHA-1/HMAC 认证
• 一个或者四个LED 直接显示控制
• 五个LED 和通过端口扩展器的更多显示
• 节能模式（典型电池组运行范围条件）
– 正常工作：< 145µA 平均电流
– 睡眠：< 84µA 平均电流
– 全睡眠：< 30µA 平均电流
• 封装：14 引脚TSSOP
器件信息
器件型号(1)
封装尺寸（标称值）
封装
BQ34Z100-R2
TSSOP (14)
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSF37
BQ34Z100-R2
ZHCSRC1 –DECEMBER 2022
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Table of Contents
6.12 Electrical Characteristics: Data Flash Memory
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Power-On Reset................5
6.6 Electrical Characteristics: LDO Regulator...................5
6.7 Electrical Characteristics: Internal Temperature
Sensor Characteristics.................................................. 5
6.8 Electrical Characteristics: Low-Frequency
Oscillator....................................................................... 6
6.9 Electrical Characteristics: High-Frequency
Oscillator....................................................................... 6
6.10 Electrical Characteristics: Integrating ADC
(Coulomb Counter) Characteristics...............................6
6.11 Electrical Characteristics: ADC (Temperature
Characteristics...............................................................7
6.13 Timing Requirements: HDQ Communication............7
6.14 Timing Requirements: I2C-Compatible Interface...... 8
6.15 Typical Characteristics..............................................9
7 Functional Block Diagram............................................ 10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Applications...................................................11
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................21
11.1 Documentation Support.......................................... 21
11.2 接收文档更新通知................................................... 21
11.3 支持资源..................................................................21
11.4 Trademarks............................................................. 21
11.5 静电放电警告...........................................................21
11.6 术语表..................................................................... 21
12 Mechanical, Packaging, and Orderable
and Cell Measurement) Characteristics........................ 6
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
P2
VEN
1
2
3
4
5
6
7
14
13
12
11
10
9
P3/SDA
P4/SCL
P5/HDQ
P6/TS
SRN
P1
BAT
CE
REGIN
REG25
SRP
8
VSS
Not to scale
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NUMBER
P2
1
O
LED 2 or Not Used (connect to VSS)
Active High Voltage Translation Enable. This signal is optionally used to switch the input voltage
divider on/off to reduce the power consumption (typ 45 µA) of the divider network. If not used,
then this pin can be left floating or tied to VSS.
VEN
P1
2
3
O
O
LED 1 or Not Used (connect to VSS). This pin is also used to drive an LED for single-LED mode.
Use a small signal N-FET (Q1) in series with the LED as shown on 图8-4.
BAT
4
5
6
I
I
Translated Battery Voltage Input
CE
Chip Enable. Internal LDO is disconnected from REGIN when driven low.
Internal integrated LDO input. Decouple with a 0.1-µF ceramic capacitor to VSS.
REGIN
P
2.5-V output voltage of the internal integrated LDO. Decouple with 1-µF ceramic capacitor to
VSS.
REG25
VSS
7
8
9
P
P
I
Device ground
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRP is nearest the BAT–connection.
SRP
Analog input pin connected to the internal coulomb-counter peripheral for integrating a small
voltage between SRP and SRN where SRN is nearest the PACK–connection.
SRN
10
11
12
I
I
P6/TS
P5/HDQ
Pack thermistor voltage sense (use a 103AT-type thermistor)
Open-drain HDQ Serial communication line (target). If not used, then this pin can be left floating
or tied to VSS.
I/O
Target I2C serial communication clock input. Use with a 10-kΩpullup resistor (typical). This pin is
P4/SCL
P3/SDA
13
14
I
also used for LED 4 in the four-LED mode. If not used, then this pin can be left floating or tied to
VSS.
Open-drain target I2C serial communication data line. Use with a 10-kΩpullup resistor (typical).
This pin is also used for LED 3 in the four-LED mode. If not used, then this pin can be left floating
or tied to VSS.
I/O
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
VREGIN
VCC
Regulator Input Range
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
Supply Voltage Range
2.75
5.5
VIOD
VBAT
VI
Open-drain I/O pins (SDA, SCL, HDQ, VEN)
Bat Input pin
5.5
Input Voltage range to all other pins (P1, P2, SRP, SRN)
Human-body model (HBM), BAT pin
Human-body model (HBM), all other pins
Operating free-air temperature range
Functional temperature range
VCC + 0.3
V
1.5
2
kV
kV
°C
°C
°C
°C
ESD
TA
TF
85
–40
–40
–65
–40
100
150
100
Storage temperature range
TSTG
Lead temperature (soldering, 10 s)
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA =–40°C to 85°C; Typical Values at TA = 25°C CLDO25 = 1.0 µF, and VREGIN = 3.6 V (unless otherwise noted)
MIN
NOM
MAX UNIT
No operating restrictions
No FLASH writes
2.7
4.5
2.7
V
V
VREGIN
Supply Voltage
2.45
External input capacitor for
internal LDO between REGIN
and VSS
CREGIN
0.1
1
μF
μF
Nominal capacitor values specified.
Recommend a 10% ceramic X5R type
capacitor located close to the device.
External output capacitor for
internal LDO between VCC and
VSS
CLDO25
0.47
NORMAL operating-mode
current
Gas Gauge in NORMAL mode,
ILOAD > Sleep Current
ICC
145
μA
μA
μA
Gas Gauge in SLEEP mode,
ILOAD < Sleep Current
ISLP
ISLP+
SLEEP operating-mode current
84
30
FULLSLEEP operating-mode
current
Gas Gauge in FULL SLEEP mode,
ILOAD < Sleep Current
Output voltage, low (SCL, SDA,
HDQ, VEN)
VOL
IOL = 3 mA
0.4
0.6
V
V
V
V
VOH(PP)
VOH(OD)
VIL
Output voltage, high
IOH = –1 mA
VCC –0.5
VCC –0.5
–0.3
Output voltage, high (SDA, SCL,
HDQ, VEN)
External pull-up resistor connected to VCC
Input voltage, low
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6.3 Recommended Operating Conditions (continued)
TA =–40°C to 85°C; Typical Values at TA = 25°C CLDO25 = 1.0 µF, and VREGIN = 3.6 V (unless otherwise noted)
MIN
NOM
MAX UNIT
Input voltage, high (SDA, SCL,
HDQ)
VIH(OD)
1.2
6
V
VA1
Input voltage range (TS)
1
5
V
V
V
VSS –0.05
VSS –0.125
VSS –0.125
VA2
Input voltage range (BAT)
VA3
Input voltage range (SRP, SRN)
Input leakage current (I/O pins)
Power-up communication delay
0.125
0.3
ILKG
tPUCD
μA
250
ms
6.4 Thermal Information
BQ34Z100-R2
TSSOP (PW)
14 PINS
103.8
THERMAL METRIC(1)
UNIT
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
31.9
46.6
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
2.0
ψJT
45.9
ψJB
RθJC(bottom)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953.
6.5 Electrical Characteristics: Power-On Reset
TA = –40°C to 85°C; Typical Values at TA = 25°C and VREGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.05
45
TYP
2.20
115
MAX UNIT
Positive-going battery voltage
input at REG25
VIT+
2.31
185
V
VHYS
Power-on reset hysteresis
mV
6.6 Electrical Characteristics: LDO Regulator
TA = 25°C, CLDO25 = 1.0 µF, VREGIN = 3.6 V (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
2.7 V ≤VREGIN ≤4.5 V,
OUT ≤16 mA
2.3
2.5
2.7
V
TA= –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
I
Regulator output
voltage
VREG25
2.45 V ≤VREGIN < 2.7 V
(low battery), IOUT ≤3 mA
2.3
Short Circuit
Current Limit
(2)
ISHORT
VREG25 = 0 V
250
mA
(1) LDO output current, IOUT, is the sum of internal and external load currents.
(2) Specified by design. Not production tested.
6.7 Electrical Characteristics: Internal Temperature Sensor Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GTEMP
Temperature sensor voltage gain
mV/°C
–2
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6.8 Electrical Characteristics: Low-Frequency Oscillator
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
32.768
0.25%
0.25%
0.25%
500
MAX UNIT
f(LOSC)
Operating frequency
Frequency error(1) (2)
Start-up time(3)
kHz
TA = 0°C to 60°C
1.5%
–1.5%
–2.5%
–4%
f(LEIO)
2.5%
TA = –20°C to 70°C
TA = –40°C to 85°C
4%
t(LSXO)
μs
(1) The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA = 25°C.
(2) The frequency error is measured from 32.768 kHz.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.9 Electrical Characteristics: High-Frequency Oscillator
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
8.389
0.38%
0.38%
0.38%
2.5
MAX UNIT
f(OSC)
Operating frequency
Frequency error(1) (2)
Start-up time(2)
MHz
TA = 0°C to 60°C
2%
3%
–2%
–3%
f(EIO)
TA = –20°C to 70°C
TA = –40°C to 85°C
4.5%
5
–4.5%
t(SXO)
ms
(1) The frequency error is measured from 2.097 MHz.
(2) The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
6.10 Electrical Characteristics: Integrating ADC (Coulomb Counter) Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(SR) = V(SRN) –V(SRP)
Single conversion
MIN
TYP
MAX UNIT
V(SR)
Input voltage range, V(SRN) and V(SRP)
Conversion time
0.125
15
V
s
–0.125
1
tSR_CONV
Resolution
14
bits
VOS(SR)
INL
ZIN(SR)
Ilkg(SR)
Input offset
10
µV
Integral nonlinearity error
Effective input resistance(1)
Input leakage current(1)
±0.007% ±0.034% FSR(2)
2.5
MΩ
0.3
µA
(1) Specified by design. Not tested in production.
(2) Full-scale reference
6.11 Electrical Characteristics: ADC (Temperature and Cell Measurement) Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN(ADC)
Input voltage range
Conversion time
Resolution
0.05
1
125
15
V
ms
tADC_CONV
14
bits
mV
MΩ
VOS(ADC)
ZADC1
Input offset
1
Effective input resistance (TS)(1)
8
8
BQ34Z100-R2 not measuring cell
voltage
MΩ
KΩ
ZADC2
Effective input resistance (BAT)(1)
BQ34Z100-R2 measuring cell
voltage
100
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6.11 Electrical Characteristics: ADC (Temperature and Cell Measurement) Characteristics
(continued)
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Ilkg(ADC)
Input leakage current(1)
0.3 µA
(1) Specified by design. Not tested in production.
6.12 Electrical Characteristics: Data Flash Memory Characteristics
TA = –40°C to 85°C, 2.4 V < REG25 < 2.6 V; Typical Values at TA = 25°C and REG25 = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Data retention(1)
10
Years
tDR
Flash-programming write cycles(1)
Word programming time(1)
Flash-write supply current(1)
20,000
Cycles
ms
tWORDPROG
ICCPROG
2
5
10
mA
(1) Specified by design. Not tested in production.
6.13 Timing Requirements: HDQ Communication
TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
190
190
0.5
32
NOM
MAX UNIT
t(CYCH)
t(CYCD)
t(HW1)
t(DW1)
t(HW0)
t(DW0)
t(RSPS)
t(B)
Cycle time, host to BQ34Z100-R2
Cycle time, BQ34Z100-R2 to host
Host sends 1 to BQ34Z100-R2
BQ34Z100-R2 sends 1 to host
Host sends 0 to BQ34Z100-R2
BQ34Z100-R2 sends 0 to host
Response time, BQ34Z100-R2 to host
Break time
μs
205
250
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
50
86
145
145
950
80
190
190
40
t(BR)
Break recovery time
t(RISE)
t(RST)
HDQ line rising time to logic 1 (1.2 V)
HDQ Reset
950
2.2
1.8
s
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1.2V
t(BR)
t(RISE)
t(B)
(a) Break and Break Recovery
(b) HDQ line rise time
t(DW1)
t(HW1)
t(DW0)
t(CYCD)
t(HW0)
t(CYCH)
(d) Gauge Transmitted Bit
(c) Host Transmitted Bit
7-bit address
1-bit
R/W
8-bit data
Break
t(RSPS)
(e) Gauge to Host Response
图6-1. Timing Diagrams
6.14 Timing Requirements: I2C-Compatible Interface
TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
tr
SCL/SDA rise time
300
300
ns
ns
tf
SCL/SDA fall time
tw(H)
SCL pulse width (high)
SCL pulse width (low)
Setup for repeated start
Start to first falling edge of SCL
Data setup time
600
1.3
600
600
100
0
ns
tw(L)
μs
ns
tsu(STA)
td(STA)
tsu(DAT)
th(DAT)
tsu(STOP)
tBUF
ns
ns
Data hold time
ns
Setup time for stop
600
66
ns
Bus free time between stop and start
Clock frequency
μs
kHz
fSCL
400
t
f
t
t
t
t
t
r
(BUF)
SU(STA)
w(H)
w(L)
SCL
SDA
t
t
t
f
d(STA)
su(STOP)
t
r
t
t
su(DAT)
h(DAT)
REPEATED
START
STOP
START
图6-2. I2C-Compatible Interface Timing Diagrams
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6.15 Typical Characteristics
200
160
120
80
15
10
5
40
0
0
-5
-40
-80
-120
-160
-200
-10
-15
-40°C
-20°C
25°C
65°C
85°C
-40èC
-20èC
25èC
65èC
85èC
-20
25.2
27
28.8 30.6 32.4 34.2
Battery Voltage (V)
36
37.8 39.6
2800 3000 3200 3400 3600 3800 4000 4200 4400
Battery Voltage (mV)
D002
D001
图6-4. V(Err) Across VIN (0 mA) 9 s
图6-3. V(Err) Across VIN (0 mA)
25
2
1
0
20
15
10
5
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
-5
-10
-15
-20
-25
-40èC
-20èC
25èC
65èC
85èC
-3000
-2000
-1000
0
Current (mA)
1000
2000
3000
-40
-20
0
20
40
60
80
100
Temperature (èC)
D003
D004
图6-5. I(Err)
图6-6. T(Err)
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7 Functional Block Diagram
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 元件规格，TI 不担保其准确性和完整性。TI 的客户负责确定元件是否
适合其用途，以及验证和测试其设计实现以确认系统功能。
8.1 Application Information
The BQ34Z100-R2 is a flexible gas gauge device with many options. The major configuration choices comprise
the battery chemistry, digital interface, and display.
8.2 Typical Applications
图 8-1 is a simplified diagram of the main features of the BQ34Z100-R2. Specific implementations detailing the
main configuration options are shown later in this section.
图8-1. BQ34Z100-R2 Simplified Implementation
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The BQ34Z100-R2 can be used to provide a single Li-ion cell gas gauge with a 5-bar LED display.
m p p 5 7 0 1 0 .
0 3 R
2
S H 1 S H
图8-2. 1-Cell Li-ion and 5-LED Display
The BQ34Z100-R2 can also be used to provide a gas gauge for a multi-cell Li-ion battery with a 5-bar LED
display.
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S
2
3
1
G
D
7 R
图8-3. Multi-Cell and 5-LED Display
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图8-4 shows the BQ34Z100-R2 full features enabled.
1
2
3
4
5
6
7
8
N R G 4 -
N R G 4 -
N R G 4 -
N R G 4 -
6 1 L 0 P T C Q
6 1 L 0 P T C Q
6 1 L 0 P T C Q
6 1 L 0 P T C Q
2
1
2 H S
1 H S
m p p 5 7 0 1 0 .
0
R 3
图8-4. Full-Featured Evaluation Module EVM
8.2.1 Design Requirements
For additional design guidelines, refer to the BQ34Z100 EVM Wide Range Impedance Track Enabled Battery
Fuel Gauge User's Guide (SLUU904).
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8.2.2 Detailed Design Procedure
8.2.2.1 Step-by-Step Design Procedure
8.2.2.1.1 STEP 1: Review and Modify the Data Flash Configuration Data.
While many of the default parameters in the data flash are suitable for most applications, the following should
first be reviewed and modified to match the intended application.
• Design Capacity: Enter the value in mAh divided by CurrScale() for the battery, even from the “design
energy”point of view.
• Design Energy: Enter the value in cWh divided by EnergyScale() .
• Cell Charge Voltage Tx-Ty: Enter the desired cell charge voltage for each JEITA temperature range.
8.2.2.1.2 STEP 2: Review and Modify the Data Flash Configuration Registers.
• LED_Comm Configuration: See in the BQ34Z100-R2 Technical Reference Manual to aid in selection of an
LED mode. Note that the pin used for the optional Alert signal is dependent upon the LED mode selected.
• Alert Configuration: See the BQ34Z100-R2 Technical Reference Manual to aid in selection of which faults
trigger the ALERT pin.
• Number of Series Cells
• Pack Configuration: Ensure that the VOLSEL bit is set for multicell applications and cleared for single-cell
applications.
8.2.2.1.3 STEP 3: Design and Configure the Voltage Divider.
If the battery contains more than 1-s cells, a voltage divider network is required. Design the divider network,
based on the formula below. The voltage division required is from the highest expected battery voltage, down to
approximately 900 mV. For example, using a lower leg resistor of 16.5 KΩ where the highest expected voltage
is 32000 mV:
Rseries = 16.5 KΩ(32000 mV –900 mV)/900 mV = 570.2 KΩ
Based on price and availability, a 600-K resistor or pair of 300-K resistors could be used in the top leg along with
a 16.5-K resistor in the bottom leg.
Set the Voltage Divider in the Data Flash Calibration section of the Evaluation Software to 32000 mV with
VoltScale() =1.
Use the Evaluation Software to calibrate to the applied nominal voltage; for example, 24000 mV. After
calibration, a slightly different value appears in the Voltage Divider parameter, which can be used as a default
value for the project. For the applications with voltage higher than 65535 mV, please refer to the BQ34Z100-R2
Technical Reference Manual.
Following the successful voltage calibration, calculate and apply the value to Flash Update OK Cell Volt as:
Flash Update OK Cell Volt = 2800 mV × Number Of Series Cells × 5000 / Voltage Divider /VoltScale() .
8.2.2.1.4 STEP 4: Determine the Sense Resistor Value.
To ensure accurate current measurement, the input voltage generated across the current sense resistor should
not exceed +/–125 mV. For applications with a very high dynamic range, it is allowable to extend this range to
absolute maximum of +/–300 mV for overload conditions where a protector device will be taking independent
protective action. In such an overloaded state, current reporting and gauging accuracy will not function correctly.
The value of the current sense resistor should be entered into both CC Gain and CC Delta parameters in the
Data Flash Calibration section of the Evaluation Software.
8.2.2.1.5 STEP 5: Review and Modify the Data Flash Gas Gauging Configuration, Data, and State.
• Load Select: See Current Model Used When Load Mode = 0 and Constant-Power Model Used When Load
Mode = 1 in the BQ34Z100-R2 Technical Reference Manual.
• Load Mode: See Current Model Used When Load Mode = 0 and Constant-Power Model Used When Load
Mode = in the BQ34Z100-R2 Technical Reference Manual.
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• Cell Terminate Voltage: This is the theoretical voltage where the system begins to fail. It is defined as a zero
state-of-charge. Generally, a more conservative level is used to have some reserve capacity. Note the value
is for a single cell only.
• Quit Current: Generally, this should be set to a value slightly above the expected idle current of the system.
• Qmax Cell 0: Start with the C-rate value of your battery.
8.2.2.1.6 STEP 6: Determine and Program the Chemical ID.
Use the BQChem feature in the Evaluation Software to select and program the chemical ID matching your cell. If
no match is found, use the procedure defined in TI's (Mathcad Chemistry Selection Tool (SLUC138).
8.2.2.1.7 STEP 7: Calibrate.
Follow the steps on the Calibration screen in the Evaluation Software. Achieving the best possible calibration is
important before moving on to Step 8. For mass production, calibration is not required for single-cell applications.
For multi-cell applications, only voltage calibration is required. Current and temperature may be calibrated to
improve gauging accuracy if needed.
8.2.2.1.8 STEP 8: Run an Optimization Cycle.
Refer to the Preparing Optimized Default Flash Constants for Specific Battery Types Application Report
(SLUA334B).
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9 Power Supply Recommendations
Power supply requirements for the BQ34Z100-R2 are simplified due to the presence of the internal LDO voltage
regulation. The REGIN pin accepts any voltage level between 2.7 V and 4.5 V, which is optimum for a single-cell
Li-ion application. For higher battery voltage applications, a simple pre-regulator can be provided to power the
bq34Z100-R2 and any optional LEDs. Decoupling the REGIN pin should be done with a 0.1-µF 10% ceramic
X5R capacitor placed close to the device. While the pre-regulator circuit is not critical, special attention should be
paid to its quiescent current and power dissipation. The input voltage should handle the maximum battery stack
voltage. The output voltage can be centered within the 2.7-V to 4.5-V range as recommended for the REGIN pin.
For high stack count applications, a commercially available LDO is often the best quality solution, but comes with
a cost tradeoff. To lower the BOM cost, the following approaches are recommended.
In 图9-1, Q1 is used to drop the battery stack voltage to roughly 4 V to power the BQ34Z100-R2 REGIN pin and
also to feed the anode of any LEDs used in the application. To avoid unwanted quiescent current consumption,
R1 should be set as high as is practical. It is recommended to use a low-current Zener diode.
From Battery Stack +
R1
Q1
~4 V
D1
5.6 V
To REGIN/LED(s)
图9-1. Q1 Dropping Battery Stack Voltage to 4 V
Alternatively, if the range of a high-voltage battery stack can be well defined, a simple source follower based on
a resistive divider can be used to lower the BOM cost and the quiescent current. For example:
From Battery Stack +
R1
Q1
2.7 V ~ 4.5 V
R2
To REGIN/LED(s)
图9-2. Source Follower on a Resistive Divider
Power dissipation of the linear pre-regulator may become an important design decision when multiple LEDs are
employed in the application. For example, the BQ34Z100-R2 EVM uses a pair of FETs in parallel to
inexpensively dissipate enough power for 10-LED evaluation.
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10 Layout
10.1 Layout Guidelines
10.1.1 Introduction
Attention to layout is critical to the success of any battery management circuit board. The mixture of high-current
paths with an ultralow-current microcontroller creates the potential for design issues that are not always trivial to
solve. Some of the key areas of concern are described in the following sections, and can help to enable
success.
10.1.2 Power Supply Decoupling Capacitor
Power supply decoupling from VCC to ground is important for optimal operation of the gas gauge. To keep the
loop area small, place this capacitor next to the IC and use the shortest possible traces. A large loop area
renders the capacitor useless and forms a small-loop antenna for noise pickup.
Ideally, the traces on each side of the capacitor should be the same length and run in the same direction to avoid
differential noise during ESD. If possible, place a via near the VSS pin to a ground plane layer.
10.1.3 Capacitors
Power supply decoupling for the gas gauges requires a pair of 0.1-µF ceramic capacitors for (BAT) and (VCC)
pins. These should be placed reasonably close to the IC without using long traces back to VSS. The LDO
voltage regulator, whether external or internal to the main IC, requires a 0.47-µF ceramic capacitor to be placed
fairly close to the regulation output pin. This capacitor is for amplifier loop stabilization and as an energy well for
the 2.5-V supply.
10.1.4 Communication Line Protection Components
The 5.6-V Zener diodes, used to protect the communication pins of the gas gauge from ESD, should be located
as close as possible to the pack connector. The grounded end of these Zener diodes should be returned to the
Pack(–) node rather than to the low-current digital ground system. This way, ESD is diverted away from the
sensitive electronics as much as possible.
In some applications, it is sometimes necessary to cause transitions on the communication lines to trigger events
that manage the gas gauge power modes. An example of one of these transitions is detecting a sustained low
logic level on the communication lines to detect that a pack has been removed. Given that most of the gas
gauges do not have internal pulldown networks, it is necessary to add a weak pulldown resistor to accomplish
this when there's an absence of a strong pullup resistor on the system side. If the weak pulldown resistor is
used, it may take less board space to use a small capacitor in parallel instead of the Zener diode to absorb any
ESD transients that are received through communication lines.
10.2 Layout Example
10.2.1 Ground System
The gas gauge requires a low-current ground system separate from the high-current PACK(–) path. ESD
ground is defined along the high-current path from the PACK(–) terminal to low-side protector FETs (if present)
or the sense resistor. It is important that the low-current ground systems only connect to the BAT(–) path at the
sense resistor Kelvin pick-off point. It is recommended to use an optional inner layer ground plane for the low-
current ground system. In 图 10-1, the green is an example of using the low-current ground as a shield for the
gas gauge circuit. Notice how it is kept separate from the high-current ground, which is shown in red. The high-
current path is joined with the low-current path only at one point, shown with the small blue connection between
the two planes.
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图10-1. Differential Filter Component with Symmetrical Layout
10.2.2 Kelvin Connections
Kelvin voltage sensing is very important to accurately measure current and cell voltage. Notice how the
differential connections at the sense resistor do not add any voltage drop across the copper etch that carries the
high current path through the sense resistor. See 图10-1 and 图10-2.
10.2.3 Board Offset Considerations
Although the most important component for board offset reduction is the decoupling capacitor for VCC, additional
benefit is possible by using this recommended pattern for the coulomb counter differential low-pass filter
network. Maintain the symmetrical placement pattern shown for optimum current offset performance. Use
symmetrical shielded differential traces, if possible, from the sense resistor to the 100-Ω resistors, as shown in
图10-2.
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图10-2. Differential Connection Between SRP and SRN Pins with Sense Resistor
10.2.4 ESD Spark Gap
Protect the communication lines from ESD with a spark gap at the connector. 图 10-3 shows the recommended
pattern with its 0.2-mm spacing between the points.
图10-3. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD
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11 Device and Documentation Support
11.1 Documentation Support
For related documentation, see the following:
• BQ34Z100-R2 Technical Reference Manual
• BQ34Z100-R2 High Cell Count and High Capacity Applications application report
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
Impedance Track™ is a trademark of Texas Instruments.
TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ34Z100PWR-R2
ACTIVE
TSSOP
PW
14
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
34Z100
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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Copyright © 2023，德州仪器 (TI) 公司
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