BQ4010LY [TI]
8 k x 8 NONVOLATILE SRAM (5 V, 3.3 V); 为8K ×8非易失性SRAM （ 5 V ， 3.3 V ）
| 型号： | BQ4010LY |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 k x 8 NONVOLATILE SRAM (5 V, 3.3 V) |
| 文件： | 总18页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4010/Y/LY
www.ti.com
SLUS116A–MAY 1999–REVISED APRIL 2007
8 k × 8 NONVOLATILE SRAM (5 V, 3.3 V)
FEATURES
GENERAL DESCRIPTION
•
•
•
•
Data Retention for at least 10 Years Without
Power
The CMOS bq4010/Y/LY is a nonvolatile 65,536-bit
static RAM organized as 8,192 words by 8 bits. The
integral control circuitry and lithium energy source
provide reliable nonvolatility coupled with the
unlimited write cycles of standard SRAM.
Automatic Write-Protection During
Power-up/Power-down Cycles
Conventional SRAM Operation, Including
Unlimited Write Cycles
The control circuitry constantly monitors the single
supply for an out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is unconditionally
write-protected to prevent an inadvertent write
operation.
Internal Isolation of Battery before Power
Application
•
•
5-V or 3.3-V Operation
Industry Standard 28-Pin DIP Pinout or
34-Pin LIFETIME LITHIUM™ SMD Pinout
At this time the integral energy source is switched on
to sustain the memory until after VCC returns valid.
•
Snap-on, Replaceable Lithium Battery
for SMD Device
(Device Number: bq401BATCAP)
The bq4010/Y/LY uses extremely low standby
current CMOS SRAMs, coupled with small lithium
coin cells to provide nonvolatility without long
write-cycle times and the write-cycle limitations
associated with EEPROM.
The bq4010/Y/LY requires no external circuitry and is
compatible with the industry-standard 64-Mb SRAM
pinout.
PIN CONNECTIONS
34−Pin
Lifetime Lithium Module
(TOP VIEW)
28−Pin DIP Module
(TOP VIEW)
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC/BW
NC
NC
NC
NC
NC
1
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
2
A
12
2
WE
NC
NC
3
A
7
3
NC/RST
4
A
6
4
A
8
V
CC
A
12
5
A
5
5
A
9
WE
OE
CE
A
11
6
A
4
A
10
7
6
A
11
A
9
8
A
3
7
OE
DQ
7
A
8
9
A
2
8
A
10
DQ
6
A
7
10
11
12
13
14
15
16
17
A
1
9
CE
DQ
DQ
5
A
6
A
0
10
11
12
13
14
7
DQ
4
A
5
DQ
DQ
DQ
DQ
DQ
0
6
5
4
3
DQ
3
A
4
DQ
1
DQ
2
A
3
DQ
2
DQ
1
A
2
V
SS
DQ
0
A
1
V
SS
A
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
bq4010/Y/LY
www.ti.com
SLUS116A–MAY 1999–REVISED APRIL 2007
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
LLM-34
VCC = 3.3 V
LLM-34
VCC = 5 V
NAME
DIP-28
A0
10
9
18
19
20
21
22
23
24
25
26
27
28
29
30
1
18
19
20
21
22
23
24
25
26
27
28
29
30
-
I
A1
I
A2
8
I
A3
7
I
A4
6
I
I
A5
5
A6
4
I
Address inputs
A7
3
I
A8
25
24
21
23
2
I
A9
I
A10
A11
A12
BW
CE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I
I
I
-
O
I
Battery warning output (open drain)
Chip-enable input
20
11
12
13
15
16
17
18
19
1
8
8
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data input/output
-
1
-
2
2
-
3
3
-
-
4
NC
26
-
-
-
-
No connect
31
32
33
34
7
31
32
33
34
7
-
-
OE
22
-
I
Output enable input
Power-up reset to system CPU output (open
drain)
RST
4
-
O
VCC
VSS
WE
28
14
27
5
17
6
5
17
6
I
-
I
Supply voltage input
Ground
Write enable input
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SLUS116A–MAY 1999–REVISED APRIL 2007
FUNCTIONAL DESCRIPTION
When power is valid, the bq4010/Y/LY operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4010/Y/LY acts as a nonvolatile memory, automatically protecting and preserving the memory
contents.
Power-down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD
.
The bq4010 monitors for VPFD = 4.62 V typical for use in 5-V systems with 5% supply tolerance. The bq4010Y
monitors for VPFD = 4.37 V typical for use in 5-V systems with 10% supply tolerance. The bq4010LY monitors for
VPFD = 2.90 V (typ) for use in 3.3-V systems.
When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as don't care. If a valid access is in process at the time of power-fail
detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time tWPT
write-protection takes place.
,
As VCC falls past VPFD and approaches VSO, the control circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
When VCC returns to a level above the internal backup cell voltage, the supply is switched back to VCC. After VCC
ramps above the VPFD threshold, write-protection continues for a time tCER (120 ms maximum in 5-V system,
85 ms maximum in 3.3-V system) to allow for processor stabilization. Normal memory operation may resume
after this time.
The internal coin cells used by the bq4010/Y/LY have an extremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from TI, the integral lithium cells of the MT-type module are electrically isolated from the memory.
(Self-discharge in this condition is approximately 0.5% per year.) Following the first application of VCC, this
isolation is broken, and the lithium backup provides data retention on subsequent power-downs. The LIFETIME
LITHIUM package option is shipped as two devices, which must be ordered separately.
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SLUS116A–MAY 1999–REVISED APRIL 2007
BLOCK DIAGRAM
DIP MODULE
bq4010/Y/LY
MA PACKAGE
LIFETIME LITHIUM
bq4010Y/LY
EBZ PACKAGE
OE
OE
A - A
A - A
0 12
0
12
8 k × 8
SRAM
Block
8 k × 8
SRAM
Block
WE
WE
DQ - DQ
DQ - DQ
0
7
0
7
Power
Power
CE
CE
CON
CON
CE
CE
V
V
Power-Fail
Control
Power-Fail
Control
CC
CC
Lithium
Cell
Lithium
Cell
+
+
bq401BATCAP
UDG-06075
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SLUS116A–MAY 1999–REVISED APRIL 2007
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of the datasheet, or see
the TI website at www.ti.com.
SELECTION GUIDE
MAXIMUM
ACCESS
TIME (ns)
NEGATIVE SUPPLY
TOLERANCE
(%)
NOMINAL INPUT
VOLTAGE
TEMPERATURE
DEVICE NUMBER
MODULE
(°C)
VCC (V)
bq4010MA-70
70
85
bq4010MA-85
-5
bq4010MA-150
bq4010MA-200
bq4010YMA-70
bq4010YMA-85
bq4010YMA-150
bq4010YMA-200
bq4010YMA-70N
bq4010YMA-85N
bq4010YMA-150N
bq4010YEBZ-70N
bq4010LYMA-70N
bq4010LYEBZ-70N
150
200
70
0 to 70
85
DIP
5
150
200
70
-10
85
150
-40 to 85
Lifetime Lithium
DIP
70
3.3
Lifetime Lithium
PART NUMBERING
INPUT
VOLTAGE
(V)
NEGATIVE
SUPPLY
TOLERANCE
PRODUCT
LINE
MEMORY
DENSITY
SPEED
(ns)
TEMPERATURE
PACKAGE
(°C)
bq40
10
L
Y
MA
70
70
N
10 = 8 k × 8
Blank = 5
L= 3.3
Blank = 5%
Y = 10%
MA = DIP
EBZ = SMD
Blank = Commercial
( 0 to 70)
11 = 32 k × 8
13 = 128 k × 8
14 = 256 k × 8
15 = 512 k × 8
16 = 1024 k × 8
17 = 2048 k × 8
85
100
120
150
200
N = Industrial
(-40 to 85)
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SLUS116A–MAY 1999–REVISED APRIL 2007
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER
CONDITION
VALUE
–0.3 to 7.0
–0.3 to 7.0
–0.3 to 6.0
–0.3 to 7.0
–0.3 to 7.0
–0.3 to (VCC + 0.3)
0 to 70
UNIT
bq4010Y
bq4010
VCC
DC voltage applied on VCC relative to VSS
V
bq4010LY
bq4010Y
bq4010
DC voltage applied on any pin excluding
VCC relative to VSS
VT
V
VT≤ VCC +0.3 V
V
bq4010LY
Commercial
Industrial
TOPR
Operating temperature
Storage temperature
–40 to 85
–10 to 70
–40 to 85
–10 to 70
–40 to 85
260
Commercial
Industrial
TSTG
°C
Commercial
Industrial
TBIAS
Temperature under bias
Soldering temperature
TSOLDER
For 10 seconds
(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the
Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended
periods of time may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (TA = TOPR
)
MIN TYP(1)
MAX UNIT
5.50
bq4010Y
bq4010
4.50
4.75
3.00
0
5.00
5.00
3.30
0
VCC
Supply voltage
5.50
bq4010LY
3.60
V
VSS
VIL
Supply voltage
0
Low-level input voltage
High-level Input voltage
–0.3
2.2
0.8
VIH
VCC + 0.3
(1) Typical values indicate operation at TA = 25°C.
CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5.0 V or VCC = 3.3 V)
PARAMETER(1)
Input/output capacitance
Input capacitance
TEST CONDITIONS
Output voltage = 0 V
Input voltage = 0 V
MIN
TYP
MAX
8
UNIT
CI/O
CIN
pF
10
(1) Ensured by design. Not production tested.
DC ELECTRICAL CHARACTERISTICS
TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
PARAMETER
TEST CONDITIONS
VIN = VSS to VCC
MIN TYP(1)
MAX
±1
UNIT
ILI
Input leakage current
Output leakage current
Output high voltage
Output low voltage
µA
ILO
CE = VIH or OE = VIH or WE = VIL
IOH = –1.0 mA
±1
VOH
VOL
ISB1
2.4
V
IOL = 2.1 mA
0.4
2
Standby supply current
CE = VIH
1
µA
CE≥ VCC– 0.2 V, 0V ≤ VIN≤ 0.2 V,
or VIN≥ VCC– 0.2
ISB2
Standby supply current
0.1
1
mA
bq4010
bq4010Y
bq4010LY
35
30
Minimum cycle, duty = 100%,
CE = VIL, II/O = 0 mA
ICC
Operating supply current
mA
(1) Typical values indicate operation at TA = 25°C, VCC = 5.0 V or VCC = 3.3 V.
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SLUS116A–MAY 1999–REVISED APRIL 2007
DC ELECTRICAL CHARACTERISTICS (continued)
TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
4.75
4.50
2.95
UNIT
bq4010
bq4010Y
bq4010LY
bq4010
4.55
4.30
2.85
4.62
4.37
2.90
3
VPFD
Power-fail-detect voltage
V
VSO
Supply switch-over voltage
bq4010Y
bq4010LY
3
2.9
TRUTH TABLE
MODE
CE
H
L
WE
X
OE
X
I/O OPERATION
High-Z
POWER
Not selected
Output disable
Read
Standby
Active
Active
Active
H
H
High-Z
L
H
L
DOUT
Write
L
L
H
DIN
7
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SLUS116A–MAY 1999–REVISED APRIL 2007
AC TEST CONDITIONS
TEST CONDITIOINS
PARAMETER
5 V
0 V to 3.0 V
5 ns
3.3 V
0 V to VCC
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figure 1 and Figure 2
50 %
See Figure 3 and Figure 4
+ 5 V
+ 5 V
1.9 kW
1.9 kW
D
D
OUT
OUT
1 kW
100 pF
1 kW
5 pF
Figure 1. 5-V Output Load A
Figure 2. 5-V Output Load A
+ 3.3 V
+ 3.3 V
1.2 kW
1.2 kW
D
D
OUT
OUT
1.4 kW
30 pF
1.4 kW
5 pF
Figure 3. 3.3-V Output Load B
Figure 4. 3.3-V Output Load B
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Table 2. READ CYCLE (TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
)
-70
-85
-150
-200
PARAMETER
Read cycle time
TEST CONDITIONS
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
tRC
70
70
70
35
5
85
85
85
45
5
150
150
150
70
5
200
200
200
90
5
tAA
Address access time
tACE
tOE
Chip enable access time
Output load A
Output enable to output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
tCLZ
tOLZ
tCHZ
tOHZ
tOH
ns
0
0
0
0
Output load B
Output load A
0
0
25
25
0
0
25
25
0
0
25
25
0
0
25
25
10
10
10
10
t
RC
Address
t
AA
t
OH
D
OUT
Previous Data Valid
Data Valid
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = VIL.
Figure 5. Read Cycle No. 1 (Address Access) (1)(2)
t
RC
CE
t
ACE
t
t
CHZ
CLZ
D
OUT
High−Z
High−Z
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = VIL.
(3) Address is valid prior to or coincident with CE transition low.
Figure 6. Read Cycle No. 2 (CE Access) (1)(2)(3)
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t
RC
Address
OE
t
AA
t
t
OE
OHZ
t
OLZ
D
OUT
Data Valid
High−Z
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = VIL.
High−Z
Figure 7. Read Cycle No. 3 (OE Access) (1)(2)
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Table 3. WRITE CYCLE (TA = TOPR, VCC(min)≤ VCC≤ VCC(max)
)
-70
-85
-150
-200
MIN MAX
200
PARAMETER
Write cycle time
TEST CONDITIONS
UNIT
MIN MAX
MIN MAX
MIN MAX
tWC
tCW
tAW
70
65
65
85
75
75
150
100
90
(1)
(1)
Chip enable to end of write
Address valid to end of write
See
See
150
150
Measured from address valid to
beginning of write.(2)
tAS
Address setup time
0
55
5
0
65
5
0
90
5
0
130
5
Measured from beginning of write to
end of write. (1)
tWP
Write pulse width
Measured from WE going high to end
of write cycle.(3)
tWR1
tWR2
tDW
tDH1
tDH2
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
ns
Measured from CE going high to end
of write cycle.(3)
15
30
0
15
35
0
15
50
0
15
70
0
Measured to first low-to- high transition
of either CE or WE.
Measured from WE going high to end
of write cycle.(4)
Measured from CE going high to end
of write cycle.(4)
0
0
0
0
tWZ
tOW
Write enbled to output in high Z
Output active from end of write
I/O pins are in output state.(5)
I/O pins are in output state. (5)
0
5
25
0
5
30
0
5
50
0
5
70
(1) A write ends at the earlier transition of CE going high and WE going high.
(2) A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low.
(3) Either tWR1 or tWR2 must be met.
(4) Either tDH1 or tDH2 must be met.
(5) If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
t
WC
Address
t
AW
t
WR1
t
CW
CE
t
AS
t
WP
WE
t
t
DW
DH1
Data−In Valid
D
IN
t
WZ
t
OW
D
OUT
Data Undefined (1)
High−Z
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance.
Figure 8. Write Cycle No. 1 (WE-Controlled) (1)(2)(3)
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t
WC
Address
t
AW
t
WR2
t
AS
t
CW
CE
t
WP
WE
t
DW
t
DH2
D
IN
Data−in Valid
t
WZ
D
OUT
Data Undefined (1)
High−Z
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance.
(4) Either tWR1 or tWR2 must be met.
(5) Either tDH1 or tDH2 must be met.
Figure 9. Write Cycle No. 2 (CE-Controlled) (1)(2)(3)(4)(5)
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Table 4. 5-V POWER-DOWN/POWER-UP (TA = TOPR
)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
µs
tPF
tFS
tPU
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
µs
VCC slew, VSO to VPFD (max.)
µs
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
Data-retention time in absence of VCC TA = 25°C(2)
Delay after VCC slews down past VPFD before SRAM
is writeprotected.
tCER
tDR
Chip enable recovery time
40
10
40
80
120
150
ms
years
µs
tWPT
Write-protect time
100
(1) Typical values indicate operation at TA = 25°C, VCC = 5V.
(2) Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the accumulated time in absence of power
beginning when power is first applied to the device.
t
PF
V
CC
4.75 V
V
PFD
V
PFD
4.25 V
V
V
SO
SO
t
FS
t
PU
t
DR
t
CER
t
WPT
CE
Figure 10. 5-V Power-Down/Power-Up Timing
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Table 5. 3.3-V POWER-DOWN/POWER-UP (TA = TOPR
)
PARAMETER
VCC slew, 3 V to 0 V
TEST CONDITIONS
MIN TYP(1)
300
MAX
UNIT
tF
µs
tR
VCC slew, VSO to VPFD (max)
100
Time during which SRAM is write-protected after
VCC passes VPFD on power-up.
Data-retention time in absence of VCC TA = 25°C(2)
tCER
Chip enable recovery time
10
10
85
ms
tDR
years
(1) Typical values indicate operation at TA = 25°C, VCC = 3.3 V.
(2) Batteries are disconnected from circuit until after VCC is applied for the first time. Data retention time (tDR) is the accumulated time in
absence of power beginning when power is first applied to the device.
V
CC
3.0 V
V
PFD(max)
V
PFD
V
SO
V
SO
t
R
t
DR
t
t
F
CER
CE
Figure 11. 3.3-V Power-Down/Power-Up Timing
CAUTION:
Negative undershoots below the absolute maximum rating of -0.3 V in
battery-backup mode may affect data integrity.
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PACKAGE OPTION ADDENDUM
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4-May-2007
PACKAGING INFORMATION
Orderable Device
BQ4010LYMA-70N
BQ4010MA-150
BQ4010MA-200
BQ4010MA-70
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DIP MOD
ULE
MA
28
28
28
28
28
28
28
28
28
28
28
28
1
1
1
1
1
1
1
1
1
1
1
1
Pb-Free
(RoHS)
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
CU SN
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
DIP MOD
ULE
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
BQ4010MA-85
DIP MOD
ULE
Pb-Free
(RoHS)
BQ4010YMA-150
BQ4010YMA-150N
BQ4010YMA-200
BQ4010YMA-70
BQ4010YMA-70N
BQ4010YMA-85
BQ4010YMA-85N
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
DIP MOD
ULE
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI061 – MAY 2001
MA (R-PDIP-T**)
PLASTIC DUAL-IN-LINE
28 PINS SHOWN
Inches
Max.
Millimeters
Min.
Max.
Dimension
A
Min.
0.365
0.015
0.017
0.008
0.710
1.470
1.670
2.070
0.710
0.590
0.090
0.120
0.105
0.075
0.375
–
9.27
0.38
9.53
–
A1
0.023
0.58
0.33
0.43
B
0.20
C
0.013
0.740
1.500
1.700
2.100
0.740
D/12 PIN
D/28 PIN
D/32 PIN
D/40 PIN
18.03
37.34
42.42
52.58
18.03
18.80
38.10
43.18
53.34
18.80
16.00
2.79
D
E
e
14.99
2.29
0.630
0.110
G
L
3.81
3.05
2.67
1.91
0.150
0.130
0.110
S/12 PIN
S
3.30
2.79
E
L
A
A1
C
B
e
S
G
4201975/A 03/01
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
1
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