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BQ4010MA-150N [TI]

8Kx8 Nonvolatile SRAM; 8Kx8非易失SRAM
BQ4010MA-150N
型号： BQ4010MA-150N
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

8Kx8 Nonvolatile SRAM
8Kx8非易失SRAM

静态存储器
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bq4010/bq4010Y  
8Kx8 Nonvolatile SRAM  
At t his tim e th e int egr a l ener gy  
Features  
➤ Data retention in the absence of  
General Description  
source is switched on to sustain the  
memory until after VCC returns valid.  
The CMOS bq4010 is a nonvolatile  
65,536-bit static RAM organized as  
8,192 words by 8 bits. The integral  
control circuitry and lithium energy  
source provide reliable nonvolatility  
coupled with th e u nlim ited wr ite  
cycles of standard SRAM.  
power  
The bq4010 uses an extremely low  
s t a n d by cu r r en t CMOS SR AM,  
coupled with a small lithium coin  
cell to provide nonvolatility without  
long write-cycle times and the write-  
cycle lim it a tion s a ssocia ted with  
EEPROM.  
➤ Automatic write-protection  
during power-up/power-down  
cycles  
➤ Industry-standard 28-pin 8K x 8  
pinout  
Th e con t r ol cir cu it r y con st a n t ly  
monitors the single 5V supply for an  
out-of-tolerance condition. When VCC  
falls out of tolerance, the SRAM is  
un conditionally wr ite-protected to  
prevent inadvertent write operation.  
➤ Conventional SRAM operation;  
The bq4010 requires no external cir-  
cuitry and is socket-compatible with  
industry-standard SRAMs and most  
EPROMs and EEPROMs.  
unlimited write cycles  
➤ 10-year minimum data retention  
in absence of power  
➤ Battery internally isolated until  
power is applied  
Pin Connections  
Pin Names  
Block Diagram  
A0 –A12  
Address inputs  
DQ0–DQ7 Data input/output  
CE  
Chip enable input  
Output enable input  
Write enable input  
No connect  
OE  
WE  
NC  
VCC  
VSS  
+5 volt supply input  
Ground  
Selection Guide  
Maximum  
Access  
Negative  
Supply  
Maximum  
Access  
Negative  
Supply  
Part  
Part  
Number  
Time (ns)  
Tolerance  
Number  
Time (ns)  
Tolerance  
bq4010Y -70  
bq4010Y -85  
bq4010Y -150  
bq4010Y -200  
70  
85  
-10%  
-10%  
-10%  
-10%  
bq4010 -85  
85  
-5%  
-5%  
-5%  
bq4010 -150  
bq4010 -200  
150  
200  
150  
200  
Sept. 1996 D  
1
bq4010/bq4010Y  
As VCC falls past VPFD and approaches 3V, the control  
circuitry switches to the internal lithium backup supply,  
which provides data retention until valid VCC is applied.  
Functional Description  
When power is valid, the bq4010 operates as a standard  
CMOS SRAM. During power-down and power-up cycles,  
the bq4010 acts as a nonvolatile memory, automatically  
protecting and preserving the memory contents.  
When VCC returns to a level above the internal backup  
cell voltage, the supply is switched back to VCC. After  
VCC ramps above the VPFD threshold, write-protection  
continues for a time tCER (120ms maximum) to allow for  
processor stabilization. Normal memory operation may  
resume after this time.  
P ower -down /power -u p con t r ol cir cu itr y con s ta n tly  
monitors the VCC supply for a power-fail-detect threshold  
VPFD. The bq4010 monitors for VPFD = 4.62V typical for  
use in systems with 5% supply tolerance. The bq4010Y  
monitors for VPFD = 4.37V typical for use in systems with  
10% supply tolerance.  
Th e in t er n a l coin cell u sed by t he bq4010 h as a n  
extremely long shelf life and provides data retention for  
more than 10 years in the absence of system power.  
When VCC falls below the VPFD threshold, the SRAM  
a u t om a t ica lly wr ite-pr otects t h e da ta . All ou tpu ts  
become high impedance, and all inputs are treated as  
“don’t care.” If a valid access is in process at the time of  
power-fail detection, the memory cycle continues to com-  
pletion. If the memory cycle fails to terminate within  
time tWPT, write-protection takes place.  
As shipped from Benchmarq, the integral lithium cell is  
electrically isolated from the memory. (Self-discharge in  
this condition is approximately 0.5% per year.) Following  
the first application of VCC, this isolation is broken, and  
th e lith iu m ba cku p cell pr ovides da ta r eten tion on  
subsequent power-downs.  
Truth Table  
Mode  
Not selected  
CE  
H
L
WE  
X
OE  
X
I/O Operation  
High Z  
High Z  
DOUT  
Power  
Standby  
Active  
Output disable  
Read  
H
H
L
H
L
Active  
Write  
L
L
X
DIN  
Active  
Absolute Maximum Ratings  
Symbol  
Parameter  
Value  
Unit  
Conditions  
VCC  
DC voltage applied on VCC relative to VSS  
-0.3 to 7.0  
-0.3 to 7.0  
V
DC voltage applied on any pin excluding VCC  
relative to VSS  
VT  
V
VT ≤ VCC + 0.3  
0 to +70  
-40 to +85  
-40 to +70  
-40 to +85  
-10 to +70  
-40 to +85  
+260  
°C  
°C  
°C  
°C  
°C  
°C  
°C  
Commercial  
TOPR  
Operating temperature  
Storage temperature  
Temperature under bias  
Industrial “N”  
Commercial  
TSTG  
Industrial “N”  
Commercial  
TBIAS  
Industrial “N”  
For 10 seconds  
TSOLDER Soldering temperature  
Note:  
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional operation  
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-  
ditions beyond the operational limits for extended periods of time may affect device reliability.  
Sept. 1996 D  
6-2  
bq4010/bq4010Y  
Recommended DC Operating Conditions (T = T  
)
A
OPR  
Symbol  
Parameter  
Minimum  
Typical Maximum  
Unit  
V
Notes  
bq4010Y/bq4010Y-xxxN  
bq4010  
4.5  
4.75  
0
5.0  
5.0  
0
5.5  
5.5  
0
VCC  
Supply voltage  
V
VSS  
VIL  
VIH  
Supply voltage  
V
Input low voltage  
Input high voltage  
-0.3  
2.2  
-
0.8  
V
-
VCC + 0.3  
V
Note:  
Typical values indicate operation at TA = 25°C.  
DC Electrical Characteristics (T = T  
, V  
≤ V  
≤ V  
CC CCmax)  
A
OPR CCmin  
Symbol  
ILI  
Parameter  
Minimum  
Typical  
Maximum  
Unit  
Conditions/Notes  
VIN = VSS to VCC  
Input leakage current  
-
-
± 1  
µA  
µA  
CE = VIH or OE = VIH or  
WE = VIL  
ILO  
Output leakage current  
-
-
± 1  
VOH  
VOL  
ISB1  
Output high voltage  
Output low voltage  
Standby supply current  
2.4  
-
-
-
0.4  
7
V
V
IOH = -1.0 mA  
IOL = 2.1 mA  
CE = VIH  
-
-
4
mA  
CE ≥ VCC - 0.2V,  
0V ≤ VIN ≤ 0.2V,  
or VIN ≥ VCC - 0.2V  
ISB2  
Standby supply current  
Operating supply current  
-
2.5  
4
mA  
Min. cycle, duty = 100%,  
CE = VIL, II/O = 0mA  
ICC  
-
65  
75  
mA  
4.55  
4.30  
-
4.62  
4.37  
3
4.75  
4.50  
-
V
V
V
bq4010  
VPFD  
Power-fail-detect voltage  
Supply switch-over voltage  
bq4010Y  
VSO  
Note:  
Typical values indicate operation at TA = 25°C, VCC = 5V.  
Capacitance (T = 25°C, F = 1MHz, V  
= 5.0V)  
A
CC  
Symbol  
CI/O  
Parameter  
Input/output capacitance  
Input capacitance  
Minimum  
Typical  
Maximum  
Unit  
Conditions  
Output voltage = 0V  
Input voltage = 0V  
-
-
-
-
10  
10  
pF  
pF  
CIN  
Note:  
These parameters are sampled and not 100% tested.  
Sept. 1996 D  
6-3  
bq4010/bq4010Y  
AC Test Conditions  
Parameter  
Test Conditions  
0V to 3.0V  
Input pulse levels  
Input rise and fall times  
5 ns  
Input and output timing reference levels  
Output load (including scope and jig)  
1.5 V (unless otherwise specified)  
See Figures 1 and 2  
Figure 1. Output Load A  
Figure 2. Output Load B  
Read Cycle (T = T  
, V  
≤ V  
≤ V )  
CCmax  
A
OPR CCmin  
CC  
-70/-70N  
-85/-85N  
-150/-150N  
-200  
Symbol  
tRC  
Parameter  
Read cycle time  
Unit  
ns  
Conditions  
Min. Max. Min. Max. Min. Max.  
Min. Max.  
70  
-
-
85  
-
-
150  
-
200  
-
tAA  
Address access time  
Chip enable access time  
70  
70  
85  
85  
-
-
150  
150  
-
-
200  
200  
ns  
Output load A  
Output load A  
tACE  
-
-
ns  
Output enable to output  
valid  
tOE  
-
5
35  
-
-
5
45  
-
-
10  
5
70  
-
-
10  
5
90  
-
ns  
ns  
ns  
ns  
ns  
ns  
Output load A  
Output load B  
Output load B  
Output load B  
Output load B  
Output load A  
Chip enable to output  
in low Z  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Output enable to output  
in low Z  
5
-
5
-
-
-
Chip disable to output  
in high Z  
0
25  
25  
-
0
40  
30  
-
0
60  
50  
-
0
70  
70  
-
Output disable to  
output in high Z  
0
0
0
0
Output hold from  
address change  
10  
10  
10  
10  
Sept. 1996 D  
6-4  
bq4010/bq4010Y  
1,2  
Read Cycle No. 1 (Address Access)  
1,3,4  
Read Cycle No. 2 (CE Access)  
1,5  
Read Cycle No. 3 (OE Access)  
Notes:  
1. WE is held high for a read cycle.  
2. Device is continuously selected: CE = OE = VIL  
3. Address is valid prior to or coincident with CE transition low.  
4. OE = VIL  
5. Device is continuously selected: CE = VIL  
.
.
.
Sept. 1996 D  
6-5  
bq4010/bq4010Y  
Write Cycle (T = T  
, V  
≤ V  
≤ V  
)
A
OPR CCmin  
CC  
-85/-85N  
CCmax  
-70/-70N  
-150/-150N  
-200  
Min. Max. Min. Max. Min. Max. Min. Max.  
Symbol  
Parameter  
Units  
Conditions/Notes  
tWC  
Write cycle time  
70  
-
85  
-
150  
-
200  
-
ns  
Chip enable to end  
of write  
tCW  
tAW  
55  
-
75  
-
100  
-
150  
-
ns  
ns  
(1)  
Address valid to end  
of write  
55  
0
-
-
75  
0
-
-
90  
0
-
-
150  
0
-
-
(1)  
Measured from  
tAS  
Address setup time  
Write pulse width  
ns address valid to  
beginning of write. (2)  
Measured from  
ns beginning of write to  
end of write. (1)  
tWP  
55  
5
-
-
-
-
-
-
65  
5
-
-
-
-
-
-
90  
5
-
-
-
-
-
-
130  
5
-
-
-
-
-
-
Measured from WE  
ns going high to end of  
write cycle. (3)  
Write recovery time  
(write cycle 1)  
tWR1  
tWR2  
tDW  
tDH1  
Measured from CE  
ns going high to end of  
write cycle. (3)  
Write recovery time  
(write cycle 2)  
15  
30  
0
15  
35  
0
15  
50  
0
15  
70  
0
Measured from first  
ns low-to-high transition  
of either CE or WE.  
Data valid to end of  
write  
Measured from WE  
ns going high to end of  
write cycle. (4)  
Data hold time  
(write cycle 1)  
Measured from CE  
ns going high to end of  
write cycle. (4)  
Data hold time  
(write cycle 2)  
tDH2  
10  
10  
0
0
Write enabled to  
output in high Z  
I/O pins are in output  
state. (5)  
tWZ  
0
5
25  
-
0
5
30  
-
0
5
50  
-
0
5
70  
-
ns  
Output active from  
end of write  
I/O pins are in output  
state. (5)  
tOW  
ns  
Notes:  
1. A write ends at the earlier transition of CE going high and WE going high.  
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition  
of CE going low and WE going low.  
3. Either tWR1 or tWR2 must be met.  
4. Either tDH1 or tDH2 must be met.  
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in  
high-impedance state.  
Sept. 1996 D  
6-6  
bq4010/bq4010Y  
1,2,3  
Write Cycle No. 1 (WE-Controlled)  
1,2,3,4,5  
Write Cycle No. 2 (CE-Controlled)  
Notes:  
1. CE or WE must be high during address transition.  
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the  
outputs must not be applied.  
3. If OE is high, the I/O pins remain in a state of high impedance.  
4. Either tWR1 or tWR2 must be met.  
5. Either tDH1 or tDH2 must be met.  
Sept. 1996 D  
6-7  
bq4010/bq4010Y  
Power-Down/Power-Up Cycle (T = T  
)
A
OPR  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
µs  
Conditions  
tPF  
VCC slew, 4.75 to 4.25 V  
300  
-
-
tFS  
tPU  
VCC slew, 4.25 to VSO  
10  
0
-
-
-
-
µs  
VCC slew, VSO to VPFD (max.)  
µs  
Time during which SRAM is  
write-protected after VCC passes  
VPFD on power-up.  
tCER  
Chip enable recovery time  
40  
80  
120  
ms  
Data-retention time in  
absence of VCC  
tDR  
10  
-
-
years  
TA = 25°C. (2)  
Data-retention time in  
absence of VCC  
TA = 25°C (2); industrial  
temperature range (-N) only.  
tDR-N  
6
-
-
years  
Delay after VCC slews down past  
VPFD before SRAM is write-  
protected.  
tWPT  
Write-protect time  
40  
100  
150  
µs  
Notes:  
1. Typical values indicate operation at TA = 25°C, VCC = 5V.  
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the  
accumulated time in absence of power beginning when power is first applied to the device.  
Ca u tion : Nega t ive u n d er sh oots b elow th e a b solu te m a xim u m r a t in g of -0.3V in ba tter y-b a ck u p m od e  
m a y a ffect d a ta in tegr it y.  
Power-Down/Power-Up Timing  
Sept. 1996 D  
6-8  
bq4010/bq4010Y  
Data Sheet Revision History  
Change No.  
Page No.  
Description  
1
2, 3, 4, 6, 8, 9  
Added industrial temperature range for bq4010YMA-85N and -150N.  
Added 70 ns speed grade for bq4010-70 and bq4010Y-70 and added  
industrial temperature range for bq4010YMA-70N.  
2
3
1, 4, 6, 9  
1
Removed 70ns speed grade for bq4010-70.  
Notes:  
Change 1 = Sept 1991 B changes from Sept. 1990 A.  
Change 2 = Feb. 1994 C changes from Sept. 1991 B.  
Change 3 = Sept. 1996 D changes from Feb. 1994 C.  
MA: 28-Pin A-Type Module  
(
)
28-Pin MA A-Type Module  
Inches  
Millimeters  
Dimension  
Min.  
0.365  
0.015  
0.017  
0.008  
1.470  
0.710  
0.590  
0.090  
0.120  
0.075  
Max.  
0.375  
-
Min.  
Max.  
9.53  
-
A
A1  
B
C
D
E
9.27  
0.38  
0.023  
0.013  
1.500  
0.740  
0.630  
0.110  
0.150  
0.110  
0.43  
0.58  
0.33  
38.10  
18.80  
16.00  
2.79  
3.81  
2.79  
0.20  
37.34  
18.03  
14.99  
2.29  
e
G
L
3.05  
S
1.91  
Sept. 1996 D  
6-9  
bq4010/bq4010Y  
Ordering Information  
bq4010 MA -  
Tem p er a tu r e:  
blank = Commercial (0 to +70°C)  
N = Industrial (-40 to +85°C)*  
Sp eed Op tion s:  
85 = 85 ns  
150 = 150 ns  
200 = 200 ns  
P a ck a ge Op tion :  
MA = A-type module  
Su p p ly Toler a n ce:  
no mark = 5% negative supply tolerance  
Y = 10% negative supply tolerance  
Device:  
bq4010 8K x 8 NVSRAM  
*Not e:  
Only 10% supply (“Y”) version is available in industrial  
temperature range; contact factory for speed grade  
availability.  
Sept. 1996 D  
6-10  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
BQ4010MA-150  
BQ4010MA-200  
BQ4010MA-70  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
DIP MOD  
ULE  
MA  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
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DIP MOD  
ULE  
MA  
MA  
MA  
MA  
MA  
MA  
MA  
MA  
MA  
MA  
DIP MOD  
ULE  
BQ4010MA-85  
DIP MOD  
ULE  
BQ4010YMA-150  
BQ4010YMA-150N  
BQ4010YMA-200  
BQ4010YMA-70  
BQ4010YMA-70N  
BQ4010YMA-85  
BQ4010YMA-85N  
DIP MOD  
ULE  
DIP MOD  
ULE  
DIP MOD  
ULE  
DIP MOD  
ULE  
DIP MOD  
ULE  
DIP MOD  
ULE  
DIP MOD  
ULE  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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