BQ4017Y [TI]
2048Kx8 Nonvolatile SRAM ; 2048Kx8非易失SRAM\n
| 型号： | BQ4017Y |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2048Kx8 Nonvolatile SRAM
|
| 文件： | 总11页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4017/bq4017Y
2048Kx8 Nonvolatile SRAM
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
Features
General Description
➤ Data retention in the absence of
The CMOS bq4017 is a nonvolatile
16,777,216-bit static RAM organized
as 2,097,152 words by 8 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
limited write cycles of standard
SRAM.
power
The bq4017 uses extremely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EE-
PROM.
➤ Automatic write-protection dur-
ing power-up/power-down cycles
➤ Conventional SRAM operation;
unlimited write cycles
➤ 5-year minimum data retention
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When VCC
falls out of tolerance, the SRAM is
unconditionally write-protected to
prevent an inadvertent write opera-
tion.
in absence of power
The bq4017 has the same interface
as industry-standard SRAMs and
requires no external circuitry.
➤ Battery internally isolated until
power is applied
Pin Connections
Pin Names
Block Diagram
A0–A20
Address inputs
NC
36
V
A
1
2
3
4
5
6
7
8
CC
19
DQ0–DQ7 Data input/output
A
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
20
18
16
14
12
A
A
A
A
A
A
NC
A
CE
Chip enable input
Output enable input
Write enable input
Supply voltage input
Ground
15
17
A
WE
OE
A
13
7
6
A
8
A
9
9
A
A
WE
VCC
VSS
NC
5
4
A
10
11
12
13
14
15
16
17
18
11
A
A
A
OE
3
2
1
0
0
1
2
A
10
CE
DQ
DQ
DQ
DQ
DQ
A
7
DQ
DQ
DQ
V
6
5
4
3
No connect
SS
36-Pin DIP Module
PN401701.eps
Selection Guide
Maximum
Access
Time (ns)
Negative
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
Supply
Part
Number
Tolerance
bq4017MC -70
70
-5%
bq4017YMC -70
70
-10%
5/95
1
bq4017/bq4017Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4017 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4017 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC
. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly moni-
tors the VCC supply for a power-fail-detect threshold
VPFD. The bq4017 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4017Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
The internal coin cells used by the bq4017 have an ex-
tremely long shelf life. The bq4017 provides data reten-
tion for more than 5 years in the absence of system
power.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs be-
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As shipped from Unitrode, the integral lithium cells are
electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Follow-
ing the first application of VCC, this isolation is broken,
and the lithium backup provides data retention on sub-
sequent power-downs.
Truth Table
Mode
Not selected
CE
H
L
WE
X
OE
X
I/O Operation
High Z
High Z
DOUT
Power
Standby
Active
Active
Active
Output disable
Read
H
H
L
L
H
Write
L
L
X
DIN
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
VT ≤ VCC + 0.3
-0.3 to 7.0
V
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-40 to +70
-10 to +70
+260
°C
°C
°C
°C
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
2
bq4017/bq4017Y
Recommended DC Operating Conditions (T = 0 to 70°C)
A
Symbol
Parameter
Minimum
4.5
Typical
Maximum
Unit
V
Notes
bq4017Y
bq4017
5.0
5.0
0
5.5
5.5
VCC
Supply voltage
4.75
0
V
VSS
VIL
VIH
Supply voltage
0
V
Input low voltage
Input high voltage
-0.3
-
0.8
V
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (T = 0 to 70°C, V
≤ V
≤ V
)
CCmax
A
CCmin
CC
Symbol
Parameter
Minimum Typical Maximum Unit
Conditions/Notes
VIN = VSS to VCC
ILI
Input leakage current
-
-
-
-
4
4
µA
µA
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
0.4
17
7
mA
0V ≤ VIN ≤ 0.2V,
CE ≥ VCC - 0.2V,
or VIN ≥ VCC - 0.2
ISB2
Standby supply current
Operating supply current
-
-
2.5
75
5
mA
mA
Min. cycle, duty = 100%,
CE = VIL ,II/O = 0mA,
A19 < VIL or A19 > VIH
A20 < VIL or A20 > VIH
ICC
115
,
4.55
4.30
-
4.62
4.37
3
4.75
4.50
-
V
V
V
bq4017
VPFD
Power-fail-detect voltage
Supply switch-over voltage
bq4017Y
VSO
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
3
bq4017/bq4017Y
Capacitance (T = 25°C, F = 1MHz, V
= 5.0V)
CC
A
Symbol
CI/O
Parameter
Input/output capacitance
Input capacitance
Minimum
Typical
Maximum
Unit
pF
Conditions
-
-
-
-
40
40
Output voltage = 0V
Input voltage = 0V
CIN
pF
Note:
These parameters are sampled and not 100% tested.
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = 0 to 70°C, V
≤ V
≤ V
)
CCmax
A
CCmin
CC
-70
Symbol
tRC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Min.
Max.
-
Read cycle time
70
-
tAA
Address access time
70
70
35
-
Output load A
tACE
tOE
Chip enable access time
-
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Output enable to output valid
Chip enable to output in low Z
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
5
0
0
10
Output enable to output in low Z
Chip disable to output in high Z
-
25
25
-
Output disable to output in high Z
Output hold from address change
4
bq4017/bq4017Y
1,2
Read Cycle No. 1 (Address Access)
1,3,4
Read Cycle No. 2 (CE Access)
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
.
5
bq4017/bq4017Y
Write Cycle (T = 0 to 70°C, V
≤ V
≤ V
)
A
CCmin
CC
CCmax
-70
Min.
Max.
Symbol
tWC
Parameter
Write cycle time
Units
ns
Conditions/Notes
70
65
65
-
-
-
tCW
Chip enable to end of write
Address valid to end of write
ns
(1)
(1)
tAW
ns
Measured from address valid to be-
ginning of write. (2)
tAS
Address setup time
Write pulse width
0
55
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Measured from beginning of write to
end of write. (1)
tWP
Write recovery time
(write cycle 1)
Measured from WE going high to
end of write cycle. (3)
tWR1
tWR2
tDW
tDH1
tDH2
Write recovery time
(write cycle 2)
Measured from CE going high to
end of write cycle. (3)
15
30
0
Measured to first low-to-high transi-
tion of either CE or WE.
Data valid to end of write
Data hold time
(write cycle 1)
Measured from WE going high to
end of write cycle. (4)
Data hold time
(write cycle 2)
Measured from CE going high to
end of write cycle. (4)
10
tWZ
tOW
Write enabled to output in high Z
Output active from end of write
0
5
25
-
ns
ns
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
6
bq4017/bq4017Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
7
bq4017/bq4017Y
Power-Down/Power-Up Cycle (T = 0 to 70°C)
A
Symbol
tPF
Parameter
Minimum
300
Typical
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
-
-
-
-
tFS
10
µs
VCC slew, VSO to VPFD
(max.)
µs
tPU
0
-
-
Time during which SRAM
is write-protected after
tCER
Chip enable recovery time
40
80
120
ms
V
CC passes VFPD on
power-up.
Data-retention time in
absence of VCC
tDR
TA = 25°C. (2)
5
-
-
years
Delay after VCC slews
down past VPFD before
SRAM is write-protected.
µs
tWPT
Write-protect time
40
100
150
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
8
bq4017/bq4017Y
MC: 36-Pin C-Type Module
(C-Type Module)
36-Pin MC
Dimension
Minimum
0.365
0.015
0.017
0.008
2.070
0.710
0.590
0.090
0.120
0.175
Maximum
0.375
-
A
A1
B
C
D
E
e
0.023
0.013
2.100
0.740
0.630
0.110
0.150
0.210
G
L
S
All dimensions are in inches.
9
bq4017/bq4017Y
Ordering Information
bq4017 MC -
Temperature:
blank = Commercial (0 to +70°C)
Speed Options:
70 = 70 ns
Package Option:
MC = C-type module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4017 2048K x 8 NVSRAM
10
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