BQ40Z50-R1 [TI]
支持涡轮模式 1.0 的 1 至 4 节串联锂离子电池组管理器;
| 型号： | BQ40Z50-R1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持涡轮模式 1.0 的 1 至 4 节串联锂离子电池组管理器 电池 |
| 文件： | 总55页 (文件大小：3968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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bq40z50-R1
ZHCSDZ9 –JULY 2015
bq40z50-R1 1 节、2 节、3 节和 4 节串联锂离子电池组管理器
1 特性
3 说明
1
•
全集成 1 节、2 节、3 节和 4 节串联锂离子或锂聚
合物电池组管理器及保护
bq40z50-R1 器件采用已获专利的 Impedance Track™
技术，是一款基于电池组的单芯片全集成解决方案，针
对 1 节、2 节、3 节和 4 节串联锂离子或锂聚合物电
池组提供电量监测、保护及认证等一些列丰富的功能。
•
下一代已获专利的 Impedance Track™ 技术可准确
测量锂离子和锂聚合物电池中的可用电量
•
•
•
高侧 N 通道保护场效应晶体管 (FET) 驱动
充电或者静止状态时集成的电池均衡
可编程保护特性的完全阵列
bq40z50-R1 器件利用其集成的高性能模拟外设，测量
锂离子或锂聚合物电池的可用容量、电压、电流、温度
和其他关键参数，保留准确的数据记录，并通过
SMBus v1.1 兼容接口将这些信息报告给系统主机控制
器。
–
–
–
–
–
–
电压
电流
温度
器件信息(1)
充电终止时间
CHG/DSG FET
模拟前端 (AFE)
器件型号
bq40z50-R1
封装
VQFN (32)
封装尺寸（标称值）
4.00mm x 4.00mm
•
精密的充电算法
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
–
–
–
–
日本电子与信息技术工业协会 (JEITA)
简化电路原理图
增强型充电
自适应充电
电池均衡
+
PACK
•
•
•
•
•
•
•
支持 TURBO 升压模式
支持电池跳变点 (BTP)
LEDCNTLA
BAT
VC4
LEDCNTLB
诊断寿命数据监视器和黑匣子记录器
发光二极管 (LED) 显示
LEDCNTLC
VC3
VC2
OUT
VC3
VC2
VC1
Cell 3
Cell 2
DISP
支持 2 线制系统管理总线 (SMBus) v1.1 接口
安全散列算法 (SHA-1) 认证
SMBD
VDD
GND
SMBD
SMBC
VC1
PBI
SMBC
PRES
VSS SRP SRN TS1 TS2 TS3 TS4 BTP PRES
紧凑封装：32 导线四方扁平无引线 (QFN) (RSM)
Cell 1
BTP
2 应用
–
PACK
•
•
•
笔记本/上网本
医疗与测试设备
便携式仪表
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCB3
bq40z50-R1
ZHCSDZ9 –JULY 2015
www.ti.com.cn
目录
7.24 Electrical Characteristics: Internal 1.8-V LDO ..... 14
1
2
3
4
5
6
7
特性.......................................................................... 1
7.25 Electrical Characteristics: High-Frequency
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明（续）............................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Electrical Characteristics: Supply Current................. 8
7.6 Electrical Characteristics: Power Supply Control...... 8
7.7 Electrical Characteristics: AFE Power-On Reset...... 9
Oscillator .................................................................. 14
7.26 Electrical Characteristics: Low-Frequency
Oscillator .................................................................. 14
7.27 Electrical Characteristics: Voltage Reference 1.... 15
7.28 Electrical Characteristics: Voltage Reference 2.... 15
7.29 Electrical Characteristics: Instruction Flash .......... 15
7.30 Electrical Characteristics: Data Flash ................... 15
7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2
Current Protection Thresholds................................. 16
7.32 Timing Requirements: OCD, SCC, SCD1, SCD2
Current Protection Timing........................................ 16
7.33 Timing Requirements: SMBus .............................. 17
7.34 Timing Requirements: SMBus XL......................... 17
7.35 Typical Characteristics ......................................... 19
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
8.2 Functional Block Diagram ...................................... 22
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 26
Applications and Implementation ...................... 27
9.1 Application Information .......................................... 27
9.2 Typical Applications ................................................ 28
7.8 Electrical Characteristics: AFE Watchdog Reset and
Wake Timer................................................................ 9
8
9
7.9 Electrical Characteristics: Current Wake
Comparator ................................................................ 9
7.10 Electrical Characteristics: VC1, VC2, VC3, VC4,
BAT, PACK .............................................................. 10
7.11 Electrical Characteristics: SMBD, SMBC.............. 10
7.12 Electrical Characteristics: PRES, BTP_INT, DISP
................................................................................. 10
7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB,
LEDCNTLC ............................................................. 11
10 Power Supply Recommendations ..................... 42
11 Layout................................................................... 43
11.1 Layout Guidelines ................................................. 43
11.2 Layout Example .................................................... 45
12 器件和文档支持 ..................................................... 47
12.1 文档支持................................................................ 47
12.2 社区资源................................................................ 47
12.3 商标....................................................................... 47
12.4 静电放电警告......................................................... 47
12.5 Glossary................................................................ 47
13 机械、封装和可订购信息....................................... 47
7.14 Electrical Characteristics: Coulomb Counter ........ 11
7.15 Electrical Characteristics: CC Digital Filter ........... 11
7.16 Electrical Characteristics: ADC ............................. 11
7.17 Electrical Characteristics: ADC Digital Filter......... 12
7.18 Electrical Characteristics: CHG, DSG FET Drive . 12
7.19 Electrical Characteristics: PCHG FET Drive......... 13
7.20 Electrical Characteristics: FUSE Drive.................. 13
7.21 Electrical Characteristics: Internal Temperature
Sensor...................................................................... 13
7.22 Electrical Characteristics: TS1, TS2, TS3, TS4 .... 13
7.23 Electrical Characteristics: PTC, PTCEN ............... 14
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
日期
修订版本
注释
2015 年 7 月
*
最初发布版本
2
版权 © 2015, Texas Instruments Incorporated
bq40z50-R1
www.ti.com.cn
ZHCSDZ9 –JULY 2015
5 说明（续）
bq40z50-R1 器件为主机系统提供最大的功率和电流，从而支持 Turbo 升压模式。 该器件还支持电池跳变点，从而
在预设的充电阈值状态向主机系统发送 BTP 中断信号。
bq40z50-R1 提供了基于软件的第 1 级和第 2 级安全保护，可防止出现过压、欠压、过流、短路、过载和过热情况
以及其他与电池组和电池相关的故障。
具有针对认证码密钥的安全内存的 SHA-1 认证能够识别真正的电池组。
这个紧凑的 32 导线 QFN 封装在尽可能地提供电池电量测量应用的功能性和安全性的同时，最大限度地降低解决
方案成本和智能电池的尺寸。
6 Pin Configuration and Functions
RSM Package
32-Pin VQFN with Exposed Thermal Pad
Top View
1
PBI
VC4
VC3
VC2
VC1
SRN
NC
PTCEN
2
3
PTC
LEDCNTLC
LEDCNTLB
LEDCNTLA
SMBC
4
5
6
7
8
21
20
19
18
17
SMBD
¯ ¯ ¯ ¯
SRP
DISP
Pin Functions
PIN NAME
NUMBER
TYPE(1)
DESCRIPTION
PBI
1
P
Power supply backup input pin
Sense voltage input pin for most positive cell, and balance current input for most positive
cell
VC4
VC3
VC2
VC1
2
3
4
5
IA
IA
IA
IA
Sense voltage input pin for second most positive cell, balance current input for second
most positive cell, and return balance current for most positive cell
Sense voltage input pin for third most positive cell, balance current input for third most
positive cell, and return balance current for second most positive cell
Sense voltage input pin for least positive cell, balance current input for least positive cell,
and return balance current for third most positive cell
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
SRN
NC
6
7
8
I
—
I
Not internally connected. Connect to VSS.
Analog input pin connected to the internal coulomb counter peripheral for integrating a
small voltage between SRP and SRN where SRP is the top of the sense resistor.
SRP
VSS
TS1
9
P
IA
IA
IA
IA
—
O
Device ground
10
11
12
13
14
15
Temperature sensor 1 thermistor input pin
Temperature sensor 2 thermistor input pin
Temperature sensor 3 thermistor input pin
Temperature sensor 4 thermistor input pin
Not internally connected
TS2
TS3
TS4
NC
BTP_INT
Battery Trip Point (BTP) interrupt output
(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output
Copyright © 2015, Texas Instruments Incorporated
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Pin Functions (continued)
PIN NAME
NUMBER
TYPE(1)
DESCRIPTION
Host system present input for removable battery pack or emergency system shutdown
input for embedded pack
PRES or SHUTDN
16
I
DISP
SMBD
SMBC
17
18
19
—
Display control for LEDs
SMBus data pin
I/OD
I/OD
SMBus clock pin
LED display segment that drives the external LEDs depending on the firmware
configuration
LEDCNTLA
LEDCNTLB
20
21
—
—
LED display segment that drives the external LEDs depending on the firmware
configuration
LED display segment that drives the external LEDs depending on the firmware
configuration
LEDCNTLC
PTC
22
23
24
—
IA
IA
Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to VSS.
Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect both PTC
and PTCEN to VSS.
PTCEN
FUSE
VCC
PACK
DSG
NC
25
26
27
28
29
30
31
32
O
P
Fuse drive output pin
Secondary power supply input
Pack sense input pin
IA
O
—
O
O
P
NMOS Discharge FET drive output pin
Not internally connected
PCHG
CHG
BAT
PMOS Precharge FET drive output pin
NMOS Charge FET drive output pin
Primary power supply input pin
4
Copyright © 2015, Texas Instruments Incorporated
bq40z50-R1
www.ti.com.cn
ZHCSDZ9 –JULY 2015
VC4
CDEN4
CDEN3
BAT
3.1 V
VCC
PACK
VC3
+
–
BATDET
ENVCC
PACK
Detector
VC2
ADC Mux
ADC
PACKDET
PBI
SHUTDOWN
Shutdown
Latch
CDEN2
Reference
System
1.8 V
Domain
SHOUT
VC1
ENBAT
BAT
Control
CDEN1
Power Supply Control
Cell Balancing
VCC
CHGEN
BAT
2 kΩ
CHG
CHG
Pump
8 kΩ
PCHG
2 kΩ
CHGOFF
PCHGEN
Pre-Charge Drive
PACK
BAT
DSGEN
ZVCD
BAT
2 kΩ
DSG
DSG
CHGEN
Pump
BAT
CHG
Pump
VCC
DSGOFF
ZVCHGEN
CHG, DSG Drive
Zero-Volt Charge
Figure 1. Pin Equivalent Diagram 1
Copyright © 2015, Texas Instruments Incorporated
5
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ZHCSDZ9 –JULY 2015
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1.8 V
ADTHx
BAT
FUSEWKPUP
18 kΩ
2 kΩ
ADC Mux
ADC
150 nA
TS1,2,3,4
FUSEEN
2 kΩ
FUSE
1.8 V
1.8 V
100 kΩ
FUSEDIG
RCWKPUP
RCPUP
FUSE Drive
1 kΩ
RCIN
RCOUT
100 kΩ
SMBCIN
SMBC
Thermistor Inputs
SMBCOUT
SMBCEN
1 MΩ
PBI
100 kΩ
SMBDIN
SMBD
RHOEN
SMBDOUT
10 kΩ
SMBDEN
1 MΩ
PRES
SMBus Interface
RHOUT
100 kΩ
RHIN
High-Voltage GPIO
PTCEN
BAT
30 kΩ
PTCDIG
PTC
Comparator
PTC
Counter
PTC
PTC
Latch
RLOEN
290 nA
10 kΩ
LED1, 2, 3
22.5 mA
RLOUT
100 kΩ
RLIN
PTC Detection
LED Drive
Figure 2. Pin Equivalent Diagram 2
6
Copyright © 2015, Texas Instruments Incorporated
bq40z50-R1
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ZHCSDZ9 –JULY 2015
10 Ω
VC4
CHANx
Φ
2
3.8 kΩ
1.9 MΩ
0.1 MΩ
SRP
SRN
Φ
1
ADC Mux
ADC
Comparator
Φ
2
1
Array
3.8 kΩ
Φ
Φ
2
10 Ω
100 Ω
PACK
Φ
1
Coulomb
Counter
Φ
2
1
CHANx
100 Ω
Φ
1.9 MΩ
0.1 MΩ
ADC Mux
ADC
OCD, SCC, SCD Comparators and Coulomb Counter
VC4 and PACK Dividers
Figure 3. Pin Equivalent Diagram 3
7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage range,
BAT, VCC, PBI
VCC
–0.3
30
V
PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP
TS1, TS2, TS3, TS4
–0.3
–0.3
–0.3
–0.3
30
V
V
V
V
VREG + 0.3
VBAT + 0.3
0.3
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
SRP, SRN
VC3 + 8.5, or
VSS + 30
VC4
VC3 – 0.3
VC2 – 0.3
VC1 – 0.3
VSS – 0.3
V
V
V
V
Input voltage range,
VIN
VC2 + 8.5, or
VSS + 30
VC3
VC1 + 8.5, or
VSS + 30
VC2
VC1
VSS + 8.5, or
VSS + 30
CHG, DSG
–0.3
–0.3
32
30
Output voltage range,
VO
PCHG, FUSE
V
Maximum VSS current, ISS
50
mA
°C
°C
Storage temperature, TSTG
–65
150
300
Lead temperature (soldering, 10 s), TSOLDER
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2015, Texas Instruments Incorporated
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7.3 Recommended Operating Conditions
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
2.2
NOM
MAX
26
UNIT
VCC
Supply voltage
BAT, VCC, PBI
V
V
V
VSHUTDOWN–
Shutdown voltage
VPACK < VSHUTDOWN–
VPACK > VSHUTDOWN– + VHYS
1.8
2.0
2.2
VSHUTDOWN+ Start-up voltage
2.05
2.25
2.45
Shutdown voltage
hysteresis
VHYS
VSHUTDOWN+ – VSHUTDOWN–
250
mV
PACK, SMBC, SMBD, PRES, BTP_IN, DISP
26
VREG
TS1, TS2, TS3, TS4
PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC
VBAT
SRP, SRN
VC4
–0.2
VVC3
VVC2
VVC1
VVSS
0.2
VIN
Input voltage range
V
VVC3 + 5
VVC2 + 5
VVC1 + 5
VVSS + 5
VC3
VC2
VC1
Output voltage
range
VO
CHG, DSG, PCHG, FUSE
26
V
External PBI
capacitor
CPBI
TOPR
2.2
µF
°C
Operating
temperature
–40
85
7.4 Thermal Information
RSM (QFN)
32 PINS
47.4
THERMAL METRIC(1)
UNIT
RθJA, High K
RθJC(top)
RθJB
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
40.3
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
0.8
ψJB
14.4
RθJC(bottom)
3.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: Supply Current
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 20 V (unless otherwise noted)
PARAMETER
NORMAL mode
TEST CONDITIONS
CHG on. DSG on, no Flash write
MIN
TYP
336
75
MAX
UNIT
INORMAL
ISLEEP
µA
CHG off, DSG on, no SBS communication
CHG off, DSG off, no SBS communication
SLEEP mode
µA
µA
52
ISHUTDOWN
SHUTDOWN mode
1.6
7.6 Electrical Characteristics: Power Supply Control
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BAT to VCC
VSWITCHOVER–
switchover
voltage
VBAT < VSWITCHOVER–
1.95
2.1
2.2
V
8
Copyright © 2015, Texas Instruments Incorporated
bq40z50-R1
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ZHCSDZ9 –JULY 2015
Electrical Characteristics: Power Supply Control (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC to BAT
VSWITCHOVER+
switchover
voltage
VBAT > VSWITCHOVER– + VHYS
2.9
3.1
3.25
V
Switchover
voltage hysteresis
VHYS
VSWITCHOVER+ – VSWITCHOVER–
1000
mV
µA
kΩ
BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V
PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V
1
1
Input Leakage
current
ILKG
BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK
= 0 V, PBI = 25 V
1
Internal pulldown
resistance
RPD
PACK
30
40
50
7.7 Electrical Characteristics: AFE Power-On Reset
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Negative-going
voltage input
VREGIT–
VHYS
VREG
1.51
1.55
1.59
V
Power-on reset
hysteresis
VREGIT+ – VREGIT–
70
100
300
130
400
mV
µs
Power-on reset
time
tRST
200
7.8 Electrical Characteristics: AFE Watchdog Reset and Wake Timer
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
372
TYP
500
MAX
628
UNIT
tWDT = 500
tWDT = 1000
tWDT = 2000
tWDT = 4000
tWAKE = 250
tWAKE = 500
tWAKE = 1000
tWAKE = 512
744
1000
2000
4000
250
1256
2512
5024
314
AFE watchdog
timeout
tWDT
ms
1488
2976
186
372
500
628
tWAKE
AFE wake timer
ms
ms
744
1000
2000
1256
2512
1488
FET off delay after
reset
tFETOFF
tFETOFF = 512
409
512
614
7.9 Electrical Characteristics: Current Wake Comparator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VWAKE = ±0.625 mV
MIN
±0.3
±0.6
±1.2
±2.4
TYP
±0.625
±1.25
±2.5
MAX
±0.9
±1.8
±3.6
±7.2
UNIT
VWAKE = ±1.25 mV
VWAKE = ±2.5 mV
VWAKE = ±5 mV
Wake voltage
threshold
VWAKE
mV
±5.0
Temperature drift
of VWAKE accuracy
VWAKE(DRIFT)
0.5%
°C
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Electrical Characteristics: Current Wake Comparator (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time from
application of
current to wake
interrupt
tWAKE
700
µs
Wake comparator
startup time
tWAKE(SU)
500
1000
µs
7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
BAT–VSS, PACK–VSS
MIN
TYP
MAX
0.2020
0.051
0.510
5
UNIT
0.1980 0.2000
K
Scaling factor
0.049
0.490
–0.2
0.050
0.500
—
VREF2
VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3
BAT–VSS, PACK–VSS
VIN
Input voltage range
Input leakage current
V
–0.2
20
VC1, VC2, VC3, VC4, cell balancing off, cell detach
detection off, ADC multiplexer off
ILKG
RCB
ICD
1
200
70
µA
Ω
Internal cell balance
resistance
RDS(ON) for internal FET switch at 2 V < VDS < 4 V
VCx > VSS + 0.8 V
Internal cell detach
check current
30
50
µA
7.11 Electrical Characteristics: SMBD, SMBC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SMBC, SMBD, VREG = 1.8 V
MIN
TYP
MAX
UNIT
V
VIH
Input voltage high
Input voltage low
Output low voltage
Input capacitance
Input leakage current
Pulldown resistance
1.3
VIL
SMBC, SMBD, VREG = 1.8 V
0.8
0.4
V
VOL
CIN
ILKG
RPD
SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA
V
5
pF
µA
MΩ
1
0.7
1.0
1.3
7.12 Electrical Characteristics: PRES, BTP_INT, DISP
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
High-level input
Low-level input
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
1.3
0.55
V
VBAT > 5.5 V, IOH = –0 µA
3.5
1.8
VOH
Output voltage high
V
VBAT > 5.5 V, IOH = –10 µA
IOL = 1.5 mA
VOL
CIN
Output voltage low
Input capacitance
Input leakage current
0.4
1
V
5
pF
µA
ILKG
Output reverse
resistance
RO
Between PRES or BTP_INT or DISP and PBI
8
kΩ
10
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7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
High-level input
Low-level input
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
1.45
0.55
V
VBAT
–
VOH
VOL
ISC
Output voltage high
Output voltage low
VBAT > 3.0 V, IOH = –22.5 mA
V
V
1.6
IOL = 1.5 mA
0.4
High level output
current protection
–30
–45
–6 0
mA
Low level output
current
IOL
VBAT > 3.0 V, VOH = 0.4 V
VBAT = VLEDCNTLx + 2.5 V
15.75
22.5
29.25
mA
Current matching
between LEDCNTLx
ILEDCNTLx
±1%
20
CIN
Input capacitance
pF
µA
ILKG
Input leakage current
1
Frequency of LED
pattern
fLEDCNTLx
124
Hz
7.14 Electrical Characteristics: Coulomb Counter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Input voltage range
TEST CONDITIONS
MIN
–0.1
TYP
MAX
0.1
UNIT
V
Full scale range
Integral nonlinearity(1)
Offset error
–VREF1/10
VREF1/10
±22.3
±10
V
16-bit, best fit over input voltage range
16-bit, Post-calibration
±5.2
±5
LSB
µV
Offset error drift
Gain error
15-bit + sign, Post-calibration
0.2
0.3
µV/°C
FSR
15-bit + sign, over input voltage range
15-bit + sign, over input voltage range
±0.2%
±0.8%
Gain error drift
150 PPM/°C
Effective input resistance
2.5
MΩ
(1) 1 LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71 µV
7.15 Electrical Characteristics: CC Digital Filter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Conversion time
Effective resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ms
Single conversion
Single conversion
250
15
Bits
7.16 Electrical Characteristics: ADC
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal reference (VREF1
External reference (VREG
VFS = VREF1 or VREG
MIN
–0.2
–0.2
–VFS
TYP
MAX
1
UNIT
)
Input voltage range
V
)
0.8 x VREG
VFS
Full scale range
V
16-bit, best fit, –0.1 V to 0.8 x VREF1
16-bit, best fit, –0.2 V to –0.1 V
±6.6
Integral nonlinearity(1)
LSB
±13.1
(1) 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms)
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Electrical Characteristics: ADC (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Offset error(2)
TEST CONDITIONS
16-bit, Post-calibration, VFS = VREF1
16-bit, Post-calibration, VFS = VREF1
16-bit, –0.1 V to 0.8 x VFS
MIN
TYP
±67
MAX
±157
3
UNIT
µV
Offset error drift
Gain error
0.6
µV/°C
FSR
±0.2%
±0.8%
Gain error drift
16-bit, –0.1 V to 0.8 x VFS
150 PPM/°C
Effective input resistance
8
MΩ
(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC
multiplexer scaling factor (K)).
7.17 Electrical Characteristics: ADC Digital Filter
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
31.25
15.63
7.81
MAX
UNIT
Single conversion
Single conversion
Single conversion
Single conversion
No missing codes
Conversion time
ms
1.95
Resolution
16
14
13
11
9
Bits
Bits
With sign, tCONV = 31.25 ms
With sign, tCONV = 15.63 ms
With sign, tCONV = 7.81 ms
With sign, tCONV = 1.95 ms
15
14
12
10
Effective resolution
7.18 Electrical Characteristics: CHG, DSG FET Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between PACK and DSG
2.133
2.333
2.433
Output voltage
ratio
—
RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V,
10 MΩ between BAT and CHG
2.133
10.5
10.5
2.333
11.5
11.5
2.433
12
VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
PACK and DSG, VBAT = 18 V
Output voltage,
CHG and DSG on
V(FETON)
V
V
VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between
BAT and CHG, VBAT = 18 V
12
VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and
DSG
–0.4
–0.4
0.4
0.4
Output voltage,
CHG and DSG off
V(FETOFF)
VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG
VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL
=
4.7 nF between DSG and PACK, 5.1 kΩ between DSG
and CL, 10 MΩ between PACK and DSG
200
200
40
500
500
300
200
tR
Rise time
Fall time
µs
µs
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL
4.7 nF between CHG and BAT, 5.1 kΩ between CHG
and CL, 10 MΩ between BAT and CHG
=
VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF
between DSG and PACK, 5.1 kΩ between DSG and CL,
10 MΩ between PACK and DSG
tF
VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7
nF between CHG and BAT, 5.1 kΩ between CHG and
CL, 10 MΩ between BAT and CHG
40
12
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7.19 Electrical Characteristics: PCHG FET Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage,
PCHG on
VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
V(FETON)
6
7
8
V
Output voltage,
PCHG off
VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and
PCHG
V(FETOFF)
–0.4
0.4
V
VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
=
tR
Rise time
Fall time
40
40
200
µs
VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥ 8 V, CL
4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG
and CL, 10 MΩ between VCC and CHG
=
tF
200
µs
7.20 Electrical Characteristics: FUSE Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
8.65
VBAT
2.5
UNIT
V
BAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA
6
VBAT – 0.1
1.5
7
Output voltage
high
VOH
V
VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA
VIH
High-level input
2.0
V
Internal pullup
current
IAFEFUSE(PU)
VBAT ≥ 8 V, VAFEFUSE = VSS
150
330
3.2
nA
RAFEFUSE
CIN
Output impedance
Input capacitance
2
2.6
5
kΩ
pF
Fuse trip detection
delay
tDELAY
tRISE
128
256
20
µs
µs
Fuse output rise
time
VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V
5
7.21 Electrical Characteristics: Internal Temperature Sensor
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal
VTEMPP
–1.9
–2.0
–2.1
temperature
sensor voltage
drift
VTEMP
mV/°C
VTEMPP – VTEMPN, assured by design
0.177
0.178
0.179
7.22 Electrical Characteristics: TS1, TS2, TS3, TS4
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TS1, TS2, TS3, TS4, VBIAS = VREF1
TS1, TS2, TS3, TS4, VBIAS = VREG
MIN
–0.2
–0.2
TYP
MAX
0.8 x VREF1
0.8 x VREG
UNIT
Input voltage
range
VIN
V
Internal pullup
resistance
RNTC(PU)
TS1, TS2, TS3, TS4
14.4
18
21.6
kΩ
Resistance drift
over
RNTC(DRIFT)
TS1, TS2, TS3, TS4
–360
–280
–200 PPM/°C
temperature
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7.23 Electrical Characteristics: PTC, PTCEN
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.95
890
350
145
UNIT
MΩ
mV
nA
PTC trip
resistance
RPTC(TRIP)
VPTC(TRIP)
IPTC
1.2
2.5
PTC trip voltage
VPTC(TRIP) = VPTCEN – VPTC
200
200
40
500
290
80
Internal PTC
current bias
TA = –40°C to 110°C
TA = –40°C to 110°C
tPTC(DELAY)
PTC delay time
ms
7.24 Electrical Characteristics: Internal 1.8-V LDO
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Regulator voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREG
1.6
1.8
2.0
V
Regulator output
over temperature
ΔVO(TEMP)
ΔVO(LINE)
ΔVREG/ΔTA, IREG = 10 mA
±0.25%
Line regulation
ΔVREG/ΔVBAT, VBAT = 10 mA
–0 .6%
–1.5%
0.5%
1.5%
ΔVO(LOAD) Load regulation
ΔVREG/ΔIREG, IREG = 0 mA to 10 mA
Regulator output
current limit
IREG
VREG = 0.9 x VREG(NOM), VIN > 2.2 V
VREG = 0 x VREG(NOM)
20
25
mA
mA
dB
Regulator short-
ISC
40
40
55
circuit current limit
Power supply
PSRRREG
ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz
rejection ratio
Slew rate
VSLEW
enhancement
VREG
1.58
1.65
V
voltage threshold
7.25 Electrical Characteristics: High-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
16.78
MAX
UNIT
fHFO
Operating frequency
MHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–2.5%
–3.5%
±0.25%
±0.25%
2.5%
3.5%
fHFO(ERR)
Frequency error
TA = –20°C to 85°C, oscillator frequency within
+/–3% of nominal
4
ms
µs
tHFO(SU)
Start-up time
oscillator frequency within +/–3% of nominal
100
7.26 Electrical Characteristics: Low-Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Operating frequency
TEST CONDITIONS
MIN
TYP
262.144
±0.25%
±0.25
MAX
UNIT
fLFO
kHz
TA = –20°C to 70°C, includes frequency drift
TA = –40°C to 85°C, includes frequency drift
–1.5%
–2.5
1.5%
2.5
fLFO(ERR)
Frequency error
Failure detection
frequency
fLFO(FAIL)
30
80
100
kHz
14
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7.27 Electrical Characteristics: Voltage Reference 1
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF1
TA = 25°C, after trim
1.21
1.215
1.22
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF1(DRIFT)
PPM/°C
7.28 Electrical Characteristics: Voltage Reference 2
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal reference
voltage
VREF2
TA = 25°C, after trim
1.22
1.225
1.23
V
TA = 0°C to 60°C, after trim
TA = –40°C to 85°C, after trim
±50
±80
Internal reference
voltage drift
VREF2(DRIFT)
PPM/°C
7.29 Electrical Characteristics: Instruction Flash
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
Data retention
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
Years
Flash programming
write cycles
1000
Cycles
µs
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
tMASSERASE
tPAGEERASE
IFLASHREAD
IFLASHWRITE
IFLASHERASE
Mass-erase time
Page-erase time
Flash-read current
Flash-write current
Flash-erase current
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
2
ms
ms
mA
mA
mA
5
15
7.30 Electrical Characteristics: Data Flash
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Data retention
10
Years
Flash programming
write cycles
20000
Cycles
µs
Word programming
time
tPROGWORD
TA = –40°C to 85°C
40
tMASSERASE
tPAGEERASE
IFLASHREAD
IFLASHWRITE
IFLASHERASE
Mass-erase time
Page-erase time
Flash-read current
Flash-write current
Flash-erase current
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
40
40
1
ms
ms
mA
mA
mA
5
15
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7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–16.6
–100
OCD detection
threshold voltage range
VOCD
mV
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
–8.3
–50
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–5.56
–2.78
OCD detection
threshold voltage
program step
ΔVOCD
mV
mV
mV
mV
mV
mV
mV
VOCD = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
44.4
22.2
200
100
SCC detection
threshold voltage range
VSCC
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
22.2
11.1
SCC detection
threshold voltage
program step
ΔVSCC
VSCD1
ΔVSCD1
VSCD2
ΔVSCD2
VSCC = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–44.4
–22.2
–200
–100
SCD1 detection
threshold voltage range
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
–11.1
SCD1 detection
threshold voltage
program step
VSCD1 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–44.4
–22.2
–200
–100
SCD2 detection
threshold voltage range
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 1
–22.2
–11.1
SCD2 detection
threshold voltage
program step
VSCD2 = VSRP – VSRN, AFE PROTECTION
CONTROL[RSNS] = 0
OCD, SCC, and SCDx
offset error
VOFFSET
VSCALE
Post-trim
–2.5
2.5
mV
—
No trim
–10%
–5%
10%
5%
OCD, SCC, and SCDx
scale error
Post-trim
7.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
OCD detection
delay time
tOCD
1
31
ms
OCD detection
delay time
program step
ΔtOCD
2
ms
µs
µs
SCC detection
delay time
tSCC
0
915
SCC detection
delay time
ΔtSCC
61
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
AFE PROTECTION CONTROL[SCDDx2] = 1
0
0
915
SCD1 detection
delay time
tSCD1
µs
1850
16
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Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
SCD1 detection
delay time
program step
AFE PROTECTION CONTROL[SCDDx2] = 0
AFE PROTECTION CONTROL[SCDDx2] = 1
61
ΔtSCD1
µs
121
AFE PROTECTION CONTROL[SCDDx2] = 0
AFE PROTECTION CONTROL[SCDDx2] = 1
AFE PROTECTION CONTROL[SCDDx2] = 0
0
0
458
915
SCD2 detection
delay time
tSCD2
µs
SCD2 detection
delay time
program step
30.5
61
ΔtSCD2
tDETECT
tACC
µs
µs
AFE PROTECTION CONTROL[SCDDx2] = 1
Current fault
detect time
VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2,
VSRP – VSRN = VT + 3 mV for SCC
160
Current fault
delay time
accuracy
Max delay setting
–10%
10%
7.33 Timing Requirements: SMBus
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
SMBus operating
frequency
fSMB
SLAVE mode, SMBC 50% duty cycle
10
100
kHz
SMBus master clock
frequency
fMAS
MASTER mode, no clock low slave extend
51.2
kHz
µs
Bus free time between start
and stop
tBUF
4.7
4.0
Hold time after (repeated)
start
tHD(START)
µs
tSU(START)
tSU(STOP)
tHD(DATA)
tSU(DATA)
tTIMEOUT
tLOW
Repeated start setup time
Stop setup time
4.7
4.0
300
250
25
µs
µs
ns
ns
ms
µs
µs
ns
ns
Data hold time
Data setup time
Error signal detect time
Clock low period
Clock high period
Clock rise time
35
4.7
4.0
tHIGH
50
1000
300
tR
10% to 90%
90% to 10%
tF
Clock fall time
Cumulative clock low slave
extend time
tLOW(SEXT)
tLOW(MEXT)
25
10
ms
ms
Cumulative clock low
master extend time
7.34 Timing Requirements: SMBus XL
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
fSMBXL
tBUF
SMBus XL operating
frequency
SLAVE mode
40
400
kHz
Bus free time between start
and stop
4.7
4.0
µs
µs
tHD(START)
Hold time after (repeated)
start
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Timing Requirements: SMBus XL (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
2.2 V to 26 V (unless otherwise noted)
MIN
4.7
4.0
5
NOM
MAX
UNIT
µs
tSU(START)
tSU(STOP)
tTIMEOUT
tLOW
Repeated start setup time
Stop setup time
µs
Error signal detect time
Clock low period
20
20
20
ms
µs
tHIGH
Clock high period
µs
TtR
TtF
TtF
TtR
TtHIGH
T
tSU(STOP)p
tHD(START)
TtBUFT
TtLOWT
SMBC
SMBD
SMBC
SMBD
P
S
tHD(DATA)
T
TtSU(DATA)
Start and Stop Condition
Wait and Hold Condition
tSU(START)
T
TtTIMEOUT
SMBC
SMBD
SMBC
SMBD
S
Repeated Start Condition
Timeout Condition
Figure 4. SMBus Timing Diagram
18
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7.35 Typical Characteristics
0.15
0.10
8.0
6.0
Max CC Offset Error
Min CC Offset Error
4.0
0.05
2.0
0.00
0.0
±2.0
±4.0
±6.0
±8.0
±0.05
±0.10
±0.15
Max ADC Offset Error
Min ADC Offset Error
0
20
40
60
80
100
120
±40
±20
0
20
40
60 80 100
120
±40
±20
Temperature (C)
Temperature (C)
C001
C003
Figure 5. CC Offset Error vs. Temperature
Figure 6. ADC Offset Error vs. Temperature
1.24
1.23
1.22
1.21
1.20
264
262
260
258
256
254
252
250
0
20
40
60
80
100
0
20
40
60
80
100
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C006
C007
Figure 7. Reference Voltage vs. Temperature
Figure 8. Low-Frequency Oscillator vs. Temperature
16.9
16.8
16.7
16.6
±24.6
±24.8
±25.0
±25.2
±25.4
±25.6
±25.8
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C008
C009
Threshold setting is 25 mV.
Figure 9. High-Frequency Oscillator vs. Temperature
Figure 10. Overcurrent Discharge Protection Threshold vs.
Temperature
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Typical Characteristics (continued)
87.4
±86.0
±86.2
±86.4
±86.6
±86.8
±87.0
±87.2
87.2
87.0
86.8
86.6
86.4
86.2
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C010
C011
Threshold setting is 25 mV.
Threshold setting is –88.85 mV.
Figure 11. Short Circuit Charge Protection Threshold vs.
Temperature
Figure 12. Short Circuit Discharge 1 Protection Threshold
vs. Temperature
11.00
10.95
10.90
10.85
10.80
10.75
10.70
±172.9
±173.0
±173.1
±173.2
±173.3
±173.4
±173.5
±173.6
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C012
C013
Threshold setting is –177.7 mV.
Threshold setting is 11 ms.
Figure 14. Overcurrent Delay Time vs. Temperature
Figure 13. Short Circuit Discharge 2 Protection Threshold
vs. Temperature
452
450
448
446
444
442
440
438
436
434
432
480
460
440
420
400
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C014
C015
Threshold setting is 465 µs.
Threshold setting is 465 µs (including internal delay).
Figure 15. Short Circuit Charge Current Delay Time vs.
Temperature
Figure 16. Short Circuit Discharge 1 Delay Time vs.
Temperature
20
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Typical Characteristics (continued)
2.4984
2.49835
2.4983
2.49825
2.4982
2.49815
2.4981
2.49805
2.498
3.49825
3.4982
3.49815
3.4981
3.49805
3.498
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C016
C017
This is the VCELL average for single cell.
Figure 17. VCELL Measurement at 2.5-V vs. Temperature
Figure 18. VCELL Measurement at 3.5-V vs. Temperature
4.24805
99.25
4.248
4.24795
4.2479
99.20
99.15
99.10
99.05
99.00
4.24785
4.2478
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C018
C019
This is the VCELL average for single cell.
ISET = 100 mA
Figure 19. VCELL Measurement at 4.25-V vs. Temperature
Figure 20. I measured vs. Temperature
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8 Detailed Description
8.1 Overview
The bq40z50-R1 device, incorporating patented Impedance Track™ technology, provides cell balancing while
charging or at rest. This fully integrated, single-chip, pack-based solution provides a rich array of features for gas
gauging, protection, and authentication for 1-series, 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer
battery packs, including a diagnostic lifetime data monitor and black box recorder.
8.2 Functional Block Diagram
Cell, Stack,
Pack
Voltage
High Side
N-CH FET
Drive
Cell
Balancing
Cell Detach
Detection
Power Mode
Control
P-CH
FET Drive
Zero Volt
Charge
Control
PTCEN
PTC
Wake
Comparator
Power On
Reset
PTC
Overtemp
Short Circuit
Comparator
FUSE
Control
FUSE
SRP
SRN
BTP_INT
Over
Current
Comparator
High
Voltage
I/O
Voltage
Reference2
/PRES or /SHUTDN
/DISP
Random
Number
Generator
Watchdog
Timer
NTC Bias
TS1
TS2
TS3
TS4
LEDCNTLC
LEDCNTLB
LEDCNTLA
Internal
Temp
Sensor
LED Display
Drive I/O
Voltage
Reference1
ADC MUX
AFE Control
Low
Frequency
Oscillator
SBS High
Voltage
Translation
SMBD
SMBC
ADC/CC
FRONTEND
1.8V LDO
Regulator
AFE COM
Engine
High
Frequency
Oscillator
Low Voltage
I/O
I/O
I/O &
Interrupt
Controller
ADC/CC
Digital Filter
Timers&
PWM
AFE COM
Engine
SBS COM
Engine
Data (8bit)
DMAddr (16bit)
bqBMP
CPU
PMInstr
(8bit)
PMAddr
(16bit)
Program
Flash
EEPROM
Data Flash
EEPROM
Data
SRAM
22
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8.3 Feature Description
8.3.1 Primary (1st Level) Safety Features
The bq40z50-R1 supports a wide range of battery and system protection features that can easily be configured.
See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each protection
function.
The primary safety features include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Cell Overvoltage Protection
Cell Undervoltage Protection
Cell Undervoltage Protection Compensated
Overcurrent in Charge Protection
Overcurrent in Discharge Protection
Overload in Discharge Protection
Short Circuit in Charge Protection
Short Circuit in Discharge Protection
Overtemperature in Charge Protection
Overtemperature in Discharge Protection
Undertemperature in Charge Protection
Undertemperature in Discharge Protection
Overtemperature FET protection
Precharge Timeout Protection
Host Watchdog Timeout Protection
Fast Charge Timeout Protection
Overcharge Protection
Overcharging Voltage Protection
Overcharging Current Protection
Over Precharge Current Protection
8.3.2 Secondary (2nd Level) Safety Features
The secondary safety features of the bq40z50-R1 can be used to indicate more serious faults via the FUSE pin.
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each
protection function.
The secondary safety features provide protection against:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Safety Overvoltage Permanent Failure
Safety Undervoltage Permanent Failure
Safety Overtemperature Permanent Failure
Safety FET Overtemperature Permanent Failure
Qmax Imbalance Permanent Failure
Impedance Imbalance Permanent Failure
Capacity Degradation Permanent Failure
Cell Balancing Permanent Failure
Fuse Failure Permanent Failure
PTC Permanent Failure
Voltage Imbalance at Rest Permanent Failure
Voltage Imbalance Active Permanent Failure
Charge FET Permanent Failure
Discharge FET Permanent Failure
AFE Register Permanent Failure
AFE Communication Permanent Failure
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Feature Description (continued)
•
•
•
•
•
Second Level Protector Permanent Failure
Instruction Flash Checksum Permanent Failure
Open Cell Connection Permanent Failure
Data Flash Permanent Failure
Open Thermistor Permanent Failure
8.3.3 Charge Control Features
The bq40z50-R1 charge control features include:
•
•
•
•
Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active
temperature range
Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-
ranges and allows for varying the charging current according to the cell voltage
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts
Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a
voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to
be active. This prevents fully charged cells from overcharging and causing excessive degradation and also
increases the usable pack energy by preventing premature charge termination.
•
•
•
Supports pre-charging/zero-volt charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicates charge status via charge and discharge alarms
8.3.4 Gas Gauging
The bq40z50-R1 uses the Impedance Track algorithm to measure and calculate the available capacity in battery
cells. The bq40z50-R1 accumulates a measure of charge and discharge currents and compensates the charge
current measurement for the temperature and state-of-charge of the battery. The bq40z50-R1 estimates self-
discharge of the battery and also adjusts the self-discharge estimation based on temperature. The device also
has TURBO BOOST mode support, which enables the bq40z50-R1 to provide the necessary data for the MCU to
determine what level of peak power consumption can be applied without causing a system reset or transient
battery voltage level spike to trigger termination flags. See the bq40z50-R1 Technical Reference Manual
(SLUUBC1) for further details.
8.3.5 Configuration
8.3.5.1 Oscillator Function
The bq40z50-R1 fully integrates the system oscillators and does not require any external components to support
this feature.
8.3.5.2 System Present Operation
The bq40z50-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external
system, the bq40z50-R1 detects this as system present.
8.3.5.3 Emergency Shutdown
For battery maintenance, the emergency shutdown feature enables a push button action connecting the
SHUTDN pin to shutdown an embedded battery pack system before removing the battery. A high-to-low
transition of the SHUTDN pin signals the bq40z50-R1 to turn off both CHG and DSG FETs, disconnecting the
power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by
another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached.
8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration
In a 1-series cell configuration, VC4 is shorted to VC, VC2 and VC1. In a 2-series cell configuration, VC4 is
shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.
24
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Feature Description (continued)
8.3.5.5 Cell Balancing
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing
mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
8.3.6 Battery Parameter Measurements
8.3.6.1 Charge and Discharge Counting
The bq40z50-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and
a second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures
bipolar signals from –0.1 V to 0.1 V. The bq40z50-R1 detects charge activity when VSR = V(SRP) – V(SRN) is
positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq40z50-R1 continuously integrates
the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.
8.3.7 Battery Trip Point (BTP)
Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has
depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based
thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the
OperationStatus[BTP_INT] on the basis of RemainingCapacity().
An internal weak pull-up is applied when the BTP feature is active. Depending on the system design, an external
pull-up may be required to put on the BTP_INT pin. See Electrical Characteristics: PRES, BTP_INT, DISP for
details.
8.3.8 Lifetime Data Logging Features
The bq40z50-R1 offers lifetime data logging for several critical battery parameters. The following parameters are
updated every 10 hours if a difference is detected between values in RAM and data flash:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum and Minimum Cell Voltages
Maximum Delta Cell Voltage
Maximum Charge Current
Maximum Discharge Current
Maximum Average Discharge Current
Maximum Average Discharge Power
Maximum and Minimum Cell Temperature
Maximum Delta Cell Temperature
Maximum and Minimum Internal Sensor Temperature
Maximum FET Temperature
Number of Safety Events Occurrences and the Last Cycle of the Occurrence
Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination
Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates
Number of Shutdown Events
Cell Balancing Time for Each Cell
(This data is updated every 2 hours if a difference is detected.)
Total FW Runtime and Time Spent in Each Temperature Range
(This data is updated every 2 hours if a difference is detected.)
•
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Feature Description (continued)
8.3.9 Authentication
The bq40z50-R1 supports authentication by the host using SHA-1.
8.3.10 LED Display
The bq40z50-R1 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a
permanent fail (PF) error code indication.
8.3.11 Voltage
The bq40z50-R1 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the
bq40z50-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate
the impedance of the cell for the Impedance Track gas gauging.
8.3.12 Current
The bq40z50-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 1-mΩ to 3-mΩ typ. sense resistor.
8.3.13 Temperature
The bq40z50-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five
temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which use a different thermistor profile.
8.3.14 Communications
The bq40z50-R1 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS
specification.
8.3.14.1 SMBus On and Off State
The bq40z50-R1 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing
this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within
1 ms.
8.3.14.2 SBS Commands
See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for further details.
8.4 Device Functional Modes
The bq40z50-R1 supports three power modes to reduce power consumption:
•
In NORMAL mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data
updates in 250-ms intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage.
•
In SLEEP mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data
updates in adjustable time intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage.
The bq40z50-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is
detected.
•
In SHUTDOWN mode, the bq40z50-R1 is completely disabled.
26
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq40z50-R1 is a gas gauge with primary protection support, and that can be used with a 1-series to 4-series
Li-Ion/Li Polymer battery pack. To implement and design a comprehensive set of parameters for a specific
battery pack, users need the Battery Management Studio (bqSTUDIO) graphical user-interface tool installed on a
PC during development. The firmware installed on the bqSTUDIO tool has default values for this product, which
are summarized in the bq40z50-R1 Technical Reference Manual (SLUUBC1). Using the bqSTUDIO tool, these
default values can be changed to cater to specific application requirements during development once the system
parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,
configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as
the "golden image."
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9.2 Typical Applications
4P
9
EP
1
1
1
1
4
6
3
5
2
1
1
1
1
1
1
1
1
2
3
4
1
1
1
5
1
1
33
32
31
30
29
28
27
26
25
PWPD
BAT
9
10
11
12
13
14
15
16
VSS
TS1
CHG
PCHG
NC
TS2
TS3
1
TS4
DSG
PACK
VCC
1
5
NC
BTP_INT
PRESorSHUTDN
4
1
1
FUSE
3
2
1
3
2
MM3ZxxVyC
MM3ZxxVyC
MM3ZxxVyC
2
GND SID2E
GND SIDE
1
1
SMBD
SMBC
SMBC
SMBD
1
1
7
6
1
1
CHGND
1
1
2
1
1
GND SIDE
2
GND SIDE
Figure 21. Application Schematic
28
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Typical Applications (continued)
9.2.1 Design Requirements
Table 1 shows the default settings for the main parameters. Use the bqSTUDIO tool to update the settings to
meet the specific application or battery pack configuration requirements.
The device should be calibrated before any gauging test. Follow the bqSTUDIO Calibration page to calibrate the
device, and use the bqSTUDIO Chemistry page to update the match chemistry profile to the device.
Table 1. Design Parameters
DESIGN PARAMETER
Cell Configuration
EXAMPLE
3s1p (3-series with 1 Parallel)(1)
Design Capacity
4400 mAh
Device Chemistry
1210 (LiCoO2/graphitized carbon)
Cell Overvoltage at Standard Temperature
Cell Undervoltage
4300 mV
2500 mV
Shutdown Voltage
2300 mV
Overcurrent in CHARGE Mode
Overcurrent in DISCHARGE Mode
Short Circuit in CHARGE Mode
Short Circuit in DISCHARGE Mode
Safety Overvoltage
6000 mA
–6000 mA
0.1 V/Rsense across SRP, SRN
0.1 V/Rsense across SRP, SRN
4500 mV
Cell Balancing
Disabled
Internal and External Temperature Sensor
Undertemperature Charging
Undertemperature Discharging
BROADCAST Mode
External Temperature Sensor is used.
0°C
0°C
Disabled
Disabled
Battery Trip Point (BTP) with active high interrupt
(1) When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to the
PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the bq40z50-R1 Technical Reference Manual
[SLUUBC1] for details) before removing the charger connection.
9.2.2 Detailed Design Procedure
9.2.2.1 High-Current Path
The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the
pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the
sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are
placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge.
9.2.2.1.1 Protection FETs
Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a
good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the
gate drive voltage is 8 V.
If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account
for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and
maximum power dissipation is (Vcharger – Vbat)2/R1.
The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source
to ensure they are turned off if the gate drive is open.
Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation
if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must
be designed to be as short and wide as possible. Ensure that the voltage rating of both C1 and C2 are adequate
to hold off the applied voltage if one of the capacitors becomes shorted.
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Figure 22. bq40z50-R1 Protection FETs
9.2.2.1.2 Chemical Fuse
The chemical fuse (Dexerials, Uchihashi, and so forth) is ignited under command from either the bq294700
secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive
voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse,
causing it to ignite and open permanently.
It is important to carefully review the fuse specifications and match the required ignition current to that available
from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device.
The fuse control circuit is discussed in detail in FUSE Circuitry.
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Figure 23. FUSE Circuit
9.2.2.1.3 Lithium-Ion Cell Connections
The important part to remember about the cell connections is that high current flows through the top and bottom
connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid
any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the
Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5
pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the
bq40z50-R1 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an
undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.
Figure 24. Lithium-Ion Cell Connections
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9.2.2.1.4 Sense Resistor
As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense
resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement
drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and
short-circuit ranges of the bq40z50-R1. Select the smallest value possible to minimize the negative voltage
generated on the bq40z50-R1 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V.
Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-
mΩ to 3-mΩ sense resistor.
The ground scheme of bq40z50-R1 is different from the older generation devices. In previous devices, the device
ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq40z50-R1,
however, connects the low-current ground on the SRP side of the Rsense resistor pad, close to the battery 1N
terminal (see Lithium-Ion Cell Connections). This is because the bq40z50-R1 has one less VC pin (a ground
reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to
SRP.
Figure 25. Sense Resistor
9.2.2.1.5 ESD Mitigation
A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the
mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack
if one of the capacitors becomes shorted.
Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.
9.2.2.2 Gas Gauge Circuit
The Gas Gauge Circuit includes the bq40z50-R1 and its peripheral components. These components are divided
into the following groups: Differential Low-Pass Filter, PBI, System Present, SMBus Communication, FUSE
circuit, and LED.
9.2.2.2.1 Coulomb-Counting Interface
The bq40z50-R1 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the
sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP
and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering, if
required for your circuit.
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Figure 26. Differential Filter
9.2.2.2.2 Power Supply Decoupling and PBI
The bq40z50-R1 has an internal LDO that is internally compensated and does not require an external decoupling
capacitor.
The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A
standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27.
Figure 27. Power Supply Decoupling
9.2.2.2.3 System Present
The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from
the system. In the host system, this pin is grounded. The PRES pin of the bq40z50-R1 is occasionally sampled
to test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs
sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ
or lower to insure that the test pulse is lower than the VIL limit. The pull-up current source is typically 10 µA to
20 µA.
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Figure 28. System Present Pull-Down Resistor
Because the System Present signal is part of the pack connector interface to the outside world, it must be
protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin
reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible
that the System Present signal may short to PACK+, then R28 and D4 must be included for high-voltage
protection.
Figure 29. System Present ESD and Short Protection
9.2.2.2.4 SMBus Communication
The SMBus clock and data pins have integrated high-voltage ESD protection circuits, however, adding a Zener
diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance.
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The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low
(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP
mode to conserve power.
Figure 30. ESD Protection for SMB Communication
9.2.2.2.5 FUSE Circuitry
The FUSE pin of the bq40z50-R1 is designed to ignite the chemical fuse if one of the various safety criteria is
violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical
fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate
gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high.
Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the
chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come from
the FUSE output during the cell connection process.
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Figure 31. FUSE Circuit
When the bq40z50-R1 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V
output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the
system, as well as widens the choices for Q5.
9.2.2.3 Secondary-Current Protection
The bq40z50-R1 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage
multiplexing, and voltage translation. The following discussion examines Cell and Battery Inputs, Pack and FET
Control, Temperature Output, and Cell Balancing.
9.2.2.3.1 Cell and Battery Inputs
Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts
to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety
protection.
The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells,
effectively balancing the entire battery stack. External series resistors placed between the cell connections and
the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ω resistance (2 V < VDS
< 4 V). Series input resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.
The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage
caused by a short-circuit event.
Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery
connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB
copper.
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Figure 32. Cell and BAT Inputs
9.2.2.3.2 External Cell Balancing
Internal cell balancing can only support up to 10 mA. External cell balancing provide as another option for faster
cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420).
9.2.2.3.3 PACK and FET Control
The PACK and VCC inputs provide power to the bq40z50-R1 from the charger. The PACK input also provides a
method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the
VCC input uses a diode to guard against input transients and prevents mis-operation of the date driver during
short-circuit events.
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Figure 33. bq40z50-R1 PACK and FET Control
The N-channel charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a
switching time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of
an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a
reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the
PACK+ input becomes slightly negative.
Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the
FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002
as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq40z50-R1
device has the capability to provide a current-limited charging path typically used for low battery voltage or low
temperature charging. The bq40z50-R1 device uses an external P-channel, pre-charge FET controlled by PCHG.
9.2.2.3.4 Temperature Output
For the bq40z50-R1 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin
can be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at
25°C (103) NTC external thermistor such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ
thermistors: RT1, RT2, RT3, and RT4. The bq40z50-R1 device supports up to four external thermistors. Connect
unused thermistor pins to VSS
.
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Figure 34. Thermistor Drive
9.2.2.3.5 LEDs
Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are
configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused
LEDCNTL pins can remain open or they can be connected to VSS. The DISP pin should be connected to VSS, if
the LED feature is not used.
Figure 35. LEDs
9.2.2.3.6 Safety PTC Thermistor
The bq40z50-R1 device provides support for a safety PTC thermistor. The PTC thermistor is connected between
the PTC pin and VSS. It can be placed close to the CHG/DSG FETs to monitor the temperature. The PTC pin
outputs a very small current, typical ~370 nA, and the PTC fault will be triggered at ~0.7 V typical. A PTC fault is
one of the permanent failure modes. It can only be cleared by a POR.
To disable this feature, connect a 10-kΩ resistor between PTC and VSS
.
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Figure 36. PTC Thermistor
40
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9.2.3 Application Curves
±24.6
±24.8
±25.0
±25.2
±25.4
±25.6
±25.8
87.4
87.2
87.0
86.8
86.6
86.4
86.2
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C009
C010
Threshold setting is 25 mV.
Threshold setting is 25 mV.
Figure 37. Overcurrent Discharge Protection Threshold Vs.
Temperature
Figure 38. Short Circuit Charge Protection Threshold Vs.
Temperature
±86.0
±86.2
±86.4
±86.6
±86.8
±87.0
±87.2
±172.9
±173.0
±173.1
±173.2
±173.3
±173.4
±173.5
±173.6
0
20
40
60
80
100
120
±40
±20
0
20
40
60
80
100
120
±40
±20
Temperature (C)
Temperature (C)
C012
C011
Threshold setting is –177.7 mV.
Threshold setting is –88.85 mV.
Figure 40. Short Circuit Discharge 2 Protection Threshold
Vs. Temperature
Figure 39. Short Circuit Discharge 1 Protection Threshold
Vs. Temperature
11.00
10.95
10.90
10.85
10.80
10.75
10.70
452
450
448
446
444
442
440
438
436
434
432
0
20
40
60
80
100
120
0
20
40
60
80
100
120
±40
±20
±40
±20
Temperature (C)
Temperature (C)
C013
C014
Threshold setting is 11 ms.
Threshold setting is 465 µs.
Figure 41. Overcurrent Delay Time Vs. Temperature
Figure 42. Short Circuit Charge Current Delay Time Vs.
Temperature
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10 Power Supply Recommendations
The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT
input is the primary power source to the device. The BAT pin should be connected to the positive termination of
the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V.
The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum Vcc. This
allows the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should
be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the
PACK pin.
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11 Layout
11.1 Layout Guidelines
A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-
current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-
trace coupling is with a component placement, such as that shown in Figure 43, where the high-current section is
on the opposite side of the board from the electronic devices. Clearly this is not possible in many situations due
to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal
traces, which enter the bq40z50-R1 directly. IC references and registers can be disturbed and in rare cases
damaged due to magnetic and capacitive coupling from the high-current path. Note that during surge current and
ESD events, the high-current traces appear inductive and can couple unwanted noise into sensitive nodes of the
gas gauge electronics, as illustrated in Figure 44.
Figure 43. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity
Figure 44. Avoid Close Spacing Between High-Current and Low-Level Signal Lines
Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell
voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor
in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity.
Figure 45 and Figure 46 demonstrates correct kelvin current sensing.
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Layout Guidelines (continued)
Current Direction
R
SNS
Current Sensing Direction
To SRP – SRN pin or HSRP – HSRN pin
Figure 45. Sensing Resistor PCB Layout
Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout
11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In
Figure 47, an example layout demonstrates this technique.
Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3
44
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Layout Guidelines (continued)
11.1.2 ESD Spark Gap
Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The
pattern in Figure 48 recommended, with 0.2-mm spacing between the points.
Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD
11.2 Layout Example
THERMISTORS
CHARGE
AND
DISCHARGE
2ND LEVEL
PATH
PROTECTOR
LEDS
CURRENT
FILTER
SENSE
RESISTOR
Figure 49. Top Layer
Figure 50. Internal Layer 1
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Layout Example (continued)
Figure 51. Internal Layer 2
CHARGE
AND
DISCHARGE
PATH
FILTER
COMPONENTS
Figure 52. Bottom Layer
46
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
如需相关文档，请参见《bq40z50-R1 技术参考手册》（文献编号：SLUUBC1）。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
Impedance Track, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
47
重要声明
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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
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TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
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产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
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www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ40Z50RSMR-R1
BQ40Z50RSMT-R1
ACTIVE
ACTIVE
VQFN
VQFN
RSM
RSM
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ40Z50
BQ40Z50
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 2.8
1.4 0.05
(0.2) TYP
4X (0.45)
28X 0.4
9
16
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.5
0.3
32X
4219107/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.4)
SYMM
32
25
32X (0.6)
1
32X (0.2)
24
SYMM
33
(3.8)
28X (0.4)
(
0.2) VIA
17
8
(R0.05)
TYP
9
16
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219107/A 11/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.3)
(R0.05) TYP
25
32
32X (0.6)
32X (0.2)
1
24
SYMM
33
(3.8)
28X (0.4)
METAL
TYP
17
8
16
9
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219107/A 11/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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