BQ4850Y_13 [TI]

RTC Module With 512Kx8 NVSRAM; RTC模块512Kx8 NVSRAM


型号：	BQ4850Y_13
厂家：	TEXAS INSTRUMENTS
描述：	RTC Module With 512Kx8 NVSRAM RTC模块512Kx8 NVSRAM 静态存储器
文件：	总17页 (文件大小：1153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Not Recommended For New Designs

bq4850Y

RTC Module With 512Kx8 NVSRAM

The clock and alarm registers are

General Description

Features

du a l-por t r ea d/wr it e SRAM loca-

➤ I n t e gr a t e d S R AM , r e a l-t im e

clock, crystal, power-fail control

circuit, and battery

The bq4850Y RTC Module is a non-

volatile 4,194,304-bit SRAM organ-

ized as 524,288 words by 8 bits with

a n in t egr a l a ccessible r ea l-t im e

clock.

tions that are updated once per sec-

ond by a clock control circuit from

the internal clock counters. The

dual-port registers allow clock up-

dates to occur without interrupting

n or m a l a ccess t o t h e r est of t h e

SRAM array.

➤ Real-Time Clock counts seconds

through years in BCD format

The device combines an internal lith-

ium battery, quartz crystal, clock and

power-fail chip, and a full CMOS

SRAM in a plastic 32-pin DIP mod-

ule. The RTC Module directly re-

places industry-standard SRAMs and

also fits into many EPROM and EE-

PROM sockets without any require-

ment for special write timing or limi-

tations on the number of write cycles.

➤ RAM-like clock access

The bq4850Y also contains a power-

fail-detect circuit. The circuit dese-

lects the device whenever V_CCfalls

below tolerance, providing a high de-

gree of data security. The battery is

electrically isolated when shipped

from the factory to provide maxi-

mum battery capacity. The battery

remains disconnected until the first

➤ Pin-compatible with industry-

standard 512K x 8 SRAMs

➤ Unlimited write cycles

➤ 10-year minimum data retention

and clock operation in the absence

of power

➤ Automatic power-fail chip dese-

Registers for the rea l-time clock,

alarm and other special functions

are located in registers 7FFF8h–

7FFFFh of the memory array.

application of V_CC

lect and write-protection

➤ Soft wa r e clock ca libr a t ion for

gr e a t e r t h a n ±1 m in u t e p e r

month accuracy

Pin Connections

Pin Names

A₀–A₁₈

Address input

Chip enable

Write enable

Output enable

DQ₀–DQ₇Data in/data out

V_CC

V_SS

+5 volts

Ground

32-Pin DIP Module

PN485001.eps

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

in clu din g m em or y a n d clock in t er fa ce, a n d da t a -

retention modes.

Functional Description

Figure 1 is a block diagram of the bq4850Y. The follow-

ing sections describe the bq4850Y functional operation,

Time-

Base

Oscillator

Internal

Quartz

Crystal

16 1 MUX

Control/Status

Registers

DQ -DQ

Bus

I/F

Clock Alarm and

Calendar Bytes

Clock/Calendar

Update

AD -AD

User Buffer

(8 Bytes)

Storage

Registers

(524,288 Bytes)

Power-

Fail

Write-

Protect

Control

Internal

Battery

BD-961

Figure 1. Block Diagram

Truth Table

V_CC

V_IH

V_IL

Mode

Deselect

Write

Power

Standby

Active

< V_CC(max.)

High Z

D_IN

V_IL

V_IH

> V_CC(min.)

V_IL

V_IH

Read

D_OUT

Active

Read

High Z

Active

< V_PFD(min.) > V_SO

Deselect

CMOS standby

Battery-backup mode

≤ V_SO

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

Figure 2 illustrates the address map for the bq4850Y.

Table 1 is a map of the bq4850Y registers.

Address Map

The bq4850Y provides 8 bytes of clock and control status

registers and 524,288 bytes of storage RAM.

Clock and

Control Status

Registers

7FFFF

Year

Month

Date

7FFFF

7FFFE

7FFFD

7FFFC

7FFFB

7FFFA

8 Bytes

7FFF8

7FFF7

Days

Hours

Minutes

Seconds 7FFF9

Control 7FFF8

32,760

Bytes

Storage

RAM

0000

MM-961

Figure 2. Address Map

Table 1. bq4850Y Clock and Control Register Map

Address

7FFFF

7FFFE

7FFFD

7FFFC

7FFFB

7FFFA

7FFF9

7FFF8

10 Years

Year

Range (h)

00–99

01–12

01–31

01–07

00–23

00–59

00–31

Year

10 Month

Month

Date

Month

Date

10 Date

FTE

Day

Hours

Days

10 Hours

Hours

Minutes

Seconds

Control

10 Minutes

10 Seconds

Minutes

Seconds

OSC

Calibration

Notes:

X = Unused bits; can be written and read.

Clock/Calendar data in 24-hour BCD format.

OSC = 1 stops the clock oscillator.

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

The internal coin cell maintains data in the bq4850Y af-

Memory Interface

Read Mode

ter the initial application of V_CCfor an accumulated pe-

riod of at least 10 years when V_CCis less than V_SO. As

system power returns and Vcc rises above V_SO, the bat-

tery is disconnected, and the power supply is switched to

The bq4850Y is in read mode whenever OE (output en-

able) is low and CE (chip enable) is low. The device ar-

chitecture allows ripple-through access of data from

eight of 4,194,304 locations in the static storage array.

Thus, the unique address specified by the 19 address in-

puts defines which one of the 524,288 bytes of data is to

be accessed. Valid data is available at the data I/O pins

within t_AA(address access time) after the last address

input signal is stable, providing that the CE and OE

(output enable) access times are also satisfied. If the CE

and OE access times are not met, valid data is available

after the latter of chip enable access time (t_ACE) or out-

put enable access time (t_OE).

external V_CC

. Write-protection continues for t_CERafter

V_CCreaches V_PFDto allow for processor stabilization.

After t_CER, normal RAM operation can resume.

Clock Interface

Reading the Clock

The interface to the clock and control registers of the

bq4850Y is the same as that for the general-purpose

storage memory. Once every second, the user-accessible

clock/calendar locations are updated simultaneously

from the internal real time counters. To prevent reading

data in transition, updates to the bq4850Y clock regis-

ters should be halted. Updating is halted by setting the

read bit D6 of the control register to 1. As long as the

read bit is 1, updates to user-accessible clock locations

are inhibited. Once the frozen clock information is re-

trieved by reading the appropriate clock memory loca-

tions, the read bit should be reset to 0 in order to allow

updates to occur from the internal counters. Because the

internal counters are not halted by setting the read bit,

reading the clock locations has no effect on clock accu-

racy. Once the read bit is reset to 0, within one second

the internal registers update the user-accessible regis-

ters with the correct time. A halt command issued dur-

ing a clock update allows the update to occur before

freezing the data.

CE and OE control the state of the eight three-state

data I/O signals. If the outputs are activated before t_AA

the data lines are driven to an indeterminate state until

t_AA. If the address inputs are changed while CE and OE

remain low, output data remains valid for t_OH(output

data hold time), but goes indeterminate until the next

address access.

Write Mode

The bq4850Y is in write mode whenever WE and CE are

active. The start of a write is referenced from the

latter-occurring falling edge of WE or CE. A write is ter-

minated by the earlier rising edge of WE or CE. The ad-

dresses must be held valid throughout the cycle. CE or

WE must return high for a minimum of t_WR2from CE or

t_WR1from WE prior to the initiation of another read or

write cycle.

Setting the Clock

Bit D7 of the control register is the write bit. Like the

read bit, the write bit when set to a 1 halts updates to

the clock/calendar memory locations. Once frozen, the

locations can be written with the desired information in

24-hour BCD format. Resetting the write bit to 0 causes

the written values to be transferred to the internal clock

counters and allows updates to the user-accessible regis-

ters to resume within one second. Use the write bit, D7,

only when updating the time registers (7FFFF–7FFF9).

Data-in must be valid t_DWprior to the end of write and

remain valid for t_DH1or t_DH2afterward. OE should be

kept high during write cycles to avoid bus contention; al-

though, if the output bus has been activated by a low on

CE and OE, a low on WE disables the outputs t_WZafter

WE falls.

Data-Retention Mode

With valid V_CCapplied, the bq4850Y operates as a

conventional static RAM. Should the supply voltage

decay, t h e RAM a u t om a t ica lly power-fa il deselect s,

Stopping and Starting the Clock Oscillator

The OSC bit in the seconds register turns the clock on or

off. If the bq4850Y is to spend a significant period of

time in storage, the clock oscillator can be turned off to

preserve battery capacity. OSC set to 1 stops the clock

oscillator. When OSC is reset to 0, the clock oscillator is

turned on and clock updates to user-accessible memory

locations occur within one second.

write-protecting itself t_WPTafter V_CCfalls below V_PFD

All outputs become high impedance, and all inputs are

treated as “don’t care.”

If power-fail detection occurs during a valid access, the

memory cycle continues to completion. If the memory

cycle fa ils t o t er m in a t e wit h in t im e t _{WP T}, wr it e-

protection takes place. When V_CCdrops below V_SO, the

control circuit switches power to the internal energy

source, which preserves data.

The OSC bit is set to 1 when shipped from the Bench-

marq factory.

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

Calibrating the Clock

The bq4850Y real-time clock is driven by a quartz con-

trolled oscillator with a nominal frequency of 32,768 Hz.

The quartz crystal is contained within the bq4850Y

package along with the battery. The clock accuracy of

the bq4850Y module is tested to be within 20ppm or

about 1 minute per month at 25°C. The oscillation rates

of crystals change with temperature as Figure 3 shows.

To compensate for the frequency shift, the bq4850Y of-

fers onboard software clock calibration. The user can

adjust the calibration based on the typical operating

temperature of individual applications.

-20

-40

-60

-80

-100

-120

The software calibration bits are located in the control

tion, and bit D5 the direction (positive or negative) of

correction. Assuming that the oscillator is running at

exactly 32,786 Hz, each calibration step of D0–D4 ad-

justs the clock rate by +4.068 ppm (+10.7 seconds per

month) or -2.034 ppm (-5.35 seconds per month) depend-

ing on the value of the sign bit D5. When the sign bit is

1, positive adjustment occurs; a 0 activates negative ad-

justment. The total range of clock calibration is +5.5 or

-2.75 minutes per month.

-30 -20 -10

10 20 30 40 50 60 70

Temperature ( C)

GR485001

Figure 3. Frequency Error

ister is set to a 1, and the oscillator is running at exactly

32,768 Hz, the LSB of the seconds register toggles at

512 Hz. Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of 512.01024 Hz

indicates a (1E6 0.01024)/512 or +20 ppm oscillator fre-

quency error, requiring ten steps of negative calibration

(10 -2.034 or -20.34) or 001010 to be loaded into the cali-

bration byte for correction. To read the test frequency,

the bq4850Y must be selected and held in an extended

read of the seconds register, location 7FFF9, without

having the read bit set. The frequency appears on DQ0.

The FTE bit must be set using the write bit control. The

FTE bit must be reset to 0 for normal clock operation to

resume.

Two methods can be used to ascertain how much cali-

bration a given bq4850Y may require in a system. The

first involves simply setting the clock, letting it run for a

month, and then comparing the time to an accurate

known reference like WWV radio broadcasts. Based on

the variation to the standard, the end user can adjust

the clock to match the system’s environment even after

the product is packaged in a non-serviceable enclosure.

The only requirement is a utility that allows the end

user to access the calibration bits in the control register.

The second approach uses a bq4850Y test mode. When

the frequency test mode enable bit FTE in the days reg-

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

DC Electrical Characteristics (T = T

≤ V

CC CCmax)

OPR, VCCmin

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions/Notes

V_IN= V_SSto V_CC

I_LI

Input leakage current

± 1

µA

CE = V_IHor OE = V_IHor

WE = V_IL

I_LO

Output leakage current

± 1

µA

V_OH

V_OL

I_SB1

Output high voltage

Output low voltage

Standby supply current

2.4

0.4

I_OH= -1.0 mA

I_OL= 2.1 mA

CE = V_IH

CE ≥ V_CC- 0.2V,

0V ≤ V_IN≤ 0.2V,

or V_IN≥ V_CC- 0.2V

I_SB2

Standby supply current

0.1

Min. cycle, duty = 100%,

CE = V_IL, I_I/O= 0mA

I_CC

Operating supply current

V_PFD

V_SO

Power-fail-detect voltage

Supply switch-over voltage

4.30

4.37

4.50

Note:

Typical values indicate operation at T_A= 25°C, V_CC= 5V.

Capacitance (T = 25°C, F = 1MHz, V

= 5.0V)

Symbol

C_I/O

Parameter

Minimum

Typical

Maximum

Unit

Conditions

Output voltage = 0V

Input voltage = 0V

Input/output capacitance

Input capacitance

C_IN

Note:

These parameters are sampled and not 100% tested.

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

AC Test Conditions

Parameter

Test Conditions

0V to 3.0V

Input pulse levels

Input rise and fall times

5 ns

Input and output timing reference levels

Output load (including scope and jig)

1.5 V (unless otherwise specified)

See Figures 4 and 5

Figure 4. Output Load A

Figure 5. Output Load B

Read Cycle (T = T

≤ V

CC CCMAX)

OPR, VCCmin

Parameter

–85

Min.

Max.

Symbol

Unit

Conditions

t_RC

Read cycle time

t_AA

Address access time

Output load A

t_ACE

t_OE

Chip enable access time

Output load A

Output load B

Output load A

Output enable to output valid

Chip enable to output in low Z

Output enable to output in low Z

Chip disable to output in high Z

Output disable to output in high Z

Output hold from address change

t_CLZ

t_OLZ

t_CHZ

t_OHZ

t_OH

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

1,2

Read Cycle No. 1 (Address Access)

1,3,4

Read Cycle No. 2 (CE Access)

1,5

Read Cycle No. 3 (OE Access)

Notes:

1. WE is held high for a read cycle.

2. Device is continuously selected: CE = OE = V_IL

3. Address is valid prior to or coincident with CE transition low.

4. OE = V_IL

5. Device is continuously selected: CE = V_IL

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

Write Cycle (T =T

≤ V

OPR , CCMIN ≤ CC

CCMAX)

–85

Min.

Max.

Symbol

t_WC

Parameter

Write cycle time

Units

Conditions/Notes

t_CW

Chip enable to end of write

Address valid to end of write

(1)

t_AW

Measured from address valid to begin-

ning of write. (2)

t_AS

Address setup time

Measured from beginning of write to

end of write. (1)

t_WP

Write pulse width

Measured from WE going high to end

of write cycle. (3)

t_WR1

t_WR2

t_DW

t_DH1

t_DH2

Write recovery time (write cycle 1)

Write recovery time (write cycle 2)

Data valid to end of write

Data hold time (write cycle 1)

Data hold time (write cycle 2)

Measured from CE going high to end of

write cycle. (3)

Measured to first low-to-high transi-

tion of either CE or WE.

Measured from WE going high to end

of write cycle. (4)

Measured from CE going high to end of

write cycle. (4)

t_WZ

t_OW

Write enabled to output in high Z

Output active from end of write

I/O pins are in output state. (5)

Notes:

1. A write ends at the earlier transition of CE going high and WE going high.

2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3. Either t_WR1or t_WR2must be met.

4. Either t_DH1or t_DH2must be met.

5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

1,2,3

Write Cycle No. 1 (WE-Controlled)

1,2,3,4,5

Write Cycle No. 2 (CE-Controlled)

Notes:

1. CE or WE must be high during address transition.

2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3. If OE is high, the I/O pins remain in a state of high impedance.

4. Either t_WR1or t_WR2must be met.

5. Either t_DH1or t_DH2must be met.

SLUS057A- January 2005

Not Recommended For New Designs

bq4850Y

Power-Down/Power-Up Cycle (T = T

OPR)

Typical

Symbol

t_PF

Parameter

Minimum

300

Maximum

Unit

µs

Conditions

V_CCslew, 4.50 to 4.20 V

V_CCslew, 4.20 to V_SO

t_FS

µs

V_CCslew, V_SOto V_PFD

(max.)

t_PU

µs

Time during which SRAM is

write-protected after V_CC

passes V_FPDon power-up.

t_CER

Chip enable recovery time

100

200

Data-retention time in

absence of V_CC

t_DR

years T_A= 25°C. (2)

Delay after V_CCslews down

t_WPT

Write-protect time

100

160

µs

past V_PFDbefore SRAM is

write-protected.

Notes:

1. Typical values indicate operation at T_A= 25°C, V_CC= 5V.

2. Battery is disconnected from circuit until after V_CCis applied for the first time. t_DRis the

accumulated time in absence of power beginning when power is first applied to the device.

Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e

m a y a ffect d a ta in tegr ity.

Power-Down/Power-Up Timing

Not Recommended For New Designs

PACKAGE OPTION ADDENDUM

www.ti.com

6-Jun-2013

PACKAGING INFORMATION

Orderable Device

BQ4850YMA-85

BQ4850YMA-85N

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

LIFEBUY DIP MODULE

Pb-Free

(RoHS)

Call TI

N / A for Pkg Type

LIFEBUY DIP MODULE

Pb-Free

(RoHS)

N / A for Pkg Type

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDI061 – MAY 2001

MA (R-PDIP-T**)

PLASTIC DUAL-IN-LINE

28 PINS SHOWN

Inches

Max.

Millimeters

Min.

Max.

Dimension

Min.

0.365

0.015

0.017

0.008

0.710

1.470

1.670

2.070

0.710

0.590

0.090

0.120

0.105

0.075

0.375

–

9.27

0.38

9.53

–

0.023

0.58

0.33

0.43

0.20

0.013

0.740

1.500

1.700

2.100

0.740

D/12 PIN

D/28 PIN

D/32 PIN

D/40 PIN

18.03

37.34

42.42

52.58

18.03

18.80

38.10

43.18

53.34

18.80

16.00

2.79

14.99

2.29

0.630

0.110

3.81

3.05

2.67

1.91

0.150

0.130

0.110

S/12 PIN

3.30

2.79

4201975/A 03/01

NOTES: A. All linear dimensions are in inches (mm).

B. This drawing is subject to change without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

MPDI062 – MAY 2001

MB (R-PDIP-T32)

PLASTIC DUAL-IN-LINE

Inches

Max.

Millimeters

Min.

Max.

Dimension

Min.

0.365

0.015

0.017

0.008

2.070

0.710

0.590

0.090

0.120

0.275

0.375

–

9.27

0.38

0.43

0.20

52.58

18.03

14.99

2.29

3.05

6.99

9.53

–

0.023

0.58

0.33

0.013

2.100

0.740

53.34

18.80

16.00

2.79

0.630

0.110

0.150

0.310

3.81

7.87

4201976/A 03/01

NOTES: A. All linear dimensions are in inches (mm).

B. This drawing is subject to change without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251–1443

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BQ4850Y_13 [TI]

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BQ48S1.5-30R

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