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bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

bq51222 双路模式 5W（WPC v1.2 和 PMA）单芯片无线电源接收器

1 特性

3 说明

1

•

稳健的 5W 解决方案，热损耗降低 50%，从而提高

热性能

bq51222 器件是一款装备齐全的无线电源接收器，此

接收器能够以无线充电联盟 (WPC) Qi 和电源事物联盟

(PMA) 协议运行，这使得无线电源系统满足这两种感

应充电标准。bq51222 器件提供针对这两种标准的单

器件电源转换（整流和稳压）以及数字控制和通信。它

还具有协议自主检测功能，并且无需额外的有源器件。

bq51222 器件符合 WPC v1.2 和 PMA 通信协议。与

WPC 或 PMA 一次侧控制器搭配使用时，bq51222 器

件可为无线电源解决方案实现一套完整的无线电源传输

系统。此接收器可采用市场领先的封装、效率和解决方

案实现同步整流、稳压和控制与通信。

–

针对最薄解决方案的无电感器接收器

可调节输出电压（4.5 至 8V），以实现线圈和

热性能优化

–

效率高达 96% 的完全同步整流器

后置调节器的效率达 97%

5 W 时系统效率达 79%

•

与 WPC v1.2 和 PMA 标准兼容的通信

已获专利的发送器焊盘检测功能提升了用户体验

与主机进行I²C通信

器件信息⁽¹⁾

2 应用范围

器件型号

bq51222

封装

封装尺寸（最大值）

•

智能手机、平板电脑和头戴式耳机

Wi-Fi 热点

DSBGA (42)

3.586mm x 2.874mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

移动电源

其他手持式器件

空白

简化原理图

双路模式效率（5V 输出）

bq51222

90

80

70

60

50

40

30

20

System

Load

AD-EN

AD

OUT

C_COMM1

C_BOOT1

C₄

COMM1

BOOT1

AC1

R₇

RECT

C₁

C₃

R₆

VO_REG

VIREG

R₉

R₈

C₂

AC2

BOOT2

COMM2

TS/CTRL

TMEM

C_BOOT2

z

HOST

NTC

C_COMM2

C_CLAMP2

C_CLAMP1

CLAMP2

CLAMP1

C₅

PMA Duracell TX

WPC A1 TX

10

0

LPRB1

LPRB2

SCL

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_OUT(A)

1

1.1 1.2

TERM

D001

SDA

CM_ILIM

PGND

FOD

ILIM

R₅

R₁

R_FOD

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSCL5

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

8.4 Device Functional Modes........................................ 18

8.5 Register Maps......................................................... 22

Application and Implementation ........................ 28

9.1 Application Information............................................ 28

9.2 Typical Applications ................................................ 29

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 8

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ....................................... 11

8.3 Feature Description................................................. 12

9

10 Power Supply Recommendations ..................... 41

11 Layout................................................................... 42

11.1 Layout Guidelines ................................................. 42

11.2 Layout Example .................................................... 42

12 器件和文档支持 ..................................................... 43

12.1 器件支持 ............................................................... 43

12.2 接收文档更新通知 ................................................. 43

12.3 社区资源................................................................ 43

12.4 商标....................................................................... 43

12.5 静电放电警告......................................................... 43

12.6 Glossary................................................................ 43

13 机械、封装和可订购信息....................................... 43

8

4 修订历史记录

Changes from Original (July 2016) to Revision A

Page

•

已更改 “产品预览”至“量产数据”............................................................................................................................................... 1

2

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

5 Device Comparison Table

DEVICE

MODE

MORE

bq51221

bq51222

bq51021

bq51020

Dual (WPC v1.1, PMA)

Dual (WPC v1.2, PMA)

WPC v1.1

Adjustable output voltage, highest system efficiency, I²C

Adjustable output voltage, highest system efficiency, standalone

WPC v1.1

6 Pin Configuration and Functions

YFP Package

42-Pin DSBGA

Top View

!1

tDb5

!2

tDb5

!3

tDb5

!4

tDb5

!ꢀ

tDb5

!6

tDb5

.1

!/1

.2

!/1

.3

!/1

.4

!/2

.ꢀ

!/2

.6

!/2

/1

.hhÇ1

/2

w9/Ç

/3

w9/Ç

/4

w9/Ç

/ꢀ

w9/Ç

/6

.hhÇ2

51

hÜÇ

52

hÜÇ

53

hÜÇ

54

hÜÇ

5ꢀ

hÜÇ

56

hÜÇ

E1

E2

E3

E4

E5

E6

CLAMP1

AD

/AD_EN

SCL

VIREG

CLAMP2

F3

LPRBEN

TERM

F5

LPRB1

WPG

F1

COMM1

F2

FOD

F4

SDA

F6

COMM2

G6

LPRB2

PD_DET

G1

VO_REG

G2

ILIM

G3

CM_ILIM

G4

TS/CTRL

G5

TMEM

Pin Functions

NUMBER

TYPE

DESCRIPTION

NAME

AC1

B1, B2, B3

I

AC input power from receiver resonant tank

AC2

B4, B5, B6

I

AD

E2

E3

C1

C6

F1

F6

E1

E6

I

Adapter sense pin

AD-EN

BOOT1

BOOT2

COMM1

COMM2

CLAMP1

CLAMP2

O

Push-pull driver for PFET that can pass AD input to the OUT pin; used for adapter mux control

Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier

Open-drain FETs used to communicate with primary by varying reflected impedance

Open-drain FETs used to clamp the secondary voltage by providing low impedance across

secondary

Enables or disables communication current limit; can be pulled high or low to disable or enable

communication current limit

CM_ILIM

G3

I

FOD

ILIM

F2

I

Input that is used for scaling the received power message

Output current or overcurrent level programming pin

G2

I/O

3

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

LPRB 1

LPRB 2

NUMBER

F5

O

Open drain – active to help drive RECT voltage high at light load on a PMA TX

G6

D1, D2, D3, D4,

D5, D6

OUT

O

Output pin, used to deliver power to the load

Open drain output that allows user to sense when receiver is on transmitter

Power and logic ground

PD_DET

PGND

G6

A1, A2, A3, A4,

A5, A6

—

RECT

SCL

C2, C3, C4, C5

O

I

Filter capacitor for the internal synchronous rectifier

E4

F4

SCL and SDA are used for I²C communication

SDA

I

TERM,

LPRBEN

Sets termination current as a percentage of I_ILIMas TERM pin. When TERM resistor is populated,

LPRB pins are enabled with appropriate function

F3

G5

G4

I

O

I

TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to

retain memory of state

TMEM

Temperature sense. Can be pulled high to send end power transfer (EPT) or end of charge (EOC)

to TX

TS/CTRL

VIREG

VO_REG

WPG

E5

G1

F5

I

Rectifier voltage feedback

Sets the regulation voltage for output

O

Open-drain output that allows user to sense when power is transferred to load

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

(2)

MIN

MAX

UNIT

AC1, AC2

–0.8

20

RECT, COMM1, COMM2, OUT, LPRB1, LPRB2, CLAMP1, CLAMP2, WPG,

PD_DET

–0.3

20

Input voltage

AD, AD-EN

–0.3

30

20

V

BOOT1, BOOT2

SCL, SDA, TERM, CM_ILIM, FOD, TS/CTRL, ILIM, TMEM, VIREG,

VO_REG, LPRBEN

–0.3

7

Input current

AC1, AC2 (RMS)

OUT

2.5

1.5

15

A

Output current

Output sink current

Junction temperature, T_J

Storage temperature, T_stg

LPRB1, LPRB2

COMM1, COMM2

mA

A

1

–40

–65

150

°C

(1) All voltages are with respect to the PGND pin, unless otherwise noted.

(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽²⁾, 100 pF, 1.5 kΩ

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

10

UNIT

V

V_RECT

I_OUT

RECT voltage range

Output current

4

1

A

I_AD-EN

I_COMM

T_J

Sink current

1

mA

ºC

COMMx sink current

Junction temperature

500

125

0

7.4 Thermal Information

bq51222

THERMAL METRIC⁽¹⁾

YFP (DSBGA)

UNIT

42 PINS

49.7

0.2

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

R_θJC(top)

R_θJB

6.1

ψ_JT

1.4

ψ_JB

6

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

5

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

MAX UNIT

7.5 Electrical Characteristics

I_LOAD= I_OUT, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_RECT: 0 to 3 V

MIN

TYP

2.8

V_UVLO

Undervoltage lockout

Hysteresis on UVLO

Input overvoltage threshold

Hysteresis on OVP

2.9

V

mV

V

V_HYS-UVLO

V_RECT-OVP

V_HYS-OVP

V_RECT: 3 to 2 V

V_RECT: 5 to 16 V

V_RECT: 16 to 5 V

393

15.1

1.5

14.6

15.6

V

Voltage at RECT pin set by

communication with primary

V_RECT(REG)

V_OUT+ 0.12

V_OUT+ 2

V

V_RECT(TRACK

)

V_RECTregulation above V_OUT

V_ILIM= 1.2 V

I_LOADfalling

140

4%

mV

I_LOADhysteresis for dynamic

V_RECTthresholds as a % of I_ILIM

I_LOAD-HYS

Rectifier under voltage

protection, restricts I_OUTat

V_RECT-DPM

3

3.1

3.2

9.2

V

Rectifier reverse voltage

protection with a supply at the

output

V_RECT-REV= V_OUT– V_RECT, V_OUT

= 10 V

V_RECT-REV

I_LPRB1-dis

I_LPRB2-dis

8.8

125

322

V

Current at which LPRB1 is

disabled

I_OUT0 to 200 mA

I_OUT0 to 400 mA

mA

Current at which LPRB2 is

disabled

QUIESCENT CURRENT

Quiescent current at the output

when wireless power is disabled

ILIM SHORT CIRCUIT

Highest value of R_ILIMresistor

I_OUT(standby)

V

_OUT≤ 5 V, 0°C ≤ T_J≤ 85°C

20

35

µA

R_ILIM: 200 to 50 Ω. I_OUTlatches

off, cycle power to reset

R_ILIM-SHORTconsidered a fault (short).

Monitored for I_OUT> 100 mA

215

1

230

Ω

Deglitch time transition from

t_DGL-Short

ms

mA

ILIM short to I_OUTdisable

I_LIM-SHORT,OKenables the ILIM

I_{LIM_SC}

I_LIM-

short comparator when I_OUTis

greater than this value

I_LOAD: 0 to 200 mA

I_LOAD: 200 to 0 mA

110

125

140

Hysteresis for I_LIM-SHORT,OK

comparator

20

mA

A

SHORT,OK

HYSTERESIS

Maximum I_LOADthat can be

delivered for 1 ms when ILIM is

shorted

I_OUT-CL

Maximum output current limit

3.7

OUTPUT

I_LOAD= 1000 mA

I_LOAD= 1 mA

0.495

0.5013

0.5014

0.5075

0.5076

V_{O_REG}

Feedback voltage set point

V

0.4951

R_ILIM= K_ILIM/ I_ILIM, where I_ILIMis

the hardware current limit

I_OUT= 850 mA

Current programming factor for

hardware short circuit protection

K_ILIM

842

AΩ

Current limit programming

range

I_{OUT_RANGE}

1500

mA

I

_OUT≥ 400 mA

I_OUT– 50

I_OUT+ 50

None

Output current limit during

communication

I_COMM

100 mA ≤ I_OUT< 400 mA

mA

s

I_OUT< 100 mA

Hold off time for the

communication current limit

during startup

t_HOLD-OFF

1

6

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

Electrical Characteristics (continued)

I_LOAD= I_OUT, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TS/CTRL

V_TS-Bias

I_TS-Bias< 100 µA and

communication is active

(periodically driven, see t_TS/CTRL-

TS bias voltage (internal)

1.8

V

)

Meas

V_CTRL-HI

CTRL pin threshold for a high

V_TS/CTRL: 50 to 150 mV

90

105

120

mV

ms

V

Time period of TS/CTRL

measurements, when TS is

being driven

T_TS/CTRL-

Meas

TS bias voltage is only driven

when power packets are sent

1700

V_TS-HOT

Voltage at TS pin when device

shuts down

0.38

THERMAL PROTECTION

T_J(OFF)

Thermal shutdown temperature

Thermal shutdown hysteresis

155

20

°C

T_J(OFF-HYS)

OUTPUT LOGIC LEVELS ON WPG

V_OL

Open drain WPG pin

I_SINK= 5 mA

V_WPG= 20 V

550

1

mV

µA

WPG leakage current when

disabled

I_OFF,STAT

COMM PIN

R_DS-

ON(COMM)

COMM1 and COMM2

V_RECT= 2.6 V

1

Ω

Signaling frequency on COMMx

pin for WPC

ƒ_COMM

2.00

Kb/s

µA

I_OFF,COMM

COMMx pin leakage current

V_COMM1= 20 V, V_COMM2= 20 V

1

CLAMP PIN

R_DS-

ON(CLAMP)

CLAMP1 and CLAMP2

0.5

Ω

ADAPTER ENABLE

V_AD-EN

V_AD-EN-HYS

I_AD

V_ADrising threshold voltage

V_AD0 V to 5 V

3.5

3.6

3.8

V

V_AD-ENhysteresis

V_AD5 V to 0 V

450

mV

μA

Input leakage current

V_RECT= 0 V, V_AD= 5 V

50

Pullup resistance from AD-EN

R_{AD_EN-OUT}to OUT when adapter mode is

disabled and V_OUT> V_AD

V_AD= 0 V, V_OUT= 5 V

230

350

Ω

Voltage difference between V_ADV_AD= 5 V, 0°C ≤ T_J≤ 85°C

4

3

4.5

6

5

7

V

V_{AD_EN-ON}

and V_AD-ENwhen adapter mode

V_AD= 9 V, 0°C ≤ T_J≤ 85°C

is enabled

SYNCHRONOUS RECTIFIER

I_OUTat which the synchronous

I_SYNC-EN

rectifier enters half synchronous I_OUT: 200 mA to 0 mA

mode

100

40

mA

V

I_SYNC-EN-

HYST

Hysteresis for I_OUT,RECT-EN(full-

I_OUT0 mA to 200 mA

synchronous mode enabled)

High-side diode drop when the

I_AC-VRECT= 250 mA, and

rectifier is in half synchronous

T_J= 25°C

V_HS-DIODE

0.7

mode

I²C

V_IL

Input low threshold level SDA

Input high threshold level SDA

Input low threshold level SCL

Input high threshold level SCL

V(PULLUP) = 1.8 V, SDA

V(PULLUP) = 1.8 V, SCL

Typical

0.4

V

V_IH

1.4

V_IL

V

V_IH

I²C speed

V

100

kHz

7

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

7.6 Typical Characteristics

Temperature = 25°C (unless otherwise noted)

0.50155

0.5015

0.50145

0.5014

0.50135

0.5013

0.50125

0.5012

60

50

40

30

20

10

0

0.0001

0.001

0.01

0.1

1

4

5

6

7

8

9

Load Current (A)

V_OUT(V)

D001

D002

Figure 1. Output Voltage Feedback as a Function of Load

850

Figure 2. Quiescent Current as a Function of Output Voltage

2.88

2.865

2.85

845

840

835

830

825

820

815

810

805

2.835

2.82

2.805

2.79

2.775

2.76

2.745

2.73

-60 -40 -20

0

20

40

60

80 100 120 140

250

350

450

550

650

750

850

950

Temperature (èC)

Load Current (mA)

D004

D001

Figure 4. V_UVLOas a Function of Junction Temperature

Figure 3. K_ILIMas a Function of Load Current

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

I²C Code

D001

Register 0x01 (B0, B1, B2)

1-mA Load

Register 0x01 (B0, B1, B2)

1-A Load

Figure 5. Register 0x01 control of V_{O_REG}

Figure 6. Register 0x01 control of V_{O_REG}

8

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

8 Detailed Description

8.1 Overview

Both WPC and PMA wireless power systems consist of a charging pad (primary, transmitter) and the secondary-

side equipment (receiver). There are coils in the charging pad and secondary equipment, which magnetically

couple to each other when the receiver is placed on the transmitter. Power is transferred from the primary to the

secondary by transformer action between the coils. The receiver can achieve control over the amount of power

transferred by getting the transmitter to change the field strength by changing the frequency, or duty cycle, or

voltage rail energizing the primary coil.

The receiver equipment communicates with the primary by modulating the load seen by the primary. This load

modulation results in a change in the primary coil current or primary coil voltage, or both, which is measured and

demodulated by the transmitter.

In WPC, the system communication is digital — packets that are transferred from the secondary to the primary.

Differential bi-phase encoding is used for the packets. The bit rate is 2 kb/s. Various types of communication

packets are defined. These include identification and authentication packets, error packets, control packets,

power usage packets, and end power transfer packets, among others.

An PMA-compliant receiver communicates based on continuous transmission of signals from the receiver to the

transmitter. The PMA specification defines six different communications symbols. These are increment (INC),

decrement (DEC), no change (NoCh), end of charge (EOC), MsgBit, and a symbol for future use. Each PMA

receiver has a unique PMA RXID, which is a 6-byte unique message that is sent to the PMA TX at startup.

Power

bq51222

Voltage/

System

Current

AC to DC

Drivers

Rectification

Load

Conditioning

Communication

LI-Ion

Battery

Charger

Controller

V/I

Sense

Controller

Transmitter

Receiver

Figure 7. Dual Mode Wireless Power System Indicating the Functional Integration of the bq51222 Family

The bq51222 device integrates fully-compliant WPC v1.2 and PMA communication protocols in order to

streamline the dual mode receiver designs (no extra software development required). Other unique algorithms

such as Dynamic Rectifier Control are integrated to provide best-in-class system efficiency while keeping the

smallest solution size of the industry.

9

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

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Overview (continued)

As a WPC system, when the receiver shown in Figure 7 is placed on the charging pad, the secondary coil

couples to the magnetic flux generated by the coil in the transmitter, which consequently induces a voltage in the

secondary coil. The internal synchronous rectifier feeds this voltage to the RECT pin, which in turn feeds the

LDO which feeds the output.

The bq51222 device identifies and authenticates itself to the primary using the COMMx pins, switching on and off

the COMM FETs, and hence switching in and out COMM capacitors. If the authentication is successful, the

primary remains powered-up. The bq51222 device measures the voltage at the RECT pin, calculates the

difference between the actual voltage and the desired voltage V_RECT(REG), and sends back error packets to the

transmitter. This process goes on until the input voltage settles at V_{RECT(REG) MAX}. During a load change, the

dynamic rectifier algorithm sets the targets specified by targets between V_{RECT(REG) MAX}and V_{RECT(REG) MIN}shown

in Table 1. This algorithm enhances the transient response of the power supply.

After the voltage at the RECT pin is at the desired value, a pass FET is enabled. The voltage control loop

ensures that the output voltage is maintained at V_OUT(REG), powering the downstream charger. The bq51222

device meanwhile continues to monitor the input voltage, and keeps sending control error packets (CEP) to the

primary on average every 250 ms. If a large transient occurs, the feedback to the primary speeds up to 32-ms

communication periods to converge on an operating point in less time.

If the receiver shown in Figure 7 is used with a PMA transmitter, the bq51222 device identifies itself to the PMA

transmitter using the COMMx pins. If sufficient power is delivered to the bq51222 device to wake up the device, it

responds by modulating the power signal according to the PMA communication protocol. Prior to enabling the

output, the bq51222 device transmits an RXID message. This is a unique identification message that is

controlled through an IEEE sanctioned database and every bq51222 device comes programmed with its own

unique RXID that can be read back using I²C. See I²C register map in Register Maps for details on the location

of the RXID. The bq51222 device then monitors the voltage at the RECT pin. If there is a difference between the

actual voltage and the desired voltage V_RECT(REG), the device sends a PMA DEC or PMA INC signal to the PMA

transmitter to control the RECT voltage to be within the desired window. The receiver regulates V_RECTto a

desired window of operation shown in Figure 15.

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bq51222

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8.2 Functional Block Diagram

RECT

I

OUT

V_REF,ILIM

V_ILIM

_{_}V_OUT,FB

+ V_OUT,REG

+

_

VO_REG

V_REF,IABS

V_IABS,FB

+

_

ILIM

V_IN,FB

+

_

V_IN,DPM

AD

+

_

VREF_AD,OVP

BOOT2

BOOT1

_

+

VREF_AD,UVLO

AD-EN

AC1

AC2

Sync

Rectifier

Control

VIREG

T_S

COMM1

COMM2

V_BG,REF

V_IN,FB

V_OUT,FB

V_ILIM

DATA_

OUT

ADC

V_IABS,FB

TS/CTRL

CLAMP1

CLAMP2

V_IABS,REF

V_IC,TEMP

V_FOD

FOD

V_RECT

V_OVP,REF

Digital Control

+

_

OVP

LPRB1

SCL

or WPG

LPRB2

or PD_DET

SDA

50 µA

CM_ILIM

TMEM

+

_

LPRBEN

or TERM

TERM

ILIM

PGND

11

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8.3 Feature Description

8.3.1 Dynamic Rectifier Control

WPC Mode Only

The Dynamic Rectifier Control algorithm offers the end system designer optimal transient response for a given

maximum output current setting. This is achieved by providing enough voltage headroom across the internal

regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a

relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target.

Therefore, a transient response is dependent on the loosely coupled transformer's output impedance profile. The

Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed

at the output of the internal regulator (output of the bq51222 device). A 1-A application allows up to a 2-Ω output

impedance. The Dynamic Rectifier Control behavior is illustrated in Figure 13 where R_ILIMis set to 680 Ω.

8.3.2 Dynamic Power Scaling

WPC Mode Only

The Dynamic Power Scaling feature allows for the loss characteristics of the bq51222 device to be scaled based

on the maximum expected output power in the end application. This effectively optimizes the efficiency for each

application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the

maximum output current. Note that the maximum output current is set by the K_ILIMterm and the R_ILIMresistance

(where R_ILIM= K_ILIM/ I_ILIM). The flow diagram in Figure 13 shows how the rectifier is dynamically controlled

(Dynamic Rectifier Control) based on a fixed percentage of the I_ILIMsetting. Table 1 summarizes how the rectifier

behavior is dynamically adjusted based on two different R_ILIMsettings. The table is shown for I_MAX, which is

typically lower than I_ILIM(about 20% lower). See RILIM Calculations for more details.

Table 1. Dynamic Rectifier Regulation

OUTPUT CURRENT

PERCENTAGE

R_ILIM= 1400 Ω

I_MAX= 0.5 A

R_ILIM= 700 Ω

I_MAX= 1.0 A

VRECT

0 to 10%

10 to 20%

20 to 40%

>40%

0 to 0.05 A

0.05 to 0.1 A

0.1 to 0.2 A

>0.2 A

0 to 0.1 A

0.1 to 0.2 A

0.2 to 0.4 A

>0.4 A

V_OUT+ 2

V_OUT+ 1.68

V_OUT+ 0.56

V_OUT+ 0.12

Dynamic Rectifier Control shows the shift in the dynamic rectifier control behavior based on the two different

R_ILIMsettings. With the rectifier voltage (V_RECT) being the input to the internal LDO, this adjustment in the

Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where:

P_DIS= V

- V_OUT∂I

OUT

(

)

RECT

(1)

Figure 40 shows how the system efficiency is improved due to the Dynamic Power Scaling feature. Note that this

feature balances efficiency with optimal system transient response.

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8.3.3 VO_REG and VIREG Calculations

WPC and PMA Modes

The bq51222 device allows the designer to set the output voltage by setting a feedback resistor divider network

from the OUT pin to the VO_REG pin as seen in Figure 8. The resistor divider network should be chosen so that

the voltage at the VO_REG pin is 0.5 V at the desired output voltage. This applies to the default I²C code for

VO_REG shown in I²C register 0x01 shown in Table 5 (Bits B0, B1, B2).

RECT

OUT

R₇

R₉

VIREG

R₈

VO_REG

R₆

NTC R₃R₄

LPRB1

LPRB2

Figure 8. VO_REG Network

Figure 9. VIREG Network (For PMA)

Choose the desired output voltage V_OUTand R₆:

0.5 V

K_VO

=

V_OUT

(2)

(3)

K_VOì R₇

1 - K_VO

R₆=

After R₆and R₇are chosen, the same divider network is attached to VIREG pin from RECT to GND, as shown in

Figure 9. R₉= R₇and R₈= R₆.

LPRB1 and LPRB2 are two additional pins that are used to implement a back cover solution and are used for

PMA (see Figure 55). In a back cover solution where the system designer cannot depend on the characteristics

of the downstream charger in the phone, these pins can be used to boost the rectifier at a lower power (Low

Power Rectifier Boost), so that the system is able to survive a load transient from 0 mA to the maximum current

by boosting the rectifier during low power output that the system is designed for. See resistor calculations for

LPRB1 and LPRB2: in the bq51222 web page "Tools & software" tab. The Excel file not only provides how to

calculate the LPRB resistor values but also assists with other calculations. The Excel file can be accessed at

www.ti.com/product/bq51222/toolssoftware.

Table 2. LPRB Condition Table

I_OUT

LPRB1

ON

LPRB2

ON

0 mA < I_OUT< 100 mA

100 mA < I_OUT< 350 mA

350 mA < I_OUT< Maximum current

OFF

ON

OFF

The LPRB1 and LPRB2 resistors can be omitted in an embedded solution where the system designer is in

control of the voltage at which the downstream charger can regulate the input current to prevent the input from

collapsing in a load transient (VIN-DPM). The functionality of LPRB1 and LPRB2 can be reverted to WPG and

PD_DET by not populating the TERM resistor. In this case, the host enables the charge complete on the

TS/CTRL pin by pulling this pin high.

For the back cover solution, the TERM resistor is populated and this enables LPRB1 and LPRB2 functionality.

The functionality can be seen in Table 2.

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8.3.4 RILIM Calculations

WPC and PMA Modes

The bq51222 device includes a means of providing hardware overcurrent protection (I_ILIM) through an analog

current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum

allowable output current (for example, current compliance). The R_ILIMresistor size also sets the thresholds for the

dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The

calculation for the total R_ILIMresistance is as follows:

R_ILIM= K_ILIM/ I_ILIM

R₁= R_ILIM– R_FOD

(4)

(5)

R_ILIMallows for the ILIM pin to reach 1.2 V at an output current equal to I_ILIM. When choosing R_ILIM, two options

are possible.

If the user's application requires an output current equal to or greater than the external I_ILIMthat the circuit is

designed for (input current limit on the charger where the receiver device is tied higher than the external I_ILIM),

ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver

device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output

does not drop to 0 V. Such behavior is referred to as Dynamic Power Management (VIN-DPM) in TI chargers.

Unless such behavior is enabled on the charger, the charger will pull the output of the receiver device to ground

when the receiver device enters current regulation. If the user's applications are designed to extract less than the

I_ILIM(1-A maximum), typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin

reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input

current limit on the charger lower than the external ILIM of the receiver device. In both cases however, the

charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a

reasonable value. This same behavior is also necessary during the WPC communication. The following

calculations show how such a design is achieved:

R_ILIM= K_ILIM/ (1.1 × I_ILIM

R₁= R_ILIM– R_FOD

)

(6)

(7)

where I_LIMis the hardware current limit.

When referring to the application diagram shown in Typical Applications, R_ILIMis the sum of the R₁and R_FOD

resistance (that is, the total resistance from the ILIM pin to GND). R_FODis chosen according to the application.

The tool for calculating R_FODcan be obtained by contacting your TI representative. Use R_FODto allow the

receiver implementation to comply with WPC v1.2 requirements related to received power accuracy.

8.3.5 Adapter Enable Functionality

WPC and PMA Modes

The bq51222 device can also help manage the multiplexing of adapter power to the output and can shut off the

TX when the adapter is plugged in and is above the V_AD-EN. After the adapter is plugged in and the output turns

off, the RX device sends an EOC to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V

below AD, which allows the device turn on the back-to-back PMOS connected between AD and OUT (Figure 54).

Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. It must also be noted that it is

required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions.

Also, when AD mode is enabled, no load can be pulled from the RECT pin as this could cause an internal device

overvoltage in the bq51222 device.

8.3.6 Turning Off the Transmitter

WPC and PMA Modes

Both specifications allow the receiver to turn off the transmitter and put the system in a low-power standby mode.

There are two different ways to accomplish this with the bq51222 device. In both modes, the EPT charge

complete (WPC) or end of charge (PMA) can be sent to the TX by pulling the TS pin high (above 1.4 V). The

bq51222 device will then sense this and send the appropriate signal to the TX, thus putting the TX in a low

power standby mode.

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8.3.6.1 WPC End Power Transfer (EPT)

The WPC allows for a special command to terminate power transfer from the TX termed EPT packet. The v1.2

specifies the following reasons and their responding data field value in Table 3.

Table 3. End Power Transfer Codes in WPC

REASON

Unknown

VALUE

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

CONDITION⁽¹⁾

AD > 3.6 V

Charge Complete

Internal Fault

Over Temperature

Over Voltage

Over Current

Battery Failure

Reconfigure

TS/CTRL = 1

T_J> 150°C or R_ILIM< 215 Ω

TS < V_TS-HOT, or TS/CTRL < 100 mV⁽²⁾

V_RECTtarget does not converge⁽³⁾

Not sent

No Response

Not sent

(1) The Condition column corresponds to the case where the bq51222 device will send the WPC EPT

command.

(2) The TS < V_TS-HOTcondition refers to using an external thermistor for temperature control. The

TS/CTRL < 100 mV condition refers to driving the TS/CTRL pin from an external GPIO.

(3) If the voltage on the RECT pin does not reach the required value (typically 8 V) within 64 error packets

during startup (weak coil coupling), the receiver sends EPT-OV and the transmitter will shut off.

8.3.6.2 PMA EOC

PMA EOC is a state where the bq51222 device disables the output and sends EOC frequency to terminate the

power transfer on a PMA transmitter. This can be done by setting the TERM pin resistor so that the voltage on

the TERM pin is higher than the ILIM pin at the desired termination current. This TERM resistor method of

sending the EOC to the transmitter only works with PMA TX. After the TERM resistor is populated, it also

changes the behavior of the LPRBx pins. Check the section on LPRBx resistors for more information. Another

way to send an EOC to the PMA TX is to pull the TS pin above 1.4 V through an external pullup.

8.3.7 CM_ILIM

WPC Mode Only

Communication current limit is a feature that allows for error free communication to happen between the RX and

TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current

during communication with the TX. The communication current limit is set according to Table 4. The

communication current limit can be disabled by pulling CM_ILIM pin high (> 1.4 V) or enabled by pulling the

CM_ILIM pin low. There is an internal pulldown that enables communication current limit when the CM_ILIM pin

is left floating.

Table 4. Communication Current Limit Table

I_OUT

COMMUNICATION CURRENT LIMIT

0 mA < I_OUT< 100 mA

100 mA < I_OUT< 400 mA

400 mA < I_OUT< Max current

None

I_OUT+ 50 mA

I_OUT– 50 mA

15

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When the communication current limit is enabled, the amount of current that the load can draw is limited. If the

charger in the system does not have a VIN-DPM feature, the output of the receiver will collapse if communication

current limit is enabled. In order to disable Communication Current Limit, pull CM_ILIM pin high.

8.3.8 PD_DET and TMEM

PD_DET is only available in WPC mode. This is an open-drain pin that goes low based on the voltage of the

TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET will be low. The voltage on the TMEM pin

depends on capturing the energy from the digital ping from the transmitter and storing it on the C₅capacitor in

Figure 10. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a low-

power mode. However, it will continue to check if the receiver would like to renegotiate a power transfer by

periodically performing the digital ping. The energy from the digital ping can be stored on the TMEM pin until the

next digital ping refreshes the capacitor. A bleedoff resistor R_MEMcan be chosen in parallel with C₅that sets the

time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between

digital pings is indeterminate and depends on each transmitter manufacturer.

TMEM

R_MEM

C₅

Figure 10. TMEM Configuration

Set capacitor on C₅= TMEM to 2.2 µF. Resistor R_MEMacross C₅can be set by understanding the duration

between digital pings (t_ping). Set the resistor such that:

t_ping

R_MEM

=

C₅

(8)

8.3.9 TS, Both WPC and PMA

The bq51222 device includes a ratio metric external temperature sense function. The temperature sense function

has a low ratio metric threshold which represents a hot condition. TI recommends an external temperature

sensor in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring

the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC)

resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to

adjust the NTC to match the trip point of the device. The implementation in Figure 11 shows the series-parallel

resistor implementation for setting the threshold at which V_TS-HOTis reached. Once V_TS-HOTis reached, the device

will send an EPT – overtemperature signal for a WPC transmitter or an EOC signal to a transmitter depending on

the mode the device is operating in. An Excel tool to assist with defining the correct resistor values is available

on the bq51222 web folder under 'Tools

www.ti.com/product/bq5122PMA2/toolssoftware.

&

Software'. The Excel file can be found at

ëÇ{.

(1ꢀ8 ë)

R₂

20 kꢀ

R₁

Ç{/ꢁÇw[

R₃

NTC

Figure 11. NTC Resistor Setup

16

bq51222

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Figure 11 shows a parallel resistor setup that can be used to adjust the trip point of V_TS-HOT. After the NTC is

chosen and R_NTCHOTat V_TS-HOTis determined from the data sheet of the NTC, Equation 9 can be used to

calculate R₁and R₃. In many cases depending on the NTC resistor, R₁or R₃can be omitted. When calculating

V_TS-HOT, omit R₁by setting it to 0 Ω, and omit R₃by setting it to 10 MΩ.

R

+ R₁ì R

(

)

NTCHOT

3

R

+ R₁+ R

)

NTCHOT

3

V_TS-HOT= 1.8 V ì

R

+ R₁ì R

(

)

NTCHOT

3

+ R₂

R

+ R₁+ R

)

(

)

NTCHOT

(9)

8.3.10 I²C Communication

WPC and PMA Modes

The bq51222 device allows for I²C communication with the internal CPU. In case the I²C is not used, ground

SCL and SDA. See Register Maps for more information.

8.3.11 Input Overvoltage

WPC and PMA Modes

If the input voltage suddenly increases in potential for some condition (for example a change in position of the

equipment on the charging pad), the voltage-control loop inside the bq51222 device becomes active, and

prevents the output from going beyond V_OUT(REG). The receiver then starts sending back error packets every 30

ms until the input voltage comes back to an acceptable level, and then maintains the error communication every

250 ms.

If the input voltage increases in potential beyond V_RECT-OVP, the device switches off the LDO and informs the

primary to bring the voltage back to V_RECT(REG). In addition, a proprietary voltage protection circuit is activated by

means of C_CLAMP1and C_CLAMP2that protects the device from voltages beyond the maximum rating of the device.

17

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8.4 Device Functional Modes

In WPC mode, at startup operation, the bq51222 device must comply with proper handshaking in order to be

granted a power contract from the WPC transmitter. The transmitter initiates the handshake by providing an

extended digital ping after analog ping detects an object on the transmitter surface. If a receiver is present on the

transmitter surface, the receiver then provides the signal strength, configuration, and identification packets to the

transmitter (see volume 1 of the WPC specification for details on each packet). These are the first three packets

sent to the transmitter. The only exception is if there is a true shutdown condition on the AD, or TS/CTRL pins

where the receiver shuts down the transmitter immediately. See Table 3 for details. After the transmitter has

successfully received the signal strength, configuration, and identification packets, the receiver is granted a

power contract and is then allowed to control the operating point of the power transfer. With the use of the

bq51222 device Dynamic Rectifier Control algorithm, the receiver will inform the transmitter to adjust the rectifier

voltage above 8 V prior to enabling the output supply. This method enhances the transient performance during

system startup. For the startup flow diagram details, see Figure 12.

Tx Powered

without Rx

Active

Tx Extended Digital Ping

Yes

AD/TS-CTRL EPT

Condition?

Send EPT packet with

reason value

No

Identification &

Configuration & SS,

Received by Tx?

No

Yes

Power Contract

Established. All

proceeding control is

dictated by the Rx.

Yes

Send control error packet

to increase V_RECT

ë_w9/Ç< 8 ë?

No

Startup operating point

established. Enable the

Rx output.

Rx Active

Power Transfer

Stage

Figure 12. Wireless Power Startup Flow Diagram on WPC TX

18

bq51222

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Device Functional Modes (continued)

After the startup procedure has been established, the receiver will enter the active power transfer stage. This is

considered the main loop of operation. The Dynamic Rectifier Control algorithm determines the rectifier voltage

target based on a percentage of the maximum output current level setting (set by K_ILIMand the R_ILIM). The

receiver will send control error packets in order to converge on these targets. As the output current changes, the

rectifier voltage target dynamically changes. As a note, the feedback loop of the WPC system is relatively slow, it

can take up to 150 ms to converge on a new rectifier voltage target. It should be understood that the

instantaneous transient response of the system is open loop and dependent on the receiver coil output

impedance at that operating point. The main loop also determines if any conditions in Table 3 are true in order to

discontinue power transfer. Figure 13 shows the active power transfer loop.

Rx Active

Power Transfer

Stage

Rx Shutdown

conditions per the EPT

Table?

Tx Powered

without Rx

Active

Yes

Send EPT packet with

reason value

No

VRECT target = VO + 2 V.

Send control error packets

to converge.

Yes

Is VILIM < 0.1 V?

No

VRECT target = VO + 1.3 V.

Send control error packets

to converge.

Yes

Is VILIM < 0.2 V?

No

VRECT target = VO + 0.6 V.

Send control error packets

to converge.

Is VILIM < 0.4 V?

No

VRECT target = VO + 0.12 V.

Send control error packets to

converge.

Measure Received Power

and Send Value to Tx

Figure 13. Active Power Transfer Flow Diagram on WPC TX

19

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Device Functional Modes (continued)

In PMA mode, during startup operation, PMA transmitter generates a digital ping in a predefined structure

regarding the frequencies and timing. If the power delivered during the digital ping is sufficient to wake up the

bq51222 device, it responds by modulating the power signal according to the PMA communication protocol. If the

transmitter receives a valid PMA signal from the receiver, it continues to the identification phase, without

removing the power signal. The receiver continues to send PMA DEC or PMA INC signals until target V_RECTis

achieved, and after desired V_RECTis achieved, the bq51222 device sends a PMA NoCh signal to indicate that no

further change is needed in transmitter frequency. Please note unlike the WPC mode receiver, in PMA mode, the

bq51222 device will continue to send the PMA NoCh signal if the target V_RECTis within a defined voltage range.

This means that the device will regulate the V_RECTvoltage within an acceptable window. This can be seen in

Figure 15.

{tandby

ꢁh

wó

w9ꢂhë95

wó

59Ç9/Ç95?

ò9{

wó

w9ꢂhë95

5LDLÇ![ ꢀLꢁD

ꢁh

hnly 2

attempts

alloꢃed

wó

w9ꢂhë95

L59ꢁÇLCL/!ÇLhꢁ

wó

w9ꢂhë95

DÜ!w5 ÇLꢂ9

9óꢀLw95?

ò9{

wó

w9ꢂhë95

ꢀhí9w Çw!ꢁ{C9w

9h/

Figure 14. Active Power Transfer Flow Diagram on PMA TX Type 1

Optimized rectification voltage is key to maintaining high efficiency on the bq51222. Figure 15 indicates the

control and communication protocol between the receiver and the transmitter. The bq51222 sends an increment

signal (INC) for increasing the operating frequency of the transmitter to decrease the transferred power if the

rectification voltage is above VREFHI_H. INC signals will occur until the rectification voltage is below VREFHI_L.

If the rectification voltage is below VREFLO_L then the bq51222 will send a decrease signal (DEC) to the

transmitter which will decrease the frequency resulting in increased power delivery. VREFLO_H is the hysteresis

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bq51222

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Device Functional Modes (continued)

level for terminating the DEC signal. A no change signal (NoCh) is sent when the rectification voltage is between

VREFLO_H and VREFHI_L indicating there is no need to increase or decrease the transferred power.

Additionally, the Hysteresis zones can be NoCh depending on the direction entered. For example, if the

rectification voltage moves through VREFHI_L to enter Hysteresis, the NoCh command is sent. If the same

Hysteresis zone is entered through VREFHI_H then the INC will continue to be sent until it reaches VREFHI_L

where the NoCh signal will commence. The device will not react to a change in load while the rectification

voltage falls within the indicated levels (VREFHI_H > V_RECT> VREFLO_L). When a load change occurs sufficient

to move V_RECToutside this range, the appropriate signal (INC or DEC) will be sent.

Lb/

ëw9CIL_I

Iysteresis

ëw9CIL_[

bo/ꢀ

ëw9C[h_I

Iysteresis

ëw9C[h_[

59/

Figure 15. PMA Active Power Control Diagram

21

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8.5 Register Maps

Locations 0x01 and 0x02 can be written to any time. Locations 0xE0 to 0xFF are only functional when V_RECT

V_UVLO. When V_RECTgoes below V_UVLO, locations 0xE0 to 0xFF are reset.

>

8.5.1 Wireless Power Supply Current Register 1 (address = 0x01) [reset = 00000001]

Figure 16. Wireless Power Supply Current Register Format

7

6

5

4

3

2

1

0

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

V_OREG2

R/W

V_OREG1

R/W

V_OREG0

R/W

LEGEND: R/W = Read/Write

Table 5. Wireless Power Supply Current Register 1 Field Descriptions

Bit

B7:B3

B2

Field

Type

R/W

Reset

Description

Reserved

V_OREG2

V_OREG1

V_OREG0

00000

Not used

0

1

450, 500, 550, 600, 650, 700, 750, or 800 mV

Changes V_{O_REG}target

B1

B0

8.5.2 Wireless Power Supply Current Register 2 (address = 0x02) [reset = 00000111 ]

Figure 17. Wireless Power Supply Current Register 2 Format

7

6

5

4

3

2

1

0

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

I_OREG2

R/W

I_OREG1

R/W

I_OREG0

R/W

LEGEND: R/W = Read/Write

Table 6. Wireless Power Supply Current Register 2 Register Field Descriptions

Bit

B7:B3

B2

Field

Type

R/W

Reset

Description

Reserved

I_OREG2

I_OREG1

I_OREG0

00000

Not used

1

10%, 20%,30%, 40%, 50%, 60%, 90%, and 100%

of I_ILIMcurrent

based on configuration

B1

B0

000, 001, ... 111

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8.5.3 I²C Mailbox Register (address = 0xE0) [reset = 10000000 ]

Figure 18. I²C Mailbox Register Format

7

6

5

4

3

2

1

0

USER_PKT_D

ONE

USER_PKT_ERR

FOD Mailer

ALIGN Mailer

FOD Scaler

Reserved

R

R/W

LEGEND: R/W = Read/Write; R = Read only

Table 7. I²C Mailbox Register Field Descriptions

Bit

Field

Type

Reset

Description

B7

USER_PKT_DONE

R

1

Set bit to 0 to send proprietary packet with header in 0xE2.

CPU checks header to pick relevant payload from 0xF1 to 0xF4

This bit will be set to 1 after the user packet with the header in

register 0xE2 is sent.

B6:B5

USER_PKT_ERR

R

00

00 = No error in sending packet

01 = Error: no transmitter present

10 = Illegal header found: packet will not be sent

11 = Error: not defined yet

B4

B3

FOD Mailer

R/W

0

Not used

ALIGN Mailer

Setting this bit to 1 will enable alignment aid mode where the

CEP = 0 will be sent until this bit is set to 0 (or CPU reset

occurs)

B2

FOD Scaler

Reserved

R/W

0

Not used,write to 0 if register is written

Not used

B1:B0

00

8.5.4 Wireless Power Supply FOD RAM Register (address = 0xE1) [reset =00000000 ]

Figure 19. Wireless Power Supply FOD RAM Register Format

7

6

5

4

3

2

1

0

ESR_ENABLE OFF_ENABLE

R/W R/W

LEGEND: R/W = Read/Write

Ro_FOD5

R/W

Ro_FOD4

R/W

Ro_FOD3

R/W

Rs_FOD2

R/W

Rs_FOD1

R/W

Rs_FOD0

R/W

Table 8. Wireless Power Supply FOD RAM Register Field Descriptions

Bit

B7

B6

B5

B4

B3

Field

Type

R/W

Reset

Description⁽¹⁾

ESR_ENABLE

OFF_ENABLE

Ro_FOD5

0

Enables I²C based ESR in received power, Enable = 1, Disable = 0

Enables I²C based offset power, Enable = 1, Disable = 0

000 – 0 mW

101 – +195 mW

110 – +234 mW

111 – +273 mW

The value is added to received

power message

001 – +39 mW

010 – +78 mW

011 – +117 mW

100 – +156 mW

Ro_FOD4

Ro_FOD3

B2

B1

B0

Rs_FOD2

Rs_FOD1

Rs_FOD0

R/W

0

000 – ESR

001 – ESR

010 – ESR × 2

011 – ESR × 3

100 – ESR x 4

101 – ESR

110 – ESR

111 – ESR x 0.5

(1) A non-zero value will change the I²R calculation resistor and offset in the received power calculation by a factor shown in the table.

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8.5.5 Wireless Power User Header RAM Register (address = 0xE2) [reset = 00000000]

Figure 20. Wireless Power User Header RAM Register Format

7

6

5

4

3

2

1

0

HEADER7

R/W

HEADER6

R/W

HEADER5

R/W

HEADER4

R/W

HEADER3

R/W

HEADER2

R/W

HEADER1

R/W

HEADER0

R/W

LEGEND: R/W = Read/Write

Table 9. Wireless Power User Header RAM Register Field Descriptions

Bit

Field

Type

Reset

00000000 Proprietary packet 8-bit header

Description⁽¹⁾

B7:B0

HEADER

R/W

(1) Must write a valid header to enable proprietary package. As soon as mailer (0xE0) is written, payload bytes are sent on the next

available communication slot as determined by CPU. Once payload is sent, the mailer (USER_PKT_DONE) is set to 1.

8.5.6 Wireless Power USER V_RECTStatus RAM Register (address = 0xE3) [reset = 00000000]

This register reads back the V_RECTvoltage with LSB = 46 mV.

Figure 21. Wireless Power USER V_RECTStatus RAM Register Format

7

V_RECT7

R

6

V_RECT6

R

5

V_RECT5

R

4

V_RECT4

R

3

V_RECT3

R

2

V_RECT2

R

1

V_RECT1

R

0

V_RECT0

R

LEGEND: R = Read only

Table 10. Wireless Power USER V_RECTStatus RAM Register Field Descriptions

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Field

Type

R

Reset

Description

V_RECT7

V_RECT6

V_RECT5

V_RECT4

V_RECT3

V_RECT2

V_RECT1

V_RECT0

0

V_RECTvoltage

Range – 0 V to 12 V, LSB = 46 mV

R

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8.5.7 Wireless Power VOUT Status RAM Register (address = 0xE4) [reset = 00000000]

This register reads back the V_OUTvoltage with LSB = 46 mV.

Figure 22. Wireless Power VOUT Status RAM Register Format

7

6

5

4

3

2

1

0

V_OUT7

R/W

V_OUT6

R/W

V_OUT5

R/W

V_OUT4

R/W

V_OUT3

R/W

V_OUT2

R/W

V_OUT1

R/W

V_OUT0

R/W

LEGEND: R/W = Read/Write

Table 11. Wireless Power VOUT Status RAM Register Field Descriptions

Bit

B7

B6

B5

B4

B3

B2

B1

B0

Field

Type

R/W

Reset

Description

V_OUT7

V_OUT6

V_OUT5

V_OUT4

V_OUT3

V_OUT2

V_OUT1

V_OUT0

0

V_OUTvoltage

LSB = 46 mV

8.5.8 Wireless Power REC PWR Byte Status RAM Register (address = 0xE8) [reset = 00000000]

This register reads back the received power with LSB = 39 mW.

Figure 23. Wireless Power REC PWR Byte Status RAM Register Format

7

6

5

4

3

2

1

0

RECPWR7

R/W

RECPWR6

R/W

RECPWR5

R/W

RECPWR4

R/W

RECPWR3

R/W

RECPWR2

R/W

RECPWR1

R/W

RECPWR0

R/W

LEGEND: R/W = Read/Write

Table 12. Wireless Power REC PWR Byte Status RAM Register Field Descriptions

Bit

Field

Type

Reset

Description

B7:B0

RECPWR

R/W

00000000 Received Power

LSB = 39 mW

8.5.9 Wireless Power Mode Indicator Register (address = 0xEF) [reset = 00000000]

This register reads back the MODE (WPC or PMA) based on the Transmitter.

Figure 24. Wireless Power Mode Indicator Register Format

7

6

ALIGN

R

5

4

3

2

1

0

MODE

R

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

Reserved

R/W

LEGEND: R/W = Read/Write; R = Read only

Table 13. Wireless Power Mode Indicator Register Field Descriptions

Bit

Field

Type

Reset

Description

B7

Reserved

Read /

Write

0

Not Used

B6

ALIGN Status

Reserved

Read

0

Alignment mode = 1, Normal operation = 0 (Status bit)

Not Used

B5:B1

Read /

Write

00000

B0

Mode

Read

0

PMA = 1, WPC = 0 (Status bit)

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ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

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8.5.10 Wireless Power Prop Packet Payload RAM Byte 0 Register (address = 0xF1) [reset = 00000000]

Figure 25. Wireless Power Prop Packet Payload RAM Byte 0 Register Format

7

6

5

4

3

2

1

0

PL0_7

R/W

PL0_6

R/W

PL0_5

R/W

PL0_4

R/W

PL0_3

R/W

PL0_2

R/W

PL0_1

R/W

PL0_0

R/W

LEGEND: R/W = Read/Write

Table 14. Wireless Power Prop Packet Payload RAM Byte 0 Register Field Descriptions

Bit

Field

Type

Reset

Description

B7:B0

PL0

R/W

00000000 Proprietary Packet Byte 0 content

8.5.11 Wireless Power Prop Packet Payload RAM Byte 1 Register (address = 0xF2) [reset = 00000000]

Figure 26. Wireless Power Prop Packet Payload RAM Byte 1

7

6

5

4

3

2

1

0

PL1_7

R/W

PL1_6

R/W

PL1_5

R/W

PL1_4

R/W

PL1_3

R/W

PL1_2

R/W

PL1_1

R/W

PL1_0

R/W

LEGEND: R/W = Read/Write

Table 15. Wireless Power Prop Packet Payload RAM Byte 1 Field Descriptions

Bit

Field

Type

Reset

Description

B7:B0

PL1

R/W

00000000 Proprietary Packet Byte 1 content

8.5.12 Wireless Power Prop Packet Payload RAM Byte 2 Register (address = 0xF3) [reset = 00000000]

Figure 27. Wireless Power Prop Packet Payload RAM Byte 2 Register Format

7

6

5

4

3

2

1

0

PL2_7

R/W

PL2_6

R/W

PL2_5

R/W

PL2_4

R/W

PL2_3

R/W

PL2_2

R/W

PL2_1

R/W

PL2_0

R/W

LEGEND: R/W = Read/Write

Table 16. Wireless Power Prop Packet Payload RAM Byte 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

B7:B0

PL2

R/W

00000000 Proprietary Packet Byte 2 content

8.5.13 Wireless Power Prop Packet Payload RAM Byte 3 Register (address = 0xF4) [reset = 00000000]

Figure 28. Wireless Power Prop Packet Payload RAM Byte 3 Register Format

7

6

5

4

3

2

1

0

PL3_7

R/W

PL3_6

R/W

PL3_5

R/W

PL3_4

R/W

PL3_3

R/W

PL3_2

R/W

PL3_1

R/W

PL3_0

R/W

LEGEND: R/W = Read/Write

Table 17. Wireless Power Prop Packet Payload RAM Byte 3 Register Field Descriptions

Bit

Field

Type

Reset

Description

B7:B0

PL3

R/W

00000000 Proprietary Packet Byte 3 content

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ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

8.5.14 RXID Readback Register (address = 0xF5 - 0xFA) [reset = see Table 18 note]

Registers 0xF5 to 0xFA store the RXID that can be read back when V_RECT> V_UVLO

.

Figure 29. RXID Readback Register Format

7

Reserved

R

6

Reserved

R

5

Reserved

R

4

Reserved

R

3

Reserved

R

2

Reserved

R

1

Reserved

R

0

Reserved

R

LEGEND: R = Read only

Table 18. RXID Readback Register Field Descriptions

Bit

Field

Type

Reset⁽¹⁾

Description

B7:B0

Reserved

R

RXID

(1) Reset value is programmed at TI factory as a unique ID for each device.

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ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The bq51222 device is a dual mode device which complies with both WPC v1.2 and PMA standards. This allows

a system designer to design a system that complies with both wireless power standards. There are several tools

available for the design of the system. These tools may be obtained by checking the product page at

www.ti.com/product/bq51222. The following sections detail how to design a dual mode RX system.

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9.2 Typical Applications

9.2.1 Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current

bq51222

{ystem

AD-EN

[oad

!ꢀ

hÜÇ

C_COMM1

C₄

C₃

/hꢂꢂ1

.hhÇ1

!/1

C_BOOT1

R₇

R₆

w9/Ç

C₁

ëh_w9D

ëLw9D

R₉

R₈

C₂

COIL

!/2

.hhÇ2

/hꢂꢂ2

Ç{ꢁ/Çw[

Çꢂ9ꢂ

C_BOOT2

z

Ih{Ç

NTC R₃R₄

C_COMM2

C_CLAMP2

C_CLAMP1

/[!ꢂꢃ2

/[!ꢂꢃ1

C₅

LPRB1

LPRB2

{/[

Ç9wꢂ

{ꢀ!

/ꢂ_L[Lꢂ

ꢃDꢄꢀ

Chꢀ

L[Lꢂ

R₅

R₁

R_OS

w9/Ç

R_FOD

Figure 30. Dual Mode Schematic using bq51222

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Typical Applications (continued)

9.2.1.1 Design Requirements

Table 19. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_OUT

I_OUTMAXIMUM

MODE

5 V

1 A

WPC and PMA

9.2.1.2 Detailed Design Procedure

To start the design procedure, start by determining the following.

•

Mode of operation – in this case dual mode (WPC and PMA)

Output voltage

Maximum output current

9.2.1.2.1 Output Voltage Set Point

The output voltage of the bq51222 device can be set by adjusting a feedback resistor divider network. The

resistor divider network is used to set the voltage gain at the VO_REG pin. The device is intended to operate

where the voltage at the VO_REG pin is set to 0.5 V. This value is the default setting and can be changed

through I²C. In Figure 31, R₆and R₇are the feedback network for the output voltage sense.

OUT

C₄

R₇

R₆

VO_REG

Figure 31. Voltage Gain for Feedback

0.5 V

K_VO

=

V_OUT

(10)

(11)

K_VOì R₇

1 - K_VO

R₆=

Choose R₇to be a standard value. In this case, care should be taken to choose R₆and R₇to be fairly large

values so as to not dissipate excessive amount of power in the resistors and thereby lower efficiency.

K_VOis set to be 0.5 / 5 = 0.1, choose R₇to be 102 kΩ, and thus R₆to be 11.3 kΩ.

After R₆and R₇are chosen, the same values should be used on R₈and R₉. This allows the device to regulate

the rectifier in the PMA mode to accurately track the output voltage when the output voltage is changed through

I²C.

9.2.1.2.2 Output and Rectifier Capacitors

Set C₄between 1 µF and 4.7 µF. This example uses 1 µF.

Set C₃between 4.7 µF and 22 µF. This example uses 20 µF.

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9.2.1.2.2.1 TMEM

Set C₅to 2.2 µF. In order to determine the bleed off resistor, the WPC transmitters for which the PD_DET is

being set for needs to be determined. After the ping timing (time between two consecutive digital pings after EPT

charge complete is sent) is determined, the bleedoff resistor can be determined. This example uses TI

transmitter EVMs as the use case. In this case the time between pings is 5 s. In order to set the time constant

using Equation 8, it is set to 5.6 MΩ.

9.2.1.2.3 Maximum Output Current Set Point

FOD1

ILIM

R₁

R_OS

RECT

R_FOD

Figure 32. Current Limit Setting for bq51222

The bq51222 device includes a means of providing hardware overcurrent protection by means of an analog

current regulation loop. The hardware current limit provides a level of safety by clamping the maximum allowable

output current (for example, a current compliance). The R_ILIMresistor size also sets the thresholds for the

dynamic rectifier levels and thus providing efficiency tuning per each application’s maximum system current. The

calculation for the total R_ILIMresistance is as follows:

K_ILIM

R_ILIM

=

I_ILIM

R₁= R_ILIM- R_{FO D}

(12)

(13)

The R_ILIMwill allow for the ILIM pin to reach 1.2 V at an output current equal to I_ILIM. When choosing R_ILIM, two

options are possible.

If the application requires an output current equal to or greater than external ILIM that the circuit is designed for

(input current limit on the charger where the RX is delivering power to is higher than the external ILIM), ensure

that the downstream charger is capable of regulating the voltage of the input into which the RX device output is

tied to by lowering the amount of current being drawn. This will ensure that the RX output does not collapse.

Such behavior is referred to as VIN-DPM in TI chargers. Unless such behavior is enabled on the charger, the

charger will pull the output of the RX device to ground when the RX device enters current regulation.

If the applications are designed to extract less than the ILIM (1-A maximum), typical designs should leave a

design margin of at least 20% so that the voltage at ILIM pin reaches 1.2 V when 20% more than maximum

current of the system is drawn from the output of the RX. Such a design would have input current limit on the

charger lower than the external ILIM of the RX device.

In both cases however, the charger must be capable of regulating the current drawn from the device to allow the

output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC v1.2

Communication. See Communication Current Limit for more details. The following calculations show how such a

design is achieved:

K_ILIM

R_ILIM

=

1.2 ì I_ILIM

(14)

(15)

R₁= R_ILIM- R_{FO D}

When referring to the application diagram shown in Figure 32, R_ILIMis the sum of the R₁and R_FODresistance

(that is, the total resistance from the ILIM pin to GND). R_FODis chosen according to the FOD application note that

can be obtained by contacting your TI representative. This is used to allow the RX implementation to comply with

WPC v1.2 requirements related to received power accuracy.

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Also note that in many applications, the resistor R_OSis needed in order to comply with WPC v1.2 requirements.

In such a case, the offset on the FOD pin from the voltage on R_FODcan cause a shift in the calculation that can

reduce the expected current limit. Therefore, it is always a good idea to check the output current limit after FOD

calibration is performed according to the FOD section shown below. Unfortunately, because the RECT voltage is

not deterministic, and depends on transmitter operation to a certain degree, it is not possible to determine R₁

with R_OSpresent in a deterministic manner.

In this example, set maximum current for the example to be 1000 mA. To set I_ILIM= 1.2 A to allow for the 20%

margin.

840

R_ILIM

=

= 700 W

1.2

(16)

9.2.1.2.4 TERM Resistor

The TERM resistor is used to set the termination threshold on the RX. The device will send an EPT Charge

Complete, or EOC message to the transmitter and thus allow for the system to go into a low standby mode. This

is also mandated through PMA specification.

By picking a resistor to ground from the TERM pin the system designer can set the termination threshold. The

device will send the EPT/EOC message, when the voltage on the ILIM pin goes below the voltage on the TERM

pin. The designer can therefore set a resistor on the TERM pin that will determine the threshold.

V_{ILIM _ TERM}

R ₅

=

50 ì 10^-6

(17)

Typically, one can use R_ILIMto set R₅resistor such that at the desired current, on OUT pin, V_{ILIM_TERM}can be

reached. However, this can be made indeterministic because of the presence of the R_osresistor that is used to

comply with WPC v1.2 FOD requirements. Therefore, the system designer is suggested to measure the voltage

on the ILIM pin at the output current where he would like to set the termination. This voltage on the ILIM pin is

termed as V_{ILIM_TERM}. In the design example, to set 50 mA, measure V_{ILIM_TERM}. After this is done, set the resistor

R₅using the equation Equation 17.

9.2.1.2.5 Setting LPRB1 and LPRB2 Resistors

ëLw9D

R₈

R₃R₄

LPRB1

LPRB2

Figure 33. Setting Low Power Rectifier Boost

LPRB1 and LPRB2 are multifunction pins. Depending on whether the termination resistor is used or not, the

LPRB pins will change function. This allows the designer to optimize the PMA design for efficiency or transient

performance.

Table 20. LPRB Setup for Different Applications

IMPLEMENTATION

Backcover

TERM RESISTOR

Populated

BALL NUMBER F5

LPRB1

BALL NUMBER G6

LPRB2

Embedded

Not populated

WPG

PD_DET

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For more information on how to set the TERM resistor, see TERM Resistor.

The LPRBx boosts the rectifier voltage to a higher voltage, and thus it sets the transmitter in PMA mode to

operate in frequency or load line that can sustain load step which is part of the PMA certification process. LPRB1

is used to boost the rectifier voltage at low power (output current below about 95 mA). LPRB2 is used to boost

the rectifier voltage when output current is below about 310 mA). Both pins are connected to VIREG through

resistors, R₃and R₄as shown in Setting LPRB1 and LPRB2 Resistors. These two values depend on the coil and

the output voltage choice. Also, the allowable voltage drop also defined by the board manufacturer can allow you

to set the voltage in these modes to optimize the efficiency and transient response. To design R₃and R₄, set a

window of V_RECTto boost the operating frequency of the TX a 0-mA load and 100 mA

Good starting points are: 7.3 to 7.8 V for 0 to 100 mA and 6.7 to 7.3 V for 100 to 400 mA

Now, find the values of R₃and R₄that can provide the chosen window. The lower and upper reference of VIREG

is 0.4906 and 0.5318 V

Calculate V_RECTas follows using the TI tool provided in the product folder under the "Tools & sofware" tab.

Figure 34. LPRB Resistor Calculations

9.2.1.2.6 I²C

The I²C lines are used to communicate with the device. In order to enable the I²C, they can be pulled up to an

internal host bus. When not in use as in Figure 55, tie them to GND. The device address is 0x6C.

9.2.1.2.7 Communication Current Limit

Communication current limit allows the device to communicate with the transmitter in an error free manner by

decoupling the coil from load transients on the OUT pin during WPC communication. In some cases this

communication current limit feature is not desirable. In this design, the user enables the communication current

limit. This is done by tying the CM_ILIM pin to GND. In the case that this is not needed, the CM_ILIM pin can be

tied to OUT pin to disable the communication current limit. In this case, take care that the voltage on the

CM_ILIM pin does not exceed the maximum rating of the pin.

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9.2.1.2.8 Receiver Coil

The receiver coil design is the most open and interesting part of the system design. The choice of the receiver

inductance, shape, and materials all intimately influence the parameters themselves in an intertwined manner.

This design can be complicated and involves optimizing many different aspects; refer to the user's guide for the

EVM (SLUUAX6).

The typical choice of the inductance of the receiver coil for a dual mode 5-V solution is between 6 to 8 µH.

9.2.1.2.9 Series and Parallel Resonant Capacitors

Resonant capacitors C₁and C₂are set according to WPC specification. Although this is a dual mode solution,

the PMA does not specify an exact resonance frequency for the resonant capacitors and in fact does not specify

that resonant capacitors are indeed needed.

The equations for calculating the values of the resonant capacitors are shown:

-1

2

é

ù

'

C =

f ´ 2p ´ L

)

S S

(

ê

ú

1

ë

û

-1

é

ù

ú

1û

2

1

C

=

f ´ 2p ´ L -

D

S

ê

(

)

2

C

ê

ë

ú

(18)

9.2.1.2.10 Communication, Boot and Clamp Capacitors

Set C_COMMxto a value ranging from C₁/ 8 to C₁/ 3. The higher the value of the communication capacitors, the

easier it is to comply with PMA specification. However, higher capacitors do lower the overall efficiency of the

system. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V.

Set C_BOOTxto be 15 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of 25 V.

Set C_CLAMPxto be 470 nF. Make sure these are X7R ceramic material and have a minimum voltage rating of

25 V.

34

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

9.2.1.3 Application Curves

Ch1: V_OUT, 1 V

Ch2: V_RECT, 1 V

Ch3: unused

400 ms/Div

Ch1: V_OUT, 1 V

Ch2: V_RECT, 1 V

Ch3: unused

2 ms/Div

Ch4: I_OUT, 200 mA

Figure 35. bq51222 No Load Start-up on a WPC TX

Figure 36. 0-mA to 1000-mA Step on a WPC TX

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

Min

Max

Difference

0

200

400

600

I_OUT(mA)

800

1000

1200

D001

Ch1: V_OUT, 1 V

Ch2: V_RECT, 1 V

Ch3: unused

Ch4: unused

2 ms/Div

Data taken over approximately 3 minutes

Figure 37. 1000-mA to 0-mA Load Dump on a WPC TX

Figure 38. Received Power Variation (mW) vs I_OUT(mA) on

a WPC TX

7.5

700 W

1400 W

7.25

7

6.75

6.5

6.25

6

5.75

5.5

5.25

5

4.75

4.5

4.25

4

0

200

400

600

800

1000

1200

Ch1: TS, 1 V

Ch2: unused

Ch3: unused

Ch4: unused

400 ms/Div

I_OUT(mA)

D001

R_ILIM= 700 Ω

R_ILIM= 1400 Ω

Figure 39. TS Voltage Bias without TS Resistor

Figure 40. Rectifier Regulation on a WPC TX

35

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

90

80

70

60

50

40

30

20

10

0

200

190

180

170

160

150

140

130

120

110

100

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_OUT(A)

1

1.1 1.2

0

200

400

600

I_OUT(mA)

800

1000

1200

D001

V_OUT= 5 V

TX: bq500210EVM-689, RX: bq51222EVM-520

Figure 41. bq51222 WPC Efficiency on a WPC TX

Figure 42. Frequency Range on a WPC TX

5.06

5.04

5.02

5

8

VRECT ASC

VRECT DEC

7.5

7

6.5

6

4.98

4.96

4.94

4.92

4.9

5.5

5

4.5

4

4.88

0

200

400

600

I_OUT(mA)

800

1000

1200

0

200

400

600

I_OUT(mA)

800

1000

1200

D001

D013

R_ILIM= 700 Ω

TX: bq500210EVM-689, RX: bq51222EVM-520

Figure 44. Output Regulation on a WPC TX

Figure 43. Dynamic Regulation on a WPC TX

555

V_{O_REG}

V_RECT

554

553

552

551

550

549

548

547

546

545

2.5

3

3.5

4

4.5

5

Voltage (V)

Ch1: PMA communication, 5 V

Ch2: I_OUT, 1 A

Ch3: V_RECT, 5 V

Ch4: V_OUT, 2 V

50 ms/Div

D015

Figure 46. Startup on a PMA TX

Figure 45. RECT Foldback in Current Limit on a WPC TX

36

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

Ch1: unused

Ch3: V_RECT, 2 V

Ch4: V_OUT, 2 V

2 ms/Div

Ch1: unused

Ch3: V_RECT, 2 V

Ch4: V_OUT, 2 V

2 ms/Div

Ch2: I_OUT, 500 mA

Figure 47. Load Step from 0 mA to 1000 mA on PMA TX

Figure 48. Load Dump from 1000 mA to 0 mA on PMA TX

290

280

270

260

250

240

230

220

210

200

8

Increment

Decrement

7.2

6.4

5.6

4.8

4

3.2

2.4

1.6

0.8

0

With LPRB1 and LPRB2

With LPRB1

Without LPRB1 and LPRB2

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

Load (mA)

I_OUT(mA)

D016

D001

V_OUT= 5 V

TX: Duracell Powermat, RX: bq51222EVM-520

Figure 49. Frequency of Operation on a PMA TX

Figure 50. V_RECTon a PMA TX

5.05

5.04

5.03

5.02

5.01

5

4.99

4.98

4.97

4.96

4.95

0

200

400

600

800

1000

1200

I_OUT(mA)

Ch1: unused

Ch2: unused

Ch3: unused

500 ms/Div

D001

Ch4: TS, 500 mV

Figure 52. Output Voltage Regulation on a PMA TX

Figure 51. TS Measurement on a PMA TX

37

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

5.5

5.0

4.5

4.0

3.5

3.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V_OUT(V)

C001

PMA mode, operating in current limit

I_ILIM= 1 A

Figure 53. V_RECTTracks V_OUT

38

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

9.2.2 Embedded in System Board

When the bq51222 device is implemented as an embedded device on the system board, LPRBEN (TERM) pin is

floated and WPG and PD_DET are set to their function. When LPRBEN has a resistor to ground to enable

TERM, PD_DET becomes LPRB1 and WPG becomes LPRB2. This second configuration with TERM enabled is

preferred for a back cover implementation. A back cover implementation is one where the receiver device and

receiver coil are contained in the back cover of the mobile phone where the receiver is being implemented. With

an embedded implementation (one where only the coil is in the mobile device back cover and the receiver device

is on the main motherboard for the mobile phone and is controlled by the host controller device in the phone), the

expectation is that the host controller (PMIC or Charger) will use the TS/CTRL pin to establish termination and

associated EPT or EOC.

{ystem

[oad

v1

bq51222

AD-EN

!ꢀ

hÜÇ

C_COMM1

C₄

C₃

/hꢂꢂ1

.hhÇ1

!/1

w9/Ç

C_BOOT1

R₇

R₆

w9/Ç

C₁

R₉

R₈

ëh_w9D

ëLw9D

C₂

COIL

!/2

.hhÇ2

/hꢂꢂ2

Ç{ꢁ/Çw[

Çꢂ9ꢂ

C_BOOT2

z

Ih{Ç

NTC

C_COMM2

C_CLAMP2

C_CLAMP1

/[!ꢂꢃ2

/[!ꢂꢃ1

C₅

WPG

DꢃLh

PD_DET

{/[

[ꢃw.9ꢄ

{/[

{ꢀ!

/ꢂ_L[Lꢂ

ꢃDꢄꢀ

Chꢀ

L[Lꢂ

R₁

R_OS

w9/Ç

R_FOD

Figure 54. bq51222 Embedded in a System Board

Refer to Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current for

all design details.

39

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

9.2.3 bq51222 Implemented in Back Cover

When the bq51222 device is implemented as a back cover solution, set TERM resistor to enable PMA term and

LPRB1 and LPRB2 functions are automatically enabled. In this implementation, the bq51222 device can

autonomously determine if EOC can be established because the termination current has been reached. In this

configuration, PD_DET becomes LPRB1 and WPG becomes LPRB2. This allows the RECT voltage to be

controlled at different levels so that transient performance from light load to maximum current can be optimized.

bq51222

System

AD-EN

Load

AD

OUT

C_COMM1

C₄

C₃

COMM1

BOOT1

AC1

C_BOOT1

R₇

R₆

RECT

C₁

VO_REG

VIREG

R₉

R₈

C₂

COIL

AC2

BOOT2

COMM2

TS/CTRL

TMEM

C_BOOT2

z

HOST

NTC R₃R₄

C_COMM2

C_CLAMP2

C_CLAMP1

CLAMP2

CLAMP1

C₅

LPRB1

LPRB2

SCL

TERM

SDA

CM_ILIM

PGND

FOD

ILIM

R₅

R₁

R_OS

RECT

R_FOD

Figure 55. bq51222 Implemented in a Back Cover

Refer to Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current for

all design details.

40

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

10 Power Supply Recommendations

These devices are intended to be operated within the ranges shown in the Recommended Operating Conditions.

Because the system involves a loosely coupled inductor set up, the voltages produced on the receiver are a

function of the inductances and the available magnetic field. Ensure that the design in the worst case keeps the

voltages within the Absolute Maximum Ratings.

41

bq51222

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

•

Keep the trace resistance as low as possible on AC1, AC2, and OUT.

Detection and resonant capacitors need to be as close to the device as possible.

COMM, CLAMP, and BOOT capacitors need to be placed as close to the device as possible.

Via interconnect on GND net is critical for appropriate signal integrity and proper thermal performance.

High frequency bypass capacitors need to be placed close to RECT and OUT pins.

ILIM and FOD resistors are important signal paths and the loops in those paths to GND must be minimized.

Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually

measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being

interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main

source of noise in the board. These traces should be shielded from other components in the board. It is

usually preferred to have a ground copper area placed underneath these traces to provide additional

shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB should have a

ground plane (return) connected directly to the return of all components through vias (two vias per capacitor

for power-stage capacitors, one via per capacitor for small-signal components).

For a 1-A fast charge current application, the current rating for each net is as follows:

•

AC1 = AC2 = 1.2 A

OUT = 1 A

RECT = 100 mA (RMS)

COMMx = 300 mA

CLAMPx = 500 mA

All others can be rated for 10 mA or less

11.2 Layout Example

Keep the trace

AD is also a

power trace.

resistance as

low as possible

on AC1, AC2,

and OUT.

Isolate noisy

traces using

GND trace.

Place signal and

sensing

components as

close as possible

to the IC.

Place detection

and resonant

capacitors Cd

and Cs here.

Place COMM,

CLAMP, and

BOOT capacitors

as close as

possible to the IC

terminals.

It is always a good

practice to place high

frequency bypass

capacitors next to RECT

and OUT.

The via interconnect is important and

must be optimized near the power pad

of the IC and the GND for good thermal

dissipation.

42

bq51222

www.ti.com.cn

ZHCSFC3A –JULY 2016–REVISED AUGUST 2016

12 器件和文档支持

12.1 器件支持

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本

文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

43

重要声明

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TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ51222YFPR

BQ51222YFPT

DSBGA

YFP

42

3000

250

330.0

12.4

2.99

3.71

0.81

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ51222YFPR

BQ51222YFPT

DSBGA

YFP

42

3000

250

335.0

25.0

Pack Materials-Page 2

PACKAGE OUTLINE

YFP0042

DSBGA - 0.5 mm max height

S

C

A

L

E

4

.

7

0

DIE SIZE BALL GRID ARRAY

B

E

A

BUMP A1

CORNER

D

C

0.5 MAX

SEATING PLANE

0.05 C

BALL TYP

0.19

0.13

2 TYP

SYMM

G

F

E

D: Max = 3.586 mm, Min =3.526 mm

E: Max = 2.874 mm, Min =2.814 mm

SYMM

2.4

D

C

TYP

0.3

0.2

42X

B

A

0.015

C A

B

0.4 TYP

2

3

4

5

6

1

0.4 TYP

4221555/B 04/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFP0042

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

3

42X ( 0.23)

(0.4) TYP

4

1

6

2

5

A

B

C

SYMM

D

E

F

G

SYMM

LAND PATTERN EXAMPLE

SCALE:25X

0.05 MAX

0.05 MIN

METAL

UNDER

(

0.23)

METAL

SOLDER MASK

(

0.23)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221555/B 04/2015

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFP0042

DSBGA - 0.5 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

42X ( 0.25)

(R0.05) TYP

4

1

2

3

5

6

A

(0.4)

TYP

B

C

METAL

TYP

SYMM

D

E

F

G

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4221555/B 04/2015

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	BQ51222YFPR
厂家：	TEXAS INSTRUMENTS
描述：	双模式 5W（WPC v1.2 和 PMA）单芯片无线电源接收器 \| YFP \| 42 \| -40 to 125 PC 无线
文件：	总52页 (文件大小：1681K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ51222YFPR [TI]

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