BQ7692000PWR [TI]
3 至 5 节电池锂离子和锂磷酸盐电池监视器（bq76940 系列） | PW | 20 | -40 to 85;
| 型号： | BQ7692000PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 至 5 节电池锂离子和锂磷酸盐电池监视器（bq76940 系列） | PW | 20 | -40 to 85 电池 监视器 光电二极管 |
| 文件： | 总69页 (文件大小：3092K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ76920, BQ76930, BQ76940
ZHCSCE2I –OCTOBER 2013 –REVISED MARCH 2022
用于锂离子电池和磷酸盐电池的BQ769x0 3 节至15 节串联、电池监控器系列
1 特性
3 说明
• AFE 监控特性
BQ769x0 可靠的模拟前端 (AFE) 器件系列是针对下一
代高功率系统（如轻型电动车辆、电动工具和不间断电
源）的完整电池组监控与保护解决方案的组成部分。
BQ769x0 专为实现低功耗而设计：不仅可通过启用/禁
用 IC 中的子块来控制整个芯片的电流消耗，还可以利
用运输模式将电池组轻松切换至超低功耗状态。
– 纯数字接口
– 内部模数转换器(ADC) 用于测量电池电压、芯
片温度和外部热敏电阻
– 一个单独的、内部ADC 测量电池组电流（库伦
电荷计数器）
– 直接支持多达三个热敏电阻(103AT)
• 硬件保护特性
BQ76920 器件支持多达5 节串联电池或典型值为 18 V
的电池组，BQ76930 可处理多达 10 节串联电池或典
型值为 36 V 的电池组，而 BQ76940 支持多达 15 节
串联电池或典型值为 48 V 的电池组。可借助这些 AFE
管理各种电池化学物质，例如锂离子、磷酸铁锂等。通
过 I2C，主机控制器可以使用 BQ769x0 来执行多种电
池组管理功能，例如监控（电池电压、电池组电流、电
池组温度）、保护（控制充电/放电 FET）以及平衡功
能。集成式模数 (A/D) 转换器可实现对关键系统参数的
纯数字读取，并会在TI 制造过程中校准这些参数。
– 放电过流(OCD)
– 放电短路(SCD)
– 过压(OV)
– 欠压(UV)
– 次级保护器故障检测
• 其他特性
– 集成电池均衡场效应晶体管(FET)
– 充电、放电低侧NCH FET 驱动器
– 到主机微控制器的警报中断
– 2.5 V 或3.3 V 输出电压稳压器
– 无需EEPROM 编程
– 高电源电压绝对最大值（高达108V）
– 可兼容I2C 的简单接口（CRC 选项）
– 可容忍电池随机连接
器件信息
器件型号1
BQ76920
封装尺寸（标称值）
6.50mm × 4.40mm
7.80mm x 4.40mm
11.00mm x 4.40mm
封装
TSSOP (20)
TSSOP (30)
TSSOP (44)
BQ76930
BQ76940
2 应用
• 轻型电动车辆(LEV)：电动自行车、电动踏板车、
脚踏电动自行车和踏板辅助自行车
• 电动工具和园艺工具
• 电池备份单元(BBUS)、储能系统(ESS) 和不间断
电源(UPS) 系统
• 其他工业电池组(≥10S)
PACK
+
Rf
BAT
VC
VC
VC
VC
VC
VC
5
4
3
2
1
0
REGSRC
REGOUT
Rc
Rc
Rc
Rc
Rc
Cc
Cc
Cc
CAP
1
10 kΩ
TS 1
1 µF
1
µF
4.7 µF
Cf
SCL
SDA
VSS
CHG
DSG
10
k
SRP
SRN
PUSH
- BUTTON FOR BOOT
Cc
Cc
ALERT
VCC
SCL
Companion
Controller
SDA
GPIO
VSS
Cc
1 M
Rc
0 .1 µF
100
0 .1 µF
0 .1 µF
100
1 M
1 M
Rsns
PACK
–
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSBK2
BQ76920, BQ76930, BQ76940
ZHCSCE2I –OCTOBER 2013 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................28
8.5 Register Maps...........................................................30
9 Application and Implementation..................................40
9.1 Application Information............................................. 40
9.2 Typical Applications ................................................. 43
10 Power Supply Recommendations..............................48
11 Layout...........................................................................50
11.1 Layout Guidelines................................................... 50
11.2 Layout Example...................................................... 50
12 Device and Documentation Support..........................52
12.1 第三方产品免责声明................................................52
12.2 Documentation Support.......................................... 52
12.3 Related Links.......................................................... 52
12.4 Receiving Notification of Documentation Updates..52
12.5 Trademarks.............................................................52
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
6.1 Versions...................................................................... 3
6.2 BQ76920 Pin Diagram................................................4
6.3 BQ76930 Pin Diagram................................................5
6.4 BQ76940 Pin Diagram................................................6
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings........................................ 8
7.2 ESD Ratings............................................................... 8
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information..................................................10
7.5 Electrical Characteristics...........................................10
7.6 Timing Requirements................................................14
7.7 Typical Characteristics..............................................15
8 Detailed Description......................................................17
8.1 Overview...................................................................17
Information.................................................................... 52
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision H (March 2019) to Revision I (March 2022)
Page
• 通篇更改了格式...................................................................................................................................................1
• Added VCn rows in Absolute Maximum Ratings table....................................................................................... 8
• Changed tablenote for POR and referenced entries........................................................................................ 10
• Changed the scale in the VCx and OV Protection plots .................................................................................. 15
• Updated 16-Bit Pack Voltage ...........................................................................................................................22
• Changed "OV Trip" to "UV Trip" in the description of undervoltage protection.................................................22
• Changed the LSB bit count from 2 to 4 for the OV_TRIP register....................................................................31
• Updated Application Information ......................................................................................................................40
• Added Device Timing .......................................................................................................................................40
• Added Random Cell Connection ..................................................................................................................... 40
• Added Power Pin Diodes .................................................................................................................................40
• Added Alert Pin ................................................................................................................................................40
• Added Sense Inputs ........................................................................................................................................ 40
• Added TSn Pins ...............................................................................................................................................40
• Updated Unused Pins ......................................................................................................................................41
• Updated Step-by-Step Design Procedure ....................................................................................................... 47
Changes from Revision G (April 2016) to Revision H (March 2019)
Page
• 更改了应用.........................................................................................................................................................1
• 更改了说明.........................................................................................................................................................1
• Added High-Side FET Driving ..........................................................................................................................24
• Added the link to the BQ769x0 Boot Switch Alternatives Application Report ..................................................28
• Added the link to the BQ769x0 Family Top Design Considerations Application Report ..................................40
• Added 图9-4 to provide an example of a high-side FET configuration............................................................ 43
• Added BQ769x0 Family Top Design Considerations Application Report link...................................................48
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ZHCSCE2I –OCTOBER 2013 –REVISED MARCH 2022
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5 Device Comparison Table
I2C ADDRESS (7-
Bit)
TUBE
TAPE & REEL
CELLS
LDO (V)
CRC
PACKAGE
BQ7692000PW
BQ7692001PW(1)
BQ7692002PW(1)
BQ7692003PW
BQ7692006PW
BQ7693000DBT
BQ7693001DBT
BQ7693002DBT
BQ7693003DBT
BQ7693006DBT
BQ7693007DBT
BQ7694000DBT
BQ7694001DBT
BQ7694002DBT
BQ7694003DBT
BQ7694006DBT
BQ7692000PWR
BQ7692001PWR(1)
BQ7692002PWR(1)
BQ7692003PWR
BQ7692006PWR
BQ7693000DBTR
BQ7693001DBTR
BQ7693002DBTR
BQ7693003DBTR
BQ7693006DBTR
BQ7693007DBTR
BQ7694000DBTR
BQ7694001DBTR
BQ7694002DBTR
BQ7694003DBTR
BQ7694006DBTR
No
Yes
No
2.5
0x08
0x18
0x08
20-TSSOP (PW)
3–5
3.3
2.5
Yes
No
No
Yes
No
30-TSSOP (DBT)
6–10
Yes
No
3.3
0x18
Yes
No
2.5
3.3
Yes
No
0x08
0x18
44-TSSOP (DBT)
9–15
Yes
No
(1) Product Preview only
Texas Instruments preconfigures the BQ769x0 devices for a specific I2C address, LDO voltage, and more.
These settings are permanently stored in EEPROM and cannot be further modified.
Contact Texas Instruments for other options not listed above, as well as any options noted as “Product Preview
only.”
6 Pin Configuration and Functions
6.1 Versions
ALERT
DSG
CHG
1
2
3
4
5
6
7
8
9
DSG
CHG
1
2
20 ALERT
DSG
CHG
1
2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
44 ALERT
43 SRN
42 SRP
41 VC0
SRN
SRP
VC0
VC1
VC2
VC3
19
18
17
16
15
14
13
12
11
SRN
SRP
VC0
VC1
VC2
VC3
VSS
VSS
3
VSS
3
SDA
SDA
4
SDA
4
SCL
SCL
SCL
VC1
VC2
5
5
40
39
20-TSSOP
TS1
TS1
TS1
6
6
CAP1
REGOUT
REGSRC
BAT
CAP1
REGOUT
REGSRC
VC5x
NC
CAP1
REGOUT
REGSRC
38 VC3
37 VC4
36 VC5
35 VC5B
34 VC6
33 VC7
32 VC8
31 VC9
30 VC10
7
7
VC4
VC5
NC
8
8
VC4
VC5
VC5B
VC6
VC7
VC8
VC9
VC10
30-TSSOP
9
9
VC5x 10
NC 11
NC 12
10
10
11
12
13
44-TSSOP
NC
13
14
15
16
17
18
TS2
TS2
CAP2
VC10x
NC
CAP2 14
BAT 15
29
28
27
VC10B
VC11
VC12
NC
TS3
CAP3 19
BAT 20
26 VC13
25 VC14
24 VC15
23 NC
NC 21
NC 22
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ZHCSCE2I –OCTOBER 2013 –REVISED MARCH 2022
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BQ76920: 3–5 Series Cells (20-TSSOP)
• 6.5 mm x 4.4 mm x 1.2 mm
BQ76930: 6–10 Series Cells (30-TSSOP)
• 7.8 mm x 4.4 mm x 1.2 mm
BQ76940: 9–15 Series Cells (44-TSSOP)
• 11.3 mm x 4.4 mm x 1.2 mm
6.2 BQ76920 Pin Diagram
DSG
CHG
1
2
20 ALERT
SRN
SRP
VC0
VC1
VC2
VC3
19
18
17
16
15
14
13
12
11
VSS
3
SDA
4
SCL
5
20-TSSOP
TS1
6
CAP1
REGOUT
REGSRC
BAT
7
VC4
VC5
NC
8
9
10
表6-1. BQ76920 Pin Functions
PIN
1
NAME
DSG
CHG
VSS
TYPE
DESCRIPTION
O
O
Discharge FET driver
Charge FET driver
Chip VSS
2
3
—
I/O
I
4
SDA
I2C communication to the host controller
I2C communication to the host controller
Thermistor #1 positive terminal(1)
Capacitor to VSS
5
SCL
6
TS1
I
7
CAP1
REGOUT
REGSRC
BAT
O
P
I
8
Output LDO
9
Input source for output LDO
10
11
12
13
14
15
16
17
18
19
20
P
Battery (top-most) terminal
NC
No connect
—
VC5
I
Sense voltage for 5th cell positive terminal
Sense voltage for 4th cell positive terminal
Sense voltage for 3rd cell positive terminal
Sense voltage for 2nd cell positive terminal
Sense voltage for 1st cell positive terminal
Sense voltage for 1st cell negative terminal
Negative current sense (nearest VSS)
Positive current sense
VC4
I
VC3
I
VC2
I
VC1
I
VC0
I
I
SRP
SRN
I
ALERT
I/O
Alert output and override input
(1) If not used, pull down to VSS with a 10-kΩnominal resistor.
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6.3 BQ76930 Pin Diagram
ALERT
DSG
CHG
1
2
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRN
SRP
VC0
VC1
VC2
VC3
VSS
3
SDA
4
SCL
5
TS1
6
CAP1
REGOUT
REGSRC
VC5x
NC
7
30-TSSOP
8
VC4
VC5
VC5B
VC6
VC7
VC8
VC9
VC10
9
10
11
12
13
NC
TS2
CAP2 14
BAT 15
表6-2. BQ76930 Pin Functions
PIN
1
NAME
DSG
CHG
VSS
TYPE
DESCRIPTION
O
O
Discharge FET driver
Charge FET driver
Chip VSS
2
3
—
I/O
I
4
SDA
I2C communication to the host controller
I2C communication to the host controller
Thermistor #1 positive terminal(1)
Capacitor to VSS
5
SCL
6
TS1
I
7
CAP1
REGOUT
REGSRC
VC5X
NC
O
P
I
8
Output LDO
9
Input source for output LDO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P
Thermistor #2 negative terminal
No connect (short to CAP2)
—
—
I
NC
No connect (short to CAP2)
TS2
Thermistor #2 positive terminal(1)
CAP2
BAT
O
P
I
Capacitor to VC5X
Battery (top-most) terminal
VC10
VC9
Sense voltage for 10th cell positive terminal
Sense voltage for 9th cell positive terminal
Sense voltage for 8th cell positive terminal
Sense voltage for 7th cell positive terminal
Sense voltage for 6th cell positive terminal
Sense voltage for 6th cell negative terminal
Sense voltage for 5th cell positive terminal
Sense voltage for 4th cell positive terminal
Sense voltage for 3rd cell positive terminal
Sense voltage for 2nd cell positive terminal
Sense voltage for 1st cell positive terminal
I
VC8
I
VC7
I
VC6
I
VC5B
VC5
I
I
VC4
I
VC3
I
VC2
I
VC1
I
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表6-2. BQ76930 Pin Functions (continued)
PIN
27
28
29
30
NAME
VC0
TYPE
DESCRIPTION
Sense voltage for 1st cell negative terminal
Negative current sense (nearest VSS)
Positive current sense
I
I
SRP
SRN
I
ALERT
I/O
Alert output and override input
(1) If not used, pull down to group ground reference (VSS for TS1 and VC5X for TS2) with a 10-kΩnominal resistor.
6.4 BQ76940 Pin Diagram
DSG
CHG
1
2
3
4
5
6
7
8
9
44 ALERT
43 SRN
42 SRP
41 VC0
VSS
SDA
SCL
VC1
VC2
40
39
TS1
CAP1
REGOUT
REGSRC
38 VC3
37 VC4
36 VC5
35 VC5B
34 VC6
33 VC7
32 VC8
31 VC9
30 VC10
VC5x 10
NC 11
NC 12
44-TSSOP
13
14
15
16
17
18
TS2
CAP2
VC10x
NC
29
28
27
VC10B
VC11
VC12
NC
TS3
CAP3 19
BAT 20
26 VC13
25 VC14
24 VC15
23 NC
NC 21
NC 22
BQ76940 Pin Functions
PIN
1
NAME
DSG
TYPE
O
DESCRIPTION
Discharge FET driver
Charge FET driver
Chip VSS
2
CHG
O
3
VSS
—
I/O
I
4
SDA
I2C communication to the host controller
I2C communication to the host controller
Thermistor #1 positive terminal(1)
Capacitor to VSS
5
SCL
6
TS1
I
7
CAP1
REGOUT
REGSRC
VC5X
NC
O
P
I
8
Output LDO
9
Input source for output LDO
Thermistor #2 negative terminal
No connect (short to CAP2)
No connect (short to CAP2)
10
11
12
P
—
—
NC
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BQ76940 Pin Functions (continued)
PIN
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NAME
TS2
TYPE
DESCRIPTION
I
Thermistor #2 positive terminal(1)
Capacitor to VC5X
CAP2
VC10X
NC
O
P
Thermistor #3 negative terminal
No connect (short to CAP3)
No connect (short to CAP3)
Thermistor #3 positive terminal(1)
Capacitor to VC10X
—
—
I
NC
TS3
CAP3
BAT
O
P
Battery (top-most) terminal
No connect
NC
—
NC
No connect
—
NC
No connect
—
VC15
VC14
VC13
VC12
VC11
VC10B
VC10
VC9
I
Sense voltage for 15th cell positive terminal
Sense voltage for 14th cell positive terminal
Sense voltage for 13th cell positive terminal
Sense voltage for 12th cell positive terminal
Sense voltage for 11th cell positive terminal
Sense voltage for 11th cell negative terminal
Sense voltage for 10th cell positive terminal
Sense voltage for 9th cell positive terminal
Sense voltage for 8th cell positive terminal
Sense voltage for 7th cell positive terminal
Sense voltage for 6th cell positive terminal
Sense voltage for 6th cell negative terminal
Sense voltage for 5th cell positive terminal
Sense voltage for 4th cell positive terminal
Sense voltage for 3rd cell positive terminal
Sense voltage for 2nd cell positive terminal
Sense voltage for 1st cell positive terminal
Sense voltage for 1st cell negative terminal
Negative current sense (nearest VSS)
Positive current sense
I
I
I
I
I
I
I
VC8
I
VC7
I
VC6
I
VC5B
VC5
I
I
VC4
I
VC3
I
VC2
I
VC1
I
VC0
I
I
SRP
SRN
ALERT
I
I/O
Alert output and override input
(1) If not used, pull down to group ground reference (VSS for TS1, VC5X for TS2, and VC10X for TS3) with a 10-kΩnominal resistor.
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7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
BQ76920
BQ76930
BQ76940
(BAT–VSS)
VBAT
Supply voltage
Input voltage
Output voltage
36
V
(BAT–VC5x), (VC5x–VSS)
–0.3
(BAT–VC10x), (VC10x–VC5x), (VC5x–VSS)
BQ76920,
BQ76930,
BQ76940
(n × 7.2)
(VCn–VSS) where n = 1..5
BQ76930,
BQ76940
(n–5) ×
V
V
–0.3
–0.3
(VCn-VC5x) where n = 6..10
7.2
(n–10) ×
BQ76940
(VCn–VC10x) where n = 11..15
7.2
Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5
9
(BQ76940/BQ76930/BQ76920, respectively)
VI
SRN, SRP, SCL, SDA
(VC0–VSS), (CAP1–VSS), (TS1–VSS)(2)
BQ76920
(VC0–VSS), (VC5b–VC5x), (CAP2–VC5x),
(CAP1–VSS), (TS2–VC5x), (TS1–VSS)(2)
BQ76930
BQ76940
3.6
–0.3
V
(VC0–VSS), (VC5b–VC5x), (VC10b–VC10x),
(CAP3–VC10x), (CAP2–VC5x), (CAP1–VSS),
(TS3–VC10x), (TS2–VC5x), (TS1–VSS)(2)
REGSRC
REGOUT, ALERT
DSG
36
3.6
–0.3
–0.3
–0.3
–0.3
VO
20
V
CHG
VCHGCLAMP
BQ76920
70
mA
mA
mA
ICB
Cell balancing current (per cell)
BQ76930,
BQ76940
5
7
IDSG
Discharge pin input current when disabled (measured into terminal)
Storage temperature
150
300
–65
TSTG
°C
Lead temperature (soldering, 10 s)
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The Absolute Maximum Ratings for (TS1–VSS) apply after the device completes POR and should be observed after tBOOTREADY
(10 ms), following the application of the boot signal on TS1. Prior to completion of POR, TS1 should not exceed 5 V.
7.2 ESD Ratings
VALUE
±2
UNIT
kV
V(ESD) Electrostatic
discharge
Human body model (HBM) ESD stress voltage(1)
Charged device model (CDM) ESD stress voltage(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over-operating free-air temperature range (unless otherwise noted). See 节9.1.8 for more information on cell configurations.
All voltages are relative to VSS, except "Cell input differential."
MIN
TYP
MAX
UNIT
BQ76920
BQ76930
(BAT–VSS)
(BAT–VC5x), (VC5x–VSS)
VBAT
Supply voltage
6
25
V
(BAT–VC10x), (VC10x–VC5x),
(VC5x–VSS)
BQ76940
Cell input pins, differential (VCn–VCn–1) where n
= 1..15/10/5 (BQ76940/BQ76930/BQ76920,
respectively), in-use cells only
2
0
5
V
V
BQ76920
(VCn–VSS) where n = 1..5
(VCn–VSS) where n = 1..5,
(VCn–VC5x) where n = 6..10
BQ76930
5 × n
(VCn–VSS) where n = 1..5,
(VCn–VC5x) where n = 6..10,
(VCn–VC10x) where n = 11..15
BQ76940
SRP
BQ76920
BQ76930
(VC0–VSS)
VIN
Input voltage
10
200
3.6
mV
mV
–10
–200
0
(VC0–VSS), (VC5b–VC5x)
(VC0–VSS), (VC5b–VC5x),
(VC10b–VC10x)
BQ76940
SRN
SCL, SDA
BQ76920
BQ76930
(TS1–VSS)
(TS1–VSS), (TS2–VC5x)
V
(TS1–VSS), (TS2–VC5x),
(TS3–VC10x)
BQ76940
REGSRC
6
0
25
16
CHG, DSG
V
V
REGOUT, ALERT
(CAP1–VSS)
BQ76920
BQ76930
VOUT
Output voltage
0
3.6
(CAP1–VSS), (CAP2–VC5x)
(CAP1–VSS), (CAP2–VC5x),
(CAP3–VC10x)
BQ76940
Cell balancing
current (internal, per
cell)
BQ76920
0
0
50
5
mA
mA
ICB
BQ76930, BQ76940
BQ76920
40
500
0.1
40
100
1K
1
1K
1K
10
1K
40
Ω
Ω
µF
External cell input
resistance
RC
BQ76930, BQ76940
CC
Rf
External cell input capacitance
External supply filter resistance
External supply filter capacitance
Sense resistor filter resistance
100
10
Ω
Cf
1
µF
RFILT
100
1K
1M
4.7
Ω
Ω
RALERT ALERT pin to VSS resistor
CL
REGOUT loading capacitance
1
1
µF
µF
CCAP
RTS
REGSRC, CAP1, CAP2, and CAP3 output capacitance
External thermistor nominal resistance (103AT) at 25°C
10K
Ω
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Over-operating free-air temperature range (unless otherwise noted). See 节9.1.8 for more information on cell configurations.
All voltages are relative to VSS, except "Cell input differential."
MIN
TYP
MAX
UNIT
TOPR
Operating free-air temperature
85
°C
–40
7.4 Thermal Information
Over-operating free-air temperature range (unless otherwise noted)
TSSOP
THERMAL METRIC(1)
BQ76920xy
UNIT
BQ76930xy
BQ76940xy
20 PINS (PW)
30 PINS (DBT)
44 PINS (DBT)
RθJA, High K Junction-to-ambient thermal resistance
93.7
28.7
44.6
1.3
86.5
19.4
41.3
0.5
70.1
17.5
33.9
0.5
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
44.1
40.6
33.4
ψJB
Rθ
Junction-to-case(bottom) thermal resistance
n/a
n/a
n/a
°C/W
JC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report (SPRA953).
7.5 Electrical Characteristics
Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940)
with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to
+85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition
sections.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
NORMAL mode: ADC off,
CC off
40
60
60
90
NORMAL mode: ADC on,
CC off
Sum of ICC_BAT and ICC_REGSRC
currents
IDD
NORMAL mode: ADC off,
CC on
110
130
165
195
NORMAL mode: ADC on,
CC on
µA
NORMAL mode: ADC off
NORMAL mode: ADC on
NORMAL mode: CC off
NORMAL mode: CC on
30
50
10
80
45
75
ICC_BAT
Into BAT pin
15
ICC_REGSRC
Into REGSRC pin
120
Device in full shutdown, only VSTUP/BG
and BOOT detector on
ISHIP
SHIP/SHUTDOWN mode
0.6
1.8
LEAKAGE AND OFFSET CURRENTS
NORMAL mode supply
current offset
dINOM
±2.5
±0.1
15
5
1.0
25
–5
Measured into VC5x (BQ76930,
BQ76940) and VC10x (BQ76940)
SHIP mode supply current
dISHIP
offset
–1.0
Supply current when
ALERT active
Measured into VC5x (BQ76930,
BQ76940) or added to BAT (BQ76920)
dIALERT
µA
Measured into VC0–VC15 except VC5,
VC10, VC15
±0.1
0.3
–0.3
Cell measurement input
current
dICELL
Measured into VC5, VC10, VC15
0.5
1
ILKG
10
Terminal input leakage
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7.5 Electrical Characteristics (continued)
Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940)
with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to
+85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition
sections.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INTERNAL POWER CONTROL (STARTUP and SHUTDOWN)
VPORA
VSHUT
Analog POR threshold
Shutdown voltage
VBAT rising. See (4)
VBAT falling. See (4)
.
4
5
V
V
.
3.6
Time delay after boot
Delay after boot sequence when I2C
communication is allowed
tI2CSTARTUP
signal on TS1 before I2C
communications allowed
1
ms
Delay after boot signal when device has
completed full boot-up sequence
tBOOTREADY
TSHUTD
Device boot startup delay
Thermal shutdown voltage
10
ms
°C
100
250
150
MEASUREMENT SCHEDULE
Cell voltage measurement
interval
tVCELL
BQ76920, BQ76930, BQ76940
Per cell, balancing off
Per cell, balancing on
50
Individual cell
measurement time
tINDCELL
12.5
Cell balancing relaxation
time before cell voltage
measured
ms
tCB_RELAX
12.5
Temperature measurement Measurement duration for temperature
tTEMP_DEC
tBAT
12.5
250
2
decimation time
reading
Pack voltage calculation
interval
Temperature measurement Period of measurement of either
interval TS1/TS2/TS3 or internal die temp
tTEMP
s
14-BIT ADC FOR CELL VOLTAGE AND TEMPERATURE MEASUREMENT
ADC measurement
recommend operation
range
VCELL measurements
2
5
3
V
V
ADCRANGE
ADCLSB
TS/Temp measurements
0.3
ADC LSB value
382
±10
±15
±25
±20
±25
±35
µV
VCELL = 3.6 V –4.3 V
VCELL = 3.2 V –4.6 V
VCELL = 2.0 V –5.0 V
VCELL = 3.6 V –4.3 V
VCELL = 3.2 V –4.6 V
VCELL = 2.0 V –5.0 V
VCELL = 3.6 V –4.3 V
VCELL = 3.2 V –4.6 V
VCELL = 2.0 V –5.0 V
ADC cell voltage accuracy
at 25°C
ADC cell voltage accuracy
0°C to 60°C
ADC
mV
40
40
50
–40
–40
–50
ADC cell voltage accuracy
–40°C to 85°C
16-BIT CC FOR PACK CURRENT MEASUREMENT
CCRANGE
CCFSR
CC input voltage range
CC full scale range
CC LSB value
200
270
mV
mV
µV
–200
–270
CCLSB
CC running constantly
Single conversion
8.44
250
tCCREAD
Conversion time
ms
16-bit, best fit over input voltage range ±
200 mV
CCINL
Integral nonlinearity
Offset error
± 2
± 1
± 40
± 3
LSB
LSB
CCOFFSET
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7.5 Electrical Characteristics (continued)
Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940)
with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to
+85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition
sections.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CCGAIN
Gain error
Over input voltage range
± 0.5%
± 1.5%
FSR
CCGAINDRIFT
CCRIN
Gain error drift
Effective input resistance
Over input voltage range
150 PPM / °C
2.5
10
MΩ
THERMISTOR BIAS
RTS
Pull-up resistance
TA = 25°C
9.85
9.7
10.15
kΩ
kΩ
Pull-up resistance across
temp
RTSDRIFT
10.3
TA = –40°C to 85°C
DIETEMP
VDIETEMP25
Die temperature voltage
TA = 25°C
1.20
V
Die temperature voltage
drift
VDIETEMPDRIFT
mV/°C
–4.2
INTEGRATED HARDWARE PROTECTIONS
OVRANGE
UVRANGE
OV threshold range
UV threshold range
0x2008
0x1000
0x2FF8
0x1FF0
ADC
ADC
OV and UV threshold step
size
OVUVSTEP
UVMINQUAL
16
LSB
UV minimum value to
qualify
Below UVMINQUAL, the cell is shorted
(unused)
0x0518
ADC
OV delay = 1 s
OV delay = 2 s
OV delay = 4 s
OV delay = 8 s
UV delay = 1 s
UV delay = 4 s
UV delay = 8 s
UV delay = 16 s
Measured across (SRP–SRN)(2)
RSNS = 0
0.7
1.6
3.5
7
1
2
1.75
2.75
5
OVDELAY
OV delay timer options
UV delay timer options
4
8
10
s
0.7
3.5
7
1
1.75
5
4
UVDELAY
8
10
14
8
16
20
OCDRANGE
OCDSTEP
OCD threshold options
OCD threshold step size
100
mV
mV
mV
ms
mV
mV
mV
µs
2.78
5.56
RSNS = 1
OCDDELAY
SCDRANGE
OCD delay options
See Note(3)
8
1280
200
Measured across (SRP–SRN)(2)
RSNS = 0
SCD threshold options
22
11.1
22.2
70
SCDSTEP
SCD threshold step size
RSNS = 1
35
50
105
150
260
520
20%
100
200
400
µs
SCDDELAY
SCD delay options
140
µs
280
µs
tPROTACC
Delay accuracy for OCD
–20%
OCD and SCD voltage
offset
OCOFFSET
2.5
mV
–2.5
OCD and SCD scale
accuracy
OCSCALEERR
10%
–10%
CHARGE AND DISCHARGE DRIVERS
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7.5 Electrical Characteristics (continued)
Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940)
with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to
+85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition
sections.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
REGSRC ≥12 V with load resistance of
10 MΩ
10
12
14
V
VFETON
CHG and DSG on
REGSRC < 12 V with load resistance of
10 MΩ
REGSRC
REGSRC –
REGSRC
250
V
–2
1
CHG/DSG driving an equivalent load
capacitance of 10 nF, measured from
10% to 90% of VFETON
CHG and DSG ON rise
time
tFET_ON
200
µs
DSG driving an equivalent load
capacitance of 10 nF, measured from
90% to 10%
DSG pull-down OFF fall
time
tDSG_OFF
60
90
µs
CHG pull-down OFF
resistance to VSS
RCHG_OFF
When CHG disabled, CHG held at 12 V
When DSG disabled, DSG held at 12 V
750
1000
1250
kΩ
DSG pull-down OFF
resistance to VSS
RDSG_OFF
1.75
0.4
2.50
0.7
4.25
1.0
kΩ
VLOAD_DETECT
Load detection threshold
V
If the CHG pin externally pulled high
(through PACK–, if load applied), 500-
µA max sink current into CHG pin. With
CHG_ON bit cleared.
VCHG_CLAMP
CHG clamp voltage
18
20
22
V
ALERT PIN
REGOUT x
0.75
VALERT_OH
ALERT output voltage high IOL = 1 mA
ALERT output voltage low Unloaded
V
V
REGOUT
x 0.25
VALERT_OL
VALERT_IH
RALERT_PD
ALERT externally forced high when
internally driven low. See note (1)
ALERT input high
1
1.5
8
V
.
ALERT pin weak pulldown Measured into ALERT pin with ALERT =
resistance when driven low REGOUT
0.8
2.5
MΩ
CELL BALANCING DRIVER
Internal cell balancing
RDSFET
VCELL = 3.6 V
Every 250 ms
1
5
10
Ω
driver resistance
Cell balancing duty cycle
when enabled
XBAL
70%
EXTERNAL REGULATOR
2.45
3.20
2.50
3.30
2.55
3.40
V
V
External LDO voltage
options
Nominal values, TI factory programmed,
unloaded, across temp
VEXTLDO
REGSRC pin stepped from 6 to 25 V,
with 10-mA load, in 100 µs
VEXTLDO_LN
VEXTLDO_LD
Line regulation
Load regulation
100
4%
mV
IREGOUT = 0 mA to 10 mA
–4%
2.4
REGOUT = 10-mA DC, 2.5-V version
REGOUT = 20-mA DC, 2.5-V version
REGOUT = 10-mA DC, 3.3-V version
REGOUT = 20-mA DC, 3.3-V version
V
V
2.3
External LDO minimum
voltage under DC load
VEXTLDO_DC
3.15
3.05
30
V
V
IEXTLDO_LIMIT
External LDO current limit REGOUT = 0 V
38
45
mA
BOOT DETECTOR
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7.5 Electrical Characteristics (continued)
Typical conditions are measured at 25°C with nominal BAT voltages of 18 V (BQ76920), 36 V (BQ76930), or 48 V (BQ76940)
with VCELL = 4 V. Min and max values include full recommended operating condition temperature range from –40°C to
+85°C. Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition
sections.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Measured at TS1 pin with device in SHIP
mode. Below MIN, the device does not
boot up. Above MAX, the device boots
up.
VBOOT
Boot threshold voltage
300
1000
mV
Measured at TS1 pin. Below MIN, the
device does not boot up. Above MAX,
the device boots up.
Boot threshold application
time
tBOOT_max
10
2000
µs
(1) MIN specifies the threshold below which the device will never register that an external alert has occurred. MAX specifies the minimum
threshold above which the device will always register that an external alert has occurred.
(2) Values indicate nominal thresholds only. For min and max variation, apply OCOFFSET and OCSCALERR
.
(3) Values indicate nominal thresholds only. For min and max variation, apply tPROTACC
.
(4) Measured at each VBAT
7.6 Timing Requirements
I2C COMPATIBLE INTERFACE
MIN
TYP
MAX
UNIT
REGOUT x
0.25
VIL
VIH
Input low logic threshold
Input high logic threshold
V
REGOUT x
0.75
V
V
VOL
Output low logic drive
0.20
0.40
N/A
tf
SCL, SDA fall time
VOH
Output high logic drive (not applicable due to open-drain outputs)
SCL pulse width high
N/A
4.0
4.7
4.7
4.0
250
0
V
µs
µs
µs
µs
ns
µs
µs
µs
ns
ns
kHz
tHIGH
tLOW
SCL pulse width low
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tBUF
Setup time for START condition
START condition hold time after which first clock pulse is generated
Data setup time
Data hold time
Setup time for STOP condition
Time the bus must be free before new transmission can start
Clock low to data out valid
4.0
4.7
tVD;DAT
tHD;DAT
fSCL
900
100
Data out hold time after clock low
Clock frequency
0
0
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SCL
SDA
SCL
SDA
SCL
SDA
图7-1. I2C Timing
7.7 Typical Characteristics
30
±0±2±
±0±18
±0±16
±0±14
±0±12
±0±1±
±0±±8
±0±±6
±0±±4
±0±±2
±0±±±
±±0±±2
±±0±±4
VC1 Error
VC2 Error
VC3 Error
VC4 Error
VC5 Error
25
20
15
10
5
0
œ5
10
35
60
85
œ40
œ15
20±± 203± 206± 209± 302± 305± 308± 401± 404± 407± 50±±
Temperature (°C)
VCx Input (V)
C005
C±±1
图7-3. Coulomb Counter Gain Error Temperature
Drift (from –0.2 V to 0.2 V)
图7-2. BQ76930 VCx Error Across Input Range at
25°C with VIN at 3.6 V
0.0
œ0.1
œ0.2
œ0.3
œ0.4
œ0.5
œ0.6
œ0.7
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
œ1.2
œ1.4
œ1.6
10
35
60
85
10
35
60
85
œ40
œ15
œ40
œ15
Temperature (°C)
Temperature (°C)
C003
C002
图7-4. Coulomb Counter Gain Error (from –0.2 V
图7-5. Coulomb Counter Offset
to 0.2 V)
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0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-40
-15
10
35
60
85
Temperature (°C)
图7-6. OV Protection Detection Error (0xFF Setting)
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8 Detailed Description
8.1 Overview
In the BQ769x0 family of analog front-end (AFE) devices, the BQ76920 device supports up to 5-series cells, the
BQ76930 device supports up to 10-series cells, and the BQ76940 device supports up to 15-series cells. Through
I2C, a host controller can use the BQ769x0 to implement battery pack management functions, such as
monitoring (cell voltages, pack current, pack temperatures), protection (controlling charge/discharge FETs), and
balancing. Integrated A/D converters enable a purely digital readout of critical system parameters including cell
voltages and internal or external temperature, with calibration handled in TI’s manufacturing process. For an
additional degree of pack reliability, the BQ769x0 includes hardware protections for voltage (OV, UV) and current
(OCD, SCD).
The BQ769x0 provides two low-side FET drivers, charge (CHG) and discharge (DSG), which may be used to
directly manipulate low-side power NCH FETs, or as signals that control an external circuit that enables high-side
PCH or NCH FETs. A dedicated ALERT input/output pin serves as an interrupt signal to the host microcontroller,
quickly informing the microcontroller of an updated status in the AFE. This may include a fault event or that a
coulomb counter sample is available for reading. An available ALERT pin may also be driven externally by a
secondary protector to provide a redundant means of disabling the CHG and DSG signals and higher system
visibility.
8.2 Functional Block Diagram
REG
SRC
CAP
Bandgap
IBIAS
VSTUP/POR
BAT
Cell Balance
Drivers/FETs
BOOT
Internal 3.3-V
LDO
External
2.5/3.3-V LDO
REG
OUT
14-bit ADC
Modulator
ALERT
256 kHz
FET
DRIVER and
CHG
DSG
Digital core
Die temp
TS
LOAD
DETECT
CC VREF
SCL
SDA
16-bit ACC
Modulator
2
I C
TS
SCD
comp
BOOT
EEPROM
OCD
comp
To POR
VSS
SRP SRN
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8.3 Feature Description
8.3.1 Subsystems
BQ769x0 consists of three major subsystems: Measurement, Protection, and Control. These work together to
ensure that the fundamental battery pack parameters—voltage, current and temperature—are accurately
captured and easily available to a host controller, while ensuring a baseline or secondary level of hardware
protection in the event that a host controller is unable or unavailable to manage certain fault conditions.
备注
The BQ769x0 is intended to serve as an analog front-end (AFE) as part of a chipset system solution:
A companion microcontroller is required to oversee and control this AFE.
• The Measurement subsystem’s core responsibility is to digitize the cell voltages, pack current (integrated
into a passed charge calculation), external thermistor temperature, and internal die temperature. It also
performs an automatic calculation of the total battery stack voltage, by simply adding up all measured cell
voltages.
• The Protection subsystem provides a baseline or secondary level of hardware protections to better support a
battery pack’s FMEA requirements in the event of a loss of host control or simply if a host is unable to
respond to a certain fault event in time. Integrated protections include pack-level faults such as OV, UV, OCD,
SCD, detection of an external secondary protector fault, and internal logic “watchdog”-style device fault
(XREADY). Protection events will trigger toggling of the ALERT pin, as well as automatic disabling of the
DSG or CHG FET driver (depending on the fault). Recovery from a fault event must be handled by the host
microcontroller.
• The Control subsystem implements a suite of useful pack features, including direct low-side NCH FET
drivers, cell balancing drivers, the ALERT digital output, an external LDO and more.
The following sections describe each subsystem in greater detail, as well as explaining the various power states
that are available.
8.3.1.1 Measurement Subsystem Overview
The monitoring subsystem ensures that all cell voltages, temperatures, and pack current may be easily
measured by the host. All ADCs are trimmed by TI.
ADC and CC data are always returned as atomic values if both high and low registers are read in the same
transaction (using address auto-increment).
8.3.1.1.1 Data Transfer to the Host Controller
The BQ769x0 has a fully digital interface: All information is transferred through I2C, simply by reading and/or
writing to the appropriate register(s) storing the relevant data. Block reads and writes, buffered by an 8-bit CRC
code per byte, ensure a fast and robust transmission of data.
8.3.1.1.2 14-Bit ADC
Each BQ769x0 device measures cell voltages and temperatures using a 14-bit ADC. This ADC measures all
differential cell voltages, thermistors and/or die temperature with a nominal full-scale unsigned range of 0–6.275
V and LSB of 382 µV.
To enable the ADC, the [ADC_EN] bit in the SYS_CTRL1 register must be set. This bit is set automatically
whenever the device enters NORMAL mode. When enabled, the ADC ensures that the integrated OV and UV
protections are functional.
For each contiguous set of five cells (VC1 to VC5, VC6 to VC10), when no cells in that particular set are being
balanced, each cell is measured over a 50-ms decimation window and a complete update is available every 250
ms. In the BQ76930 and BQ76940, every set of five cells above the primary five cells is measured in parallel.
The 50-ms decimation greatly assists with removing the aliasing effects present in a noisy motor environment.
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When any cells in a contiguous set of 5 cells are being balanced, those affected cells are measured in a reduced
12.5-ms decimation period, to allow the cell balancing to function properly without affecting the integrated OV
and UV protections. Since cell balancing is typically only performed during pack charge or idle periods, the
shortened decimation periods should not impact accuracy as the system noise during these times is greatly
reduced. This reduced decimation period is only applied to sets where one of the cells is being balanced. The
following summarizes this for the BQ76920–BQ76940 devices:
• VC1 to VC5 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL1 register
are 0, and a 12.5-ms decimation period when any bits in CELLBAL1 register are 1.
• VC6 to VC10 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL2 register
are 0, and a 12.5-ms decimation period when any bits in CELLBAL2 register are 1.
• VC11 to VC15 measurements are each taken in a 50-ms decimation period when all bits in CELLBAL3
register are 0, and a 12.5-ms decimation period when any bits in CELLBAL3 register are 1.
• Total update interval is 250 ms.
Each differential cell input is factory-trimmed for gain or offset, such that the resulting reading through I2C is
always consistent from part-to-part and requires no additional calibration or correction factor application.
The ADC is required to be enabled in order for the integrated OV and UV protections to be operating.
The following shows how to convert the 14-bit ADC reading into an analog voltage. Each device is factory
calibrated, with a GAIN and OFFSET stored into EEPROM.
The ADC transfer function is a linear equation defined as follows:
V(cell) = GAIN x ADC(cell) + OFFSET
(1)
GAIN is stored in units of µV/LSB, while OFFSET is stored in mV units.
Some example cell voltage calculations are provided in the table below. For illustration purposes, the example
uses a hypothetical GAIN of 380 µV/LSB (ADCGAIN<4:0> = 0x0F) and OFFSET of 30 mV (ADCOFFSET<7:0>
= 0x1E).
14-Bit ADC Result
0x1800
ADC Result in Decimal
GAIN (µV/LSB)
OFFSET (mV)
Cell Voltage (mV)
6144
7952
380
380
30
30
2365
3052
0x1F10
备注
When entering NORMAL mode from SHIP mode, please allow for the following times before reading
out initial cell voltage data:
BQ76920: 250 ms
BQ76930: 400 ms
BQ76940: 800 ms
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8.3.1.1.2.1 Optional Real-Time Calibration Using the Host Microcontroller
The performance of the cell voltage values measured by the 14-bit ADC has a factory-calibrated accuracy, as
follows:
• +/–10 mV TYP, +/–40 mV MIN and MAX from 3.6 to 4.3 V,
• +/–15 mV TYP, +/–40 mV MIN and MAX from 3.2 to 4.6 V, and
• +/–50 mV MIN and MAX from 2.0 to 5.0 V
While this is suitable for the majority of pack protection and basic monitoring applications the BQ769x0 AFE
family is intended to support, certain systems may require a higher accuracy performance.
To achieve this, use an available ADC channel and general purpose output terminal on the host microcontroller
paired with the BQ769x0. A simple external circuit consisting of two precision resistors and a small-signal FET is
activated by the host microcontroller to determine the total stack voltage, VSTACK. This is then compared against
the sum of the individual cell voltages as measured by the internal ADC of the BQ769x0. The resulting transfer
function coefficient, GAIN2, is simply applied to each cell voltage ADC value for improved accuracy.
Host microcontroller
A/D input
Gen. purpose output
图8-1. External Real-Time Calibration Circuit to Host Microcontroller
The process is as follows:
1. Periodically measure VSTACK
.
a. VSTACK = VAD × (R1 + R2) / R1
2. Read out all VCELL ADC readings from the BQ769x0 and apply the standard GAIN and OFFSET values
stored in the BQ769x0.
a. V(1) = GAIN x ADC1 + OFFSET, V(2) = GAIN x ADC2 + OFFSET, and so on
3. Sum up all VCELL values, VSUM
.
a. VSUM = V(1) + V(2) + V(3) …
4. Calculate GAIN2.
a. GAIN2 = VSTACK / VSUM
As a general recommendation, a new GAIN2 function should be generated when the cell voltages increase or
decrease by more than 100 mV. With GAIN2, each cell voltage calculation becomes:
V(cell) = GAIN2 × (GAIN x ADC(cell) + OFFSET)
(2)
For systems that do not require this additional in-use calibration function, GAIN2 is simply “1”.
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8.3.1.1.3 16-Bit CC
A 16-bit integrating ADC, commonly referred to as the coulomb counter (CC), provides measurements of
accumulated charge across the current sense resistor. The integration period for this reading is 250 ms.
The CC may be operated in one of two modes: ALWAYS ON and 1-SHOT.
• In ALWAYS ON mode, the CC runs at 100%, gathering a fresh reading every 250 ms. The conclusion of each
reading sets the CC_READY bit, which toggles the ALERT pin high to inform the microcontroller that a new
reading is available. To enable Always On mode, set [CC_EN] = 1.
• In 1-SHOT mode, the CC performs a single 250-ms reading, and similarly sets the CC_READY bit when
completed. This mode is intended for non-gauging usages, where the host simply desires to check the pack
current.
To enable a 1-SHOT reading, ensure [CC_EN] = 0 and set [CC_ONESHOT] = 1.
The fullscale range of the CC is ± 270 mV, with a max recommended input range of ± 200 mV, thus yielding an
LSB of approximately 8.44 µV.
The following equation shows how to convert the 16-bit CC reading into an analog voltage if no board-level
calibration is performed:
CC Reading (in µV) = [16-bit 2’s Complement Value] × (8.44 µV/LSB)
(3)
16-Bit CC Result
0x0001
ADC Result in Decimal
CC Reading (in µV)
8.44
1
0x2710
10000
32000
–32000
–15536
–1
84,400
0x7D00
270,080
0x8300
–270,080
–131,123.84
–8.44
0xC350
0xFFFF
8.3.1.1.4 External Thermistor
One (BQ76920), two (BQ76930), or three (BQ76940) 10-kΩ NTC 103AT thermistors may be measured by the
device. These are measured by applying a factory-trimmed internal 10-k pull-up resistance to an internal
regulator value of nominally 3.3 V, the result of which can be read out from the TSx (TS1, TS2, TS3) registers.
To select thermistor measurement mode, set [TEMP_SEL] = 1.
Thermistor TS1 is connected between TS1 and VSS; TS2 is connected between TS2 and VC5x (BQ76930 and
BQ76940 only); and TS3 is connected between TS3 and VC10x (BQ76940 only). These thermistors may be
placed in various areas in the battery pack to measure such things as localized cell temperature, FET heating,
and so forth.
The thermistor impedance may be calculated using the 14-bit ADC reading in the TS1, TS2, and TS3 registers
and 10-k internal pull-up resistance as follows:
The following equations show how to use the 14-bit ADC readings in TS1, TS2, and TS3 to determine the
resistance of the external 103AT thermistor:
VTSX = (ADC in Decimal) x 382 µV/LSB
(4)
(5)
RTS = (10,000 × VTSX) ÷ (3.3 –VTSX)
To convert the thermistor resistance into temperature, please refer to the thermistor component manufacturer’s
data sheet.
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8.3.1.1.5 Die Temperature Monitor
备注
When switching between external and internal temperature monitoring, a 2-s latency may be incurred
due to the natural scheduler update interval.
A die temperature block generates a voltage that is proportional to the die temperature, and provides a way of
reducing component count if pack thermistors are not used or ensuring that the die power dissipation
requirements are observed. The die is measured using the same on-board 14-bit ADC as the cell voltages.
To select internal die temperature measurement mode, set [TEMP_SEL] = 0.
For BQ76930 and BQ76940, multiple die temperature measurements are available. These are stored in TS2 and
TS3.
To convert a DIETEMP reading into temperature, refer to the following equation box. If more accurate
temperature readings are needed from DIETEMP, the DIETEMP at room temperature value should be stored
during production calibration.
The following equation shows how to use the 14-bit ADC readings in TS1, TS2, and TS3 when [TEMPSEL] = 0
to determine the internal die temperature:
V25 = 1.200 V (nominal)
(6)
(7)
(8)
VTSX = (ADC in Decimal) x 382 µV/LSB
TEMPDIE = 25° –((VTSX –V25) ÷ 0.0042)
8.3.1.1.6 16-Bit Pack Voltage
Once converted to digital form, each cell voltage is added up and the summation result stored in the BAT
registers. The sum is divided by 4 so that the result of summing 15 cells fits in the 16-bit value. This 16-bit value
has a nominal LSB of 1.532 mV.
The following shows how to convert the 16-bit pack voltage ADC reading into an analog voltage. This value also
uses the GAIN and OFFSET stored into EEPROM.
The ADC transfer function is a linear equation defined as follows:
V(BAT) = 4 × GAIN × ADC(cell) + (#Cells x OFFSET)
(9)
GAIN is stored in units of µV/LSB, while OFFSET is stored in mV units.
8.3.1.1.7 System Scheduler
A master scheduler oversees the monitoring intervals, creating a full update every 250 ms. Temperature
measurements are taken every 2 seconds. Pack voltage is calculated every 250 ms. More information on the
System Scheduler can be found in the Embedded Scheduler in Cell Battery Monitor of the BQ769x0 application
report.
8.3.1.2 Protection Subsystem
8.3.1.2.1 Integrated Hardware Protections
Integrated hardware protections are provided as an extra degree of safety and are meant to supplement the
standard protection feature set that would be incorporated into the host controller firmware. They should not be
used as the sole means of protecting a battery pack, but are useful for FMEA purposes; for example, in the
event that a host microcontroller is unable to react to any of the below protection situations. All hardware
protection thresholds and delays should be loaded into the AFE by the host microcontroller during system
startup. The AFE will also default to predefined threshold and delay settings, in case the host microcontroller is
unable to or does not wish to program the protection settings.
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Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) are implemented using sampled analog
comparators that run at 32 kHz, and that continuously monitor the voltage across (SRP–SRN) while the device
is in NORMAL mode. Upon detection of a voltage that exceeds the programmed OCD or SCD threshold, a
counter begins to count up to a programmed delay setting. If the counter reaches its target value, the SYS_STAT
register is updated to indicate the fault condition, the FET state(s) are updated as shown in 表 8-1, and the
ALERT pin is driven high to interrupt the host.
The protection fault threshold and delay settings for OCD and SCD protections are configured through the
PROTECT1 and PROTECT2 registers. See 节8.5 for details about supported values.
Overvoltage (OV) and undervoltage (UV) protections are handled digitally, by comparing the cell voltage
readings against the 8-bit programmed thresholds in the OV and UV registers.
The OV threshold is stored in the OV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading,
with the upper 2 MSB preset to “10” and the lower 4 LSB preset to “1000”. In other words, the
corresponding OV trip level is mapped to “10-XXXX-XXXX–1000”. The programmable range of OV
thresholds is approximately 3.15 to 4.7 V, but this is subject to variation due to the (GAIN, OFFSET) linear
equation used to map the ADC values.
The UV threshold is stored in the UV_TRIP register and is a direct mapping of 8 bits of the 14-bit ADC reading,
with the upper 2 MSB preset to “01” and lower 4 LSB preset to “0000”. In other words, the corresponding
UV trip level is mapped to “01-XXXX-XXXX–0000”. The programmable range of UV thresholds is
approximately 1.58 to 3.1 V, but this is subject to variation due to the (GAIN, OFFSET) linear equation used to
map the ADC values.
Protection
OV
Upper 2 MSB
Middle 8 Bits
Lower 4 LSB
1000
10
01
Set in OV_TRIP Register
Set in UV_TRIP Register
UV
0000
备注
To support flexible cell configurations within BQ76920, BQ76930, and BQ76940, UV is ignored on any
cells that have a reading under UVMINQUAL. This allows cell pins to be shorted in implementations
where not all cells are needed (for example, 6-series cells using the BQ76930).
Default protection thresholds and delays are shown in the register description at the end of this data sheet.
These are loaded into the digital register (RAM) of the device when the device enters NORMAL mode. These
RAM values may then be overwritten by the host controller to any other values, which they will retain until a POR
event. It is recommended that the host controller reload these values during its standard power-up and/or
reinitialization sequence.
To calculate the correct OV_TRIP and UV_TRIP register values for a device, use the following procedure:
1. Determine desired OV.
2. Read out [ADCGAIN] and [ADCOFFSET] from their corresponding registers. Note that ADCGAIN is stored in
units of µV/LSB, while ADCOFFSET is stored in mV.
3. Calculate the full 14-bit ADC value needed to meet the desired OV and UV trip thresholds as follows:
a. OV_TRIP_FULL = (OV –ADCOFFSET) ÷ ADCGAIN
b. UV_TRIP_FULL = (UV –ADCOFFSET) ÷ ADCGAIN
4. Remove the upper 2 MSB and lower 4 LSB from the full 14-bit value, retaining only the remaining middle 8
bits. This can be done by shifting the OV_TRIP_FULL and UV_TRIP_FULL binary values 4 bits to the right
and removing the upper 2 MSB.
5. Write OV_TRIP and UV_TRIP to their corresponding registers.
Both OV and UV protections require the ADC to be enabled. Ensure that the [ADC_EN] bit is set to 1 if OV and
UV protections are needed.
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8.3.1.2.2 Reduced Test Time
A special debug and test configuration bit is provided in the SYS_CTRL2 register, called [DELAY_DIS]. Setting
[DELAY_DIS] bypasses the OV/UV protection fault timers and allows a fault condition to be registered within 200
ms after application of such a fault condition.
8.3.1.3 Control Subsystem
8.3.1.3.1 FET Driving (CHG AND DSG)
Each BQ769x0 device provides two low-side FET drivers, CHG and DSG, which control NCH power FETs or
may be used as a signal to enable various other circuits such as a high-side NCH charge pump circuit.
Both DSG and CHG drivers have a fast pull-up to nominally 12 V when enabled. DSG uses a fast pull-down to
VSS when disabled, while CHG utilizes a high impedance (nominally 1 MΩ) pull-down path when disabled.
An additional internal clamp circuit ensures that the CHG pin does not exceed a maximum of 20 V.
DSG
CHG
Q3 is a low-cost PCH FET and is used to keep CHG away
from any voltages below VSS. When CHG is not being
pulled high, PACKœ being pulled below VSS will not be
seen by CHG as Q2 does not turn on. Q3 also allows R2 to
keep Q1 OFF, since all voltages below this FET can
"follow" PACKœ as it goes below VSS.
Q3
R1 drops the voltage when PACKœ is pulled high and
limits the current going into the CHG pin. Since CHG
clamps at ~ 18 V, R1 will limit current to approximately
(V(PACKœ) - 18) / R1.
R1
(1M)
This diode allows CHG
to pull the Q1 gate high.
This zener clamp may
be needed to prevent
Q1 from turning on
R2
(1M)
R2
too quickly (optional).
Q1
Q2
BATœ
PACKt
R2 clamps Q1 when
CHG is turned off.
Rsns
图8-2. CHG and DSG FET Circuit
The power path for the CHG and DSG pull-up circuit originates from the REGSRC pin, instead of BAT.
To enable the CHG fet, set the [CHG_ON] register bit to 1; to disable, set [CHG_ON] = 0. The discharge FET
may be similarly controlled through the [DSG_ON] register bit.
Certain fault conditions or power state transitions will clear the state of the CHG/DSG FET controls. 表 8-1
shows what action, if any, to take to [CHG_ON] and [DSG_ON] in response to various system events:
8.3.1.3.1.1 High-Side FET Driving
The BQ769x0 battery monitors provide low-side FET drivers that work well for many systems. For some
systems, high-side FETs may also be beneficial. High-side FETs enable continuous communication between a
host controller and the monitor, regardless of whether the FETs are on or off. This allows the controller to read
critical pack parameters despite safety faults, enabling the system to access pack conditions before allowing
normal operations to resume. The BQ769200 high-side N-channel FET driver can be used with the BQ769x0
monitor in systems where high-side FETs are needed. See 图9-4.
表8-1. CHG, DSG Response Under Various System Events
EVENT
OV Fault
UV Fault
OCD Fault
[CHG_ON]
Set to 0
—
[DSG_ON]
—
Set to 0
Set to 0
—
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表8-1. CHG, DSG Response Under Various System Events (continued)
EVENT
[CHG_ON]
[DSG_ON]
Set to 0
Set to 0
Set to 0
Set to 0
SCD Fault
—
ALERT Override
Set to 0
Set to 0
Set to 0
DEVICE_XREADY is set
Enter SHIP mode from NORMAL
备注
The host microcontroller must initiate all protection recovery. To resume FET operation after a fault
condition, the host microcontroller must first clear the corresponding status bit in the SYS_STAT
register, which will clear the ALERT pin, and then manually reenable the CHG and/or DSG bit. Certain
faults, such as OV or UV, may immediately retoggle if such a condition still persists. Refer to 表8-3 for
details on clearing status bits.
There are no conditions under which the BQ769x0 automatically sets either [CHG_ON] or [DSG_ON] to 1.
8.3.1.3.2 Load Detection
A load detection circuit is present on the CHG pin and activated whenever the CHG FET is disabled ([CHG_ON]
= 0). This circuit detects if the CHG pin is externally pulled high when the high impedance (approximately 1 MΩ)
pull-down path should actually be holding the CHG pin to VSS, and is useful for determining if the PACK– pin
(outside of the AFE) is being held at a high voltage—for example, if the load is present while the power FETs are
off. The state of the load detection circuit is read from the [LOAD_PRESENT] bit of the SYS_CTRL1 register.
After an OCD or SCD fault has occurred, the DSG FET will be disabled ([DSG_ON] cleared), and the CHG FET
must similarly be explicitly disabled to activate the load detection circuit. The host microcontroller may
periodically poll the [LOAD_PRESENT] bit to determine the state of the PACK– pin and determine when the
load is removed ([LOAD_PRESENT] = 0).
8.3.1.3.3 Cell Balancing
Both internal and external passive cell balancing options are fully supported by the BQ76920, while external cell
balancing is recommended for BQ76930 and BQ76940. It is left to the host controller to determine the exact
balancing algorithm to be used in any given system. Each BQ769x0 device provides the cell voltages and
balancing drivers to enable this. If using the internal cell balance drivers, up to 50 mA may be balanced per cell.
If using external cell balancing, much higher balancing currents may be employed.
To activate a particular cell balancing channel, simply set the corresponding bit for that cell in the CELLBAL1,
CELLBAL2, or CELLBAL3 register. For example, VC1–VC0 is enabled by setting [CB1], while VC12–VC11 is
set through [CB12].
Multiple cells may be simultaneously balanced. It is left to the user’s discretion to determine the ideal number
of cells to concurrently balance. Adjacent cells should not be balanced simultaneously. This may cause cell pins
to exceed their absolute maximum conditions and is also not recommended for external balancing
implementations. Additionally, if internal balancing is used, care should be taken to avoid exceeding package
power dissipation ratings.
备注
The host controller must ensure that no two adjacent cells are balanced simultaneously within each
set of the following:
• VC1–VC5
• VC6–VC10
• VC11–VC15
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The total duty cycle devoted to balancing is approximately 70% per 250 ms. This is because a portion of the 250
ms is allotted for normal cell voltage measurements through the ADC.
If [ADC_EN] =1, OV and UV protections are not affected by cell balancing, since the cell balancing is temporarily
suspended for a small slice of time every 250 ms during which the cell voltage readings are taken. This ensures
that the OV and UV protections do not accidentally trigger, or miss an actual OV/UV condition on the cells while
balancing is enabled.
备注
All cell balancing control bits in CELLBAL1, CELLBAL2, and CELLBAL3 are automatically cleared
under the following events, and must be explicitly rewritten by the host microcontroller following
clearing of the event:
• DEVICE_XREADY is set
• Enters NORMAL mode from SHIP mode
8.3.1.3.4 Alert
The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host
microcontroller. This signal is an OR of all bits in the SYS_STAT register.
In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a
“1”to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared.
The ALERT pin may also be driven by an external source; for example, the pack may include a secondary
overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will recognize this
as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling of both CHG and
DSG FET drivers. The device cannot recognize the ALERT signal input high when it is already forcing the
ALERT signal high from another condition.
The ALERT pin has no internal debounce support so care should be taken to protect the pin from noise or other
parasitic transients.
备注
It is highly recommended to place an external 500 kΩ–1 MΩ pull-down resistor from ALERT to VSS
as close to the IC as possible. Additional recommendations are:
a) To keep all traces between the IC and components connected to the ALERT pin very short.
b) To include a guard ring around the components connected to the ALERT pin and the pin itself.
8.3.1.3.5 Output LDO
An adjustable output voltage regulator LDO is provided as a simple way to provide power to additional
components in the battery pack, such as the host microcontroller or LEDs. The LDO is configured in EEPROM
by TI during the production test process, and can support 2.5-V or 3.3-V options.
A cascode small-signal FET must be added in the external path between BAT and REGSRC with the BQ76930
and BQ76940. This helps drop most of the power dissipation outside of the package and cuts down on package
power dissipation.
8.3.1.4 Communications Subsystem
The AFE implements a standard 100-kHz I2C interface and acts as a slave device. The I2C device address is 7-
bits and is factory programmed. Consult the Device Comparison Table (节 5) of this data sheet for more
information.
A write transaction is shown in 图8-3. Block writes are allowed by sending additional data bytes before the Stop.
The I2C block will auto-increment the register address after each data byte.
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When enabled, the CRC is calculated as follows:
• In a single-byte write transaction, the CRC is calculated over the slave address, register address, and data.
• In a block write transaction, the CRC for the first data byte is calculated over the slave address, register
address, and data. The CRC for subsequent data bytes is calculated over the data byte only.
The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.
When the slave detects a bad CRC, the I2C slave will NACK the CRC, which causes the I2C slave to go to an
idle state.
SCL
... A0
... R0
... D0
... C0
A6 A5
R/W ACK
R7 R6
ACK
D7 D6
ACK
C7 C6
ACK
SDA
Register
Address
CRC
(optional)
Start
Slave Address
Stop
Data
图8-3. I2C Write
图8-4 shows a read transaction using a Repeated Start.
SCL
... A0
... R0
... A0
A6 A5
A6 A5
R/W ACK
R7 R6
ACK
R/W ACK
SDA
Register
Address
Start
Slave Address
Slave Address
Repeated
Start
... D0
... C0 NACK
D7 D6
ACK
C7 C6
Slave
Drives Data
Slave
Drives CRC
(optional)
Stop
Master
Drives NACK
图8-4. I2C Read with Repeated Start
图 8-5 shows a read transaction where a Repeated Start is not used, for example if not available in hardware.
For a block read, the master ACK’s each data byte except the last and continues to clock the interface. The I2C
block will auto-increment the register address after each data byte.
When enabled, the CRC for a read transaction is calculated as follows:
• In a single-byte read transaction, the CRC is calculated after the second start and uses the slave address
and data byte.
• In a block read transaction, the CRC for the first data byte is calculated after the second start and uses the
slave address and data byte. The CRC for subsequent data bytes is calculated over the data byte only.
The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.
When the master detects a bad CRC, the I2C master will NACK the CRC, which causes the I2C slave to go to an
idle state.
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SCL
... A0
... R0
... A0
A6 A5
R/W ACK
R7 R6
ACK
A6 A5
R/W ACK
SDA
Register
Address
Start
Slave Address
Stop Start Slave Address
... D0
... C0 NACK
D7 D6
ACK
C7 C6
Slave
Drives Data
Slave
Drives CRC
(optional)
Stop
Master
Drives NACK
图8-5. I2C Read Without Repeated Start
8.4 Device Functional Modes
Each BQ769x0 device supports the following modes of operation.
表8-2. Supported Power Modes
Mode
Description
Fully operational state. Both ADC and CC may be on, or disabled by host microcontroller.
OV and UV protection enabled if ADC is on. OCD and SCD enabled. ADC and CC may
be disabled to reduce power consumption, and CC may be operated in a “1-SHOT”
mode for flexible power savings.
NORMAL
Lowest possible power state, intended for pack assembly and/or longterm pack storage.
Must see a BOOT signal (> 1 VBOOT) on TS1 pin to boot from SHIP →NORMAL. Note
that the device always enters SHIP mode upon POR.
SHIP
8.4.1 NORMAL Mode
NORMAL mode represents the fully operational mode where all blocks are enabled and the device sees its
highest current consumption. In this mode, certain blocks/functions may be disabled to save power—these
include the ADC and CC. OV and UV are running continuously as long as the ADC is enabled. The OCD and
SCD comparators may not be disabled in this mode.
Transitioning from NORMAL to SHIP mode is also initiated by the host, and requires consecutive writes to two
bits in the SYS_CTRL1 register.
8.4.2 SHIP Mode
SHIP mode is the basic and lowest power mode that BQ769x0 supports. SHIP mode is automatically entered
during initial pack assembly and after every POR event. When the device is in NORMAL mode, it may enter
SHIP by the host controller through a specific sequence of I2C commands.
In SHIP mode, only a minimum of blocks is turned on, including the VSTUP power supply and primal boot
detector. Waking from SHIP mode to NORMAL mode requires pulling the TS1 pin greater than VBOOT, which
triggers the device boot-up sequence.
To enter SHIP mode from NORMAL mode, the [SHUT_A] and [SHUT_B] bits in the SYS_CTRL1 register must
be written with specific patterns across two consecutive writes:
• Write #1: [SHUT_A] = 0, [SHUT_B] = 1
• Write #2: [SHUT_A] = 1, [SHUT_B] = 0
Note that [SHUT_A] and [SHUT_B] should each be in a 0 state prior to executing the shutdown command
above. If this specific sequence is entered into the device, the device transitions into SHIP mode. If any other
sequence is written to the [SHUT_A] and [SHUT_B] bits or if either of the two patterns is not correctly entered,
the device will not enter SHIP mode.
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CAUTION
DO NOT OPERATE THE DEVICE BELOW POR. When designing with the BQ76940, the
intermediate voltages (BAT–VC10x), (VC10x–VC5x), and (VC5x–VSS) must each never fall
below VSHUT. When this occurs, a full device reset must be initiated by powering down all three
intermediate voltages (BAT–VC10x), (VC10x–VC5x), and (VC5x–VSS) below VSHUT and
rebooting by applying the appropriate VBOOT signal to the TS1 pin. When designing with the
BQ76930, the intermediate voltages (BAT–VC5x) and (VC5x–VSS) must each never fall below
VSHUT. If this occurs, a full device reset must be initiated by powering down both intermediate
voltages (BAT–VC5x) and (VC5x–VSS) below VSHUT and rebooting by applying the appropriate
VBOOT signal to the TS1 pin.
The device will also enter SHIP mode during a POR event; however, this is not a recommended method of SHIP
mode entry. If any of the supply-side voltages fall below VSHUT and then back up above VPORA, the device
defaults into the SHIP mode state. This is similar to an initial pack assembly condition. In order to exit SHIP
mode into NORMAL mode, the device must follow the standard boot sequence by applying a voltage greater
than the VBOOT threshold on the TS1 pin. The BQ769x0 Boot Switch Alternatives Application Report details
multiple methods for generating the needed signal on the TS1 pin.
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8.5 Register Maps
Name
Addr
D7
D6
D5
D4
D3
D2
D1
D0
SYS_STAT
0x00
CC_READY
RSVD
DEVICE_
XREADY
OVRD_
ALERT
UV
OV
SCD
OCD
CELLBAL1
CELLBAL2(1)
CELLBAL3(2)
SYS_CTRL1
0x01
0x02
0x03
0x04
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CB<5:1>
CB<10:6>
CB<15:11>
RSVD
LOAD_
PRESENT
ADC_EN
TEMP_SEL
RSVD
SHUT_A
DSG_ON
SHUT_B
CHG_ON
SYS_CTRL2
0x05
DELAY_DIS
CC_EN
RSVD
CC_
ONESHOT
PROTECT1
PROTECT2
PROTECT3
OV_TRIP
UV_TRIP
CC_CFG
VC1_HI
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
RSNS
RSVD
RSVD
SCD_DELAY
SCD_THRESH
OCD_DELAY
OCD_THRESH
RSVD
UV_DELAY
OV_DELAY
OV_THRESH
UV_THRESH
RSVD
RSVD
RSVD
RSVD
Must be programmed to 0x19
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
<13:8>
VC1_LO
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
<7:0>
VC2_HI
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VC2_LO
VC3_HI
VC3_LO
VC4_HI
VC4_LO
VC5_HI
VC5_LO
VC6_HI(1)
VC6_LO(1)
VC7_HI(1)
VC7_LO(1)
VC8_HI(1)
VC8_LO(1)
VC9_HI(1)
VC9_LO(1)
VC10_HI(1)
VC10_LO(1)
VC11_HI(2)
VC11_LO(2)
VC12_HI(2)
VC12_LO(2)
VC13_HI(2)
VC13_LO(2)
VC14_HI(2)
VC14_LO(2)
VC15_HI(2)
VC15_LO(2)
BAT_HI
<7:0>
<15:8>
<7:0>
BAT_LO
TS1_HI
RSVD
RSVD
RSVD
RSVD
<13:8>
<13:8>
TS1_LO
<7:0>
TS2_HI(1)
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Name
TS2_LO(1)
TS3_HI(2)
TS3_LO(2)
CC_HI
Addr
0x2F
0x30
0x31
0x32
0x33
0x50
0x51
0x59
D7
D6
D5
D4
D3
D2
D1
D0
<7:0>
RSVD
RSVD
<13:8>
<7:0>
<15:8>
<7:0>
CC_LO
ADCGAIN1
ADCOFFSET
ADCGAIN2
RSVD
ADCGAIN<4:3>
ADCOFFSET<7:0>
RSVD
ADCGAIN<2:0>
RSVD
(1) These registers are only valid for BQ76930 and BQ76940.
(2) These registers are only valid for BQ76940.
8.5.1 Register Details
表8-3. SYS_STAT (0x00)
BIT
7
6
5
4
3
2
1
0
NAME
CC_READY
RSVD
DEVICE_
XREADY
OVRD_
ALERT
UV
OV
SCD
OCD
RESET
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
备注
Bits in SYS_STAT may be cleared by writing a "1" to the corresponding bit.
Writing a "0" does not change the state of the corresponding bit.
CC_READY (Bit 7): Indicates that a fresh coulomb counter reading is available. Note that if this bit is not cleared between two adjacent CC
readings becoming available, the bit remains latched to 1. This bit may only be cleared (and not set) by the host.
0 = Fresh CC reading not yet available or bit is cleared by host microcontroller.
1 = Fresh CC reading is available. Remains latched high until cleared by host.
RSVD (Bit 6): Reserved. Do not use.
DEVICE_XREADY (Bit 5): Internal chip fault indicator. When this bit is set to 1, it should be cleared by the host. May be set due to
excessive system transients. This bit may only be cleared (and not set) by the host.
0 = Device is OK.
Internal chip fault detected, recommend that host microcontroller clear this bit after waiting a few seconds. Remains latched
high until cleared by the host.
1 =
OVRD_ALERT (Bit 4): External pull-up on the ALERT pin indicator. Only active when ALERT pin is not already being driven high by the
AFE itself.
0 = No external override detected
1 = External override detected. Remains latched high until cleared by the host.
UV (Bit 3): Undervoltage fault event indicator.
0 = No UV fault is detected.
1 = UV fault is detected. Remains latched high until cleared by the host.
OV (Bit 2): Overvoltage fault event indicator.
0 = No OV fault is detected.
1 = OV fault is detected. Remains latched high until cleared by the host.
SCD (Bit 1): Short circuit in discharge fault event indicator.
0 = No SCD fault is detected.
1 = SCD fault is detected. Remains latched high until cleared by the host.
OCD (Bit 0): Over current in discharge fault event indicator.
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0 = No OCD fault is detected.
1 = OCD fault is detected. Remains latched high until cleared by the host.
表8-4. CELLBAL1 (0x01) for BQ76920, BQ76930, and BQ76940
BIT
7
6
5
4
CB5
0
3
CB4
0
2
CB3
0
1
CB2
0
0
CB1
0
NAME
—
0
—
0
—
0
RESET
ACCESS
R
R
R
RW
RW
RW
RW
RW
CBx (Bits 4–0):
0 =
1 =
Cell balancing on Cell “x”is disabled.
Cell balancing on Cell “x”is enabled.
表8-5. CELLBAL2 (0x02) for BQ76930 and BQ76940
BIT
7
6
5
4
CB10
0
3
CB9
0
2
CB8
0
1
CB7
0
0
CB6
0
NAME
RESET
—
0
—
0
—
0
ACCESS
R
R
R
RW
RW
RW
RW
RW
CBx (Bits 4–0):
0 =
1 =
Cell balancing on Cell “x”is disabled.
Cell balancing on Cell “x”is enabled.
表8-6. CELLBAL3 (0x03) for BQ76940
BIT
7
6
5
4
CB15
0
3
CB14
0
2
CB13
0
1
CB12
0
0
CB11
0
NAME
RESET
—
0
—
0
—
0
ACCESS
R
R
R
RW
RW
RW
RW
RW
CBx (Bits 4–0):
0 =
1 =
Cell balancing on Cell “x”is disabled.
Cell balancing on Cell “x”is enabled.
表8-7. SYS_CTRL1 (0x04)
BIT
7
6
5
4
3
2
1
0
LOAD_
PRESENT
NAME
RESET
ADC_EN
TEMP_SEL
RSVD
SHUT_A
SHUT_B
—
—
0
0
0
0
0
0
0
0
ACCESS
R
R
R
RW
RW
RW
RW
RW
LOAD_PRESENT (Bit 7): Valid only when [CHG_ON] = 0. Is high if CHG pin is detected to exceed VLOAD_DETECT while CHG_ON = 0,
which suggests that external load is present. Note this bit is read-only and automatically clears when load is removed.
0 = CHG pin < VLOAD_DETECT or [CHG_ON] = 1.
1 = CHG pin >VLOAD_DETECT, while [CHG_ON] = 0.
ADC_EN (Bit 4): ADC enable command
0 = Disable voltage and temperature ADC readings (also disables OV protection)
1 = Enable voltage and temperature ADC readings (also enables OV protection)
TEMP_SEL (Bit 3): TSx_HI and TSx_LO temperature source
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0 = Store internal die temperature voltage reading in TSx_HI and TSx_LO
1 = Store thermistor reading in TSx_HI and TSx_LO (all thermistor ports)
RSVD (Bit 2): Reserved, do not set to 1.
SHUT_A, SHUT_B (Bits 1–0): Shutdown command from host microcontroller. Must be written in a specific sequence, shown below:
Starting from: [SHUT_A] = 0, [SHUT_B] = 0
Write #1: [SHUT_A] = 0, [SHUT_B] = 1
Write #2: [SHUT_A] = 1, [SHUT_B] = 0
Other writes cause the command to be ignored.
表8-8. SYS_CTRL2 (0x05)
BIT
7
6
5
4
3
2
1
0
CC_
ONESHOT
NAME
DELAY_DIS
CC_EN
RSVD
RSVD
RSVD
DSG_ON
CHG_ON
RESET
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
DELAY_DIS (Bit 7): Disable OV, UV, OCD, and SCD delays for faster customer production testing.
0 = Normal delay settings
1 = OV, UV, OCD, and SCD delay circuit is bypassed, creating zero delay (approximately 250 ms).
CC_EN (Bit 6): Coulomb counter continuous operation enable command. If set high, [CC_ONESHOT] bit is ignored.
0 = Disable CC continuous readings
1 = Enable CC continuous readings and ignore [CC_ONESHOT] state
CC_ONESHOT (Bit 5): Coulomb counter single 250-ms reading trigger command. If set to 1, the coulomb counter will be activated for a
single 250-ms reading, and then turned back off. [CC_ONESHOT] will also be cleared at the conclusion of this reading, while [CC_READY]
bit will be set to 1.
0 = No action
1 = Enable single CC reading (only valid if [CC_EN] = 0), and [CC_READY] = 0)
RSVD (Bits 4–2): Reserved. Do not use.
DSG_ON (Bit 1): Discharge FET driver (low side NCH) or discharge signal control
0 = DSG is off.
1 = DSG is on.
CHG_ON (Bit 0): Discharge FET driver (low side NCH) or discharge signal control
0 = CHG is off.
1 = CHG is on.
表8-9. PROTECT1 (0x06)
BIT
7
RSNS
0
6
5
RSVD
0
4
SCD_D1
0
3
SCD_D0
0
2
SCD_T2
0
1
SCD_T1
0
0
SCD_T0
0
NAME
—
0
RESET
ACCESS
RW
R
RW
RW
RW
RW
RW
RW
RSNS (Bit 7): Allows for doubling the OCD and SCD thresholds simultaneously
0 = OCD and SCD thresholds at lower input range
1 = OCD and SCD thresholds at upper input range
RSVD (Bit 5): Reserved, do not set to 1.
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SCD_D1:0 (Bits 4–3): Short circuit in discharge delay setting. A 400-µs setting is recommended only in systems using maximum cell
measurement input resistance, Rc, of 1 kΩ(which corresponds to minimum internal cell balancing current or external cell balancing
configuration).
Code
0x0
(in µs)
70
0x1
100
200
400
0x2
0x3
SCD_T2:0 (Bits 2–0): Short circuit in discharge threshold setting
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
RSNS = 1 (in mV)
RSNS = 0 (in mV)
44
67
22
33
44
56
67
78
89
100
89
111
133
155
178
200
表8-10. PROTECT2 (0x07)
BIT
7
6
5
OCD_D1
0
4
OCD_D0
0
3
OCD_T3
0
2
1
0
OCD_T0
0
NAME
OCD_D2
OCD_T2
OCD_T1
—
0
RESET
ACCESS
0
0
0
R
RW
RW
RW
RW
RW
RW
RW
OCD_D2:0 (Bits 6–4): Overcurrent in discharge delay setting
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
(in ms)
8
20
40
80
160
320
640
1280
OCD_T3:0 (Bits 3–0): Overcurrent in discharge threshold setting
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
RSNS = 1 (in mV)
(RSNS = 0 (in mV)
17
22
28
33
39
44
50
8
11
14
17
19
22
25
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Code
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
RSNS = 1 (in mV)
(RSNS = 0 (in mV)
56
61
67
72
78
83
89
94
100
28
31
33
36
39
42
44
47
50
表8-11. PROTECT3 (0x08)
BIT
7
UV_D1
0
6
5
OV_D1
0
4
OV_D0
0
3
RSVD
0
2
RSVD
0
1
RSVD
0
0
RSVD
0
NAME
UV_D0
0
RESET
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
UV_D1:0 (Bits 7–6): Undervoltage delay setting
Code
0x0
(in s)
1
4
0x1
0x2
8
0x3
16
OV_D1:0 (Bits 5–4): Overvoltage delay setting
Code
0x0
(in s)
1
2
4
8
0x1
0x2
0x3
RSVD (Bits 3–0): These bits are for TI internal debug use only and must be configured to the default settings indicated.
表8-12. OV_TRIP (0x09)
BIT
7
OV_T7
1
6
OV_T6
0
5
OV_T5
1
4
OV_T4
0
3
OV_T3
1
2
OV_T2
1
1
OV_T1
0
0
OV_T0
0
NAME
RESET
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
OV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired OV protection threshold, with upper 2 MSB set to 10 and lower
4 LSB set to 1000. The equivalent OV threshold is mapped to:
10-OV_T<7:0>1000.
By default, OV_TRIP is configured to a 0xAC setting.
Note that OV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in
ADCGAIN<4:0>and ADCOFFSET<7:0>.
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表8-13. UV_TRIP (0x0A)
BIT
7
UV_T7
1
6
UV_T6
0
5
UV_T5
0
4
UV_T4
1
3
UV_T3
0
2
UV_T2
1
1
UV_T1
1
0
UV_T0
1
NAME
RESET
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
UV_T7:0 (Bits 7–0): Middle 8 bits of the direct ADC mapping of the desired UV protection threshold, with upper 2 MSB set to 01 and lower
4 LSB set to 0000. In other words, the equivalent OV threshold is mapped to: 01-UV_T<7:0>–0000.
By default, UV_TRIP is configured to a 0x97 setting.
Note that UV_TRIP is based on the ADC voltage, which requires back-calculation using the GAIN and OFFSET values stored in
ADCGAIN<4:0>and ADCOFFSET<7:0>.
表8-14. CC_CFG REGISTER (0x0B)
BIT
7
6
5
CC_CFG5
0
4
CC_CFG4
0
3
CC_CFG3
0
2
CC_CFG2
0
1
CC_CFG1
0
0
CC_CFG0
0
NAME
—
0
—
0
RESET
ACCESS
R
R
RW
RW
RW
RW
RW
RW
CC_CFG5:0 (Bits 5–0): For optimal performance, these bits should be programmed to 0x19 upon device startup.
8.5.2 Read-Only Registers
表8-15. CELL VOLTAGE REGISTERS
VC1_HI, _LO (0x0C–0x0D), VC2_HI, _LO (0x0E–0x0F), VC3_HI, _LO (0x10–0x11), VC4_HI, _LO (0x12–0x13), VC5_HI, _LO
(0x14–0x15) / BQ76930, BQ76940: VC6_HI, _LO (0x16–0x17), VC7_HI, _LO (0x18–0x19), VC8_HI, _LO (0x1A–0x1B), VC9_HI,
_LO (0x1C–0x1D), VC10_HI, _LO (0x1E–0x1F) / BQ76940: VC11_HI, _LO (0x20–0x21), VC12_HI, _LO (0x22–0x23), VC13_HI, _LO
(0x24–0x25), VC14_HI, _LO (0x26–0x27), VC15_HI, _LO (0x28–0x29)
BIT
7
6
5
D13
0
4
D12
0
3
D11
0
2
D10
0
1
D9
0
0
D8
0
NAME
RESET
NAME
RESET
—
0
—
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D11:8 (Bits 3–0): Cell “x”ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the
same transaction (using address auto-increment).
D7:0 (Bits 7–0): Cell ”x”ADC reading, lower 8 LSB.
表8-16. BAT_HI (0x2A) and BAT_LO (0x2B)
BIT
7
D15
0
6
D14
0
5
D13
0
4
D12
0
3
D11
0
2
D10
0
1
D9
0
0
D8
0
NAME
RESET
NAME
RESET
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D15:8 (Bits 7–0): BAT calculation based on adding up Cells 1–15, upper 8 MSB. Always returned as an atomic value if both high and low
registers are read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): BAT calculation based on adding up Cells 1–15, lower 8 LSB
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表8-17. TS1_HI (0x2C) and TS1_LO (0x2D)
BIT
7
6
5
D13
0
4
D12
0
3
D11
0
2
D10
0
1
D9
0
0
D8
0
NAME
RESET
NAME
RESET
—
0
—
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D11:8 (Bits 3–0): TS1 or DIETEMP ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are
read in the same transaction (using address auto-increment).
D7:0 (Bits 7–0): TS1 or DIETEMP ADC reading, lower 8 LSB
表8-18. TS2_HI (0x2E) and TS2_LO (0x2F)
BIT
7
6
5
D13
0
4
D12
0
3
D11
0
2
D10
0
1
D9
0
0
D8
0
NAME
RESET
NAME
RESET
—
0
—
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D11:8 (Bits 3–0): TS2 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same
transaction (using address auto-increment).
D7:0 (Bits 7–0): TS2 ADC reading, lower 8 LSB
表8-19. TS3_HI (0x30) and TS3_LO (0x31)
BIT
7
6
5
D13
0
4
D12
0
3
D11
0
2
D10
0
1
D9
0
0
D8
0
NAME
RESET
NAME
RESET
—
0
—
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
D11:8 (Bits 3–0): TS3 ADC reading, upper 6 MSB. Always returned as an atomic value if both high and low registers are read in the same
transaction (using address auto-increment).
D7:0 (Bits 7–0): TS3 ADC reading, lower 8 LSB
表8-20. CC_HI (0x32) and CC_LO (0x33)
BIT
7
CC15
0
6
CC14
0
5
CC13
0
4
CC12
0
3
CC11
0
2
CC10
0
1
CC9
0
0
CC8
0
NAME
RESET
NAME
RESET
CC7
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
CC15:8 (Bits 7–0): Coulomb counter upper 8 MSB. Always returned as an atomic value if both high and low registers are read in the same
transaction (using address auto-increment).
CC7:0 (Bits 7–0): Coulomb counter lower 8 LSB
表8-21. ADCGAIN1 (0x50)
BIT
7
6
5
4
3
ADCGAIN4
—
2
ADCGAIN3
—
1
0
NAME
RESET
—
—
—
—
—
—
—
—
—
—
—
—
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表8-21. ADCGAIN1 (0x50) (continued)
BIT
7
6
5
4
3
2
1
0
ACCESS
R
R
R
R
R
R
R
R
表8-22. ADCGAIN2 (0x59)
BIT
7
6
5
4
3
2
1
0
NAME
ADCGAIN2
ADCGAIN1
ADCGAIN0
—
—
R
—
—
R
—
—
R
—
—
R
—
—
R
RESET
ACCESS
—
—
—
R
R
R
ADCGAIN4:3 (Bits 3–2, address 0x50):
ADC GAIN offset upper 2 MSB
ADCGAIN2:0 (Bits 7–5, address 0x59):
ADC GAIN offset lower 3 LSB
ADCGAIN<4:0> is a production-trimmed value for the ADC transfer function, in units of µV/LSB. The range is
365 µV/LSB to 396 µV/LSB, in steps of 1 µV/LSB, and may be calculated as follows:
GAIN = 365 µV/LSB + (ADCGAIN<4:0>in decimal) × (1 µV/LSB)
Alternately, a conversion table is provided below:
ADC GAIN
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Gain (µV/LSB)
365
ADC GAIN
0x10
0x11
Gain (µV/LSB)
381
366
382
367
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
383
368
384
369
385
370
386
371
387
372
388
373
389
374
390
375
391
376
392
377
393
378
394
379
395
380
396
表8-23. ADCOFFSET (0x51)
BIT
7
6
5
4
3
2
1
0
NAME
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
OFFSET7
OFFSET6
OFFSET5
OFFSET4
OFFSET3
OFFSET2
OFFSET1
OFFSET0
RESET
—
—
—
—
—
—
—
—
ACCESS
R
R
R
R
R
R
R
R
ADCOFFSET7:0 (Bits 7–0):
ADC offset, stored in 2’s complement format in mV units. Positive full-scale range corresponds to 0x7F and
negative full-scale corresponds to 0x80. The full-scale input range is –128 mV to 127 mV, with an LSB of 1
mV.
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The table below shows example offsets.
ADCOFFSET
0x00
Offset (mV)
0
0x01
1
0x7F
127
–128
–127
–1
0x80
0x81
0xFF
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The BQ769x0 family of battery monitoring AFEs enabling cell parametric measurement and protection is a
variety of 3-series to 15-series Li-ion/li-polymer battery packs.
To evaluate the performance and configurations of the device users need the , BQ76940, BQ76930, and
BQ76920 Evaluation Software tool to configure the internal registers for a specific battery pack and application.
The Evaluation Software tool is a graphical user-interface tool installed on a PC during development. This can be
used in conjunction with the BQ76920EVM, BQ76930EVM or BQ76940EVM.
The BQ769x0 devices are expected to be implemented in a system with a microcontroller that can perform
additional functions based on the data made collected. The BQ78350-R1 is one example of a companion to the
BQ769x0 family. Additional application information is available in the BQ769x0 Family Top Design
Considerations Application Report.
9.1.1 Device Timing
The device timeline accuracy is typically 3.5%. Each five-cell group in the BQ76930 and BQ76940 devices uses
an independent 250-ms timeline, so voltage and temperature measurements of different groups drift with respect
to one another.
9.1.2 Random Cell Connection
The device design anticipated transient conditions during cell connection, but that design did not result in unique
specifications. The large component value ranges used in the application circuits may require special
considerations for random cell connection. See additional information in the BQ769x0 Family Top Design
Considerations Application Report.
9.1.3 Power Pin Diodes
The VC5X, VC10X, and BAT pins must have a diode from the top group input to the associated power pin, as
shown in 图 9-2 and 图 9-3. These diodes limit the excursion of the input voltage above the supply. The diodes
should be conventional diodes rather than Schottky type to allow some variation of the supply voltage without
loading the cell input. When needed, two diodes may be used in series.
9.1.4 Alert Pin
The ALERT pin is an input and output. The input is sensitive to noise and may benefit from a RC filter at the pin
to reduce noise at the pin. A maximum 250-μs time constant is suggested to allow the pin to fall when it is
cleared as an output before it is sampled as an input. 500-kΩ and 470-pF values are commonly recommended.
Guard traces around the traces may be helpful to avoid crosstalk to the ALERT trace.
9.1.5 Sense Inputs
The SRP input should operate near VSS, so VSS references the battery negative on the battery side of the
sense resistor near the filter connection for SRP. The SRP and SRN have a common mode range to their supply
from REGOUT and the VSS rail. When moving away from the recommended level due to high current or a buffer
amplifier, the OCD and SCD may still trip, but accuracy could be compromised.
9.1.6 TSn Pins
The TSn pins must connect with a thermistor or resistor to the reference power pin for the associated cell group,
as shown in the applications diagram. A resistor must be connected for normal operation even if external
temperature measurement is not used. When thermistors are removable, they should be substituted with a test
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resistance at board test to prevent XREADY faults during test. The TSn pins should not be pulled below their
reference power pin or the device may not start properly or the ADC may not operate properly.
A capacitor across the thermistor is not required but may filter noise picked up by thermistor leads. The
thermistor is biased 37.5 ms before measurement begins, so a 4.7-nF capacitor, such as is used on the
evaluation module or smaller, allows many time constants for settling before measurement.
备注
The capacitor across the thermistor does not filter noise that may be picked up by the thermistor leads
between different thermistors on the BQ76930 or BQ76940 devices.
TS1 is also used to boot the part. A rising edge is required for boot. A high level maintained on TS1 does not
prevent shutdown or waking the part. A voltage level maintained on the TS1 pin after boot affects the voltage on
the thermistor and the temperature determined by the MCU if external temperature sensing is used in normal
operation.
9.1.7 Unused Pins
Pins should be connected to the appropriate circuits, as shown in the simplified diagrams in Typical Applications
and as described in the Pin Configuration and Functions section. See Pin Usage for additional comments.
表9-1. Pin Usage
PIN NAME
RECOMMENDATION
DSG, CHG
VSS
DSG and CHG are outputs and may be left unconnected if not used.
Must be used
Must be used
SDA, SCL
TSn
Must have a thermistor or pull down resistor to the group reference.
TS1 must have a rising edge to boot the part.
CAPn
A capacitor must be installed.
REGOUT
REGOUT also supplies internal circuits. A capacitor must be
installed even if REGOUT is not used for external circuitry.
REGSRC
BAT
Must be supplied
Primary power pin for the part, must be connected to the top cell
through the power filter
VC5x, VC10x
NC
Must connect to the appropriate cell through the power filter
Some pins named NC must be connected to the appropriate CAPn
pin. See Pin Configuration and Functions .
VCn
Cell voltage sense input pins. Must be connected through the input
filter to the cells. When not all cells are needed, connect as
described in Configuring Alternative Cell Counts.
SRP, SRN
ALERT
Current sense inputs. When not used, connect to VSS.
When not used, a pulldown is recommended. See Alert Pin.
9.1.8 Configuring Alternative Cell Counts
Each BQ769x0 family of IC's support a variety of cell counts. The following tables provide guidance on which
device and which input pins to use, depending on the number of cells in the pack.
表9-2. Cell Connections for BQ76920
Cell Input
VC5–VC4
VC4–VC3
VC3–VC2
VC2–VC1
VC1–VC0
3 Cells
CELL 3
short
4 Cells
CELL 4
short
5 Cells
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
short
CELL 3
CELL 2
CELL 1
CELL 2
CELL 1
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表9-3. Cell Connections for BQ76930
Cell Input
VC10–VC9
VC9–VC8
VC8–VC7
VC7–VC6
VC6–VC5b
VC5–VC4
VC4–VC3
VC3–VC2
VC2–VC1
VC1–VC0
6 Cells
CELL 6
short
7 Cells
CELL 7
short
8 Cells
CELL 8
short
9 Cells
CELL 9
short
10 Cells
CELL 10
CELL 9
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
short
short
CELL 7
CELL 6
CELL 5
CELL 4
short
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
CELL 5
CELL 4
CELL 3
short
CELL 6
CELL 5
CELL 4
short
short
CELL 3
CELL 2
CELL 1
CELL 3
CELL 2
CELL 1
CELL 2
CELL 1
表9-4. Cell Connections for BQ76940
Cell Input
VC15–VC14
VC14–VC13
VC13–VC12
VC12–VC11
VC11–VC10b
VC10–VC9
VC9–VC8
VC8–VC7
VC7–VC6
VC6–VC5b
VC5–VC4
VC4–VC3
VC3–VC2
VC2–VC1
VC1–VC0
9 Cells
CELL 9
short
10 Cells
CELL 10
short
11 Cells
CELL 11
short
12 Cells
CELL 12
short
13 Cells
CELL 13
short
14 Cells
CELL 14
short
15 Cells
CELL 15
CELL 14
CELL 13
CELL 12
CELL 11
CELL 10
CELL 9
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
short
short
short
CELL 11
CELL 10
CELL 9
CELL 8
short
CELL 12
CELL 11
CELL 10
CELL 9
short
CELL 13
CELL 12
CELL 11
CELL 10
CELL 9
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
CELL 8
CELL 7
CELL 6
short
CELL 9
CELL 8
CELL 7
short
CELL 10
CELL 9
CELL 8
short
short
short
CELL 7
CELL 6
CELL 5
CELL 4
short
CELL 7
CELL 6
CELL 5
CELL 4
short
CELL 8
CELL 7
CELL 6
CELL 5
CELL 4
CELL 3
CELL 2
CELL 1
CELL 5
CELL 4
CELL 3
short
CELL 6
CELL 5
CELL 4
short
short
CELL 3
CELL 2
CELL 1
CELL 3
CELL 2
CELL 1
CELL 3
CELL 2
CELL 1
CELL 2
CELL 1
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9.2 Typical Applications
CAUTION
The external circuitries in the following schematics show minimum requirements to ensure device
robustness during cell connection to the PCB and normal operation.
PACK
+
Rf
BAT
VC 5
VC 4
VC 3
VC 2
VC 1
VC 0
SRP
REGSRC
REGOUT
Rc
Rc
Rc
Rc
Rc
Cc
Cc
Cc
CAP
1
10 kΩ
TS 1
1 µF
1 µF
4.7 µF
Cf
SCL
SDA
VSS
CHG
DSG
10
k
SRN
ALERT
PUSH
- BUTTON FOR BOOT
Cc
Cc
VCC
SCL
SDA
GPIO
VSS
Companion
Controller
Cc
1 M
Rc
0 .1 µF
100
0 .1 µF
0 .1 µF
100
1 M
1 M
Rsns
PACK
–
图9-1. BQ76920 with BQ78350 Companion Controller IC
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PACK+
Rc
Cc
Rc
Cc
Rc
Cc
Rf
Rc
BAT
VC10
Cc
CAP2
VC9
VC8
TS2
NC
NC
Rc
Cf
Cc
VC7
10k
1 µF
VC5x
VC6
Cc
Rc
A
VC5b
VC5x
A
Rf
VC5
REGSRC
Rc
VC4
REGOUT
CAP1
Cc
VC3
10 kΩ
10k
Rc
VC2
TS1
1µF
1µF
Cf
4.7 µF
Cc
VC1
SCL
SDA
VSS
Rc
Rc
Rc
Rc
VC0
Cc
SRP
SRN
CHG
DSG
PUSH-BUTTON FOR BOOT
Cc
Cc
ALERT
VCC
SCL
SDA
GPIO
VSS
Companion
Controller
Cc
1M
0.1 µF
100
0.1 µF
Rsns
0.1µF
100
1M
1M
PACK-
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图9-2. BQ76930 With BQ78350 Companion Controller IC
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PACK+
Rc
Rc
Cc
Cc
Cc
Rc
Rc
Rc
Cc
Cc
VC10
x
Cc
Rc
Rf
B
Rc
Rc
Rc
Rc
Rc
Rc
Cc
Cc
Cc
VC15
VC14
VC13
VC12
VC11
VC10b
VC10
VC9
BAT
CAP3
TS3
NC
Cf
10k
1 µF
NC
VC10x
CAP2
B
Cc
Cc
Rf
VC8
TS2
NC
Cf
VC7
10k
1 µF
VC5x
Cc
VC6
NC
A
VC5b
VC5
VC5x
A
Rf
REGSRC
REGOUT
CAP1
Rc
Rc
Rc
Rc
Rc
Rc
VC4
Cc
Cc
Cc
VC3
10 kΩ
10k
VC2
TS1
1µF
1µF
Cf
4.7 µF
VC1
SCL
SDA
VSS
CHG
DSG
VC0
SRP
SRN
PUSH-BUTTON FOR BOOT
Cc
Cc
ALERT
VCC
SCL
SDA
GPIO
VSS
Companion
Controller
Cc
1M
0.1 µF
100
0.1 µF
Rsns
0.1 µF
100
1M
1M
PACK–
Copyright © 2016, Texas Instruments Incorporated
图9-3. BQ76940 with BQ78350 Companion Controller IC
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1 Mꢀ
Rpchg
10 Mꢀ
Rgs
Rc
Cc
PACK+
10 Mꢀ
Rgs
10 Mꢀ
Rgs
Rc
Cc
Rc
Cc
Rc
Cc
Rc
Cc
VC10x
Cc
Rc
B
Analog Front End
Rf
Rc
470 nF
CVDDCP
100 ꢀ
Rfilter
Cc
Cc
Cc
VC15
VC14
VC13
VC12
VC11
VC10b
VC10
VC9
bq76200
VDDCP
100 ꢀ
Rfilter
BAT
CHG
NC
Rc
Rc
Rc
CAP3
BAT
0.01 µF
Cfilter
TS3
PCHG
NC
NC
Cf
10k
1 µF
Rf
Rf
CHG_EN
CP_EN
DSG_EN
DSG
PACK
VC10x
CAP2
Cc
Cc
A
0.01 µF
Cfilter
PMON_EN PACKDIV
VC8
TS2
Cf
Rc
PCHG_EN
VSS
bq76940
VC7
VC6
VC5b
VC5
VC4
VC3
VC2
VC1
VC0
SRP
SRN
ALERT
VC5x
10k
1 µF
Ra
Cc
Rc
Rc
Rc
Rc
Rc
Rc
Rc
VC5x
REGSRC
REGOUT
CAP1
A
Cc
Cc
Cc
10 kΩ
10 kꢀ
TS1
1 µF
Cf
1 µF
4.7 µF
SCL
SDA
VSS
CHG
DSG
Cc
Cc
GPIO
GPIO
GPIO
VCC
SCL
PUSH-BUTTON FOR BOOT
ADC_IN
µC
SDA
GPIO
VSS
Cc
Rb
0.1 µF 0.1 µF 0.1 µF
100 ꢀ
100 ꢀ
Rsns
PACK-
图9-4. BQ76940 with BQ78350 Companion Controller IC and BQ76200 High-Side N-Channel FET Driver
9.2.1 Design Requirements
表9-5. BQ769x0 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE at TA = 25°C
Minimum system operating voltage
Cell minimum operating voltage
Series Cell Count
24 V
3.0 V
8
Charge Voltage
33.6 V
3.0 A
10.0 A
4.30 V
2s
Maximum Charge Current
Peak Discharge Current
OV Protection Threshold
OV Protection Delay
UV Protection Threshold
UV Protection Delay
2.5 V
4s
OCD Protection Threshold Max
OCD Protection Delay Time
SCD Protection Threshold Max
15 A
320 ms
25 A
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表9-5. BQ769x0 Design Requirements (continued)
DESIGN PARAMETER
EXAMPLE VALUE at TA = 25°C
SCD Protection Delay Time
100 µs
9.2.2 Detailed Design Procedure
To begin the design process, there are some key steps required for component selection and protection
configuration.
9.2.2.1 Step-by-Step Design Procedure
• Determine the number of series cells.
– This value depends on the cell chemistry and the load requirements of the system. For example, to
support a minimum battery voltage of 24 V using Li-CO2 type cells with a cell minimum voltage of 3.0 V,
there needs to be at least 8-series cells.
• Select the correct BQ769x0 device.
– For 8-series cells, the BQ76930 is needed.
– For the correct cell connections, see 表9-3.
• Select the correct protection FETs.
– The BQ76930 uses a low-side drive suitable for N-CH FETs.
– These FETs should be rated for the maximum:
• Voltage, which should be approximately 5 V (DC) 10 V (peak) per series cell: for example, 40 V.
• Current, which should be calculated based on both the maximum DC current and the maximum
transient current with some margin: for example, 30 A.
• Power Dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the
PCB design: for example, 5 W, assuming 5 mΩRDS(ON).
• Select the correct sense resistor.
– The resistance value should be selected to maximize the input bandwidth use of the coulomb counter
range, CCRANGE, as well as keeping the SCD and OCD thresholds in the available selections, and not
exceed the absolute maximum ratings. The sense resistance RSNS is the threshold or input voltage
divided by the current.
• Using the normal max discharge current, RSNS = 200 mV / 10.0 A = 20 mΩmaximum.
• However, considering the maximum SCD threshold of 200 mV and ISCD of 25 A , RSNS = 200 mV / 25
A = 8 mΩmaximum.
• The maximum OCD threshold available is 100 mV, with the maximum current of 15 A, RSNS = 100
mV / 15.0 A = 6.7 mΩmaximum.
– Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin
should also be considered, so RSNS of 5 mΩwould be suitable with a 75-ppm temperature coefficient
and power rating of 5 W.
– With VSS referenced at the SRP terminal charge current creates a negative voltage on SRN. The 5 mΩ
with 3 A charge current is within the absolute maximum range.
• The BQ76930 is chosen, and so the REGSRC pin needs to be powered through a source follower circuit
where the FET is used to provide current for REGSRC from the battery positive terminal while reducing the
voltage to a suitable value for the IC.
– The FET also dissipates the power resulting from the load current and dropped voltage external to the IC
and care should be taken to ensure the correct dissipation ratings are specified by the chosen FET.
• Configure the Current-based protection settings through PROTECT1 and PROTECT2:
– Ideal SCD Threshold = 25 A × 5 mΩ= 125 mV.
• However, the closest options are 111 mV (0x03) and 133 mV (0x04) providing 22.2 A and 26.6 A,
respectively. Both options have the RSNS bit = 1.
• 0x03 (22.2 A) will be used in this example.
– The SCD delay threshold setting for a 100 µs delay is 0x01.
– Therefore, PROTECT1 should be programmed with 0x8B.
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– Ideal OCD Threshold = 15 A × 5 mΩ= 75 mV.
• However, the closest options are 72 mV (0x0A) and 78 mV (0x0B), providing 14.4 A and 15.6 A,
respectively. Both options have the RSNS bit = 1.
• 0x0A (14.4A) will be used in this example.
– The OCD delay threshold setting for a 320-ms delay is 0x05.
– Therefore, PROTECT2 should be programmed with 0x5B.
备注
Care should be taken when determining the setting of OV_TRIP and UV_TRIP as these are ADC
value outputs and correlation to cell voltage also requires consideration of the ADC GAIN and ADC
OFFSET registers. More specific details can be found in 节8.3.1.2.
• Configure the Voltage-based protection settings through OV_TRIP, UV_TRIP and PROTECT3:
– The selected OV Threshold is 4.30 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 11257
or 0x2BF9.
• Therefore, OV_TRIP should be programmed with 0xBF.
– The selected UV Threshold is 2.5 V. If ADCOFFSET is 0 and GAIN is 382, the desired threshold is 6545
or 0x1991.
• Therefore, UV_TRIP should be programmed with 0x99.
– The selected OV Delay is 2 s and the selected UV Delay is 4 s.
• Therefore, PROTECT3 should be programmed with 0x50.
9.2.3 Application Curves
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
œ1.2
œ1.4
œ1.6
±0±2±
±0±18
±0±16
±0±14
±0±12
±0±1±
±0±±8
±0±±6
±0±±4
±0±±2
±0±±±
±±0±±2
±±0±±4
VC1 Error
VC2 Error
VC3 Error
VC4 Error
VC5 Error
10
35
60
85
œ40
œ15
20±± 203± 206± 209± 302± 305± 308± 401± 404± 407± 50±±
Temperature (°C)
VCx Input (V)
C002
C±±1
图9-6. Coulomb Counter Offset
图9-5. BQ76930 VCx Error Across Input Range at
25°C
10 Power Supply Recommendations
The BQ769x0 devices are powered through the BAT and REGSRC pins but the BQ76930 and BQ76940 have
additional ‘Power’pins to provide the power to the entire device in the higher cell configurations.
The use of Rf and Cf connected to the BAT pin, noted in the typical application diagrams, are required to filter
system transients from disturbing the device power supply. These components should be placed as close as to
the IC as possible.
Additionally, for the BQ76930 and BQ76940 there are additional requirements to ensure a stable power supply to
the device. The REGSRC pin is powered through a source follower circuit where the FET is used to provide
current for REGSRC from the battery positive terminal while reducing the voltage to a suitable value for the IC.
The FET also dissipates the power resulting from the load current and dropped voltage external to the IC and
care should be taken to ensure the correct dissipation ratings are specified by the chosen FET.
The BQ76920 does not use a FET because the battery voltage is within the REGSRC range.
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More information on this topic is available in the BQ769x0 Family Top Design Considerations Application Report.
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11 Layout
11.1 Layout Guidelines
It is strongly recommended for best measurement performance to keep high current signals from interfering with
the measurement system inputs and ground.
A second key recommendation is to ensure that the BQ769x0 input filtering capacitors and power capacitors are
connected to a common ground with as little parasitic resistance between the connections as possible.
11.2 Layout Example
图 11-1 shows a guideline of how to place key components compared to respective ground zones, based on the
BQ76920, BQ76930, and BQ76940 EVMs.
Low Current Ground Plane Available Area
Key components placed here
bq78350
bq76920/30/40
Measurement Filter
Ground
Resistors and Capacitors
interconnect
BAT-
PACK-
PACK+
RSNS
DSG
CHG
Key components placed here
Protection FETs
Sense Resistor
BAT+
High Current Ground Plane Available Area
图11-1. System Component Placement Layout vs. Ground Zone Guide
CAUTION
Care should be taken when placing key power pin capacitors to minimize PCB trace impedances.
These impedances could result in device resets or other unexpected operations when the device is
at peak power consumption.
Although not shown in the diagrams, this caution also applies to the resistor and capacitor network
surrounding the current sense resistor.
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BATTERY–
bq76920
REGSRC
REGOUT
VC1
VC0
PCB Trace impedance
VSS
SENSE
RESISTOR
图11-2. Good Layout: Input Capacitor Grounding With Low Parasitic PCB Impedance
BATTERY–
bq76920
REGSRC
REGOUT
VC1
VC0
PCB Trace impedance
VSS
SENSE
RESISTOR
图11-3. Weak Layout: Input Capacitor Grounding with High Parasitic PCB Impedance
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12 Device and Documentation Support
12.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 Documentation Support
For related documentation, see the following:
• BQ76200 High Voltage Battery Pack Front-End Charge/Discharge High-Side NFET Driver Data Sheet
(SLUSC16)
• BQ769x0 Family Top Design Considerations Application Report (SLUA749)
• BQ769x0 Boot Switch Alternatives Application Report (SLUA769)
• BQ769x0 Pin Equivalent Diagrams (SLVA682)
• BQ769x0 BMS Configurations for Cordless Appliances (SLUA810)
• Fault Monitoring for High-Availability Systems Using the BQ769x0 (SLUA805)
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
BQ76920
BQ76930
BQ76940
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Trademarks
所有商标均为其各自所有者的财产。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7692000PW
BQ7692000PWR
BQ7692003PW
BQ7692003PWR
BQ7692006PW
BQ7692006PWR
BQ7693000DBT
BQ7693000DBTR
BQ7693001DBT
BQ7693001DBTR
BQ7693002DBT
BQ7693002DBTR
BQ7693003DBT
BQ7693003DBTR
BQ7693006DBT
BQ7693006DBTR
BQ7693007DBT
BQ7693007DBTR
BQ7694000DBT
BQ7694000DBTR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
20
20
20
20
20
20
30
30
30
30
30
30
30
30
30
30
30
30
44
44
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ7692000
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
Call TI | NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
BQ7692000
BQ7692003
BQ7692003
BQ7692006
BQ7692006
BQ7693000
BQ7693000
BQ7693001
BQ7693001
BQ7693002
BQ7693002
BQ7693003
BQ7693003
BQ7693006
BQ7693006
BQ7693007
BQ7693007
BQ7694000
BQ7694000
PW
PW
PW
PW
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7694001DBT
BQ7694001DBTR
BQ7694002DBT
BQ7694002DBTR
BQ7694003DBT
BQ7694003DBTR
BQ7694006DBT
BQ7694006DBTR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
44
44
44
44
44
44
44
44
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ7694001
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
BQ7694001
BQ7694002
BQ7694002
BQ7694003
BQ7694003
BQ7694006
BQ7694006
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Mar-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ7692000PWR
BQ7692003PWR
BQ7692006PWR
BQ7693000DBTR
BQ7693001DBTR
BQ7693002DBTR
BQ7693003DBTR
BQ7693006DBTR
BQ7693007DBTR
BQ7694000DBTR
BQ7694001DBTR
BQ7694002DBTR
BQ7694003DBTR
BQ7694006DBTR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
20
20
20
30
30
30
30
30
30
44
44
44
44
44
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
24.4
24.4
24.4
24.4
24.4
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.8
7.1
7.1
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
24.0
24.0
24.0
24.0
24.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
PW
7.1
8.0
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
8.3
8.0
8.3
8.0
8.3
8.0
8.3
8.0
8.3
8.0
8.3
8.0
11.7
11.7
11.7
11.7
11.7
12.0
12.0
12.0
12.0
12.0
6.8
6.8
6.8
6.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ7692000PWR
BQ7692003PWR
BQ7692006PWR
BQ7693000DBTR
BQ7693001DBTR
BQ7693002DBTR
BQ7693003DBTR
BQ7693006DBTR
BQ7693007DBTR
BQ7694000DBTR
BQ7694001DBTR
BQ7694002DBTR
BQ7694003DBTR
BQ7694006DBTR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
20
20
20
30
30
30
30
30
30
44
44
44
44
44
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
PW
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
BQ7692000PW
BQ7692003PW
BQ7692006PW
BQ7693000DBT
BQ7693001DBT
BQ7693002DBT
BQ7693003DBT
BQ7693006DBT
BQ7693007DBT
BQ7694000DBT
BQ7694001DBT
BQ7694002DBT
BQ7694003DBT
BQ7694006DBT
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
20
20
20
30
30
30
30
30
30
44
44
44
44
44
70
70
70
60
60
60
60
60
60
40
40
40
40
40
530
530
530
530
530
530
530
530
530
530
530
530
530
530
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
PW
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
Pack Materials-Page 3
PACKAGE OUTLINE
DBT0044A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6
6.2
TYP
C
A
0.1 C
PIN 1 INDEX
AREA
42X 0.5
44
1
2X
10.5
11.1
10.9
NOTE 3
22
B
23
0.27
44X
1.2 MAX
0.17
4.5
4.3
NOTE 4
0.08
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220223/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
44X (1.5)
(R0.05) TYP
44
1
44X (0.3)
42X (0.5)
SYMM
23
22
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220223/A 02/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0044A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
44X (1.5)
SYMM
(R0.05) TYP
44
1
44X (0.3)
42X (0.5)
SYMM
22
23
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
4220223/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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