BQ7694202PFBR_技术文档

BQ76942

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SLUSE14A – DECEMBER 2020 – REVISED FEBRUARY 2021

BQ76942 3-Series to 10-Series High Accuracy Battery Monitor and Protector for Li-

Ion, Li- Polymer, and LiFePO₄Battery Packs

1 Features

2 Applications

•

Battery monitoring capability for 3-series to 10-

series cells

•

Cordless power tools and garden tools

Vacuum cleaners

E-bike, e-scooter, and LEV

Non-military drones

Other industrial battery pack (3-series–10-series)

Integrated charge pump for high-side NFET

protection with optional autonomous recovery

Extensive protection suite including voltage,

temperature, current, and internal diagnostics

Two independent ADCs

3 Description

– Support for simultaneous current and voltage

sampling

– High-accuracy coulomb counter with input

offset error < 1 µV (typical)

– High-accuracy cell voltage measurement

< 10 mV (typical)

Wide-range current applications (±200-mV

measurement range across sense resistor)

Integrated secondary chemical fuse drive

protection

The Texas Instruments BQ76942 is

a

highly

integrated, high accuracy battery monitor and

protector for 3-series to 10-series Li-ion, Li-polymer,

and LiFePO₄battery packs. The device includes a

high-accuracy

monitoring

system,

a

highly

configurable protection subsystem, and support for

autonomous or host controlled cell balancing.

Integration includes high-side charge-pump NFET

drivers, dual programmable LDOs for external system

use, and a host communication peripheral supporting

400-kHz I²C, SPI, and HDQ one-wire standards. The

BQ76942 is available in a 48-pin TQFP package.

•

Autonomous or host-controlled cell balancing

Multiple power modes (typical battery pack

operating range conditions)

Device Information

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

– NORMAL mode: 286 µA

BQ76942xx

PFB (48-pin)

7 mm × 7 mm

– Multiple SLEEP mode options: 24 µA to 41 µA

– Multiple DEEPSLEEP mode options: 9 µA to

10 µA

(1) See the Device Comparison Table for information on the

device family. For all available devices, see the orderable

addendum at the end of the data sheet.

– SHUTDOWN Mode: 1 µA

•

High-voltage tolerance of 85 V on cell connect and

select additional pins

Tolerant of random cell attach sequence on

production line

Support for temperature sensing using internal

sensor and up to nine external thermistors

Integrated one-time-programmable (OTP) memory

programmable by customers on production line

Communication options include 400-kHz I²C, SPI,

and HDQ one-wire interface

PACK+

CHG

DSG

CAN

TRANSCEIVER

5 V

COMM TO

SYSTEM

+

COMM

NC

REGIN

VC9

NC

REG1

REG2

VDD

3.3 V

VC8

NC

RST_SHUT

DDSG

VC7

NC

DCHG

DFETOFF

CFETOFF

HDQ

MCU

VC6

NC

Dual programmable LDOs for external system

usage

48-pin TQFP package (PFB)

SDA

VC5

NC

SCL

ALERT

VC4

GND

+

PACKœ

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

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intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

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1

DATA.

BQ76942

www.ti.com

SLUSE14A – DECEMBER 2020 – REVISED FEBRUARY 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 3

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings ....................................... 7

7.2 ESD Ratings .............................................................. 8

7.3 Recommended Operating Conditions ........................8

7.4 Thermal Information BQ76942 .................................10

7.5 Supply Current .........................................................10

7.6 Digital I/O ................................................................. 10

7.7 LD Pin ...................................................................... 11

7.8 Precharge (PCHG) and Predischarge (PDSG)

FET Drive ................................................................... 11

7.9 FUSE Pin Functionality ............................................ 11

7.10 REG18 LDO ...........................................................12

7.11 REG0 Pre-regulator ............................................... 12

7.12 REG1 LDO .............................................................13

7.13 REG2 LDO .............................................................13

7.14 Voltage References ................................................13

7.15 Coulomb Counter ...................................................14

7.16 Coulomb Counter Digital Filter (CC1) .................... 14

7.17 Current Measurement Digital Filter (CC2) ............. 14

7.18 Current Wake Detector .......................................... 15

7.19 Analog-to-Digital Converter ....................................15

7.20 Cell Balancing ........................................................17

7.21 Cell Open Wire Detector ........................................17

7.22 Internal Temperature Sensor ................................. 17

7.23 Thermistor Measurement .......................................17

7.24 Internal Oscillators ................................................. 17

7.25 High-side NFET Drivers .........................................18

7.26 Comparator-Based Protection Subsystem .............19

7.27 Timing Requirements – I²C Interface, 100kHz

10.6 Thermistor Temperature Measurement...................37

10.7 Factory Trim of Voltage ADC.................................. 38

10.8 Voltage Calibration (ADC Measurements)..............38

10.9 Voltage Calibration (COV and CUV Protections)....39

10.10 Current Calibration................................................39

10.11 Temperature Calibration........................................39

11 Primary and Secondary Protection Subsystems......40

11.1 Protections Overview.............................................. 40

11.2 Primary Protections.................................................40

11.3 Secondary Protections............................................41

11.4 High-Side NFET Drivers..........................................42

11.5 Protection FETs Configuration and Control.............43

11.6 Load Detect Functionality........................................43

12 Device Hardware Features..........................................44

12.1 Voltage References.................................................44

12.2 ADC Multiplexer......................................................44

12.3 LDOs.......................................................................44

12.4 Standalone Versus Host Interface.......................... 45

12.5 Multifunction Pin Controls....................................... 45

12.6 RST_SHUT Pin Operation......................................46

12.7 CFETOFF, DFETOFF, BOTHOFF Pin

Functionality................................................................ 46

12.8 ALERT Pin Operation............................................. 46

12.9 DDSG and DCHG Pin Operation............................47

12.10 Fuse Drive.............................................................47

12.11 Cell Open Wire......................................................48

12.12 Low Frequency Oscillator..................................... 48

12.13 High Frequency Oscillator.....................................48

13 Device Functional Modes........................................... 49

13.1 Overview.................................................................49

13.2 NORMAL Mode.......................................................49

13.3 SLEEP Mode.......................................................... 50

13.4 DEEPSLEEP Mode.................................................50

13.5 SHUTDOWN Mode.................................................51

13.6 CONFIG_UPDATE Mode........................................52

14 Serial Communications Interface...............................52

14.1 Serial Communications Overview...........................52

14.2 I²C Communications Subsystem............................ 52

14.3 SPI Communications Interface............................... 54

14.4 HDQ Communications Interface............................. 60

15 Cell Balancing..............................................................62

15.1 Cell Balancing Overview.........................................62

16 Application and Implementation................................63

16.1 Application Information........................................... 63

16.2 Typical Applications................................................ 63

16.3 Random Cell Connection Support.......................... 69

16.4 Startup Timing.........................................................70

16.5 FET Driver Turn-Off................................................ 71

16.6 Unused Pins............................................................73

17 Power Supply Requirements......................................75

18 Layout...........................................................................75

18.1 Layout Guidelines................................................... 75

18.2 Layout Example...................................................... 75

19 Device and Documentation Support..........................78

19.1 Third-Party Products Disclaimer............................. 78

19.2 Documentation Support.......................................... 78

19.3 Support Resources................................................. 78

19.4 Trademarks.............................................................78

Mode .......................................................................... 21

7.28 Timing Requirements – I²C Interface, 400kHz

Mode .......................................................................... 21

7.29 Timing Requirements – HDQ Interface ..................22

7.30 Timing Requirements – SPI Interface .................... 22

7.31 Interface Timing Diagrams......................................23

7.32 Typical Characteristics............................................25

8 Device Description........................................................ 31

8.1 Overview...................................................................31

8.2 BQ76942 Device Versions........................................31

8.3 Functional Block Diagram.........................................32

8.4 Diagnostics............................................................... 32

9 Device Configuration.................................................... 33

9.1 Commands and Subcommands................................33

9.2 Configuration Using OTP or Registers......................33

9.3 Device Security.........................................................33

9.4 Scratchpad Memory..................................................33

10 Measurement Subsystem........................................... 34

10.1 Voltage Measurement.............................................34

10.2 General Purpose ADCIN Functionality................... 36

10.3 Coulomb Counter and Digital Filters.......................36

10.4 Synchronized Voltage and Current Measurement.. 36

10.5 Internal Temperature Measurement........................37

2

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19.5 Electrostatic Discharge Caution..............................78

20 Mechanical, Packaging, Orderable Information....... 78

19.6 Glossary..................................................................78

4 Revision History

Changes from Revision * (November 2020) to Revision A (January 2021)

Page

•

Updated Description .......................................................................................................................................... 1

Updated the BQ76942xy devices from PRODUCT PREVIEW to Production Data............................................4

Updated Specifications ......................................................................................................................................7

Updated Typical Characteristics ...................................................................................................................... 25

Updated Voltage Measurement ....................................................................................................................... 34

Updated I²C Communications Subsystem .......................................................................................................52

Updated SPI Communications Interface ..........................................................................................................54

Updated SPI Protocol ...................................................................................................................................... 55

Updated HDQ Communications Interface ....................................................................................................... 60

Updated Documentation Support .................................................................................................................... 78

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5 Device Comparison Table

BQ76942 Device Family

PART NUMBER

BQ76942

Communications Interface

CRC Enabled

REG1 LDO Default

I²C

SPI

I²C

SPI

N

Y

Disabled

BQ7694201

BQ7694202

BQ7694203

BQ7694204

Disabled

Enabled, set to 3.3 V

Enabled, set to 5 V

Enabled, set to 3.3 V

6 Pin Configuration and Functions

NC

VC9

NC

1

36

35

34

33

32

31

30

29

28

27

26

25

REGIN

2

REG1

3

REG2

VC8

NC

4

RST_SHUT

DDSG

5

VC7

NC

6

DCHG

DFETOFF

CFETOFF

HDQ

7

VC6

NC

8

9

VC5

NC

10

11

12

SDA

SCL

VC4

ALERT

Not to scale

Figure 6-1. Pinout (top)

Table 6-1. BQ76942 TQFP Package (PFB) Pin Functions

NAME

I/O

TYPE

DESCRIPTION

NO.

1

NC

VC9

NC

—

This pin is not connected to silicon.

Sense voltage input pin for the ninth cell from the bottom of the stack, balance current

input for the ninth cell from the bottom of the stack, and return balance current for the tenth

cell from the bottom of the stack

2

3

I

IA

—

This pin is not connected to silicon.

4

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Table 6-1. BQ76942 TQFP Package (PFB) Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

4

NAME

VC8

NC

Sense voltage input pin for the eighth cell from the bottom of the stack, balance current

input for the eighth cell from the bottom of the stack, and return balance current for the

ninth cell from the bottom of the stack

I

—

I

IA

—

IA

—

IA

—

IA

—

IA

5

This pin is not connected to silicon.

Sense voltage input pin for the seventh cell from the bottom of the stack, balance current

input for the seventh cell from the bottom of the stack and return balance current for the

eighth cell from the bottom of the stack

6

VC7

NC

7

—

I

This pin is not connected to silicon.

Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input

for the sixth cell from the bottom of the stack, and return balance current for the seventh

cell from the bottom of the stack

8

VC6

NC

9

—

I

This pin is not connected to silicon.

Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input

for the fifth cell from the bottom of the stack, and return balance current for the sixth cell

from the bottom of the stack

10

11

12

VC5

NC

—

I

This pin is not connected to silicon.

Sense voltage input pin for the fourth cell from the bottom of the stack, balance current

input for the fourth cell from the bottom of the stack, and return balance current for the fifth

cell from the bottom of the stack

VC4

Sense voltage input pin for the third cell from the bottom of the stack, balance current input

for the third cell from the bottom of the stack, and return balance current for the fourth cell

from the bottom of the stack

13

14

15

VC3

VC2

VC1

I

IA

Sense voltage input pin for the second cell from the bottom of the stack, balance current

input for the second cell from the bottom of the stack, and return balance current for the

third cell from the bottom of the stack

Sense voltage input pin for the first cell from the bottom of the stack, balance current input

for the first cell from the bottom of the stack, and return balance current for the second cell

from the bottom of the stack

Sense voltage input pin for negative terminal of the first cell from the bottom of the stack,

and return balance current for first cell from the bottom of the stack

16

17

VC0

VSS

I

IA

P

—

Device ground

Analog input pin connected to the internal coulomb counter peripheral for integrating a

small voltage between SRP and SRN, where SRP is the top of the sense resistor. A

charging current generates a positive voltage at SRP relative to SRN.

18

19

20

SRP

NC

I

—

I

IA

—

IA

This pin is not connected to silicon.

Analog input pin connected to the internal coulomb counter peripheral for integrating a

small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A

charging current generates a positive voltage at SRP relative to SRN.

SRN

21

22

TS1

TS2

I/O

OD, I/OA Thermistor input, or general purpose ADC input

Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC

OD, I/OA

input

23

24

TS3

I/O

O

OD, I/OA Thermistor input, or general purpose ADC input

REG18

P

Internal 1.8 V-LDO output (only for internal use)

Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general

purpose ADC input, or general purpose digital output

25

ALERT

I/O

I/OD, I/OA

26

27

SCL

SDA

I/O

I/OD

Multifunction pin, can be SCL or SPI_SCLK

Multifunction pin, can be SDA or SPI_MISO

Multifunction pin, can be HDQ I/O, or SPI_MOSI, or thermistor input, or general purpose

ADC input, or general purpose digital output

28

29

HDQ

I/O

I/OD, I/OA

Multifunction pin, can be CFETOFF, or SPI_CS, or thermistor input, or general purpose

ADC input, or general purpose digital output

CFETOFF

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Table 6-1. BQ76942 TQFP Package (PFB) Pin Functions (continued)

NAME

I/O

TYPE

DESCRIPTION

NO.

Multifunction pin, can be DFETOFF or BOTHOFF, or thermistor input, or general purpose

ADC input, or general purpose digital output

30

DFETOFF

DCHG

I/O

I/OD, I/OA

OD, I/OA

Multifunction pin, can be DCHG, or thermistor input, or general purpose ADC input, or

general purpose digital output

31

Multifunction pin, can be DDSG, or thermistor input, or general purpose ADC input, or

general purpose digital output

32

33

34

DDSG

RST_SHUT

REG2

I/O

I

OD, I/OA

ID

P

Digital input pin for reset or shutdown

Second LDO (REG2) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or

5.0 V

O

35

36

37

38

39

40

41

42

43

44

45

46

47

REG1

REGIN

BREG

FUSE

PDSG

PCHG

LD

O

I

P

IA

First LDO (REG1) output, which can be programmed for 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V

Input pin for REG1 and REG2 LDOs

Base control signal for external preregulator transistor

Fuse sense and drive

O

I/O

O

I/O

I

OA

I/OA

OA

I/OA

IA

Predischarge PFET control

Precharge PFET control

Load detect pin

PACK

DSG

NC

Pack sense input pin

O

—

O

I/O

I

OA

—

NMOS discharge FET drive output pin

This pin is not connected to silicon.

NMOS charge FET drive output pin

Charge pump capacitor

CHG

CP1

OA

I/OA

P

BAT

Primary power supply input pin

Sense voltage input pin for the tenth cell from the bottom of the stack, balance current

input for the tenth cell from the bottom of the stack, and top-of-stack measurement point

48

VC10

I

IA

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

DESCRIPTION

PINS

MIN

VSS–0.3

MAX

VSS+85

UNIT

V

Supply voltage range

BAT

Input voltage range, V_IN

PACK, LD

V

the maximum

of V_BAT–10 or

V_LD–10

PACK, PCHG, PDSG, LD

REGIN

VSS+85

V

the minimum

of VSS+6 or

V_BAT+0.3 or

V_BREG+0.3

the maximum

of VSS–0.3 or

V_BREG–5.5

Input voltage range, V_IN

the minimum

VSS–0.3 of VSS+20 or

V_BAT+0.3

Input voltage range, V_IN

FUSE⁽²⁾

BREG

V

the maximum

of VSS–0.3 or

V_REGIN–0.3

V_REGIN+5.5

minimum of

VSS+6

or V_REGIN+0.3

Input voltage range, V_IN

REG1, REG2

VSS–0.3

V

ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF,

DCHG, DDSG, RST_SHUT ⁽³⁾

VSS+6

TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ,

DCHG, DDSG (when used as thermistor or general

purpose ADC input)

Input voltage range, V_IN

VSS–0.3 V_REG18+ 0.3

V

SRP, SRN

maximum of

VC10

VSS–0.3 and

VC9–0.3

VSS+85

maximum of

VSS–0.3 and

VC8–0.3

Input voltage range, V_IN

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC2

VC1

V

maximum of

VSS–0.3 and

VC7–0.3

maximum of

VSS–0.3 and

VC6–0.3

maximum of

VSS–0.3 and

VC5–0.3

maximum of

VSS–0.3 and

VC4–0.3

maximum of

VSS–0.3 and

VC3–0.3

maximum of

VSS–0.3 and

VC2–0.3

maximum of

VSS–0.3 and

VC1–0.3

maximum of

VSS–0.3 and

VC0–0.3

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over operating free-air temperature range (unless otherwise noted)⁽¹⁾

DESCRIPTION

PINS

MIN

MAX

VSS+6

UNIT

Input voltage range, V_IN

VC0

VSS–0.3

V

the minimum

Output voltage range, V_O

CP1

V_BAT–0.3 of VSS+85 or

V_BAT+15

V

Output voltage range, V_O

CHG

DSG

VSS–0.3

VSS+85

V

REG1, REG2, TS2 (for wakeup function), ALERT,

CFETOFF, DFETOFF, HDQ, DCHG, DDSG, when

configured to drive a digital output

Output voltage range, V_O

VSS–0.3

VSS+6

V

REG18

VSS+2

100

V

Maximum cell balancing current

through a single cell

VC0 – VC10

mA

Maximum VSS current, I_SS

Functional temperature, T_FUNC

Junction temperature, T_J

75

85

mA

°C

–40

–55

150

Storage temperature, T_STG

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The current allowed to flow into the FUSE pin must be limited (such as by using external series resistance) to 2 mA or less.

(3) When the ALERT, HDQ, CFETOFF, DFETOFF, DCHG, or DDSG pins are selected for thermistor input or general purpose ADC–input,

their voltage is limited to V_REG18+ 0.3 V. These pins can accept up to 6 V when configured for other uses, such as a digital input.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

±1000

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±250

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage on BAT pin (normal

operation)

V_BAT

Supply voltage

4.7

55

V

Voltage on BAT pin (OTP

programming)

Supply voltage⁽²⁾

10

12

V

OTP programming

temperature⁽²⁾

T_OTP

–40

3

45

4

°C

V

V_PORA

Power-on reset

Rising threshold on BAT

Device shuts down when BAT <

V_PORA- V_{PORA_HYS}

V_{PORA_HYS}

Power-on reset hysteresis

180

mV

Rising edge on LD, with BAT already

in valid range

V_WAKEONLD

Wake on LD voltage

0.8

1.45

2.25

V

8

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

0.7

0

TYP

MAX

1.1

55

UNIT

Falling edge on TS2, with BAT

already in valid range. TS2 will be

weakly driven with a 5 V level during

shutdown.

V_WAKEONTS2

Wake on TS2 voltage

Input voltage range⁽²⁾

V

V_IN

PACK, LD

the

maximum

of V_BAT–9

or V_LD–9

PCHG, PDSG

55

REG1, REG2, RST_SHUT, ALERT,

SCL, SDA, HDQ, CFETOFF,

DFETOFF, DCHG, DDSG, except

when the pin is being used for

general purpose ADC input or

thermistor measurement.

V_IN

Input voltage range⁽²⁾

0

5.5

V

TS1, TS2, TS3, CFETOFF,

DFETOFF, DCHG, DDSG, ALERT,

HDQ, when the pin is configured for

general purpose ADC input or

thermistor measurement.

V_IN

Input voltage range⁽²⁾

Input voltage range⁽³⁾

0

V_REG18

V

SRP, SRN, SRP-SRN (while

measuring current)

V_IN

–0.2

0.2

SRP, SRN (without measuring

current)

V_IN

Input voltage range⁽²⁾

–0.2

0.75

0.5

V

V_VC(0)

maximum

of V_VC(x–1)

– 0.2 or

minimum

of V_VC(x–

₁₎+5.5 or

VSS+55

V_IN

Input voltage range⁽³⁾

V_VC(x),1 ≤ x ≤ 4

V

VSS–0.2

maximum

of V_VC(x–1)

– 0.2 or

minimum

of V_VC(x–1)

+ 5.5 or

V_IN

Input voltage range

V_VC(x),x ≥ 5

VSS + 2.0

VSS + 55

External cell input resistance⁽²⁾

R_C

20

100

1

Ω

(4)

External cell input

capacitance^{(2) (4)}

0.1

0.22

µF

V_O

Output voltage range

Output voltage range⁽³⁾

Operating temperature⁽³⁾

LD

55

70

85

V

V_O

CHG, DSG, CP1

T_OPR

–40

–5

°C

Cell voltage measurement

accuracy

2 V < V_VC(x)- V_VC(x-1)< 5 V, T_A=

25°C, 1 ≤ x ≤ 10⁽¹⁾

V_CELL(ACC)

V_STACK(ACC)

V_PACK(ACC)

V_LD(ACC)

5

10

mV

V

Cell voltage measurement

accuracy⁽³⁾

2 V < V_VC(x)- V_VC(x-1)< 5 V, T_A= 0°C

to 60°C, 1 ≤ x ≤ 10⁽¹⁾

–10

–15

Cell voltage measurement

accuracy⁽³⁾

–0.2 V < V_VC(x)- V_VC(x-1)< 5.5 V, T_A

= -40°C to 85°C, 1 ≤ x ≤ 10⁽¹⁾

15

Stack voltage (VC10 - VSS)

measurement accuracy⁽³⁾

0 V < V_VC10- V_VSS≤ 55 V, T_A=

-40°C to 85°C⁽¹⁾

–0.5

0.5

PACK pin voltage measurement 0 V < V_PACK- V_VSS≤ 55 V, T_A=

V

accuracy⁽³⁾

-40°C to 85°C⁽¹⁾

LD pin voltage measurement

accuracy⁽³⁾

0 V < V_LD- V_VSS≤ 55 V, T_A= -40°C

to 85°C⁽¹⁾

V

(1) Cell voltage accuracy is specified after completion of board offset calibration

(2) Specified by design

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(3) Specified by characterization

(4) Values may need to be optimized during system design and evaluation for best performance

7.4 Thermal Information BQ76942

BQ76942

PFB (TQFP)

48 PINS

66.0

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

19.6

29.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.8

Ψ_JB

29.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Supply Current

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Regular measurements and protections active,

REG1 = 3.3 V with no load, REG2 = OFF, CHG

= ON in 11 V overdrive mode, DSG = ON in 11 V

overdrive mode, Settings:Configuration:Power

Config[FASTADC] = 0, no communication

I_NORMAL

I_{SLEEP_1}

I_{SLEEP_2}

Normal Mode

286

µA

Periodic protections and monitoring, no pack

current, REG1 = OFF, REG2 = OFF, CHG =

OFF, DSG = ON in 11 V overdrive mode, no

communication, Power:Sleep:Voltage Time = 5

s

SLEEP Mode

41

24

µA

Periodic protections and monitoring, no pack

current, REG1 = OFF, REG2 = OFF, CHG =

OFF, DSG = source follower mode, no

communication, Power:Sleep:Voltage Time = 5

s

No monitoring or protections, REG1 = 3.3 V with

no load, REG2 = OFF, LFO = ON, no

communication

I_{DEEPSLEEP_1}

I_{DEEPSLEEP_2}

I_SHUTDOWN

DEEPSLEEP Mode

SHUTDOWN Mode

10.7

9.2

1

µA

No monitoring or protections, REG1 = 3.3 V with

no load, REG2 = OFF, LFO = OFF, no

communication

All blocks powered down, with the exception of

the TS2 wakeup circuit, no monitoring or

protections, no communication

3.1

µA

7.6 Digital I/O

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

High-level input

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ALERT (configured as HDQ), SCL, SDA,

HDQ, CFETOFF, DFETOFF, RST_SHUT

0.66 x

V_REG18

V_IH

V_IL

5.5

V

ALERT (configured as HDQ), SCL, SDA,

HDQ, CFETOFF, DFETOFF, RST_SHUT

0.33 x

V_REG18

Low-level input

V

TS2 during SHUTDOWN mode, V_BAT> 6

V

V_OH

Output voltage high, TS2

4.5

6

10

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TS2 during SHUTDOWN mode, 4.7 V ≤

V_BAT≤ 6 V

V_OH

Output voltage high, TS2 low voltage

3

6

V

ALERT, SDA (configured as SPI_MISO),

CFETOFF (configured as GPO),

DFETOFF (configured as GPO), DCHG,

DDSG pins driving from REG1, V_REG1set

0.9 x

V_REG1

V_OH

Output voltage high, 5 V case

Output voltage low, 5 V case

V_REG1

V

to 5 V nominal setting, V_BAT> 8 V, I_OH

5.0 mA, 10 pF load

=

ALERT, SCL, SDA, HDQ, DCHG, DDSG,

CFETOFF (configured as GPO),

DFETOFF (configured as GPO), pins

driving from REG1, V_REG1set to 5 V

nominal setting, V_BAT> 8 V, I_OL= -5 mA,

10 pF load

V_OL

0.77

R_OH

C_IN

Output weak high resistance

Input capacitance⁽¹⁾

TS2 during SHUTDOWN mode

4600

2

kΩ

pF

ALERT, SCL, SDA, HDQ, CFETOFF,

DFETOFF, DCHG, DDSG, REGIN, TS1,

TS2, TS3

ALERT, SCL, SDA, HDQ, CFETOFF,

DFETOFF, DCHG, DDSG, REGIN, device

in SHUTDOWN mode

I_LKG

Input leakage current

1

µA

(1) Specified by design

7.7 LD Pin

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_BAT≥ 4.7 V, V_LD= VSS

V_BAT≥ 4.7 V

MIN

TYP

MAX

UNIT

Internal pullup current from BAT pin to LD

pin, used for load detect functionality

I_(PULLUP)

R_PD

35

100

172

µA

Internal pulldown resistance on LD pin in

SHUTDOWN mode

80

kΩ

7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

max(V_PACK, V_BAT)- V_PCHG, V_PACK≥ 8 V,

V_BAT≥ 4.7 V

V_{(PCHG_ON)}

Output voltage, PCHG on

7.5

8.4

9.7

V

V_PACK- V_PCHG, 4.7 V ≤ V_PACK< 8 V, V_BAT

≥ 4.7 V, V_PACK> V_BAT

V_PACK

0.5 V

–

V_{(PCHG_ON)}

V_{(PDSG_ON)}

Output voltage, PCHG on

Output voltage, PDSG on

V_PACK

9.7

V

max(V_LD, V_BAT) - V_PDSG, V_BAT≥ 8 V

7.47

8.4

30

V_BAT- V_PDSG, 4.7 V ≤ V_BAT< 8 V, V_BAT

V_LD

>

V_BAT

0.5 V

–

V_BAT

Current sink capability, PCHG and

PDSG

I_(PULLDOWN)

PCHG and PDSG enabled, V_BAT= 37.0 V

µA

7.9 FUSE Pin Functionality

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_(OH)

Output voltage high (when driving fuse)

V_BAT≥ 8 V, C_L= 1 nF, 5 kΩ load.

6

7

9

V

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_BAT

1.75

–

V_(OH)

Output voltage high (when driving fuse)

4.7 V ≤ V_BAT< 8 V, C_L= 1 nF, 5 kΩ load.

V

Current into device pin must be limited to

maximum 2 mA

V_(IH)

V_(IL)

High-level input (for fuse detection)

Low-level input (for fuse detection)

2

12

V

0.7

V_BAT≥ 8 V, C_L= 1 nF, R_SERIES= 100 Ω,

V_(OH)= 10% to 90% of final settled

voltage

t_(RISE)

Output rise time (when driving fuse)

0.5

µs

7.10 REG18 LDO

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

1.8

TYP

2.2

MAX

22

UNIT

µF

C_REG18

V_REG18

External capacitor, REG18 to VSS⁽¹⁾

Regulator voltage

1.6

1.8

2

V

ΔV_REG18vs (V_REG18at 25°C), I_REG18= 1

mA, V_BAT= 37.0 V

ΔV_O(TEMP)

Regulator output over temperature

Line regulation

±0.15

%

ΔV_REG18vs (V_REG18at 25°C, V_BAT= 37.0

V), I_REG18= 1 mA, as V_BATvaries across

specified range

ΔV_O(LINE)

–0.6

0.5

ΔV_REG18vs (V_REG18, V_BAT= 37.0 V),

I_REG18= 0 mA to 1 mA, at 25°C

ΔV_O(LOAD)

I_SC

Load regulation

–1.5

3

1.5

14

%

Regulator short-circuit current limit

V_REG18= 0 V

mA

(1) Specified by design

7.11 REG0 Pre-regulator

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_BAT≥ 4.7 V

MIN

TYP

MAX

UNIT

Pre-regulator control voltage

headroom ( min(V_BAT- V_BREG) )

V_{BREG_HDRM}

V_{REGIN_INT}

V_{REGIN_EXT}

ΔV_O(TEMP)

I_Max

1.5

1.9

V

Pre-regulator voltage, when

generated using BREG

V_BAT> 8 V, although specific requirement

depends on external device selected

5

5.5

5.8

5.5

V

Pre-regulator voltage when using

externally supplied REGIN⁽³⁾

See requirements based on settings of

REG1 and REG2

ΔV_REGINvs V_REGINat 25°C, I_REGIN= 50

mA, V_BAT> 8 V

Regulator output over temperature

±0.05

3.33

22

%

Maximum current driven out from

BREG

Under short circuit conditions (V_REGIN= 0

V)

2.5

15

mA

External capacitor REGIN to VSS⁽²⁾

C_EXT

27

nF

pF

(3)

C_BREG

External capacitor BREG to VSS⁽³⁾

150

(1) Supported output current is limited for V_STACK< 5.5 V. V_REGINlimited to 2.5 V below V_BAT

(2) Capacitance should be above 7 nF after consideration for aging and derating.

(3) Specified by design

.

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7.12 REG1 LDO

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

1.6

TYP

1.84

2.55

3.05

3.36

5.19

MAX

2

UNIT

V_{REG1_1.8}

V_{REG1_2.5}

V_{REG1_3.0}

V_{REG1_3.3}

V_{REG1_5.0}

Regulator voltage (nominal 1.8V setting) V_REGIN≥ 3.0 V, I_REG1= 0 mA to 45 mA

Regulator voltage (nominal 2.5V setting) V_REGIN≥ 3.5 V, I_REG1= 0 mA to 45 mA

Regulator voltage (nominal 3.0V setting) V_REGIN≥ 3.8 V, I_REG1= 0 mA to 45 mA

Regulator voltage (nominal 3.3V setting) V_REGIN≥ 4.1 V, I_REG1= 0 mA to 45 mA

Regulator voltage (nominal 5.0V setting) V_REGIN≥ 5.0 V, I_REG1= 0 mA to 45 mA

ΔV_REG1vs (V_REG1at 25°C, I_REG1= 20

V

2.25

2.7

2.75

3.3

3.6

5.5

3.0

4.5

ΔV_O(TEMP)Regulator output over temperature

mA, V_REGIN= 5.5 V, V_REG1set to

nominal 3.3 V setting)

±0.25

%

ΔV_REG1vs (V_REG1at 25°C, V_REGIN

=

5.5 V, I_REG1= 20 mA), as V_REGINvaries

from 5 V to 6 V, V_REG1set to nominal

3.3 V setting

ΔV_O(LINE)

Line regulation

–1

1

I_SC

Regulator short-circuit current limit

External capacitor REG1 to VSS⁽¹⁾

V_REG1= 0 V

47

1

80

mA

µF

C_EXT

(1) Specified by design

7.13 REG2 LDO

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

1.6

TYP

1.84

2.55

3.06

3.38

5.23

MAX

2

UNIT

V_{REG2_1.8}

V_{REG2_2.5}

V_{REG2_3.0}

V_{REG2_3.3}

V_{REG2_5.0}

Regulator voltage (nominal 1.8V setting) V_REGIN≥ 3.0 V, I_REG2= 0 mA to 45 mA

Regulator voltage (nominal 2.5V setting) V_REGIN≥ 3.5 V, I_REG2= 0 mA to 45 mA

Regulator voltage (nominal 3.0V setting) V_REGIN≥ 3.8 V, I_REG2= 0 mA to 45 mA

Regulator voltage (nominal 3.3V setting) V_REGIN≥ 4.1 V, I_REG2= 0 mA to 45 mA

Regulator voltage (nominal 5.0V setting) V_REGIN≥ 5.0 V, I_REG2= 0 mA to 45 mA

ΔV_REG2vs (V_REG2at 25°C, I_REG2= 20

V

2.25

2.7

2.75

3.3

3.6

5.5

3.0

4.5

ΔV_O(TEMP)Regulator output over temperature

mA, V_REGIN= 5.5 V, V_REG2set to

nominal 3.3 V setting)

±0.25

%

ΔV_REG2vs (V_REG2at 25°C, V_REGIN

=

5.5 V, I_REG2= 20 mA), as V_REGINvaries

from 5 V to 6 V, V_REG2set to nominal

3.3 V setting

ΔV_O(LINE)

Line regulation

–1

1

I_SC

Regulator short-circuit current limit

External capacitor REG2 to VSS⁽¹⁾

V_REG2= 0 V

47

1

80

mA

µF

C_EXT

(1) Specified by design

7.14 Voltage References

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

VOLTAGE REFERENCE 1

V_(REF1)

Internal reference voltage ⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= 25°C

1.210

1.212

±10

1.214

V

V_(REF1DRIFT)Internal reference voltage drift ^{(1) (3)}

VOLTAGE REFERENCE 2

T_A= -10°C to 60°C

T_A= -40°C to 85°C

PPM/°C

±10

V_(REF2)

Internal reference voltage ⁽²⁾

T_A= 25°C

1.23

1.24

1.25

V

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= -10°C to 60°C

T_A= -40°C to 85°C

MIN

TYP

±20

±50

MAX

UNIT

V_(REF2DRIFT)Internal reference voltage drift^{(2) (3)}

PPM/°C

(1) V_(REF1)is used for the ADC reference. Its effective value is determined through indirect measurement using the ADC and measuring

the differential voltage on VC1 - VC0.

(2) V_(REF2)is used for the LDO, coulomb counter, and current measurement

(3) Specified by characterization

7.15 Coulomb Counter

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range

V_{(CC_IN)}

V_SRP- V_SRN

V_SRP, V_SRN

–0.2

0.2

V

for measurements⁽³⁾

Input voltage range

for measurements⁽³⁾

V_{(CC_IN)}

–0.2

0.2

V

B_{(CC_INL)}

B_{(CC_DNL)}

Integral nonlinearity⁽²⁾16-bit, best fit over input voltage range

±5.2

±0.1

±22.3 LSB⁽¹⁾

LSB⁽¹⁾

Differential

16-bit, no missing codes

nonlinearity⁽²⁾

V_{(CC_OFF)}

Offset error

Offset error drift⁽²⁾

Gain⁽²⁾

16-bit, uncalibrated

–1

–0.03

1

LSB⁽¹⁾

V_{(CC_OFF_DRIFT)}

B_{(CC_GAIN)}

16-bit, post-calibration

0.03 LSB/°C⁽¹⁾

16-bit, over ideal input voltage range

130845

131454

2

132335 LSB/V⁽¹⁾

Effective input

resistance⁽³⁾

R_{(CC_IN)}

MΩ

(1) 1 LSB (16-bit mode, using CC1 filter) = V_REF2/ (5 x 2^N-1) ≈ 1.24 / (5 x 2¹⁵) = 7.6µV

(2) Specified by characterization

(3) Specified by design

7.16 Coulomb Counter Digital Filter (CC1)

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single conversion (when operating from

LFO in 262.144kHz mode)

t_{(CC1_CONV_FAST)}

Conversion-time

250

ms

Single conversion (when operating from

LFO in 32.768kHz mode)

t_{(CC1_CONV_SLOW)}

B_{(CC1_RSL)}

Conversion-time

4

s

Code stability^{(1) (2)}

Single conversion

14.3

bits

(1) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.

(2) Specified by a combination of design and production test

7.17 Current Measurement Digital Filter (CC2)

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 0

t_{(CC2_CONV)}

Conversion-time

2.93

ms

Single conversion, in NORMAL mode,

t_{(CC2_CONV_FAST)}

Conversion-time in fast mode Settings:Configuration:Power

Config[FASTADC] = 1

1.46

ms

14

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 0

B_{(CC2_RES)}

Code stability^{(1) (2)}

14

15

bits

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 1

B_{(CC2_RES_FAST)}

Code stability in fast mode⁽¹⁾

13.5

bits

(1) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.

(2) Specified by characterization

7.18 Current Wake Detector

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= 25°C, V_WAKE= V_SRP– V_SRN, setting

between ±0.5 mV and ±5 mV. Measured

using averaged data to remove effects of

noise.

V_{WAKE_THR}

Wakeup voltage threshold error⁽¹⁾

–200

200

µV

T_A= 25°C, V_WAKE= V_SRP– V_SRN, setting

beyond ±5 mV. Measured using

averaged data to remove effects of noise.

% of

setting

V_{WAKE_THR}

t_WAKE

Wakeup voltage threshold error⁽¹⁾

Measurement interval⁽¹⁾

–5

5

12

ms

(1) Specified by design

7.19 Analog-to-Digital Converter

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

Input voltage range

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_{(ADC_IN_CELLS)}

(differential cell input Internal reference (Vref = V_REF1

)

–0.2

5.5

V

mode)⁽⁴⁾

Internal reference (Vref = V_REF1), applicable

to ADCIN measurements using the TS1, TS2,

TS3, ALERT, CFETOFF, DFETOFF, HDQ,

DCHG, and DDSG pins

Input voltage range

(ADCIN measurement

mode)⁽⁵⁾

V_{(ADC_IN)}

–0.2

V_REG18

V

Regulator reference (Vref = V_REG18),

applicable to external thermistor

measurements using the TS1, TS2, TS3,

ALERT, CFETOFF, DFETOFF, HDQ, DCHG,

and DDSG pins

Input voltage range

(external thermistor

V_{(ADC_IN_TS)}

V_REG18

V

measurement mode)

(6)

Input voltage range

Internal reference (Vref = V_REF1), applicable

(divider measurement to divider measurements using the VC10,

V_{(ADC_IN_DIV)}

–0.2

–6.6

55

mode)⁽⁷⁾

PACK, and LD pins relative to VSS.

Integral nonlinearity

(when using V_REF1

and differential cell

voltage measurement

16-bit, best fit over -0.1 V to 5.5 V

6.6 LSB⁽⁴⁾

B_{(ADC_INL)}

16-bit, best fit over -0.2 V to 0.2 V

–4

4

LSB⁽⁴⁾

mode at VC10 - VC9)

(3)

Differential

nonlinearity

16-bit, no missing codes, using differential

cell voltage measurement at VC10-VC9

B_{(ADC_DNL)}

±0.12

LSB⁽⁴⁾

Differential cell offset

error

B_{(ADC_OFF_CELL)}

16-bit, uncalibrated, using VC10 - VC9

–2.75

3.5 LSB⁽⁴⁾

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SLUSE14A – DECEMBER 2020 – REVISED FEBRUARY 2021

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

ADCIN offset error

Divider offset error

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16-bit, uncalibrated, using ADCIN mode on

TS1 pin

B_{(ADC_OFF)}

0.53

LSB⁽⁵⁾

16-bit, uncalibrated, using divider mode on

PACK pin

B_{(ADC_OFF_DIV)}

0.17

LSB⁽⁷⁾

Offset error measured 16-bit, post calibratoin,

Differential cell offset using VC10 - VC9. Drift measured as

B_{(ADC_OFF_DRIFT_CELL)}

0.004

0.07 LSB/°C⁽⁴⁾

5427 LSB/V⁽⁴⁾

error drift⁽³⁾

change in offset over operating temperature

range as compared to offset at 30°C.

Gain measured 16-bit, over ideal input

voltage range, differential cell input mode on

VC10 - VC9, uncalibrated.

B_{(ADC_GAIN)}

Gain

5385

5406

Gain measured 16-bit, over ideal input

voltage range, differential cell input mode on

VC10 - VC9, uncalibrated. Drift value

measured as change in gain over operating

temperature range, compared to gain at

30°C.

LSB/V/

0.25

B_{(ADC_GAIN_DRIFT)}

Gain drift⁽³⁾

–0.25

3.0

0.025

°C⁽⁴⁾

Effective input

resistance⁽²⁾

R_{(ADC_IN_CELL)}

R_{(ADC_IN_LD)}

Differential cell input mode on VC10 - VC9⁽⁸⁾

MΩ

Effective input

resistance

Divider measurement on LD pin (only active

while the LD pin is being measured)

2

Divider measurement on VC10 and PACK

pins (only active while the pin is being

measured)

Effective input

resistance

R_{(ADC_IN_DIV)}

600

kΩ

bits

ms

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 0

B_{(ADC_RES)}

Code stability^{(1) (3)}

13.5

15

14

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 1

Code stability in fast

mode⁽¹⁾

B_{(ADC_RES_FAST)}

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 0

t_{(ADC_CONV)}

Conversion-time

2.93

1.46

Single conversion, in NORMAL mode,

Settings:Configuration:Power

Config[FASTADC] = 1

Conversion-time in

fast mode

t_{(ADC_CONV_FAST)}

(1) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.

(2) Specified by design

(3) Specified by characterization

(4) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x V_REF1/ 2^N-1≈ 5 x 1.215 V / 2¹⁵= 185 µV

(5) The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x V_REF1/ 2^N-1≈ 5 / 3 x 1.215 V / 2¹⁵= 62 µV

(6) The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x V_REG18/ 2^N-1

≈

5 / 3 x 1.8 V / 2²³= 358 nV

(7) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x V_REF1/ 2^N-1≈ 425 / 3 x 1.215 / 2²³= 5.25 mV

(8) Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, three or more

thermistors in use, and a 5 V differential voltage applied.

16

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7.20 Cell Balancing

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_DS(ON)for internal FET switch at V_VC(n)

V_VC(n-1)= 1.5V, 1 ≤ n ≤ 10, V_BAT≥ 4.7 V

-

R_(CB)

Internal cell balancing resistance⁽¹⁾

15

28

46

Ω

(1) Cell balancing must be controlled to limit the current based on the absolute maximum allowed current, and to avoid exceeding the

recommended device operating temperature. This can be accomplished by appropriate sizing of the offchip cell input resistors and

limiting the number of cells that can be balanced simultaneously.

7.21 Cell Open Wire Detector

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

Internal cell open wire check current from VCx > VSS + 0.8 V, 1 ≤ x ≤ 4; VCx > VSS

VCx pin to VSS, 1 ≤ x ≤ 10 + 2.8 V, 5 ≤ x ≤ 10

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_(OW)

22

54

95

µA

7.22 Internal Temperature Sensor

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_(TEMP)

Internal temperature sensor voltage drift ΔV_BEmeasurement

0.410

mV/°C

7.23 Thermistor Measurement

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Setting for nominal 18-kΩ

MIN

14.4

140

TYP

18.3

178

MAX

21.6

216

UNIT

kΩ

Internal pullup

R_{(TS_PU)}

resistance⁽¹⁾

Setting for nominal 180-kΩ

kΩ

Internal pad

resistance⁽²⁾

R_{(TS_PAD)}

526

±200

Ω

Change over -40°C/+85°C vs value at 25°C

for nominal 18-kΩ

Internal pullup

resistance change

over temperature

R_{(TS_PU_DRIFT)}

Change over -40°C/+85°C vs value at 25°C

for nominal 180-kΩ

±2000

(1) The internal pullup resistance includes only the resistance between the REG18 pin and the point where the voltage is sensed by the

ADC.

(2) The internal pad resistance includes the resistance between the point where the voltage is sensed by the ADC and the pin where an

external thermistor is attached (which includes the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins)

7.24 Internal Oscillators

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

High-frequency Oscillator

f_HFOOperating frequency

TEST CONDITIONS

MIN

TYP

MAX

UNIT

16.78

±0.25

MHz

%

T_A= –20°C to +70°C, includes frequency

drift

–3.0

–4.0

3.0

4.0

f_HFO(ERR)Frequency error⁽²⁾

T_A= –40°C to +85°C, includes frequency

drift

±0.25

%

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= –20°C to +85°C, at power-up from

SHUTDOWN or exiting DEEPSLEEP

mode, oscillator frequency within ±3% of

nominal

4.3

ms

f_HFO(SU)Start-up time⁽¹⁾

T_A= –20°C to +85°C, cases other than

power-up from SHUTDOWN or exiting

DEEPSLEEP mode, oscillator frequency

within ±3% of nominal

135

µs

Low-frequency Oscillator

f_LFOOperating frequency

Full-speed setting

Low speed setting

262.144

32.768

kHz

T_A= –20°C to +70°C, includes frequency

drift

–1.5

–2.5

8.5

±0.25

12

1.5

2.5

18

%

f_LFO(ERR)Frequency error⁽²⁾

T_A= –40°C to +85°C, includes frequency

drift

Detects oscillator failure if the LFO

frequency falls below this level.

f_LFO(FAIL)Failure detection frequency

(1) Specified by design

kHz

(2) Specified by a combination of design and production test

7.25 High-side NFET Drivers

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

CHG pin voltage with

TEST CONDITIONS

MIN

TYP

MAX

UNIT

respect to BAT, DSG

pin voltage with

CHG/DSG C_L= 20 nF, charge pump high

overdrive setting

V_{(FETON_HI)}

10

11

13

V

respect to BAT, 8

V ≤ V_BAT≤ 55 V,

(1)

V_LD≤ V_DSG

CHG pin voltage with

respect to BAT, DSG

pin voltage with

CHG/DSG C_L= 20 nF, charge pump high

overdrive setting

V_{(FETON_HI_LOBAT)}

8

4.5

3.5

11

13

V

respect to BAT, 4.7

V ≤ V_BAT< 8 V, V_LD

V_DSG

≤

(1)

CHG pin voltage with

respect to BAT, DSG

pin voltage with

CHG/DSG C_L= 20 nF, charge pump low

overdrive setting

V_{(FETON_LO)}

5.7

7

respect to BAT, 8

V ≤ V_BAT≤ 55 V,

(1)

V_LD≤ V_DSG

CHG pin voltage with

respect to BAT, DSG

pin voltage with

CHG/DSG C_L= 20 nF, charge pump low

overdrive setting

V_{(FETON_LO_LOBAT)}

5

0

7

respect to BAT, 4.7

V ≤ V_BAT< 8 V, V_LD

V_DSG

≤

(1)

DSG on voltage with

respect to BAT

V_{(SRCFOL_FETON)}

V_(CHGFETOFF)

V_(DSGFETOFF)

CHG/DSG C_L= 20 nF, source follower mode

CHG/DSG C_L= 20 nF, steady state value

V

CHG off voltage with

respect to BAT

0.4

0.7

DSG off voltage with

respect to LD

18

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SLUSE14A – DECEMBER 2020 – REVISED FEBRUARY 2021

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CHG/DSG C_L= 20 nF, R_GATE= 100 Ω, 0.5 V

to 4 V gate-source overdrive, charge pump

mode^{(3) (4)}

CHG and DSG rise

time

t_{(FET_ON)}

21

40

µs

CHG C_L= 20 nF, R_GATE= 100 Ω, 90% to

10% of V_(FETON)

t_(CHGFETOFF)

t_(DSGFETOFF)

t_{(CP_START)}

C_(CP1)

CHG fall time to BAT

DSG fall time to LD

46

2

65

20

µs

(4)

DSG C_L= 20 nF, R_GATE= 100 Ω, 90% to 10%

(4)

of V_(FETON)

Charge pump start up C_L= 20 nF, C_(CP1)= 470 nF, 10% to 90% of

100

2200

ms

nF

time

V_(FETON)

Charge pump

capacitor⁽²⁾

100

470

(1) When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that V_LD> V_DSG, the voltage

at DSG will rise to ≈ V_LD- 0.7 V

(2) Specified by design

(3) Specified by characterization

(4) R_GATEcan be optimized during design and system evaluation for best performance. A larger value may be desired to avoid an overly

fast FET turn off, which can result in a large voltage transient due to cell and harness inductance.

7.26 Comparator-Based Protection Subsystem

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.012 V

to 5.566

V in 50.6

mV steps

V_(OVP)

Overvoltage detection range

Nominal setting (50.6 mV steps)

V

T_A= +25°C, nominal setting between

1.012 V and 5.566 V⁽¹⁾

±2

±3

±5

mV

T_A= +25°C, nominal setting between

3.036 V and 5.06 V⁽¹⁾

–10

–15

–25

10

15

25

T_A= –10°C to +60°C, nominal setting

between 1.012 V and 5.566 V⁽¹⁾

Overvoltage detection voltage

threshold accuracy⁽³⁾

V_{(OVP_ACC)}

T_A= –10°C to +60°C, nominal setting

between 3.036 V and 5.06 V⁽¹⁾

T_A= –40°C to +85°C, nominal setting

between 1.012 V and 5.566 V⁽¹⁾

T_A= –40°C to +85°C, nominal setting

between 3.036 V and 5.06 V⁽¹⁾

10 ms to

6753 ms

in 3.3 ms

steps

V_{(OVP_DLY)}

Overvoltage detection delay⁽²⁾

Undervoltage detection range

Nominal setting (3.3 ms steps)

Nominal setting (50.6 mV steps)

ms

V

1.012 V

to 4.048

V in 50.6

mV steps

V_(UVP)

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_A= +25°C, nominal setting between

1.012 V and 4.048 V⁽¹⁾

±1.3

mV

T_A= +25°C, nominal setting between

1.518 V and 3.542 V⁽¹⁾

–10

10

mV

T_A= –10°C to +60°C, nominal setting

between 1.012 V and 4.048 V⁽¹⁾

±1.4

±1.6

Undervoltage detection voltage

threshold accuracy⁽³⁾

V_{(UVP_ACC)}

T_A= –10°C to +60°C, nominal setting

between 1.518 V and 3.542 V⁽¹⁾

–15

–25

15

25

T_A= –40°C to +85°C, nominal setting

between 1.012 V and 4.048 V⁽¹⁾

T_A= –40°C to +85°C, nominal setting

between 1.518 V and 3.542 V⁽¹⁾

10 ms to

6753 ms

in 3.3 ms

steps

V_{(UVP_DLY)}

Undervoltage detection delay⁽²⁾

Nominal setting (3.3 ms steps)

ms

–10,

–20,

–40,

–60,

–80,

–100,

–125,

–150,

–175,

–200,

–250,

–300,

–350,

–400,

–450,

–500

Short circuit in discharge voltage

threshold range

Nominal settings, threshold based on

V_SRP- V_SRN

V_(SCD)

mV

% of

15 nominal

threshold

T_A= –40°C to +85°C, V_(SCD)settings ≤ –

20 mV

–15

–35

Short circuit in discharge voltage

threshold detection accuracy⁽³⁾

V_{(SCD_ACC)}

% of

35 nominal

threshold

T_A= –40°C to +85°C, V_(SCD)settings > –

20 mV

Fastest setting (with 3 mV on V_SRN

V_SRP

–

8

µs

ns

)

Fastest setting (with 25 mV on V_SRN

V_SRP

–

600

Short circuit in discharge detection

delay

)

V_{(SCD_DLY)}

15 µs to

450 µs in

15 µs

Nominal setting (15 µs steps)

µs

steps

4 mV to

124 mV

in 2 mV

steps

Overcurrent in charge (OCC) voltage Nominal settings, threshold based on

V_(OCC)

mV

threshold range

V_SRP– V_SRN

–4 mV to

–200 mV

in 2 mV

steps

Overcurrent in discharge (OCD1,

OCD2) voltage threshold ranges

Nominal settings, thresholds based on

V_SRP– V_SRN

V_(OCD)

20

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

2.65

4

UNIT

|Setting| < 20 mV

–2

mV

Overcurrent (OCC, OCD1, OCD2)

detection voltage threshold

accuracy⁽³⁾

|Setting| = 20 mV ~ 56 mV

|Setting| = 56 mV ~ 100 mV

|Setting| > 100 mV

–4

mV

V_{(OC_ACC)}

–5

5

mV

–7

5

mV

10 ms to

425 ms

in 3.3 ms

steps

Overcurrent (OCC, OCD1, OCD2)

detection delay (independent delay

setting for each protection)

V_{(OC_DLY)}

Nominal setting (3.3 ms steps)

ms

(1) Measured by fault triggered using 100 ms detection delay.

(2) Cell balancing not active. Timing of overvoltage and undervoltage protection checks is modified when cell balancing is in progress.

(3) Specified by a combination of characterization and production test

7.27 Timing Requirements – I²C Interface, 100kHz Mode

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SCL duty cycle = 50%

MIN

TYP

MAX

UNIT

kHz

µs

f_SCL

Clock operating frequency⁽¹⁾

START condition hold time⁽¹⁾

Low period of the SCL clock⁽¹⁾

High period of the SCL clock⁽¹⁾

Setup repeated START⁽¹⁾

Data hold time (SDA input)⁽¹⁾

Data setup time (SDA input)⁽¹⁾

Clock rise time⁽¹⁾

100

t_HD:STA

t_LOW

t_HIGH

t_SU:STA

t_HD:DAT

t_SU:DAT

t_r

4.0

4.7

4.0

4.7

0

µs

ns

250

ns

10% to 90%

90% to 10%

1000

300

ns

t_f

Clock fall time⁽¹⁾

ns

t_SU:STO

t_BUF

Setup time STOP condition⁽¹⁾

Bus free time STOP to START⁽¹⁾

4.0

4.7

µs

Bus interface is reset if SCL is detected

low for this duration

t_RST

I²C bus reset⁽¹⁾

1.9

1.5

2.1

s

R_PULLUPPullup resistor⁽²⁾

Pullup voltage rail ≤ 5 V

kΩ

(1) Specified by design

(2) Specified by characterization

7.28 Timing Requirements – I²C Interface, 400kHz Mode

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SCL duty cycle = 50%

MIN

TYP

MAX

UNIT

kHz

µs

f_SCL

Clock operating frequency⁽¹⁾

START condition hold time⁽¹⁾

Low period of the SCL clock⁽¹⁾

High period of the SCL clock⁽¹⁾

Setup repeated START⁽¹⁾

Data hold time (SDA input)⁽¹⁾

Data setup time (SDA input)⁽¹⁾

Clock rise time⁽¹⁾

400

t_HD:STA

t_LOW

t_HIGH

t_SU:STA

t_HD:DAT

t_SU:DAT

t_r

0.6

1.3

600

0

µs

ns

100

ns

10% to 90%

90% to 10%

300

ns

t_f

Clock fall time⁽¹⁾

ns

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Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_SU:STO

t_BUF

Setup time STOP condition⁽¹⁾

Bus free time STOP to START⁽¹⁾

0.6

µs

1.3

µs

Bus interface is reset if SCL is detected

low for this duration

t_RST

I²C bus reset⁽¹⁾

1.9

1.5

2.1

s

R_PULLUPPullup resistor⁽²⁾

Pullup voltage rail ≤ 5 V

kΩ

(1) Specified by design

(2) Specified by characterization

7.29 Timing Requirements – HDQ Interface

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted)

PARAMETER

Break Time⁽¹⁾

TEST CONDITIONS

MIN

190

40

TYP

MAX

UNIT

µs

t_B

t_BR

Break Recovery Time⁽¹⁾

Host Write 1 Time⁽¹⁾

t_HW1

t_HW0

t_CYCH

t_CYCD

t_DW1

t_DW0

t_RSPS

t_TRND

t_RISE

Host drives HDQ

0.5

86

50

Host Write 0 Time⁽¹⁾

Host drives HDQ

145

Cycle Time, Host to device⁽¹⁾

Cycle Time, device to Host⁽¹⁾

Device Write 1 Time⁽¹⁾

Device drives HDQ

190

32

Device drives HDQ

205

250

50

Device drives HDQ

Device Write 0 Time⁽¹⁾

Device drives HDQ

80

145

Device Response Time^{(1) (3)}

Host Turn Around Time⁽¹⁾

HDQ Line Rising Time to Logic 1⁽¹⁾

Device drives HDQ

190

210

Host drives HDQ after device drives HDQ

1.8

2.1

Host holds bus low to initiate device

interface reset

t_RST

HDQ Bus Reset⁽¹⁾

1.9

1.5

s

R_PULLUPPullup Resistor⁽²⁾

Pullup voltage rail ≤ 5 V

kΩ

(1) Specified by design

(2) Specified by characterization

(3) Response time may vary due to internal device processing

7.30 Timing Requirements – SPI Interface

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted). All values specified with SPI pin filtering enabled.

PARAMETER

SPI clock period⁽¹⁾

TEST CONDITIONS

MIN

500⁽⁴⁾

625

TYP

MAX

UNIT

ns

µs

ns

t_SCK

t_LEAD

t_LAG

t_TD

t_SU

t_HI

Enable lead-time⁽¹⁾

Enable lag time⁽¹⁾

50

Sequential transfer delay⁽²⁾

Data setup time^{(1) (5)}

Data hold time (inputs)^{(1) (5)}

Data hold time (outputs)⁽¹⁾

Responder access time⁽¹⁾

Responder DOUT disable time⁽¹⁾

Data valid⁽¹⁾

50

0

t_HO

t_A

t_DIS

t_V

500

450

235⁽⁴⁾

30

t_R

Rise time⁽¹⁾

Up to 25pF load

t_F

Fall time⁽¹⁾

Up to 25pF load

30

22

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SLUSE14A – DECEMBER 2020 – REVISED FEBRUARY 2021

Typical values stated where T_A= 25°C and V_BAT= 55.0 V, min/max values stated where T_A= -40°C to 85°C and V_BAT= 4.7 V

to 55 V (unless otherwise noted). All values specified with SPI pin filtering enabled.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Bus interface is reset if SPI_CS is

low and SPI_SCLK is detected

unchanged for this duration

t_RST

SPI bus reset⁽¹⁾

1.9

2.1

s

(1) Specified by design

(2) See later discussion in datasheet for more details

(3) Specified by characterization

(4) This assumes 15 ns setup time on the SPI controller for MISO. If additional setup time is required, the clock period should be

extended accordingly.

(5) When SPI pin filtering is enabled, pulses on input pins of duration below 200 ns may be filtered out.

7.31 Interface Timing Diagrams

SDA

t

BUF

t

LOW

t

f

HD;STA

t

r

t

SP

t

r

f

SCL

t

SU;STA

t

SU;STO

HD;STA

t

HIGH

t

SU;DAT

HD;DAT

STOP START

START

REPEATED

START

Figure 7-1. I²C Communications Interface Timing

SPI_CS

S

t

TD

t

LAG

SCK

LEAD

t

R

F

t

sckl

SPI_SCLK

t

sckh

t

HO

V

t

DIS

BIT_N-2… BIT₁

MSB OUT

LSB OUT

SPI_MISO

SPI_MOSI

t

A

t

SU

HI

BIT_N-2… BIT₁

MSB IN

LSB IN

Figure 7-2. SPI Communications Interface Timing

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1.2 V

t_(RISE)

t_(B)

t_(BR)

(a) Break and Break Recovery

(b) HDQ Line Rise Time

T_(DW1)

T_(HW1)

T_(HW0)

T_(DW0)

T_(CYCH)

T_(CYCD)

(c) HDQ Host Transmitted Bit

(d) Device Transmitted Bit

7-bit address

1-bit

R/W

Break

7-bit address

t_(RSPS)

(e) Device to HDQ Host Response

t_(RST)

(f) HDQ Reset

a. HDQ Breaking

b. Rise time of HDQ line

c. HDQ Host to Device communication

d. Device to HDQ Host communication

e. Device to HDQ Host response format

f. HDQ Host to Device

Figure 7-3. HDQ Communications Interface Timing

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7.32 Typical Characteristics

Figure 7-4. Cell Voltage Measurement Error at 25°C

Across Input Range

Figure 7-5. Cell Voltage Measurement Error vs.

Temperature with Cell Voltage = 1.5 V

Figure 7-6. Cell Voltage Measurement Error vs.

Temperature with Cell Voltage = 2.5 V

Figure 7-7. Cell Voltage Measurement Error vs.

Temperature with Cell Voltage = 3.5 V

Figure 7-8. Cell Voltage Measurement Error vs.

Temperature with Cell Voltage = 4.5 V

Figure 7-9. Cell Voltage Measurement Error vs.

Temperature with Cell Voltage = 5.5 V

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Error in measurement of differential voltage between SRP and

SRN pins.

Figure 7-11. Internal Voltage References vs.

Temperature (V_REF1and V_REF2

)

Figure 7-10. Current Measurement Error vs.

Temperature

LFO measured in full speed mode (262 kHz)

Figure 7-12. Internal Temperature Sensor

(Delta V_BE) Voltage vs. Temperature

Figure 7-13. Low Frequency Oscillator (LFO)

Accuracy vs. Temperature

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Figure 7-14. High Frequency Oscillator (HFO)

Figure 7-15. Overcurrent in Discharge Protection 1

(OCD1) Threshold vs. Temperature

Accuracy vs. Temperature

Figure 7-17. Cell Balancing Resistance vs.

Temperature

Figure 7-16. Overcurrent in Charge Protection

(OCC) Threshold vs. Temperature

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This test uses a resistor divider across the VCx

pins to enable one common voltage to be scaled

across the cell inputs. The top of the string is swept

and captured as the cell voltage.

Figure 7-19. REG1 Voltage vs. Load at 25°C

Figure 7-18. Cell Balancing Resistance vs. Cell

Common-Mode Voltage at 25°C

Figure 7-20. REG2 Voltage vs. Load at 25°C

Figure 7-21. Thermistor Pullup Resistance vs.

Temperature (18-kΩ Setting)

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Error calculated as percentage of nominal gain across ±200-mV

input range

Figure 7-22. Thermistor Pullup Resistance vs.

Temperature (180-kΩ Setting)

Figure 7-23. Coulomb Counter Gain Error vs.

Temperature

Figure 7-24. LD Wake Voltage vs. Temperature

Figure 7-25. REG18 Voltage vs. Temperature, with

No Load

1.835

BAT=4.7V, 0mA

BAT=8V, 0mA

BAT=4.7V, 1mA

BAT=8V, 1mA

1.83

1.825

1.82

BAT=10V, 0mA

BAT=20V, 0mA

BAT=25.9V, 0mA

BAT=40V, 0mA

BAT=60V, 0mA

BAT=10V, 1mA

BAT=20V, 1mA

BAT=25.9V, 1mA

BAT=40V, 1mA

BAT=60V, 1mA

1.815

1.81

1.805

1.8

1.795

1.79

1.785

1.78

-40

-20

0

20

40

60

80

100

Temp (°C)

Figure 7-26. REG18 Voltage vs. Temperature,

across BAT Levels

Measurements taken using external BJT

Figure 7-27. REGIN Voltage vs. BAT Voltage

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Figure 7-28. BAT Current in NORMAL Mode vs.

Temperature

Figure 7-29. BAT Current in SHUTDOWN Mode vs.

Temperature

Figure 7-30. BAT Current in SLEEP2 (SRC

Follower) Mode vs. Temperature

Figure 7-31. BAT Current in DEEPSLEEP2 (No

LFO) Mode vs. Temperature

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8 Device Description

8.1 Overview

The BQ76942 product is a highly integrated, accurate battery monitor and protector for 3-series to 10-series Li-

ion, Li-polymer, and LiFePO₄battery packs. A high accuracy voltage, current, and temperature measurement

accuracy provides data for host-based algorithms and control. A feature-rich and highly configurable protection

subsystem provides a wide set of protections that can be triggered and recovered completely autonomously by

the device or under full control of a host processor. The integrated charge pump with high-side protection NFET

drivers enables host communication with the device even when FETs are off by preserving the ground

connection to the pack. Dual programmable LDOs are included for external system use, with each independently

programmable to voltages of 1.8 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V, capable of providing up to 45 mA each.

The BQ76942 device includes one-time-programmable (OTP) memory for customers to setup device operation

on their own production line. Multiple communications interfaces are supported, including 400-kHz I²C, SPI, and

HDQ one-wire standards. Multiple digital control and status data are available through several multifunction pins

on the device, including an interrupt to the host processor, and independent controls for host override of each

high-side protection NFET. Three dedicated pins are provided for temperature measurement using external

thermistors. Additionally, multifunction pins can be programmed to use additional thermistors, with the device

supporting a total of up to nine thermistors. An internal die temperature measurement is also provided.

8.2 BQ76942 Device Versions

The BQ76942 device family includes several versions with differing default settings programmed during factory

test. These different settings, which may include having a different default communications interface or a

different setting for the REG1 LDO, are described in the Device Comparison Table.

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8.3 Functional Block Diagram

8.4 Diagnostics

The BQ76942 device includes a suite of diagnostic tests which can be used by the system to improve

robustness of operation. These include comparisons between the two voltage references integrated within the

device, a hardware monitor of the LFO frequency, memory checks at power-up or reset, an internal watchdog on

the embedded processor, and more. These are described in detail in the BQ76942 Technical Reference Manual.

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9 Device Configuration

9.1 Commands and Subcommands

The BQ76942 device includes support for direct commands and subcommands. The direct commands are

accessed using a 7-bit command address that is sent from a host through the device serial communications

interface and either triggers an action, or provides a data value to be written to the device, or instructs the device

to report data back to the host. Subcommands are additional commands that are accessed indirectly using the 7-

bit command address space and provide the capability for block data transfers. For more information on the

commands and subcommands supported by the device, refer to the BQ76942 Technical Reference Manual.

9.2 Configuration Using OTP or Registers

The BQ76942 device includes registers, with values which are stored in the RAM and can be loaded

automatically from one-time programmable (OTP) memory. At initial power-up, the device loads OTP settings

into registers, which are used by the device firmware during operation. The recommended procedure is for the

customer to write settings into OTP on the manufacturing line, in which case the device will use these settings

whenever it is powered up. Alternatively, the host processor can initialize registers after power-up, without using

the OTP memory, but the registers will need to be reinitialized after each power cycle of the device. Register

values are preserved while the device is in NORMAL, SLEEP, or DEEPSLEEP modes. If the device enters

SHUTDOWN mode, all register memory is cleared, and the device will return to the default parameters (or the

OTP configuration if that has been programmed) when powered again. See the BQ76942 Technical Reference

Manual for more details.

9.3 Device Security

The BQ76942 device includes three security modes: SEALED, UNSEALED, and FULLACCESS, which can be

used to limit the ability to view or change settings.

•

In SEALED mode, most data and status can be read using commands and subcommands, but only selected

settings can be changed. Data memory settings cannot be changed directly.

UNSEALED mode includes SEALED functionality, and also adds the ability to execute additional

subcommands, and read and write data memory.

FULLACCESS mode allows capability to read and modify all device settings, including writing OTP memory.

Selected settings in the device can be modified while the device is in operation through supported commands

and subcommands, but in order to modify all settings, the device must enter CONFIG_UPDATE mode (see

CONFIG_UPDATE Mode), which stops device operation while settings are being updated. After the update is

completed, operation is restarted using the new settings. CONFIG_UPDATE mode is only available in

FULLACCESS mode.

The BQ76942 device implements a key-access scheme to transition among SEALED, UNSEALED, and

FULLACCESS modes. Each transition requires that a unique set of keys be sent to the device through

subcommands. Refer to the BQ76942 Technical Reference Manual for more details.

The device provides additional checks which can be used to optimize system robustness, including

subcommands which calculate the digital signature of the integrated instruction ROM and data ROM. These

signatures should never change for a particular product. If these were to change, it would indicate an error,

either that the ROM had been corrupted, or the readback of the ROM or calculation of the signature experienced

an error. An additional subcommand calculates a digital signature for the static configuration data (which

excludes calibration values) and compares it to a stored value, returning a flag if the result does not match.

9.4 Scratchpad Memory

The BQ76942 device integrates a 32-byte scratchpad memory which can be used by the customer for storing

manufacturing data, such as serial numbers, production or test dates, and so forth. The scratchpad data can be

written into OTP memory on the customer production line. This data can only be written while in FULLACCESS

mode, although it can be read in all modes.

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10 Measurement Subsystem

10.1 Voltage Measurement

The BQ76942 device integrates a voltage ADC that is multiplexed between measurements of cell voltages, an

internal temperature sensor, and up to nine external thermistors, as well as performs measurements of the

voltage at the VC10 pin, the PACK pin, the LD pin, the internal REG18 LDO voltage, and the VSS rail (for

diagnostic purposes). The BQ76942 device supports measurements of individual differential cell voltages in a

series configuration, ranging from 3-series cells to 10-series cells. Each cell voltage measurement is a

differential measurement of the voltage between two adjacent cell input pins, such as VC1–VC0, VC2–VC1, and

so forth. The cell voltage measurements are processed based on trim and calibration corrections, and then

reported in a 16-bit resolution using units of 1 mV. The raw 24-bit digital output of the ADC is also available for

readout using 32-bit subcommands. The cell voltage measurements can support a recommended voltage range

from –0.2 V to 5.5 V. The voltage ADC saturates at a level of 5 × V_REF1(approximately 6.06 V) when measuring

cell voltages, although for the best performance, it is recommended to stay at a maximum input of 5.5 V.

10.1.1 Voltage Measurement Schedule

The BQ76942 device's voltage measurements are taken in a measurement loop that consists of multiple

measurement slots. All 10 cell voltages are measured on each loop, then one slot is used for one of the VC10 or

PACK or LD pin voltages, one slot is used for internal temperature or V_REFor VSS measurement, then up to

three slots are used to measure thermistors or multifunction pin voltages (ADCIN functionality). Over the course

of three loops, a full set of measurements is completed. One measurement loop consists of either 12 (if no

thermistors or ADCIN are enabled), 13 (if one thermistor or ADCIN is enabled), 14 (if two thermistors or ADCIN

are enabled), or 15 (if three or more thermistors or ADCIN are enabled) measurement slots.

The speed of a measurement loop can be controlled by settings. Each voltage measurement (slot) takes 3 ms

(or 1.5 ms depending on setting), so a typical measurement loop with 15 slots per loop takes 45 ms (or 22.5 ms

depending on setting). If measurement data is not required as quickly, the timing for the measurement loop can

be programmed to slower speeds, which injects idle slots in each loop after the measurement slots. Using slower

loop cycle time will reduce the power dissipation of the device when in NORMAL mode.

10.1.2 Usage of VC Pins for Cells Versus Interconnect

If the BQ76942 device is used in a system with fewer than 10-series cells, the additional cell inputs can be used

to improve measurement performance. For example, a long connection may exist between two cells in a pack,

such that there may be significant interconnect resistance between the cells, such as shown in Figure 10-1

between CELL-A and CELL-B. By connecting VC7 close to the positive terminal of CELL-B, and connecting VC8

close to the negative terminal of CELL-A, more accurate cell voltage measurements are obtained for CELL-A

and CELL-B, since the I·R voltage across the interconnect resistance between the cells is not included in either

cell voltage measurement. Because the device reports the voltage across the interconnect resistance and the

synchronized current, the resistance of the interconnect between CELL-A and CELL-B can also be calculated

and monitored during operation. It is recommended to include the series resistance and bypass capacitor on cell

inputs connected in this manner, as shown below.

Note

It is important that the differential input for each cell input not fall below –0.3 V (the absolute maximum

data sheet limit), with the recommended minimum voltage of –0.2 V. Therefore, it is important that the

I·R voltage drop across the interconnect resistance not cause a violation of this requirement.

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ꢀꢂ>>Ͳꢄ

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sꢀϴ

Eꢀ

sꢀϳ

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ꢀ

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Figure 10-1. Using Cell Input Pins for Interconnect Measurement

If this connection across an interconnect is not needed (or it is preferred to avoid the extra resistor and

capacitor), then unused cell input pins should be shorted to adjacent cell input pins, as shown in Figure 10-2 for

VC8.

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Figure 10-2. Terminating an Unused Cell Input Pin

A configuration register is used to specify which cell inputs are used for actual cells. The device uses this

information to disable cell voltage protections associated with inputs that are used to measure interconnect or

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are not used at all. Voltage measurements for all inputs are reported in a 16-bit format (in units of mV), as well as

32-bit format (in units of raw ADC counts), irrespective of whether they are used for cells or not.

10.2 General Purpose ADCIN Functionality

Several multifunction pins on the BQ76942 device can be used for general purpose ADC input (ADCIN)

measurement, if not being used for other purposes. This includes the TS1, TS2, TS3, CFETOFF, DFETOFF,

HDQ, DCHG, DDSG, and ALERT pins. When used for ADCIN functionality, the internal bandgap reference is

used by the ADC, and the input range of the ADC is limited to the REG18 pin voltage. The digital fullscale range

of the ADC is effectively 1.6667 × VREF1, which is approximately 2.08 V during normal operation.

The BQ76942 device also reports the raw ADC counts when a measurement is taken using the TS1 pin. This

data can be used during manufacturing to better calibrate the ADCIN functionality.

10.3 Coulomb Counter and Digital Filters

The BQ76942 device monitors pack current using a low-side sense resistor that connects to the SRP and SRN

pins through an external RC filter, which should be connected such that a charging current will create a positive

voltage on SRP relative to SRN. The differential voltage between SRP and SRN is digitized by an integrated

coulomb counter ADC, which can digitize voltages over a ±200 mV range and uses multiple digital filters to

provide optimized measurement of the instantaneous, averaged, and integrated current. The device supports a

wide range of sense resistor values, with a larger value providing better resolution for the digitized result. The

maximum value of sense resistor should be limited to ensure the differential voltage remains within the ±200-mV

range for system operation when current measurement is desired. For example, a system with maximum

discharge current of 200 A during normal operation (not a fault condition) should limit the sense resistor to 1 mΩ

or below.

The SRP and SRN pins can also support higher positive voltages relative to VSS, such as may occur during

overcurrent or short circuit in discharge conditions, without damage to the device, although the current is not

accurately digitized in this case. For example, a system with a 1-mΩ sense resistor and the Short Circuit in

Discharge protection threshold programmed to a 500 mV level would trigger an SCD protection fault when a

discharge current of 500 A was detected.

Multiple digitized current values are available for readout over the serial communications interface, including two

using separate hardware digital filters, CC1 and CC2, as well as a firmware filter CC3.

The CC1 filter generates a 16-bit current measurement that is used for charge integration and other decision

purposes, with one output generated every 250 ms when the device is operating in NORMAL mode.

The CC2 filter generates a 24-bit current measurement that is used for current reporting, with one output every 3

ms when the device is operating in NORMAL mode (which can be reduced to one output every 1.5 ms based on

setting, with reduced measurement resolution). It is reported in 16-bit format, and the 24-bit CC2 data is also

available as raw coulomb counter ADC counts, provided in 32-bit format (with the data contained in the lower 24

bits and the upper 8 bits sign-extended).

The CC3 filter output is an average of a programmable number of CC2 current samples (up to 255), based on

configuration setting. The CC3 output is reported in 32-bit format.

The integrated passed charge is available as a 64-bit value, which includes the upper 32 bits of accumulated

charge as the integer portion, the lower 32 bits of accumulated charge as the fractional portion, and a 32-bit

accumulated time over which the charge has been integrated in units of seconds. The accumulated charge

integration and timer can be reset by a command from the host over the digital communications interface.

10.4 Synchronized Voltage and Current Measurement

While the cell voltages are digitized sequentially using a single muxed ADC during normal operation, the current

is digitized continuously by the dedicated coulomb counter ADC. The current is measured synchronously with

each cell voltage measurement, and can be used for individual cell impedance analysis. The ongoing periodic

current measurements can be read out through the digital communication interface, while the measurements

taken that were synchronized with particular cell voltage measurements are stored paired with the associated

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cell voltage measurement for separate readout. These values can be read using a block subcommand, which

ensures the synchronously aligned voltage and current data are read out together.

10.5 Internal Temperature Measurement

The BQ76942 device integrates the capability to measure its internal die temperature by digitizing the difference

in internal transistor base-emitter voltages (deltaV_BE). This voltage is measured periodically as part of the

measurement loop and is processed to provide a reported temperature value available through the digital

communications interface. This internal temperature measurement can be used for cell or FET temperature

protections and logic based on configuration settings.

10.6 Thermistor Temperature Measurement

The BQ76942 device includes an on-chip temperature measurement and can support up to nine external

thermistors on multifunction pins (TS1, TS2, TS3, CFETOFF, DFETOFF, ALERT, HDQ, DCHG, and DDSG). The

device includes an internal pullup resistor to bias a thermistor during measurement.

The internal pullup resistor has two options that can set the pullup resistor to either 18-kΩ or 180-kΩ (or none at

all). The 18-kΩ option is intended for use with thermistors such as the Semitec 103-AT, which has 10-kΩ

resistance at room temperature. The 180-kΩ option is intended for use with higher resistance thermistors such

as the Semitec 204AP-2, which has 200-kΩ resistance at room temperature. The resistor values are measured

during factory production and stored within the device for use during temperature calculation. The individual pin

configuration registers determine which pin is used for a thermistor measurement, what value of pullup resistor is

used, as well as whether the thermistor measurement is used for a cell or FET temperature reading.

REG18 (≈1.8V)

VREF1

≈162 kΩ

≈18 kΩ

reference

input

Voltage

ADC

T

S

T

S

T

S

T

S

T

S

T

S

T

S

T

S

T

S

Figure 10-3. External Thermistor Biasing

To provide a high precision temperature result, the device uses the same 1.8 V LDO voltage for the ADC

reference as is used for biasing the thermistor pullup resistor, thereby implementing a ratiometric measurement

that removes the error contribution from the LDO voltage level. The device processes the digitized thermistor

voltage to calculate the temperature based on multiorder polynomials, which can be programmed by the user

based on the specific thermistor selected.

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10.7 Factory Trim of Voltage ADC

The BQ76942 device includes factory trim for the cell voltage ADC measurements in order to optimize the

voltage measurement performance even if no further calibration is performed by the customer. Calibration can

be performed by the customer on the production line to further optimize the performance in the system. The trim

information is used to correct the raw ADC readings before they are reported as 16-bit voltage values. The 32-bit

ADC voltage data, which is generated in units of ADC counts, is modified before reporting by subtracting a

stored offset trim value. The resulting reported data does not include any further correction (such as for gain),

therefore the customer will need to process them before use.

The device includes a factory gain trim for the voltage measurements performed using the general purpose ADC

input capability on the multifunction pins as well as the TS1, TS2, and TS3 pins. It also includes factory gain trim

on the voltage measurements of the PACK pin, the LD pin, and the top-of-stack (VC10) pin.

10.8 Voltage Calibration (ADC Measurements)

The BQ76942 device includes optional capability for the customer to calibrate each cell voltage gain and the

gain for the stack voltage, the PACK pin voltage, and the LD pin voltage individually, and multifunction pin

general ADC measurements. An offset calibration value Calibration:Vcell Offset:Vcell Offset is included for

use with the cell voltage measurements, and Calibration:Vdiv Offset:Vdiv Offset is used with the TOS (stack),

PACK, and LD voltage measurements. The cell voltage gains determined during calibration are written in

Calibration:Voltage:Cell 1 Gain – Cell 10 Gain, where Cell 1 Gain is used for the measurement of VC1-VC0,

Cell 2 Gain is used for the measurement of VC2-VC1, and so forth. Similarly, the calibration voltage gain for the

TOS voltage should be written in Calibration:Voltage:TOS Gain, the PACK pin voltage gain in

Calibration:Voltage:Pack Gain, the LD pin voltage gain in Calibration:Voltage:LD Gain, and multifunction pin

general purpose ADCIN measurement gain in Calibration:Voltage:ADC Gain.

If values for the calibration gain configuration are not written, the BQ76942 device uses factory trim or default

values for the respective gain values. When a calibration gain configuration value is written, the device uses that

in place of any factory trim or default gain. The raw ADC measurement data (in units of counts) is corrected by

first subtracting a stored offset trim value, then the gain is applied, then the Calibration:Vcell Offset:Vcell

Offset (for cell voltage measurements) or the Calibration:Vdiv Offset:Vdiv Offset (for TOS, PACK, or LD

voltage measurements) is subtracted before the final voltage value is reported.

The factory trim values for the Cell Gain parameters can be read from the Cell Gain data memory registers while

in FULLACCESS mode but not in CONFIG_UPDATE mode, if the data memory values have not been

overwritten. While in CONFIG_UPDATE mode, the Cell Gain values read back either all zeros, if they have not

been overwritten, or the values written to these registers. Upon exiting CONFIG_UPDATE mode, readback of

the Cell Gain parameters provides the values presently used in operation.

See the BQ76942 Technical Reference Manual for further details.

The effective fullscale digital range of the cell measurement is 5 × VREF1, and the effective fullscale digital

range of the ADCIN measurement is 1.667 × VREF1, although the voltages applied for these measurement

should be limited based on the specifications in Specifications. Using a value for VREF1 of 1.25 V, the nominal

gain for the cell measurements is 12409, while the nominal gain for the ADCIN measurements is 4166. The

reported voltages are calculated as:

Cell # Voltage() = Calibration:Voltage:Cell # Gain × (16-bit ADC counts) / 65536 – Calibration:Vcell Offset:Vcell Offset

Stack Voltage() = Calibration:Voltage:TOS Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset

PACK Pin Voltage() = Calibration:Voltage:Pack Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset

LD Pin Voltage() = Calibration:Voltage:LD Gain × (16-bit ADC counts) / 65536 – Calibration:Vdiv Offset:Vdiv Offset

ADCIN Voltage = Calibration:Voltage:ADC Gain × (16-bit ADC counts) / 65536

Note

Cell # Voltage() and Calibration:Vcell Offset:Vcell Offset have units of mV. The divider voltages

(Stack Voltage(), PACK Pin Voltage(), and LD Pin Voltage()) and Calibration:Vdiv Offset:Vdiv Offset

have units of userV.

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10.9 Voltage Calibration (COV and CUV Protections)

The BQ76942 device includes optional capability for the customer to calibrate the COV (cell overvoltage) and

CUV (cell undervoltage) protection thresholds on the production line, in order to improve threshold accuracy in

system or to realize a threshold between the preset thresholds available from the device.

This calibration is performed while the device is in CONFIG_UPDATE mode. To calibrate the COV threshold, an

external voltage is first applied between VC10 and VC9 that is equal to the desired COV threshold. Next, the

CAL_COV() subcommand is sent by the host, which causes the BQ76942 device to perform a search for the

appropriate calibration coefficients to realize a COV threshold at or close to the applied voltage level. When this

search is completed, the resulting calibration coefficient is returned by the subcommand and automatically

written into the Protections:COV:COV Threshold Override configuration parameter. If this parameter is

nonzero, the device will not use its factory trim settings but will instead use this value.

The CUV threshold is calibrated similarly, an external voltage is applied between VC10 and VC9 equal to the

desired CUV threshold. Next, while in CONFIG_UPDATE mode, the CAL_CUV() subcommand is sent by the

host, which causes the BQ76942 device to perform a search for the appropriate calibration coefficients to realize

a CUV threshold at or close to the applied voltage level. When this search is completed, the resulting calibration

coefficient is returned by the subcommand and automatically written into the Protections:CUV:CUV Threshold

Override configuration parameter.

10.10 Current Calibration

The BQ76942 device coulomb counter ADC measures the differential voltage between the SRP and SRN pins to

calculate the system current. The device includes the optional capability for the customer to calibrate the

coulomb counter offset and current gain on the production line.

The Calibration:Current Offset:CC Offset configuration register contains an offset value in units of 32-bit

coulomb counter ADC counts / Calibration:Current Offset:Coulomb Counter Offset Samples. The value of

Calibration:Current Offset:CC Offset / Calibration:Current Offset:Coulomb Counter Offset Samples is

subtracted from the raw coulomb counter ADC counts, then the result is multiplied by Calibration:Current:CC

Gain and scaled to provide the final result in units of userA.

The BQ76942 device uses the Calibration:Current:CC Gain and Calibration:Current:Capacity Gain

configuration values to convert from the ADC value to current. The CC Gain reflects the value of the sense

resistor used in the system, while the Capacity Gain is simply the CC Gain multiplied by 298261.6178.

The CC Gain and Capacity Gain are encoded using a 32-bit IEEE-754 floating point format. The effective value

of the sense resistor is given by:

CC Gain = 7.4768 / (Rsense in mΩ)

10.11 Temperature Calibration

The BQ76942 device enables the customer to calibrate the internal as well as external temperature

measurements on the production line, by storing an offset value that is added to the calculated measurement

before reporting. A separate offset for each temperature measurement can be stored in the configuration

registers shown below.

Table 10-1. Temperature Calibration Settings

Section

Subsection

Temperature

Register Description

Internal Temp Offset

CFETOFF Temp Offset

DFETOFF Temp Offset

ALERT Temp Offset

TS1 Temp Offset

Comment

Units

0.1 K

Calibration

CFETOFF pin thermistor

DFETOFF pin thermistor

ALERT pin thermistor

TS1 pin thermistor

TS2 Temp Offset

TS2 pin thermistor

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Table 10-1. Temperature Calibration Settings (continued)

Section

Subsection

Temperature

Register Description

Comment

Units

0.1 K

Calibration

TS3 Temp Offset

TS3 pin thermistor

HDQ pin thermistor

DCHG pin thermistor

DDSG pin thermistor

HDQ Temp Offset

DCHG Temp Offset

DDSG Temp Offset

11 Primary and Secondary Protection Subsystems

11.1 Protections Overview

An extensive protection subsystem is integrated within the BQ76942 device, which can monitor a variety of

parameters, initiate protective actions, and autonomously recover based on conditions. The device also includes

a wide range of flexibility, such that the device can be configured to monitor and initiate protective action, but

with recovery controlled by the host processor, or such that the device only monitors and alerts the host

processor whenever conditions warrant protective action, but with action and recovery fully controlled by the host

processor.

The primary protection subsystem includes a suite of individual protections that can be individually enabled and

configured, including cell undervoltage and overvoltage, overcurrent in charge, three separate overcurrent in

discharge protections, short circuit current in discharge, cell overtemperature and undertemperature in charge

and discharge, FET overtemperature, a host processor communication watchdog timeout, and PRECHARGE

mode timeout. The cell undervoltage and overvoltage, overcurrent in charge, overcurrent in discharge 1 and 2,

and short circuit in discharge protections are based on comparator thresholds, while the remaining protections

(such as those involving temperature, host watchdog, and precharging) are based on firmware on the internal

controller.

The device integrates NFET drivers for high-side CHG and DSG protection FETs, which can be configured in a

series or parallel configuration. An integrated charge pump generates a voltage that is driven onto the NFET

gates based on a host command or the on-chip protection subsystem settings. Support is also included for high-

side PFETs used to implement a precharge and predischarge functionality.

The secondary protection suite within the BQ76942 device can react to more serious faults and take action to

permanently disable the pack by initiating a Permanent Fail (PF). The secondary safety provides protection

against safety cell undervoltage and overvoltage, safety overcurrent in charge and discharge, safety

overtemperature for cells and FETs, excessive cell voltage imbalance, internal memory faults, and internal

diagnostic failures.

When a Permanent Fail occurs, the BQ76942 device can be configured either to simply provide a flag, to

indefinitely disable the protection FETs, or to assert the FUSE pin to permanently disable the pack. The FUSE

pin can be used to blow an in-line fuse and can monitor if a separate secondary protector IC has attempted to

blow the fuse.

11.2 Primary Protections

The BQ76942 device integrates a broad suite of protections for battery management and provides the capability

to enable individual protections, as well as to select which protections will result in autonomous control of the

FETs. See the BQ76942 Technical Reference Manual for detailed descriptions of each protection function.

The primary protection features include:

•

Cell Undervoltage Protection

Cell Overvoltage Protection

Cell Overvoltage Latch Protection

Overcurrent in Charge Protection

Overcurrent in Discharge Protection (Three Tiers)

Overcurrent in Discharge Latch Protection

Short Circuit in Discharge Protection

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•

Short Circuit in Discharge Latch Protection

Undertemperature in Charge Protection

Undertemperature in Discharge Protection

Internal Undertemperature Protection

Overtemperature in Charge Protection

Overtemperature in Discharge Protection

Internal Overtemperature Protection

FET Overtemperature Protection

Precharge Timeout Protection

Host Watchdog Fault Protection

11.3 Secondary Protections

The BQ76942 device integrates a suite of secondary protection checks on battery operation and status that can

trigger a permanent fail (PF) if conditions are considered so serious that the pack should be permanently

disabled. The various PF checks can be enabled individually based on configuration settings, along with

associated thresholds and delays for most checks. When a permanent fail has occurred, the BQ76942 device

can be configured to either simply provide a flag, or to indefinitely disable the protection FETs, or to assert the

FUSE pin to permanently disable the pack. The FUSE pin can be used to blow an in-line fuse and also can

monitor if a separate secondary protector IC has attempted to blow the fuse.

Since the device stores permanent fail status in RAM, that status would be lost when the device resets. To

mitigate this, the device can write permanent fail status to OTP based on configuration setting. OTP

programming may be delayed in low-voltage and high-temperature conditions until OTP programming can

reliably be accomplished.

Normally, a permanent fail causes the FETs to remain off indefinitely and the fuse may be blown. In that

situation, no further action would be taken on further monitoring operations, and charging would no longer be

possible. To avoid rapidly draining the battery, the device may be configured to enter DEEPSLEEP mode when a

permanent fail occurs. Entrance to DEEPSLEEP mode will still be delayed until after fuse blow and OTP

programming are completed, if those options are enabled.

When a permanent fail occurs, the device may be configured to either turn the REG1 and REG2 LDOs off, or to

leave them in their present state. Once disabled, they may still be reenabled through command.

The permanent fail checks incorporate a programmable delay, to avoid triggering a PF fault on an intermittent

condition or measurement. When the threshold is first detected as being met or exceeded by an enabled PF

check, the device will set a PF Alert signal, which can be monitored using commands and can also trigger an

interrupt on the ALERT pin.

Note

The device only evaluates the conditions for permanent fail at one-second intervals while in NORMAL

and SLEEP modes. It does not continuously compare measurements to the permanent fail fault

thresholds between intervals. Thus, it is possible for a condition to trigger a PF Alert if detected over

threshold, but even if the condition drops back below threshold briefly between the one second

interval checks, the PF Alert would not be cleared until it was detected below threshold at a periodic

check.

For more details on the permanent fail checks implemented in the BQ76942, refer to the BQ76942 Technical

Reference Manual. The secondary protection features include:

•

Safety Cell Undervoltage Permanent Fail

Safety Cell Overvoltage Permanent Fail

Safety Overcurrent in Charge Permanent Fail

Safety Overcurrent in Discharge Permanent Fail

Safety Overtemperature Permanent Fail

Safety Overtemperature FET Permanent Fail

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•

Copper Deposition Permanent Fail

Short Circuit in Discharge Latch Permanent Fail

Voltage Imbalance Active Permanent Fail

Voltage Imbalance at Rest Permanent Fail

Second Level Protector Permanent Fail

Discharge FET Permanent Fail

Charge FET Permanent Fail

OTP Memory Permanent Fail

Data ROM Permanent Fail

Instruction ROM Permanent Fail

Internal LFO Permanent Fail

Internal Voltage Reference Permanent Fail

Internal VSS Measurement Permanent Fail

Internal Stuck Hardware Mux Permanent Fail

Commanded Permanent Fail

Top of Stack Versus Cell Sum Permanent Fail

11.4 High-Side NFET Drivers

The BQ76942 device includes an integrated charge pump and high-side NFET drivers for driving CHG and DSG

protection FETs. The charge pump uses an external capacitor connected between the BAT and CP1 pins that is

charged to an overdrive voltage when the charge pump is enabled. Due to the time required for the charge pump

to bring the overdrive voltage on the external CP1 pin to full voltage, it is recommended to leave the charge

pump powered whenever it may be needed quickly to drive the CHG or DSG FETs.

The DSG FET driver includes a special option (denoted source follower mode) to drive the DSG FET with the

BAT pin voltage during SLEEP mode. This capability is included to provide low power in SLEEP mode, when

there is no significant charge or discharge current flowing. It is recommended to keep the charge pump enabled

even when the source follower mode is enabled, so whenever a discharge current is detected, the device can

quickly transition to driving the DSG FET using the charge pump voltage. The source-follower mode is enabled

using a configuration setting and is not intended to be used when significant charging or discharging current is

flowing, since the FET will exhibit a large drain-source voltage and may undergo excessive heating.

The overdrive level of the charge pump voltage can be set to 5.5 V or 11 V based on configuration setting. In

general, the 5.5-V setting results in lower power dissipation when a FET is being driven, while the higher 11-V

overdrive reduces the on-resistance of the FET. If a FET exhibits significant gate leakage current when driven at

the higher overdrive level, this can result in a higher device current for the charge pump to support this. In this

case, using the lower overdrive level can reduce the leakage current and thus the device current.

The BQ76942 device supports a system with FETs in a series or parallel configuration, where the parallel

configuration includes a separate path for the charger connection versus the discharge (load) connection. The

control logic for the device operates slightly differently in these two cases, which is set based on the

configuration setting.

The FET drivers in the BQ76942 device can be controlled in several different manner, depending on customer

requirements:

Fully autonomous

The BQ76942 device can detect protection faults and autonomously disable the FETs, monitor for a recovery

condition, and autonomously reenable the FETs without requiring any host processor involvement.

Partially autonomous

The BQ76942 device can detect protection faults and autonomously disable the FETs. When the host receives

an interrupt and recognizes the fault, the host can send commands across the digital communications interface

to keep the FETs off until the host decides to release them.

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Alternatively, the host can assert the CFETOFF or DFETOFF pins to keep the FETs off. As long as these pins

are asserted, the FETs are blocked from being reenabled. When these pins are deasserted, the BQ76942 will

reenable the FETs if nothing is blocking them being reenabled (such as fault conditions still present, or the

CFETOFF or DFETOFF pins are asserted).

Manual control

The BQ76942 device can detect protection faults and provide an interrupt to a host processor over the ALERT

pin. The host processor can read the status information of the fault over the communication bus (if desired) and

can quickly force the CHG or DSG FETs off by driving the CFETOFF or DFETOFF pins from the host processor,

or commands over the digital communications interface.

When the host decides to allow the FETs to turn on again, it writes the appropriate command or deasserts the

CFETOFF and DFETOFF pins, and the BQ76942 device will reenable the FETs if nothing is blocking them being

reenabled.

If the device is in series FET configuration and a single FET is on, it is possible for current to flow through the off-

FET body diode. This current can damage the FET if high enough for a long enough time. In this case, when the

BQ76942 device is autonomously controlling the FETs, if a current is detected above a programmable threshold,

the device will automatically turn on the off-FET to prevent further damage.

11.5 Protection FETs Configuration and Control

11.5.1 FET Configuration

The BQ76942 device supports both a series configuration and a parallel configuration for the protection FETs in

the system, as well as a system that does not use one or both FETs. When a series FET configuration is used,

the BQ76942 device provides body diode protection for the case when one FET is off and one FET is on.

If the CHG FET is off, the DSG or PDSG FET is on, and a discharge current greater in magnitude than a

programmable threshold (that is, a significant discharging current) is detected, the device will turn on the CHG

FET to avoid current flowing through the CHG FET body diode and damaging the FET. When the current rises

above the threshold (that is, less discharge current flowing), the CHG FET will be turned off again if the reasons

for its turn-off are still present.

If the DSG FET is off, the CHG or PCHG FET is on, and a current in excess of a programmable threshold (that

is, a significant charging current) is detected, the device will turn on the DSG FET to avoid current flowing

through the DSG FET body diode and damaging the FET. When the current falls below the threshold (that is,

less charging current flowing), the DSG FET will be turned off again if the reasons for its turn-off are still present.

When a parallel configuration is used, the body diode protection is disabled.

11.5.2 PRECHARGE and PREDISCHARGE Modes

The BQ76942 device includes precharge functionality, which can be used to reduce the charging current for an

undervoltage battery by charging using a high-side PCHG PFET (driven from the PCHG pin) with a series

resistor until the battery reaches a programmable voltage level. When the minimum cell voltage is less than a

programmable threshold, the PCHG FET is used for charging.

The device also supports predischarge functionality, which can be used to reduce inrush current when the load is

initially powered, by first enabling a high-side PDSG PFET (driven from the PDSG pin) with a series resistor,

which allows the load to slowly charge. If PREDISCHARGE mode is enabled, whenever the DSG FET is turned

on to power the load, the device will first enable the PDSG FET, then transition to turn on the DSG FET and turn

off the PDSG FET.

The PCHG and PDSG drivers are limited in the current they can sink while enabled. As such, it is recommended

to use 1 MΩ or larger resistance across the FET gate-source.

11.6 Load Detect Functionality

When a Short Circuit in Discharge Latch or Overcurrent in Discharge Latch protection fault has occurred and the

DSG FET is off, the device can be configured to recover when load removal is detected. This feature is useful if

the system has a removable pack, such that the user can remove the pack from the system when a fault occurs,

or if the effective system load that remains on the battery pack is higher than ~20-kΩ when the DSG FET is

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disabled. The device will periodically enable a current source out the LD pin and will recover the fault if a voltage

is detected at the LD pin above a 4-V level. If a low-impedance load is still present on the pack, the voltage the

device measures on the LD pin is generally below 4 V, preventing recovery based on Load Detect. If the pack

was removed from the system and the effective load is high, such that the current source generates a voltage on

the LD pin above a 4-V level, then the device can recover from the fault.

Note

Typically, a 10-kΩ resistor is connected between the PACK+ terminal and the LD pin, this resistance

should be comprehended when considering the load impedance. The Load Detect current is enabled

for a programmable time duration, then is disabled for another programmable time duration, with this

sequence repeating until the load has been detected as removed or it times out.

12 Device Hardware Features

12.1 Voltage References

The BQ76942 device includes two voltage references, V_REF1and V_REF2, with V_REF1used by the voltage ADC for

most measurements except external thermistors. The integrated 1.8-V LDO, internal oscillators, and integrated

coulomb counter ADC use V_REF2. The value of V_REF2can be measured indirectly by the voltage ADC's

measurement of the REG18 LDO voltage while using V_REF1for diagnostic purposes.

12.2 ADC Multiplexer

The ADC multiplexer connects various signals to the voltage ADC, including the individual differential cell voltage

pins, the on-chip temperature sensor, the biased thermistor pins, the REG18 LDO voltage, the VSS pin voltage,

and internal dividers connected to the VC10, PACK, and LD pins.

12.3 LDOs

The BQ76942 device contains an integrated 1.8-V LDO (REG18) that provides a regulated 1.8-V supply voltage

for the device's internal circuitry and digital logic. This regulator uses an external capacitor connected to the

REG18 pin, which should only be used for internal circuitry.

The device also integrates two separately programmable LDOs (REG1 and REG2) for external circuitry, such as

a host processor or external transceiver circuitry, which can be programmed to independent output voltages. The

REG1 and REG2 LDOs take their input from the REGIN pin, with this voltage either provided externally or

generated by an on-chip preregulator (referred to as REG0). The REG1 and REG2 LDOs can provide an output

current of up to 45 mA each.

12.3.1 Preregulator Control

The REG1 and REG2 LDOs take their input from the REGIN pin, which should be approximately 5.5 V. This

REGIN pin voltage can be supplied externally (such as by a separate DC/DC converter) or using the integrated

voltage preregulator (referring to as REG0), which drives the base of an external NPN BJT (using the BREG pin)

to provide the 5.5 V REGIN pin voltage. When the preregulator is being used, special care should be taken to

ensure the device retains sufficient voltage on its BAT pin per the Specifications.

Note

•

The system designer should ensure the external BJT can tolerate the peak power that may be

dissipated in it under maximum load expected on REG1 and REG2. If the maximum stack voltage

is 50 V, then the BJT experiences a collector-emitter voltage of approximately 45 V; thereby,

dissipating 4.05 W if REG1 and REG2 are both used to support a 45-mA load.

There is a diode connection between the REGIN pin (anode) and the BAT pin (cathode), so the

voltage on REGIN should not exceed the voltage on BAT.

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12.3.2 REG1 and REG2 LDO Controls

The REG1 and REG2 LDOs in the BQ76942 device are for customer use, and their output voltages can be

programmed independently to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V. The REG1 and REG2 LDOs and the REG0

preregulator are disabled by default in the BQ76942 device. While in SHUTDOWN mode, the REG1 and REG2

pins have ≈10-MΩ resistances to VSS, to discharge any output capacitance. While in other power modes, when

REG1 and REG2 are powered down, they are pulled to VSS with an internal resistance of ≈2.5-kΩ. If pullup

resistors for serial communications are connected to the REG1 voltage output, the REG1 voltage can be

overdriven from an external voltage supply on the manufacturing line, to allow communications with the device.

The BQ76942 device can then be programmed to enable REG0 and REG1 with the desired configuration, and

this setting can be programmed into OTP memory. Thus, at each later power-up, the device will autonomously

load the OTP settings and enable the LDO as configured, without requiring communications first.

12.4 Standalone Versus Host Interface

The BQ76942 device can be configured to operate in a completely standalone mode, without any host processor

in the system, or together with a host processor. If in standalone mode, the device can monitor conditions,

control FETs and an in-line fuse based on threshold settings, and recover FETs when conditions allow, all without

requiring any interaction with an external processor. If a host processor is present, the device can still be

configured to operate fully autonomously, while the host processor can read measurements and exercise control

as desired. In addition, the device can be configured for manual host control, such that the device can monitor

and provide a flag when a protection alert or fault has occurred, but will rely on the host to disable FETs.

The host processor can interface with the BQ76942 device through a serial bus as well as selected pin controls.

Serial bus communication through I²C (supporting speeds up to 400 kHz), SPI or HDQ is available, with the

serial bus configured for I²C by default in the BQ76942, while the default communications mode may differ for

other versions of the device. The pin controls available include RST_SHUT, ALERT, CFETOFF, DFETOFF,

DDSG, and DCHG, which are described in detail below.

12.5 Multifunction Pin Controls

The BQ76942 device provides flexibility regarding the multifunction pins on the device, which includes the TS1,

TS2, TS3, CFETOFF, DFETOFF, ALERT, HDQ, DCHG, and DDSG pins. Several of the pins can be used as

active-high outputs with configurable output level. The digital output driver for these pins can be configured to

drive an output powered from the REG1 LDO or from the internal REG18 LDO, and thus when asserted active-

high will drive out the voltage of the selected LDO.

Note: the REG18 LDO is not capable of driving high current levels, so it is recommended to only use this LDO to

provide a digital output if it will be driving a very high resistance (such as > 1 MΩ) or light capacitive load.

Otherwise the REG1 should be powered and used to drive the output signal.

The options supported on each pin include:

ALERT

Alarm interrupt output

HDQ communications

CFETOFF

Input to control the CHG FET (that is, CFETOFF functionality)

DFETOFF

Input to control the DSG FET (that is, DFETOFF functionality)

Input to control both the DSG and CHG FETs (that is, BOTHOFF functionality)

HDQ

HDQ communications

SPI MOSI pin

DCHG

DCHG functionality—a logic-level output corresponding to a fault that would normally cause the CHG driver to be disabled

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DDSG

DDSG functionality—a logic-level output corresponding to a fault that would normally cause the DSG driver to be disabled

ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG

General purpose digital output

Can be driven high or low by command.

Can be configured for an active-high output to be driven from the REG1 LDO or the REG18 LDO.

Can be configured to have a weak pull-down to VSS or weak pullup to REG1 enabled continuously.

ALERT, CFETOFF, DFETOFF, TS1, TS2, TS3, HDQ, DCHG, and DDSG

Thermistor temperature measurement

A thermistor can be attached between the pin and VSS.

ADCIN

The pin can be used for general purpose ADC measurement.

12.6 RST_SHUT Pin Operation

The RST_SHUT pin provides a simple way to reset or shutdown the BQ76942 device without needing to use

serial bus communication. During normal operation, the RST_SHUT pin should be driven low. When the pin is

driven high, the device will immediately reset most of the digital logic, including that associated with the serial

communications bus. However, it does not reset the logic that holds the state of the protection FETs and FUSE,

these remain as they were before the pin was driven high. If the pin continues to be driven high for 1 second, the

device will then transition into SHUTDOWN mode, which involves disabling external protection FETs, and

powering off the internal oscillators, the REG18 LDO, the on-chip preregulator, and the REG1 and REG2 LDOs.

12.7 CFETOFF, DFETOFF, BOTHOFF Pin Functionality

The BQ76942 device includes two pins (CFETOFF and DFETOFF) that can be used to disable the protection

FET drivers quickly, without going through the host serial communications interface. When the selected pin is

asserted, the device disables the respective protection FET.

Note

When the selected pin is deasserted, the respective FET is only enabled if there are no other items

blocking them from being reenabled, such as if the host also sent a command to disable the FETs

using the serial communications interface after setting the selected pin. The CFETOFF and DFETOFF

pins can be used for other functions if the FET turnoff feature is not required.

The CFETOFF pin can be used optionally to disable the CHG and PCHG FETs, and the DFETOFF pin can be

used optionally to disable the DSG and PDSG FETs. The device also includes the option to configure the

DFETOFF pin as BOTHOFF functionality, such that if that pin is asserted, the CHG, PCHG, DSG, and PDSG

FETs will be disabled. This allows the CFETOFF pin to be used for an additional thermistor in the system, while

still providing pin control to disable the FETs.

The CFETOFF or BOTHOFF functionality disables both the CHG FET and the PCHG FET when asserted.

The DFETOFF or BOTHOFF functionality disables both the DSG FET and the PDSG FET when asserted.

12.8 ALERT Pin Operation

The ALERT pin is a multifunction pin that can be configured either as ALERT (to provide an interrupt to a host

processor), a thermistor input, a general purpose ADC input, a general purpose digital output, or an HDQ serial

communication interface. The pin can be configured as active-high, active-low, or open-drain to accommodate

different system design preferences. When configured as the HDQ interface pin, the pin will operate in open-

drain mode.

When the pin is configured to drive an active high output, the output voltage is driven from either the REG18 1.8-

V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V).

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Note

If a DC or significant transient current may be driven by this pin, then the output should be configured

to drive using the REG1 LDO, not the REG18 LDO.

The BQ76942 device includes functionality to generate an alarm signal at the ALERT pin, which can be used as

an interrupt to a host processor. When used for the alarm function, the pin can be programmed to drive the

signal as an active-low or hi-Z signal, an active-high or low signal, or an active-low or high signal (that is,

inverted polarity). The alarm function within the BQ76942 device includes a programmable mask to allow the

customer to decide which of many flags or events can trigger an alarm.

12.9 DDSG and DCHG Pin Operation

The BQ76942 device includes two multifunction pins, DDSG and DCHG, which can be configured as logic-level

outputs to provide a fault-related signal to a host processor or external circuitry (that is, DDSG and DCHG

functionality), as a thermistor input, a general purpose ADC input, or a general purpose digital output.

When used as digital outputs, the pins can be configured to drive an active high output, with the output voltage

driven from either the REG18 1.8-V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V).

Note

If a DC or significant transient current can be driven by a pin, then the output should be configured to

drive using the REG1 LDO, not the REG18 LDO.

When the pins are configured for DDSG and DCHG functionality, they provide signals related to protection faults

that (on the DCHG pin) would normally cause the CHG driver to be disabled or (on the DDSG pin) would

normally cause the DSG driver to be disabled. These signals can be used to control external protection circuitry,

if the integrated high-side NFET drivers will not be used in the system. They can also be used as interrupts in

manual FET control mode for the host processor to decide whether to disable the FETs through commands or

using the CFETOFF and DFETOFF pins.

12.10 Fuse Drive

The FUSE pin on the BQ76942 device can be used to blow a chemical fuse in the presence of a permanent fail

(PF), as well as to detect if an external secondary protector in the system has detected a fault and is attempting

to blow the fuse itself. The pin is intended to drive the gate of an NFET, which can be combined with the drive

from an external secondary protector, as shown in Figure 12-1. When the FUSE pin is not asserted by the

BQ76942 device, it remains in a high-impedance state and detects a voltage applied at the pin by a secondary

protector. The device can be configured to generate a PF if it detects a high signal at the FUSE pin.

The device can be configured to blow the fuse when a PF occurs. In this case, the device only attempts to blow

the fuse if the stack voltage is above a programmed threshold, based on a system configuration with the fuse

placed between the top of stack and the high-side protection FETs. If instead the fuse is placed between the

FETs and the PACK+ connector, then the device instead bases its decision on the PACK pin voltage (based on

configuration setting). This voltage threshold check is disregarded under certain cases, as described in the

BQ76942 Technical Reference Manual.

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Figure 12-1. FUSE Pin Operation

12.11 Cell Open Wire

The BQ76942 device supports detection of a broken connection between a cell in the pack and the cell

attachment to the PCB containing the BQ76942 device. Without this check, the voltage at the cell input pin of the

BQ76942 device may persist for some time on the board-level capacitor, leading to incorrect voltage readings.

The Cell Open Wire detection in the BQ76942 device operates by enabling a small current source from each cell

to VSS at programmable intervals. If a cell input pin is floating due to an open wire condition, this current

discharges the capacitance, causing the voltage at the pin to slowly drop. This drop in voltage eventually triggers

a protection fault on that particular cell and the cell above it. Eventually, the voltage drops low enough to trigger a

permanent fail on the particular cell and on the cell above it.

The Cell Open Wire current will be enabled at a periodic interval set by configuration register. The current source

is enabled once every interval for a duration of the ADC measurement time (which is 3 ms by default). This

provides programmability in the average current drawn from ≈0.65 nA to ≈165 nA, based on the typical current

level of 55 µA.

Note

The Cell Open Wire check can create a cell imbalance, so the settings should be selected

appropriately.

12.12 Low Frequency Oscillator

The low frequency oscillator (LFO) in the BQ76942 device operates continuously while in NORMAL and SLEEP

modes, and can be configured to remain powered or shutdown (except when needed) during DEEPSLEEP

mode. The LFO runs at ≈262.144 kHz during NORMAL mode, and reduces to ≈32.768 kHz in SLEEP or

DEEPSLEEP modes. The LFO is trimmed during manufacturing to meet the specified accuracy across

temperature.

12.13 High Frequency Oscillator

The high frequency oscillator (HFO) in the BQ76942 device operates at 16.78 MHz and is frequency locked to

the LFO. The HFO powers up as needed for internal logic functions.

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13 Device Functional Modes

13.1 Overview

This device supports four functional modes to support optimized features and power dissipation, with the device

able to transition between modes either autonomously or controlled by a host processor.

•

NORMAL mode: In this mode, the device performs frequent measurements of system current, cell voltages,

internal and thermistor temperature, and various other voltages, operates protections as configured, and

provides data and status updates.

•

SLEEP mode: In this mode, the DSG FET is enabled, the CHG FET can optionally be disabled, and the

device performs measurements, calculations, and data updates in adjustable time intervals. Battery

protections are still enabled. Between the measurement intervals, the device is operating in a reduced power

stage to minimize total average current consumption.

•

DEEPSLEEP mode: In this mode, the CHG, PCHG, DSG, and PDSG FETs are disabled, all battery

protections are disabled, and no current or voltage measurements are taken. The REG1 and REG2 LDOs

can be kept powered, in order to maintain power to external circuitry, such as a host processor.

SHUTDOWN mode: The device is completely disabled (including the internal, REG1, and REG2 LDOs), the

CHG, PCHG, DSG, and PDSG FETs are all disabled, all battery protections are disabled, and no

measurements are taken. This is the lowest power state of the device, which may be used for shipment or

long-term storage. All register settings are lost when in SHUTDOWN mode.

The device also includes a CONFIG_UPDATE mode, which is used for parameter updates. Transitioning

between functional modes is shown below.

SHUTDOWN MODE

Charger detect on

TS2 pulldown detect on

Shutdown signal by

Very low V_BAT

RST_SHUT pin or

low V_BATor high

temp

Charger

detection or TS2

pulldown

Shutdown signal by

RST_SHUT pin or

command or low

V_BATor high temp

detection

SLEEP MODE

DEEPSLEEP MODE

REG18, REG1, REG2 on

LFO on

REG18, REG1, REG2 on

Comparator protections on

Periodic ADC protections on

Current wake detector on

DEEPSLEEP()

command twice

EXIT_DEEPSLEEP() command or reset

signal by RST_SHUT pin or charger

detected

NORMAL MODE

Monitoring on

Protection on

Low current

REG18, REG1, REG2 on

DEEPSLEEP() command

twice, or Permanent Fail

SLEEP_DISABLE() command or fault or fault recovery

or current detected or charger detected or reset signal

by RST_SHUT pin

Reset signal by RST_SHUT

Blue = programmable

Figure 13-1. Device Functional Modes

13.2 NORMAL Mode

NORMAL mode is the highest performance mode of the device, in which the device regularly measures voltage,

current, and temperature, the LFO (low frequency oscillator) is operating, and the internal processor powers up

(as needed) for data processing and control. Full battery protections operate based on device configuration

settings. System current is measured at intervals of 3 ms, with cell voltages measured at intervals of 45 ms or

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slower, depending on configuration. The device also provides a configuration bit that causes the conversion

speed for both voltages and CC2 current to be doubled, with a reduction in measurement resolution.

The device is generally in NORMAL mode when any active charging or discharging is underway. When the CC1

Current() measurement falls below a programmable current threshold, the system is considered in relax mode,

and the BQ76942 device can autonomously transition into SLEEP mode, depending on configuration.

13.3 SLEEP Mode

SLEEP mode is a reduced functionality state that can be optionally used to reduce power dissipation when there

is little or no system load current or charging in progress, but still provides voltage at the battery pack terminals

to keep the system active. At initial powerup, a configuration bit determines whether the device can enter SLEEP

mode. After initialization, SLEEP mode can be allowed or disallowed using subcommands. Status bits are

provided to indicate whether the device is presently allowed to enter SLEEP mode or not, and whether it is

presently in SLEEP mode or not.

When the magnitude of the CC1 Current measurement falls below a programmable current threshold, the

system is considered in relax mode, and the BQ76942 device autonomously transitions into SLEEP mode, if

settings permit. During SLEEP mode, comparator-based protections operate the same as during NORMAL

mode. ADC-based current, voltage, and temperature measurements are taken at programmable intervals. All

temperature protections use the ADC measurements taken at these intervals, so they will update at a reduced

rate during SLEEP mode.

The BQ76942 device exits SLEEP mode if a protection fault occurs, current begins flowing, a charger is

attached, if forced by a subcommand, or if the RST_SHUT pin is asserted for < 1 s. When exiting based on

current flow, the device quickly enables the FETs (if the CHG FET was off or the DSG FET was in source-

follower mode), but the standard measurement loop does not restart until the next 1-s boundary occurs within

the device timing. Therefore, new data may not be available for up to ≈1 s after the device exits SLEEP mode.

The coulomb counter ADC operates in a reduced power and speed mode to monitor current during SLEEP

mode. The current is measured every 12 ms and, if it exceeds a programmable threshold in magnitude, the

device quickly transitions back to NORMAL mode. In addition to this check, if CC1 Current measurement taken

at each programmed interval exceeds this threshold, the device exits SLEEP mode.

The device monitors the PACK pin voltage and the top-of-stack voltage at each programmed measurement

interval. If the PACK pin voltage is higher than the top-of-stack voltage by more than a programmable delta and

the top-of-stack voltage is less than a programmed threshold, the device exits SLEEP mode. The BQ76942

device also includes a hysteresis on the SLEEP mode entrance to avoid the device quickly entering and exiting

SLEEP mode based on a dynamic load. After transitioning to NORMAL mode, the device will not enter SLEEP

mode again for a number of seconds given by the hysteresis setting.

During SLEEP mode, the DSG FET can be driven either using the charge pump or in source-follower mode (as

described in High-side NFET Drivers). The CHG FET can be disabled or driven using the charge pump, based

on the configuration setting.

13.4 DEEPSLEEP Mode

The BQ76942 device integrates a DEEPSLEEP mode, which is a low-power mode that allows the REG1 and

REG2 LDOs to remain powered, but disables other subsystems. In this mode, the protection FETs are disabled,

so no voltage is provided at the battery pack terminals. All protections are disabled, and all voltage, current, and

temperature measurements are disabled.

DEEPSLEEP mode can be entered by sending a subcommand over the serial communications interface. The

device exits DEEPSLEEP mode returns to NORMAL mode if directed by a subcommand, or if the RST_SHUT

pin is asserted for < 1-s, or if a charger is attached (which is detected by the voltage on the LD pin rising from

below V_WAKEONLDto exceed it). In addition, if the BAT pin voltage falls below V_PORA– V_{PORA_HYS}, the device

transitions to SHUTDOWN mode.

When the device exits DEEPSLEEP mode, it first completes a full measurement loop and evaluates conditions

relative to enabled protections to ensure that conditions are acceptable to proceed to NORMAL mode. This may

take ≈250 ms plus the time for the measurement loop to complete.

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The REG1 and REG2 LDOs maintain their power state when entering DEEPSLEEP mode based on the

configuration setting. The device also provides the ability to keep the LFO running while in DEEPSLEEP mode,

which enables a faster responsiveness to communications and transition back to NORMAL mode, but consumes

additional power.

Other than sending a subcommand to exit DEEPSLEEP mode, communications with the device over the serial

interface do not cause it to exit DEEPSLEEP mode; however, since no measurements are taken while in

DEEPSLEEP mode, there is no new information available for readout.

13.5 SHUTDOWN Mode

SHUTDOWN mode is the lowest power mode of the BQ76942 device, which can be used for shipping or long-

term storage. In this mode, the device loses all register state information, the internal logic is powered down, the

protection FETs are all disabled, so no voltage is provided at the battery pack terminals. All protections are

disabled, all voltage, current, and temperature measurements are disabled, and no communications are

supported. When the device exits SHUTDOWN, it will boot and read parameters stored in OTP (if that has been

written). If the OTP has not been written, the device will power up with default settings, and then settings can be

changed by the host writing device registers.

Entering SHUTDOWN mode involves a sequence of steps. The sequence can be initiated manually through the

serial communications interface. The device can also be configured to enter SHUTDOWN mode automatically

based on the top of stack voltage or the minimum cell voltage. If the top-of-stack voltage falls below a

programmed stack voltage threshold, or if the minimum cell voltage falls below a programmed cell voltage

threshold, the SHUTDOWN mode sequence is automatically initiated. The shutdown based on cell voltage does

not apply to cell input pins being used to measure interconnect.

While the BQ76942 device is in NORMAL mode or SLEEP mode, the device can also be configured to enter

SHUTDOWN mode if the internal temperature measurement exceeds a programmed temperature threshold for a

programmed delay.

When the SHUTDOWN mode sequence has been initiated by subcommand or the RST_SHUT pin driven high

for 1-sec, the device will wait for a delay then disable the protection FETs. After the delay from when the

sequence begins, the device will enter SHUTDOWN mode. However, if the voltage on the LD pin is still above

the V_WAKEONLDlevel, shutdown will be delayed until the voltage on LD falls below that level.

While the device is in SHUTDOWN mode, a ≈5-V voltage is provided at the TS2 pin with high source

impedance. If the TS2 pin is pulled low (such as by a switch to VSS) or if a voltage is applied at the LD pin above

V_WAKEONLD(such as when a charger is attached in series FET configuration), the device will exit SHUTDOWN

mode.

Note

If a thermistor is attached from the TS2 pin to VSS, this may prevent the device from fully entering

SHUTDOWN mode.

As a countermeasure to avoid an unintentional wake from SHUTDOWN mode when putting the BQ76942 device

into long-term storage, the device can be configured to automatically reenter SHUTDOWN mode after a

programmed number of minutes.

The BQ76942 device performs periodic memory integrity checks and will force a watchdog reset if any corruption

is detected. To avoid a cycle of resets in the case of a memory fault, the device will enter SHUTDOWN mode

rather than resetting if a memory error is detected within a programmed number of seconds after a watchdog

reset has occurred.

When the device is wakened from SHUTDOWN, it generally requires approximately 200 ms–300 ms for the

internal circuitry to power up, load settings from OTP memory, perform initial measurements, evaluate those

relative to enabled protections, then to enable FETs if conditions allow. This can be much longer depending on

settings.

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The BQ76942 device integrates a hardware overtemperature detection circuit, which determines when the die

temperature passes an excessive temperature of approximately 120°C. If this detector triggers, the device

automatically begins the sequence to enter SHUTDOWN (if this functionality is enabled through configuration).

13.6 CONFIG_UPDATE Mode

The BQ76942 device uses a special CONFIG_UPDATE mode to make changes to the data memory settings. If

changes were made to the data memory settings while the firmware was in normal operation, it could result in

unexpected operation or consequences if settings used by the firmware changed in the midst of operation. When

changes to the data memory settings are needed (which generally should only be done on the customer

manufacturing line or in an offline condition), the host should put the device into CONFIG_UPDATE mode,

modify settings as required, then exit CONFIG_UPDATE mode. See the BQ76942 Technical Reference Manual

for more details.

When in CONFIG_UPDATE mode, the device stops normal firmware operation and stops all measurements and

protection monitoring. The host can then make changes to data memory settings (either writing registers directly

into RAM, or instructing the device to program the RAM data into OTP). After changes are complete, the host

then exits CONFIG_UPDATE mode, at which point the device restarts normal firmware operation using the new

data memory settings.

14 Serial Communications Interface

14.1 Serial Communications Overview

The BQ76942 device integrates three serial communication interfaces—an I²C bus, which supports 100 kHz and

400 kHz modes with an optional CRC check, an SPI bus with an optional CRC check, and a single-wire HDQ

interface. The BQ76942 device is configured default in I²C mode, while other versions of the device may have a

different default configuration (such as the BQ7694201 device, which by default is configured in SPI mode with

CRC enabled). The communication mode can be changed by programming either the register or OTP

configuration. The customer can program the device's integrated OTP on the manufacturing line to set the

desired communications speed and protocol to be used at power up in operation.

14.2 I²C Communications Subsystem

The I²C serial communications interface in the BQ76942 device acts as a responder device and supports rates

up to 400 kHz with an optional CRC check. If the OTP is not programmed, the BQ76942 device will initially

power up by default in 400 kHz I²C mode, although other versions of the device may initially power up in a

different mode (as shown in the Device Comparison Table ). The OTP setting can be programmed on the

manufacturing line, then when the device powers up, it automatically enters the selected mode per OTP setting.

The host can also change the I²C speed setting while in CONFIG_UPDATE mode, then the new speed setting

will take effect upon exit of CONFIG_UPDATE mode. Alternatively, the host can use the SWAP_TO_I2C()

subcommand to change the communications interface to I²C immediately.

The I²C device address (as an 8-bit value including responder address and R/W bit) is set by default as 0x10

(write), 0x11 (read), which can be changed by configuration setting.

The communications interface includes programmable timeout capability, this should only be used if the bus will

be operating at 100 kHz or 400 kHz. If this is enabled with the device set to 100 kHz mode, then the device will

reset the communications interface logic if a clock is detected low longer than a t_TIMEOUTof 25 ms to 35 ms, or if

the cumulative clock low responder extend time exceeds ≈25 ms, or if the cumulative clock low controller extend

time exceeds 10 ms. If the timeouts are enabled with the device set to 400 kHz mode, then the device will reset

the communications interface logic if a clock is detected low longer than t_TIMEOUTof 5 ms to 20 ms. The bus also

includes a long-term timeout if the SCL pin is detected low for more than 2 seconds, which applies whether or

not the timeouts above are enabled.

An I²C write transaction is shown in I²C Write. Block writes are allowed by sending additional data bytes before

the Stop. The I²C logic will auto-increment the register address after each data byte.

When enabled, the CRC is calculated as follows:

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•

In a single-byte write transaction, the CRC is calculated over the responder address, register address, and

data.

In a block write transaction, the CRC for the first data byte is calculated over the responder address, register

address, and data. The CRC for subsequent data bytes is calculated over the data byte only.

The CRC polynomial is x⁸+ x²+ x + 1, and the initial value is 0.

When the responder detects an invalid CRC, the I²C responder will NACK the CRC, which causes the I²C

responder to go to an idle state.

SCL

... _A1

... _R0

... _D0

... _C0

A7 A6

R/W ACK

R7 R6

ACK

D7 D6

ACK

C7 C6

ACK

SDA

Register

Address

CRC

(optional)

Responder

Address

Start

Stop

Data

Figure 14-1. I²C Write

I²C Read with Repeated Start shows a read transaction using a Repeated Start.

SCL

... _A1

... _R0

... _A1

A7 A6

R/W ACK

R7 R6

ACK

R/W ACK

SDA

Register

Address

Responder

Address

Responder

Address

Start

Repeated

Start

... _D0

... _C0NACK

D7 D6

ACK

C7 C6

Responder

Drives Data

Respsonder

Drives CRC

(optional)

Stop

Controller

Drives NACK

Figure 14-2. I²C Read with Repeated Start

I²C Read without Repeated Start shows a read transaction where a Repeated Start is not used, for example if

not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to

clock the interface. The I²C block will auto-increment the register address after each data byte.

When enabled, the CRC for a read transaction is calculated as follows:

•

In a single-byte read transaction, the CRC is calculated beginning at the first start, so will include the

responder address, the register address, then the responder address with read bit set, then the data byte.

In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will

include the responder address, the register address, then the responder address with read bit set, then the

data byte. The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is

calculated over the data byte only.

•

The CRC polynomial is x⁸+ x²+ x + 1, and the initial value is 0.

When the controller detects an invalid CRC, the I²C controller will NACK the CRC, which causes the I²C

responder to go to an idle state.

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SCL

... _A1

... _R0

... _A1

A7 A6

R/W ACK

R7 R6

ACK

R/W ACK

SDA

Responder

Address

Register

Address

Responder

Address

Start

Stop Start

... _D0

... _C0NACK

D7 D6

ACK

C7 C6

Responder

Drives Data

Responder

Drives CRC

(optional)

Stop

Controller

Drives NACK

Figure 14-3. I²C Read without Repeated Start

14.3 SPI Communications Interface

The SPI interface in the BQ76942 device operates as a responder-only interface with an optional CRC check. If

the OTP has not been programmed, the BQ76942 device will initially power up by default in 400 kHz I²C mode,

while other device versions will initially powerup by default in SPI mode with CRC enabled, as described in the

Device Comparison Table. The OTP setting to select SPI mode can be programmed into the BQ76942 on the

manufacturing line, then when the device powers up, it enters SPI mode automatically. The host can also

change the serial communication setting while in CONFIG_UPDATE mode, although the device will not

immediately change communication mode upon exit of CONFIG_UPDATE mode, in order to avoid losing

communications during evaluation or production. The host can reset the device or write the SWAP_TO_SPI()

subcommand to change the communications interface to SPI immediately.

The SPI interface logic operates with clock polarity (CPOL) = 0 and clock phase (CPHA) = 0, as shown in the

figure below.

SPI_CS

SPI_SCLK

CYCLE #

SPI_MISO

SPI_MOSI

1

2

3

4

5

6

7

8

Figure 14-4. SPI with CPOL = 0 and CPHA = 0

The device also includes an optional 8-bit CRC using polynomial x⁸+x²+x+1. The interface must use 16-bit

transactions if CRC is not enabled, and must use 24-bit transactions when CRC is enabled. CRC mode is

enabled or disabled based on the setting of Settings:Configuration:Comm Type. Based on configuration

settings, the logic will:

(a) only work with CRC, will not accept data without valid CRC, or

(b) will only accept transactions without CRC (so the host must only clock 16-bits per transaction, the device will

detect an error if more or less clocks are sent).

If the host performs a write with CRC and the CRC is not correct, then the incoming data is not transferred to the

incoming buffer, and the outgoing buffer (used for the next transaction) is also reset to 0xFFFF. This transaction

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is considered invalid. On the next transaction, the CRC (if clocked out) will be 0xAA, so the 0xFFFFAA will

indicate to the controller that a CRC error was detected.

The internal oscillator in the BQ76942 device may not be running when the host initiates a transaction (for

example, this can occur if the device is in SLEEP mode). If this occurs, the interface will drive out 0xFFFF on

SPI_MISO for the first 16 bits clocked out. It will also drive out 0xFF for the third (CRC) byte as well, if CRC is

enabled. So the 0xFFFF or 0xFFFFFF will indicate to the controller that the internal oscillator is not ready yet.

The device will automatically wake the internal oscillator at a falling edge of SPI_CS, but it may take up to 50 µs

to stabilize and be available for use to the SPI interface logic (this stabilization time may be longer depending on

the state of the device, such as waking from DEEPSLEEP2 mode, in which the LFO is powered off). The

address 0x7F used in the device is defined in such a manner that there should be no valid transaction to write

0xFF into this address. Thus the two-byte pattern 0xFFFF should never occur as a valid sequence in the first two

bytes of a transaction (that is, it is only used as a flag that something is wrong, similar to an I²C NACK).

Due to the delay in the HFO powering up if initially off, the device includes a programmable hysteresis to cause

the HFO to stay powered for a programmable number of seconds after it is wakened by a falling edge on

SPI_CS. This hysteresis is controlled by the Settings:Configuration:Comm Idle Time configuration setting,

which can be set from 0 to 255 seconds (while in SPI mode, the device will use a minimum hysteresis of 1

second even if the value is set to 0). The host can set this to a longer time (up to 255 seconds) and maintain

regular communications within this time window, causing the HFO to stay powered, so the device can respond

quickly to SPI transactions. However, keeping the HFO running continuously will cause the device to consume

additional supply current beyond what it would consume if the HFO were only powered when needed (the HDO

draws ≈ 30 µA when powered). To avoid this extra supply current, the host can send an initial, unnecessary SPI

transaction to cause the HFO to waken, and retry this until a valid response is returned on SPI_MISO. At this

point, the host can begin sending the intended SPI transactions.

If an excessive number of SPI transactions occur over a long period of time, the device may experience a

watchdog fault. It is recommended to limit the frequency of SPI transactions by providing approximately 50 μs

from the end of one transaction to the start of a new transaction.

The device includes ability to detect a frozen or disconnected SPI bus condition, and it will then reset the bus

logic. This condition is recognized when the SPI_CS is low and the SPI_SCLK is static and not changing for a

two second timeout.

Depending on the version of the device being used, the SPI_MISO pin may be configured by default to use the

REG18 LDO for its output drive, which results in a 1.8-V signal level. This may cause communications errors if

the host processor operates with a higher voltage, such as 3.3 V or 5 V. The SPI_MISO pin can be programmed

to instead use the REG1 LDO for its output drive by setting the Settings:Configuration:SPI

Configuration[MISO_REG1] data memory configuration bit. This bit should only be set if the REG1 LDO is

powered. After this bit has been modified, it is necessary to send the SWAP_TO_SPI() or

SWAP_COMM_MODE() subcommands for the device to use the new value.

The device includes optional pin filtering on the SPI input pins, which implements a filter with approximately 200

ns delay on each input pin. This filtering is enabled by default but can be disabled by clearing the

Settings:Configuration:SPI Configuration[FILT] data memory configuration bit.

14.3.1 SPI Protocol

The first byte of a SPI transaction consists of an R/W bit (R = 0, W = 1), followed by a 7-bit address, MSB-first. If

the controller (host) is writing, then the second byte will be the data to be written. If the controller is reading, then

the second byte sent on SPI_MOSI is ignored (except for CRC calculation).

If CRC is enabled, then the controller must send as the third byte the 8-bit CRC code, which is calculated over

the first two bytes. If the CRC is correct, then the values clocked in will be put into the incoming buffer. If the

CRC is not correct, then the outgoing buffer will be set to 0xFFFF, and the outgoing CRC will be set to 0xAA

(these are clocked out on the next transaction).

During this transaction, the logic will clock out the contents of the outgoing buffer. If the outgoing buffer has not

been updated since the last transaction, then the logic will clock out 0xFFFF, and if the CRC is clocked, it will

clock out 0x00 for the CRC (if enabled). Thus the 0xFFFF00 will indicate to the controller that the outgoing buffer

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was not updated by the internal logic before the transaction occurred. This can occur when the device did not

have sufficient time to update the buffer between consecutive transactions.

When the internal logic takes the write-data from the interface logic and processes it, it also causes the R/W bit,

address, and data to be copied into the outgoing buffer. On the next transaction, this data is clocked back to the

controller.

When the controller is initiating a read, the internal logic will put the R/W bit and address into the outgoing buffer,

along with the data requested. The interface will compute the CRC on the two bytes in the outgoing buffer and

clock that back to the controller if CRC is enabled (with the exceptions associated with 0xFFFF as noted above).

A diagram of three transaction sequences with and without CRC are shown below, assuming CPOL=0.

SPI_CS

SPI_SCLK

SPI_MOSI

R/W bit & 7-bit

address # 1

8-bit write

data # 1

8-bit CRC

(for previous

two bytes)

SPI_MISO

Previous R/W bit

& 7-bit address

Previous 8-bit

write or read data

8-bit CRC

(for previous

two bytes)

Figure 14-5. SPI Transaction #1 Using CRC

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SPI_CS

SPI_SCLK

SPI_MOSI

8-bit write data

# 2 (or don’t

care if read)

8-bit CRC (for

previous two

bytes)

R/W bit & 7-bit

address # 2

SPI_MISO

R/W bit & 7-bit

address # 1

8-bit write

data # 1

8-bit CRC

(for previous

two bytes)

Figure 14-6. SPI Transaction #2 Using CRC

SPI_CS

SPI_SCLK

SPI_MOSI

SPI_MISO

R/W bit & 7-bit

address # 3

8-bit write data

# 3 (or don’t

care if read)

8-bit CRC

(for previous

two bytes)

R/W bit & 7-bit

address # 2

8-bit write or

read data # 2

8-bit CRC

(for previous

two bytes)

Figure 14-7. SPI Transaction #3 Using CRC

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SPI_CS

SPI_SCLK

SPI_MOSI

R/W bit & 7-bit

address # 1

8-bit write

data # 1

SPI_MISO

Previous R/W bit

& 7-bit address

Previous 8-bit

write or read

data

Figure 14-8. SPI Transaction #1 Without CRC

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SPI_CS

SPI_SCLK

SPI_MOSI

R/W bit & 7-bit

address # 2

8-bit write data

# 2 (or don’t

care if read)

SPI_MISO

R/W bit & 7-bit

address # 1

8-bit write

data # 1

Figure 14-9. SPI Transaction #2 Without CRC

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SPI_CS

SPI_SCLK

SPI_MOSI

R/W bit & 7-bit

address # 3

8-bit write data

# 3 (or don’t

care if read)

SPI_MISO

R/W bit & 7-bit

address # 2

8-bit write or

read data # 2

Figure 14-10. SPI Transaction #3 Without CRC

The time required for the device to process commands and subcommands will differ based on the specifics of

each. The direct commands generally will complete within 50 μs, while subcommands can take longer, with

different subcommands requiring different duration to complete. For example, when a particular subcommand is

sent, the device requires approximately 200 μs to load the 32-byte data into the internal subcommand buffer. If

the host provides sufficient time for this load to complete before beginning to read the buffer (readback from

addresses 0x40 to 0x5F), the device will respond with valid data, rather than 0xFFFF00. When data has already

been loaded into the subcommand buffer, this data can be read back with approximately 50 μs interval between

SPI transactions. The BQ76942 Technical Reference Manual provides more details on the approximate time

duration required for specific commands and subcommands.

The host software should incorporate a scheme to retry transactions that may not be successful. For example, if

the device returns 0xFFFFFF on SPI_MISO, then the internal clock is not powered, and the transaction needs to

be retried. Similarly, if the device returns 0xFFFFAA on a transaction, this indicates the previous transaction

encountered a CRC error, and so the previous transaction must be retried. As described above, if the device

returns 0xFFFF00, then the previous transaction had not completed when the present transaction was sent,

which may mean the previous transaction should be retried, or needs more time to complete.

14.4 HDQ Communications Interface

The HDQ interface is an asynchronous return-to-one protocol where a processor communicates with the

BQ76942 device using a single-wire connection to the ALERT pin or the HDQ pin, depending on configuration.

Both the controller (host device) and responder (BQ76942) drive the HDQ interface using an open-drain driver

with a pullup resistor from the HDQ interface to a supply voltage required on the circuit board. The BQ76942

device can be changed from the default communication mode to HDQ communication mode by setting the

Settings:Configuration:Comm Type configuration register or by sending a subcommand (at which point the

device switches to HDQ mode immediately).

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Note

The SWAP_COMM_MODE() subcommand immediately changes the communications interface to that

selected by the Comm Type configuration, while the SWAP_TO_HDQ() subcommand immediately

changes the interface to HDQ using the ALERT pin.

With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first.

The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field

(MSB Bit 7). The R/W field directs the device to do one of the following:

•

Accept the next 8 bits as data from the host to the device, or

Output 8 bits of data from the device to the host in response to the 7-bit command.

The HDQ peripheral on the BQ76942 device can transmit and receive data as an HDQ responder only.

The return-to-one data bit frame of HDQ consists of the following sections:

1. The first section is used to start the transmission by the host sending a Break (the host drives the HDQ

interface to a logic-low state for a time t_(B)) followed by a Break Recovery (the host releases the HDQ

interface for a time t_(BR)).

2. The next section is for host command transmission, where the host transmits 8 bits by driving the HDQ

interface for 8 T_(CYCH)time slots. For each time slot, the HDQ line is driven low for a time T_(HW0)(host writing

a "0") or T_(HW1)(host writing a "1"). The HDQ pin is then released and remains high to complete each T_(CYCH)

time slot.

3. The next section is for data transmission where the host (if a write was initiated) or device (if a read was

initiated) transmits 8 bits by driving the HDQ interface for 8 T_(CYCH)(if host is driving) or T_(CYCD)(if device is

driving) time slots. The HDQ line is driven low for a time T_(HW0)(host writing a "0"), T_(HW1)(host writing a "1"),

T_(DW0)(device writing a "0"), or T_(DW1)(device writing a "1"). The HDQ pin is then released and remains high

to complete the time slot. The HDQ interface does not auto-increment, so a separate transaction must be

sent for each byte to be transferred.

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15 Cell Balancing

15.1 Cell Balancing Overview

The BQ76942 device supports passive cell balancing by bypassing the current of a selected cell during charging

or at rest, using either integrated bypass switches between cells, or external bypass FET switches. The device

incorporates a voltage-based balancing algorithm which can optionally autonomously balance cells without

requiring any interaction with a host processor. Or if preferred, balancing can be entirely controlled manually

from a host processor. For autonomous balancing, the device will only balance non-adjacent cells in use (it does

not consider inputs used to measure interconnect as cells in use). In order to avoid excessive power dissipation

within the BQ76942 device, the maximum number of cells allowed to balance simultaneously can be limited by

configuration setting. For host-controlled balancing, adjacent as well as non-adjacent cells can be balanced.

Host-controlled balancing can be controlled using specific subcommands sent by the host. The device also

returns status information regarding how long cells have been balanced through subcommands.

When host-controlled balancing is initiated using subcommands, the device starts a timer and will continue

balancing until the timer reaches a programmed value, or a new balancing subcommand is issued (which resets

the timer). This is included as a precaution, in case the host processor initiated balancing but then stopped

communication with the BQ76942 device, so that balancing would not continue indefinitely.

The BQ76942 device can automatically balance cells using a voltage-based algorithm based on environmental

and system conditions. Several settings are provided to control when balancing is allowed, which are described

in detail in the BQ76942 Technical Reference Manual.

Due to the current that flows into the cell input pins on the BQ76942 device while balancing is active, the

measurement of cell voltages and evaluation of cell voltage protections by the device is modified during

balancing. Balancing is temporarily disabled during the regular measurement loop while the actively balanced

cell is being measured by the ADC, as well as when the cells immediately adjacent to the active cell are being

measured. Similarly, balancing on the top cell is disabled while the stack voltage measurement is underway. This

occurs on every measurement loop, and so can result in significant reduction in the average balancing current

that flows. In order to help alleviate this, additional configuration bits are provided which cause the device to slow

the measurement loop speed when cell balancing is active. The BQ76942 device will insert current-only

measurements after each voltage and temperature scan loop to slow down voltage measurements and thereby

increase the average balancing current.

The device includes an internal die temperature check, to disable balancing if the die temperature exceeds a

programmable threshold. However, the customer should still carefully analyze the thermal effect of the balancing

on the device in system. Based on the planned ambient temperature of the device during operation and the

thermal properties of the package, the maximum power should be calculated that can be dissipated within the

device and still ensure operation remains within the recommended operating temperature range. The cell

balancing configuration can then be determined such that the device power remains below this level by limiting

the maximum number of cells that can be balanced simultaneously, or by reducing the balancing current of each

cell by appropriate selection of the external resistance in series with each cell.

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16 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

16.1 Application Information

The BQ76942 device can be used with 3-series to 10-series battery packs, supporting a top-of-stack voltage

ranging from 5 V up to 55 V. To design and implement a comprehensive set of parameters for a specific battery

pack, during development the user can utilize Battery Management Studio (BQSTUDIO), which is a graphical

user-interface tool installed on a PC. Using BQSTUDIO, the device can be configured for specific application

requirements during development once the system parameters, such as fault trigger thresholds for protection,

enable or disable of certain features for operation, configuration of cells, and more are known. This results in a

"golden image" of settings, which can then be programmed into the device registers or OTP memory.

16.2 Typical Applications

Figure 16-1 shows a simplified application schematic for a 10-series battery pack, using the BQ76942 together

with an external secondary protector, a host microcontroller, and a communications transceiver. This

configuration uses CHG and DSG FETs in series, together with high-side PFET devices used to implement

precharge and predischarge functionality. See the following implementation considerations:

•

The external NPN BJT used for the REGIN preregulator can be configured with its collector routed either to

the cell battery stack or the middle of the protection FETs.

•

A diode is recommended in the drain circuit of the external NPN BJT, which avoids reverse current flow from

the BREG pin through the BJT base to collector in the event of a pack short circuit. This diode can be a

Schottky diode if low voltage pack operation is needed; otherwise, a conventional diode can be used.

•

A series diode is recommended at the BAT pin, together with a capacitor from the pin to VSS. These

components enable the device to continue operating for a short time when a pack short circuit occurs, which

may cause the PACK+ and top-of-stack voltages to drop to approximately 0 V. In this case, the diode

prevents the BAT pin from being pulled low with the stack, and the device will continue to operate, drawing

current from the capacitor. Generally, operation is only required for a short time until the device detects the

short circuit event and disables the DSG FET. A Schottky diode can be used if low voltage pack operation is

needed; otherwise, a conventional diode can be used.

•

The diode in the BAT connection and the diode in the BJT collector should not be shared, because the REG0

circuit might discharge the capacitor on BAT too quickly during a short circuit event.

The recommended voltage range on the VC0 to VC4 pins extends to –0.2 V. This can be used, for example,

to measure a differential voltage that extends slightly below ground, such as the voltage across a second

sense resistor in parallel with that connected to the SRP and SRN pins.

•

If a system does not use high-side protection FETs, then the PACK pin can be connected through a series

10-kΩ resistor to the top of the stack. The LD pin can be connected to VSS. In this case, the LD pin can also

be controlled separately to wake the device from SHUTDOWN mode, such as through external circuitry that

holds the LD pin at the voltage of VSS while the device stays in SHUTDOWN, and to be driven above a

voltage of V_WAKEONLDto wake from SHUTDOWN.

TI recommends using 100-Ω resistors in series with the SRP and SRN pins, and a 100 nF capacitor with

optional 100-pF differential filter capacitance between the pins for filtering. The routing of these components,

together with the sense resistor, to the pins should be minimized and fully symmetric, with all components

recommended to stay on the same side of the PCB with the device. Capacitors should not be connected from

the pins to VSS.

Due to thermistors often being attached to cells and possibly needing long wires to connect back to the

device, it may be helpful to add a capacitor from the thermistor pin to the device VSS. However, it is important

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to not use too large of a value of capacitor, since this will affect the settling time when the thermistor is biased

and measured periodically. A rule of thumb is to keep the time constant of the circuit < 5% of the

measurement time. When Settings:Configuration:Power Config[FASTADC] = 0, the measurement time is

approximately 3 ms, and with [FASTADC] = 1, the measurement time is halved to approximately 1.5 ms.

When using the 18-kΩ pullup resistor with the thermistor, the time constant is generally less than (18 kΩ) × C,

so a capacitor less than 4 nF is recommended. When using the 180-kΩ pullup resistor, the capacitor should

be less than 400 pF.

•

The integrated charge pump generates a voltage on the CP1 capacitor, requiring approximately 60 ms to

charge up to approximately 11 V when first enabled using the recommended 470-nF capacitor value. When

the CHG or DSG drivers are enabled, charge redistribution occurs from the CP1 capacitor to the CHG and

DSG capacitive FET loads. This generally results in a brief drop in the voltage on CP1, which is then

replenished by the charge pump. If the FET capacitive loading is large, such that at FET turn-on the voltage

on CP1 drops below an acceptable level for the application, then the value of the CP1 capacitor can be

increased. This has the drawback of requiring a longer startup time for the voltage on CP1 when the charge

pump is first powered on, and so should be evaluated to ensure it is acceptable in the system. For example, if

the CHG and DSG FETs are enabled simultaneously and their combined gate capacitance is approximately

400 nF, then changing CP1 to a value of 2200 nF results in the 11-V charge pump level dropping to

approximately 9 V before being restored to the 11-V level by the charge pump.

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PCHG

PDSG

SECONDARY

PROTECTOR

FUSE

PACK+

CAN

TRANSCEIVER

5V

COMM TO

SYSTEM

+

COMM

NC

REGIN

REG1

VC9

NC

3.3V

+

VDD

REG2

GPIO

VC8

NC

RST_SHUT

DDSG

DSG Logic Out

CHG Logic Out

MCU

VC7

NC

DCHG

+

GPIO

DFETOFF

CFETOFF

HDQ

VC6

NC

SDA

SCL

INT

SDA

VC5

NC

+

SCL

ALERT

VC4

GND

TS1

+

TS2

+

TS3

PACK-

Figure 16-1. BQ76942 10-Series Cell Typical Implementation (Simplified Schematic)

16.2.1 Design Requirements (Example)

Table 16-1. BQ76942 Design Requirements

DESIGN PARAMETER

Minimum system operating voltage

Cell minimum operating voltage

Series cell count

EXAMPLE VALUE

25 V

2.5 V

10

Sense resistor

1 mΩ

Number of thermistors

Charge voltage

3 (using TS1, TS2, and TS3 pins, all for cells)

42.5 V

Maximum charge current

Peak discharge current

Configuration settings

8.0 A

20.0 A

programmed in OTP during customer production

Protection subsystem configuration

Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously

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Table 16-1. BQ76942 Design Requirements (continued)

DESIGN PARAMETER

OV protection threshold

OV protection delay

EXAMPLE VALUE

4.30 V

500 ms

OV protection recovery hysteresis

UV protection threshold

UV protection delay

100 mV

2.5 V

20 ms

UV protection recovery hysteresis

SCD protection threshold

SCD protection delay

100 mV

80 mV (corresponding to a nominal 80 A, based on a 1-mΩ sense resistor)

50 µs

OCD1 protection threshold

OCD1 protection delay

OCD2 protection threshold

OCD2 protection delay

OCD3 protection threshold

OCD3 protection delay

OCC protection threshold

OCC protection delay

68 mV (corresponding to a nominal 68 A, based on a 1-mΩ sense resistor)

10 ms

56 mV (corresponding to a nominal 56 A, based on a 1-mΩ sense resistor)

80 ms

28 mV (corresponding to a nominal 28 A, based on a 1-mΩ sense resistor)

160 ms

8 mV (corresponding to a nominal 8 A, based on a 1-mΩ sense resistor)

160 ms

OTD protection threshold

OTD protection delay

60°C

2 s

OTC protection threshold

OTC protection delay

45°C

2 s

UTD protection threshold

UTD protection delay

–20°C

10 s

UTC protection threshold

UTC protection delay

0°C

5 s

Host watchdog timeout protection delay

CFETOFF pin functionality

DFETOFF pin functionality

ALERT pin functionality

REG1 LDO Usage

5 s

Use as CFETOFF, polarity = normally high, driven low to disable FET

Use as DFETOFF, polarity = normally high, driven low to disable FET

Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise

Use for 3.3-V output

Cell balancing

Enabled when imbalance exceeds 100 mV

16.2.2 Detailed Design Procedure

•

Determine the number of series cells.

– This value depends on the cell chemistry and the load requirements of the system. For example, to

support a minimum battery voltage of 25 V using Li-CO₂type cells with a cell minimum voltage of 2.5 V,

10-series cells should be used.

– For the correct cell connections, see Usage of VC Pins for Cells Versus Interconnect.

Protection FET selection and configuration

•

– The BQ76942 device is designed for use with high-side NFET protection (low-side protection NFETs can

be used by leveraging the DCHG / DDSG signals).

– The configuration should be selected for series Versus parallel FETs, which may lead to different FET

selection for charge Versus discharge direction.

– These FETs should be rated for the maximum:

•

Voltage, which should be approximately 5 V (DC) to 10 V (peak) per series cell.

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•

Current, which should be calculated based on both the maximum DC current and the maximum

transient current with some margin.

•

Power dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the

PCB design.

– The overdrive level of the BQ76942 device charge pump should be selected based on RDS(ON)

requirements for the protection FETs and their voltage handling requirements. If the FETs are selected

with a maximum gate-to-source voltage of 15 V, then the 11-V overdrive mode within the BQ76942 device

can be used. If the FETs are not specified to withstand this level, or there is a concern over gate leakage

current on the FETs, the lower overdrive level of 5.5 V can be selected.

•

Sense resistor selection

– The resistance value should be selected to maximize the input range of the coulomb counter but not

exceed the absolute maximum ratings, and avoid excessive heat generation within the resistor.

•

Using the normal maximum charge or discharge current, the sense resistor = 200 mV / 20.0 A = 10 mΩ

maximum.

•

However, considering a short circuit discharge current of 80 A, the recommended maximum SRP, SRN

voltage of ≈0.75 V, and the maximum SCD threshold of 500 mV, the sense resistor should be below

500 mV / 80 A = 6.25-mΩ maximum.

– Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin

should also be considered, so a sense resistor of 1 mΩ is suitable with a 50-ppm temperature coefficient

and power rating of 1 W.

•

The REG1 is selected to provide the supply for an external host processor, with output voltage selected for

3.3 V.

– The NPN BJT used for the REG0 preregulator should be selected to support the maximum collector-to-

emitter voltage of the maximum charging voltage of 42.5 V. The gain of the BJT should be chosen so it

can provide the required maximum output current with a base current level that can be provided from the

BQ76942 device.

– The BJT should support the maximum current expected from the REG1 (maximum of 45 mA, with short

circuit current limit of up to ≈80 mA).

– A diode can optionally be included in the collector circuit of the BJT, in order to avoid reverse current flow

from BREG through the base-collector junction of the BJT to PACK+ during a pack short circuit event. This

diode can be seen in Figure 16-1 at D2.

– A large resistor (such as 10 MΩ) is recommended from BREG to VSS to avoid any unintended leakage

current that may occur during SHUTDOWN mode.

16.2.3 Application Performance Plot

Figure 16-2 shows the error in measured temperature using an external Semitec 103-AT thermistor, the default

temperature polynomial, and the internal 18-kΩ pullup resistor.

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Measurements are taken using a Semitec 103-AT thermistor, the default temperature polynomial, and the 18-kΩ internal pullup resistor.

Figure 16-2. Thermistor Temperature Error

16.2.4 Calibration Process

The BQ76942 device includes the ability for the user to calibrate the current, voltage, and temperature

measurements on the customer production line. Detailed procedures are included in the BQ76942 Technical

Reference Manual. The device provides capability to calibrate individual cell voltage measurements, stack

voltage, PACK pin voltage, LD pin voltage, current measurement, and individual temperature measurements.

16.2.5 Design Example

Figure 16-3 and Figure 16-4 show a full schematic of a basic monitor circuit based on the BQ76942 for a 7-

series battery pack. Layout Example shows the board layout for this design.

TP1

7P

D1

BAT

R1

TP2

100

C1

1uF

C2

100pF

C3

0.47uF

100V

CD

U1

CP1

VSS

46

47

45 CHG

44

CHG

NC

CHG

D2

100V

BAT

R2

43 DSG

42 PACK

41 LD

40

DSG

PACK

LD

TP3

BAT+

20.0

R3

C4

220nF

J1

48

2

4

6

8

10

12

13

14

15

16

VC10

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

PACK

R4

150

1

2

3

4

5

6

7

8

9

NC

7P

6P

5P

4P

3P

2P

1P

1N

20.0

LD

C5

220nF

PCHG

PDSG

FUSE

39

C22

1uF

38 FUSE

37

TP4

Q1

FCX495TA

FUSE

R5

BREG

REGIN

1

BREG

REGIN

REG1

39502-1009

20.0

R6

C6

220nF

VSS

18

19

20

36

SRP

NC

REG1

35

C7

C8

22nF

20.0

R7

TP5

C9

220nF

1uF

34

33

32

31

30

29

SRN

REG2

TP6

20.0

R9

R8

1.0k

C10

220nF

VSS

RST_SHUT

DDSG

DCHG

DFETOFF

CFETOFF

HDQ

TS1

21

22

23

TS1

TS2

TS3

20.0

R10

C11

220nF

TS2

TP8

RT1

TP7

20.0

R11

1

3

5

7

9

NC

C12

220nF

SRP

SRN

VSS

RT2

R12

28

C13

220nF

1.0k

27

26

11

VSS

SDA

SCL

ALERT

VSS

TP9

24

25

17

R13

1.0k

REG18

VSS

REG1

REG18

VSS

BQ76942PFBR

External I2C Connection

R15

10k

C14

2.2uF

R14

10k

J2

4

3

2

1

SDA

SCL

PACK-

VSS

TS2

SRP

TP11

SRN

TP12

PGND

E2

TP10

U2

U3

E1

BAT-

C16

J3

1

2

100pF

C17

PEC02SAAN

NT1

Net-Tie

TP13

VSS

TP14

VSS

TP15

VSS

TP16

VSS

0.1uF

PGND

GND

R16

100

R17

100

WAKE

VSS

R18

10k

TP17

BAT-

R19

0.001

VSS

PGND

Figure 16-3. BQ76942 7-Series Cell Schematic Diagram—Monitor

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7P

TP18

C18

C19

D3

Red

0.1uF

FUSE

R20

3.9k

FUSE

TP19

Q2

Q3

R21

3.9k

1,2,3

7,8

5,6,

7,8

5,6,

R22

10M

R23

R24

C20

0.1uF

D4

16V

D5

16V

D6

16V

10M

C21

0.1uF

PACK+

4

3

2

1

PACK+

PACK-

Q4

4

3

2

1

R25

0

FUSE

R26

10k

TP20

TP21

E3

R27

5.1k

TP22

FUSEPIN

J4

Output

Q5

PMV213SN,215

R28

5.1k

1

D7

CHG

TP23

100V

R29

20k

C22

0.1uF

PGND

D8

10V

R30

5.1k

R31

7.50k

DSG

CHG

CD

R32

5.1k

TP24

VSS

PACK

TP25

LD

TP26

PGND

TP27

D9

100V

R33

R34

PACK

LD

5.1k

R35

5.1k

R36

DSG

5.1k

Figure 16-4. BQ76942 7-Series Cell Schematic Diagram—Additional Circuitry

16.3 Random Cell Connection Support

The BQ76942 device supports a random connection sequence of cells to the device during pack manufacturing.

For example, cell 7 in a 10-cell stack might be first connected at the input terminals leading to pins VC7 and

VC6, then cell 4 may next be connected at the input terminals leading to pins VC4 and VC3, and so on. It is not

necessary to connect the negative terminal of cell 1 first at VC0. As another example, consider a cell stack that

is already assembled and cells already interconnected to each other, then the stack is connected to the PCB

through a connector plugged in or soldered to the PCB. In this case, the sequence order in which the

connections are made to the PCB can be random in time; they do not need to be controlled in a certain

sequence.

There are, however, some restrictions to how the cells are connected during manufacturing:

•

IMPORTANT: The cells in a stack cannot be connected to any VC pin on the device randomly, such as the

lowest cell (cell 1) connected to VC9, while the top cell (cell 10) is connected to VC4, and so on. It is

important that the cells in the stack be connected in ascending pin order, with the lowest cell (cell 1)

connected between VC1 and VC0, the next higher voltage cell (cell 2) connected between VC2 and VC1, and

so on.

•

The random cell connection support is possible due to high voltage tolerance on pins VC1–VC10.

Note

VC0 has a lower voltage tolerance. This is because VC0 should be connected through the series-

cell input resistor to the VSS pin on the PCB, before any cells are attached to the PCB. Thus, the

VC0 pin voltage is expected to remain close to the VSS pin voltage during cell attach. If VC0 is not

connected through the series resistor to VSS on the PCB, then cells cannot be connected in

random sequence.

•

Each of the VC1–VC10 pins includes a diode between the pin and the adjacent lower cell input pin (that is,

between VC10 and VC9, between VC9 and VC8, and so on), which is reverse-biased in normal operation.

This means an upper cell input pin should not be driven to a low voltage while a lower cell input pin is driven

to a higher voltage, since this would forward bias these diodes. During cell attach, the cell input terminals

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should generally be floating before they are connected to the appropriate cell. It is expected that transient

current will flow briefly when each cell is attached, but the cell voltages quickly stabilize to a state without DC

current flowing through the diodes. However, if a large capacitance is included between a cell input pin and

another terminal (such as VSS or another cell input pin), the transient current may become excessive and

lead to device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin to the

values recommended in the specifications.

16.4 Startup Timing

At initial power up of the BQ76942 from a SHUTDOWN state, the device will progress through a sequence of

events before entering NORMAL mode operation. These are described below for an example configuration, with

approximate timing shown for the cases when [FASTADC] = 0 and [FASTADC] = 1.

Note

When the device is configured for autonomous FET control (that is, [FET_EN] = 1), the decision to

enable FETs is only evaluated every 250 ms while in NORMAL mode, which is why the FETs are not

enabled until approximately 280 ms after the wakeup event, even though the data was available

earlier.

Table 16-2. Startup Sequence and Timing

Step

Comment

FASTADC Setting

Time (relative to wakeup event)

Either the TS2 pin is pulled low,

or the LD pin is pulled up,

triggering the device to exit

SHUTDOWN mode.

Wakeup event

0, 1

0

This was measured with the OTP

programmed to autonomously

power the REG1 LDO.

REG1 powered

0, 1

20 ms

22 ms

This was measured with the OTP

programmed to provide the

INITSTART bit in the Alarm signal

on the ALERT pin.

INITSTART asserted

This was measured with the OTP

programmed to provide the

INITCOMP and ADSCAN bits in

the Alarm signal on the ALERT

pin.

0

1

69 ms

47 ms

INITCOMP and ADSCAN

asserted

This was measured with the OTP

programmed to provide the

FULLSCAN bit in the Alarm

signal on the ALERT pin.

0

1

164 ms

97 ms

FULLSCAN asserted

FETs enabled

This was measured with the OTP

programmed to autonomously

enable FETs.

0

1

282 ms

283 ms

Figure 16-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP

with [FASTADC] = 1, [FET_EN] = 1 for autonomous FET control, setup to use three thermistors, and providing

the [INITCOMP] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.

70

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Figure 16-5. Startup Sequence Using [FASTADC] = 1, with the [INITCOMP] Flag Displayed on the ALERT

Pin.

16.5 FET Driver Turn-Off

The high-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective

FET. The CHG driver includes an internal switch which discharges the CHG pin toward the BAT pin level. The

DSG FET driver will discharge the DSG pin toward the LD pin level, but it includes a more complex structure

than just a switch, to support a faster turn off.

When the DSG driver is triggered to turn off, the device will initially begin discharging the DSG pin toward VSS.

However, since the PACK+ terminal may not fall to a voltage near VSS quickly, the DSG FET gate should not be

driven significantly below PACK+, otherwise the DSG FET may be damaged due to excessive negative gate-

source voltage. Thus, the device monitors the voltage on the LD pin (which is connected to PACK+ through an

external series resistor) and will stop the discharge when the DSG pin voltage drops below the LD pin voltage.

When the discharge has stopped, the DSG pin voltage may relax back above the LD pin voltage, at which point

the device will again discharge the DSG pin toward VSS, until the DSG gate voltage again falls below the LD pin

voltage. This repeats in a series of pulses which over time discharge the DSG gate to the voltage of the LD pin.

This pulsing continues for approximately 100 to 200 μs, after which the driver remains in a high impedance state

if within approximately 500 mV of the voltage of the LD pin. The external resistor between the DSG gate and

source then discharges the remaining FET V_GSvoltage so the FET remains off.

The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the

turn-off transient. A low resistance (such as 100 Ω) will provide a fast turn-off during a short circuit event, but this

may result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value

(such as 1 kΩ or 4.7 kΩ) will reduce this speed and the corresponding inductive spike level.

Oscilloscope captures of DSG driver turn-off are shown below, with the DSG pin driving the gate of a

CSD19536KCS NFET, which has a typical C_issof 9250 pF. Figure 16-6 shows the signals when using a 1 kΩ

series gate resistor between the DSG pin and the FET gate, and a light load on PACK+, such that the voltage on

PACK+ drops slowly as the FET is disabled. The pulsing on the DSG pin can be seen lasting for approximately

170 μs.

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Figure 16-6. Moderate Speed DSG FET Turn-Off, Using a 1-kΩ Series Gate Resistor, and a Light Load on

PACK+.

A zoomed-in version of the pulsing generated by the DSG pin is shown in Figure 16-7, this time with PACK+

shorted to the top of stack.

Figure 16-7. Zoomed-In View of the Pulsing on the DSG Pin During FET Turn-Off

A slower turn-off case is shown in Figure 16-8, using a 4.7 kΩ series gate resistor, and the PACK+ connector

shorted to the top of stack.

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Figure 16-8. A Slower Turn-Off Case Using a 4.7-kΩ Series Gate Resistor, and the PACK+ Connector

Shorted to the Top of the Stack

A fast turn-off case is shown in Figure 16-9, in which a 100 Ω series gate resistor is used between the DSG pin

and the FET gate.

Figure 16-9. A Fast Turn-Off Case with a 100-Ω Series Gate Resistor

16.6 Unused Pins

Some device pins may not be needed in a particular application. The manner in which each should be

terminated in this case is described below.

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Table 16-3. Terminating Unused Pins

Name

Recommendation

Cell inputs 1, 2, and 10 should always be connected to actual cells with cells connected between VC1 and VC0,

between VC2 and VC1, and VC10 and VC9. VC0 should be connected through a resistor and capacitor on the

pcb to pin 17 (VSS). Pins related to any unused cells (which may be cell 3–cell 9) can be connected to the cell

stack to measure interconnect resistance or provide a Kelvin-connection to actual cells, in which case they

should include a series resistor and parallel capacitor in similar fashion to pins connected to actual cells (see

Usage of VC Pins for Cells Versus Interconnect). Another option is to short unused VC pins directly to an

adjacent VC pin. All VC pins should be connected to either an adjacent VC pin, an actual cell (through R and C),

or stack interconnect resistance (through R and C).

2, 4, 6, 8,

10, 12–

16, 48

VC0 – VC10

18, 20

SRP, SRN

NC

If not used, these pins should be connected to pin 17 (VSS).

1, 3, 5, 7,

9, 11, 19,

44

These pins are not connected to silicon. They can be left floating or connected to an adjacent pin or connected

to VSS.

TS1, TS3,

21, 23,

25, 28,

29, 30,

31, 32

ALERT, HDQ, If not used, these pins can be left floating or connected to pin 17 (VSS). Any of these pins (except for TS1 and

CFETOFF, TS3) may be configured with the internal weak pulldown resistance enabled during operation, although this is

DFETOFF, not necessary.

DCHG, DDSG

If the device is intended to enter SHUTDOWN mode, the TS2 pin should be left floating. If SHUTDOWN mode is

22

TS2

not used in the application and the TS2 pin is not used for a thermistor or ADCIN measurement, the TS2 pin can

be left floating or connected to pin 17 (VSS).

33

34, 35

36

RST_SHUT If not used, this pin should be connected to pin 17 (VSS).

REG1, REG2 If not used, these pins can be left floating or connected to pin 17 (VSS).

REGIN

If not used, this pin should be connected to pin 17 (VSS).

If this pin is not used and pin 36 (REGIN) is also not used, both pins should be connected to pin 17 (VSS). If this

pin is not used but pin 36 is used (such as driven from an external source), then this pin should be connected to

pin 36 (REGIN).

37

BREG

38

39

40

FUSE

PDSG

PCHG

If not used, this pin can be left floating or connected to pin 17 (VSS).

If not used, this pin should be left floating.

If the DSG driver is not used, this pin can be connected through a series resistor to the PACK+ connector or can

be connected to pin 17 (VSS).

41

LD

43

45

DSG

CHG

If not used, this pin should be left floating.

If not used, this pin should be connected to pin 47 (BAT). Note: If the charge pump is enabled with CP1

connected to BAT, the device consumes an additional ≈200 µA.

46

CP1

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17 Power Supply Requirements

The BQ76942 device draws its supply current from the BAT pin, which is typically connected to the top of stack

point through a series diode, to protect against any fault within the device resulting in unintended charging of the

pack. A series resistor and capacitor is included to lowpass filter fast variations on the stack voltage. During a

short circuit event, the stack voltage may be momentarily pulled to a very low voltage before the protection FETs

are disabled. In this case, the charge on the BAT pin capacitor will temporarily support the BQ76942 device

supply current, to avoid the device losing power.

18 Layout

18.1 Layout Guidelines

•

The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a

temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with

temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-

circuit ranges of the BQ76942 device. Parallel resistors can be used as long as good Kelvin sensing is

ensured. The device is designed to support a 1-mΩ sense resistor.

•

In reference to the system circuitry, the following features require attention for component placement and

layout: Differential Low-Pass Filter, and I²C communication.

The BQ76942 device uses an integrating delta-sigma ADC for current measurements. For best performance,

100-Ω resistors should be included from the sense resistor terminals to the SRP and SRN inputs of the

device, with a 0.1-μF filter capacitor placed across the SRP and SRN pins. Optional 0.1-µF filter capacitors

can be added for additional noise filtering at each sense input pin to ground. All filter components should be

placed as close as possible to the device, rather than close to the sense resistor, and the traces from the

sense resistor routed in parallel to the filter circuit. A ground plane can also be included around the filter

network to add additional noise immunity.

•

The BQ76942 device internal REG18 LDO requires an external decoupling capacitor, which should be placed

as close to the REG18 pin as possible, with minimized trace inductance, and connected to a ground plane

electrically connected to VSS.

The I²C clock and data pins have integrated ESD protection circuits; however, adding a Zener diode and

series resistor on each pin provides more robust ESD performance.

18.2 Layout Example

An example circuit layout using the BQ76942 device in a 7-series cell design is described below. The design

implements the schematic shown in Figure 16-3 and Figure 16-4, and uses a 2.5-inch × 2.75-inch 2-layer circuit

card assembly, with cell connections on the left edge, and pack connections along the top edge of the board.

Wide trace areas are used, reducing voltage drops on the high current paths.

The board layout, which is shown in Figure 18-1 and Figure 18-2, includes spark gaps with the reference

designator prefix E. These spark gaps are fabricated with the board, and no component is installed..

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Figure 18-1. BQ76942 Example Board Layout—Top Layer

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Figure 18-2. BQ76942 Example Board Layout—Bottom Layer

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19 Device and Documentation Support

19.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

19.2 Documentation Support

For additional information, see the following related documents:

•

BQ76942 Technical Reference Manual

BQ76942 Evaluation Module User's Guide

Using Low-Side FETs with the BQ76952 Battery Monitor Family

Cell Balancing with BQ76952, BQ76942 Battery Monitors

Multiple FETs with the BQ76952, BQ76942 Battery Monitors

A glossary that defines terms, acronyms, and definitions can be found at TI Glossary.

19.2.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

19.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

19.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

19.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

19.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

20 Mechanical, Packaging, Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	BQ7694202PFBR
厂家：	TEXAS INSTRUMENTS
描述：	BQ76942 3-Series to 10-Series High Accuracy Battery Monitor and Protector for Li-Ion, Li- Polymer, and LiFePO4 Battery Packs 电池
文件：	总83页 (文件大小：3481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ7694202PFBR [TI]

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