BQ7718_V04 [TI]
BQ7718 Overvoltage Protection for 2-Series to 5-Series Cell Li-Ion Batteries with Internal Delay Timer;
| 型号： | BQ7718_V04 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BQ7718 Overvoltage Protection for 2-Series to 5-Series Cell Li-Ion Batteries with Internal Delay Timer |
| 文件： | 总28页 (文件大小：1476K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ7718
SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
BQ7718 Overvoltage Protection for 2-Series to 5-Series Cell Li-Ion Batteries
with Internal Delay Timer
1 Features
3 Description
•
•
•
•
2-, 3-, 4-, and 5-series cell overvoltage protection
Internal delay timer
Fixed OVP threshold
High-accuracy overvoltage protection:
± 10 mV
The BQ7718xy family of products provides an
overvoltage monitor and protector for Li-Ion battery
pack systems. Each cell is monitored independently
for an overvoltage condition. For quicker production-
line testing, the BQ7718xy device provides
a
•
Low power consumption ICC ≈ 1 µA
Customer Test Mode (CTM) with greatly reduced
delay time.
(VCELL(ALL) < VPROTECT
)
•
•
Low leakage current per cell input < 100 nA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
In the BQ7718xy device, an internal delay timer is
initiated upon detection of an overvoltage condition
on any cell. Upon expiration of the delay timer, the
output is triggered into its active state (either high or
low depending on the configuration).
•
Package footprint options:
– Small 8-pin QFN (3.00 mm × 4.00 mm)
– Leaded 8-pin MSOP (3.00 mm × 5.00 mm,
including leads)
Device Information Table
PART NUMBER PACKAGE
BODY SIZE (NOM)
BQ771800(1)
DPJ (8)
DGK (8)
3.00 mm × 4.00 mm
2 Applications
3.00 mm x 3.00 mm (3.00
mm x 5.00 mm, including
leads)
BQ771800(2)
•
Protection for li-ion battery packs used in:
– Handheld garden tools
– Handheld power tools
– Cordless vacuum cleaners
– UPS battery backup
(1) For available catalog packages, see the orderable addendum
at the end of the data sheet and Section 5.
(2) Contact TI for more information.
– Light electric vehicles (eBike, eScooter, pedal
assist bicycles)
PACK+
R
VD
C
VD
VDD
R
IN
V5
V4
V3
V2
C
IN
R
IN
REG
C
IN
R
IN
INT_EN
V
OV
Delay
Timer
C
IN
R
IN
OUT
C
IN
R
IN
V1
OSC
C
IN
VSS
–
PACK
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
BQ7718
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 DC Characteristics......................................................6
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Systems Examples................................................... 15
10 Power Supply Recommendations..............................15
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Third-Party Products Disclaimer............................. 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks.............................................................17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (April 2021) to Revision L (June 2021)
Page
•
Changed the BQ771825 device to Production Data...........................................................................................3
Changes from Revision J (September 2020) to Revision K (June 2021)
Page
•
Added the BQ771825 device to the Device Comparison Table .........................................................................3
Changes from Revision I (July 2020) to Revision J (September 2020)
Page
•
•
•
Added the BQ771824 device to the Device Comparison Table .........................................................................3
Added BQ771824 to the DC Characteristics ..................................................................................................... 6
Added BQ771824 delay settings........................................................................................................................ 7
Changes from Revision H (February 2020) to Revision I (July 2020)
Page
•
•
•
•
Added the Functional Safety-Capable feature....................................................................................................1
Added the BQ771823 device to the Device Comparison Table .........................................................................3
Added BQ771823 to the DC Characteristics ..................................................................................................... 6
Added BQ771823 delay settings to Section 7.6 ................................................................................................ 7
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5 Device Comparison Table
Package
Designator
OV Hysteresis
(V)
Tape and Reel
(Large)
Tape and Reel
(Small)
TA
Part Number
BQ771800
BQ771801
Package
OVP (V)
4.300
Output Delay
Output Drive
0.300
0.050
4 s
3 s
CMOS Active High
BQ771800DPJR
BQ771801DPJR
BQ771800DPJT
BQ771801DPJT
NCH Active Low,
Open Drain
4.275
NCH Active Low,
Open Drain
BQ771802
BQ771803
4.225
4.275
0.300
0.050
1 s
1 s
BQ771802DPJR
BQ771802DPJT
BQ771803DPJR
BQ771803DGKR(2)
BQ771806DPJR
BQ771807DPJR
BQ771803DPJT
BQ771803DGKT(2)
BQ771806DPJT
BQ771807DPJT
NCH Active Low,
Open Drain
BQ771806
BQ771807
4.350
4.450
0.300
0.300
3 s
3 s
CMOS Active High
CMOS Active High
NCH Active Low,
Open Drain
BQ771808
4.200
0.050
1 s
BQ771808DPJR
BQ771808DPJT
BQ771809
BQ771811
4.200
4.225
0.050
0.050
1 s
1 s
CMOS Active High
CMOS Active High
BQ771809DPJR
BQ771811DPJR
BQ771809DPJT
BQ771811DPJT
–40°C to
110°C
8-Pin QFN or
8-Pin MSOP
DPJ/DGK
NCH Active Low,
Open Drain
BQ771815
BQ771817
4.225
4.275
0.050
0.050
1 s
1 s
BQ771815DPJR
BQ771815DPJT
CMOS Active High
BQ771817DPJR
BQ771818DPJR
BQ771818DGKR
BQ771817DPJT
BQ771818DPJT
BQ771818DGKT
BQ771818
4.300
0.300
1 s
CMOS Active High
NCH Active Low,
Open Drain
BQ771823
BQ771824
4.275
3.850
0.300
0.300
3 s
4 s
BQ771823DPJR
—
CMOS Active High
BQ771824DPJR
BQ771825DPJR
BQ771825DGKR(2)
BQ7718xyDPJR
—
BQ771825DPJT
BQ771825DGKT(2)
BQ7718xyDPJT
NCH Active Low,
Open Drain
BQ771825
3.950
0.050
3 s
BQ7718xy(1)
3.850 – 4.650 Latch, 0.05, 0.25,
0.3
1, 4, 3,
5.5 s
NCH, Active Low,
Open Drain,
CMOS Active High
(1) Future option. Contact TI for more information.
(2) Contact TI for more information.
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
6 Pin Configuration and Functions
VDD
V5
1
2
3
4
8
7
6
5
OUT
VSS
V1
V4
V3
V2
Figure 6-1. DPJ Package 8-Pin (WSON) Top View
VDD
V5
1
2
3
4
8
7
6
5
OUT
VSS
V1
V4
V3
V2
Not to scale
Figure 6-2. DGK Package 8-Pin (PDSO) Top View
Table 6-1. Pin Functions
NO.
1
NAME
TYPE I/O
DESCRIPTION
VDD
V5
P
I
Power supply
2
Sense input for positive voltage of the fifth cell from the bottom of the stack
Sense input for positive voltage of the fourth cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
3
V4
I
4
V3
I
5
V2
I
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the lowest cell in the stack
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
Output drive for overvoltage fault signal
6
V1
I
7
VSS
OUT
P
O
8
O = Output, I = Input, P = Power connection
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7 Specifications
7.1 Absolute Maximum Ratings
Over-operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage range
Input voltage range
Output voltage range
VDD – VSS
–0.3
30
V
V5 – VSS or V4 – VSS or
V3 – VSS or V2 – VSS or V1 – VSS
–0.3
–0.3
30
30
V
V
OUT – VSS
Continuous total power dissipation,
PTOT
See Section 7.4.
Functional temperature
–40
–65
110
150
°C
°C
Storage temperature range, TSTG
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum–rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM) ESD stress voltage(1)
Charged device model (CDM) ESD stress voltage(2)
V(ESD) Rating Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over-operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
(1)
Supply voltage, VDD
Input voltage range
25
5
V
V
V5–V4 or V4–V3 or
0
V3–V2 or V2–V1 or V1–VSS
Operating ambient temperature range, TA
(1) See Section 9.2.
–40
110
°C
7.4 Thermal Information
BQ7718xy
THERMAL METRIC(1)
DPJ (WSON)
8 PINS
56.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
56.4
30.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
1.0
ψJB
37.8
RθJCbot
11.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 DC Characteristics
Typical values stated where TA = 25°C and VDD = 18 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V to
25 V (unless otherwise noted).
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Voltage Protection Threshold VCx
BQ771800
BQ771801
BQ771803
BQ771802
BQ771806
BQ771807
BQ771808
BQ771809
BQ771811
BQ771815
BQ771817
BQ771818
BQ771823
BQ771824
BQ771800
BQ771801
BQ771802
BQ771803
BQ771806
BQ771807
BQ771808
BQ771809
BQ771811
BQ771815
BQ771817
BQ771818
BQ771823
BQ771824
TA = 25°C
TA = –40°C
TA = 0°C
4.300
V
V
4.275
4.275
4.225
4.350
4.450
4.200
4.200
4.225
4.225
4.275
4.300
4.275
3.850
300
V
V
V
V
V
V(PROTECT) Overvoltage
Detection
VOV
V
V
V
V
V
V
V
250
0
400
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
50
100
400
100
400
400
100
100
100
100
100
400
400
400
10
250
0
300
50
250
250
0
300
300
50
VHYS
OV Detection Hysteresis
0
50
0
50
0
50
0
50
250
250
250
–10
–40
–20
–24
–54
300
300
300
VOA
OV Detection Accuracy
44
20
OV Detection Accuracy Across
Temperature
VOADRIFT
TA = 60°C
TA = 110°C
24
54
Supply and Leakage Current
(V5–V4) = (V4–V3) = (V3–V2) = (V2–V1) =
(V1–VSS) = 4 V (See Figure 8-2.)
ICC
IIN
Supply Current
1
2
µA
µA
(V5–V4) = (V4–V3) = (V3–V2) = (V2–V1) =
(V1–VSS) = 4 V (See Figure 8-2.)
Input Current at Vx Pins
–0.1
0.1
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Typical values stated where TA = 25°C and VDD = 18 V, MIN/MAX values stated where TA = –40°C to 110°C and VDD = 3 V to
25 V (unless otherwise noted).
SYMBOL
Output Drive OUT, CMOS Active HIGH Versions Only
(V5–V4), (V4–V3), (V3–V2), (V2–V1), or
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
(V1–VSS) > VOV, VDD = 18 V, IOH = 100
µA
6
V
If three of four cells are short circuited and
Output Drive Voltage, Active
High
VOUT1
only one cell remains powered and > VOV
VDD = Vx (cell voltage), IOH = 100 µA
,
VDD – 0.3
250
V
(V5–V4), (V4–V3), (V3–V2), (V2–V1), and
(V1–VSS) < VOV, VDD = 18 V, IOL = 100 µA
measured into pin
400
mV
mA
mA
(V5–V4), (V4–V3), (V3–V2), (V2–V1), or
(V1–VSS) > VOV, VDD = 18 V. OUT = 0 V.
Measured out of OUT pin
OUT Source Current (during
OV)
IOUTH1
4.5
14
(V5–V4), (V4–V3), (V3–V2), (V2–V1), and
(V1–VSS) < VOV, VDD = 18 V, OUT = VDD.
Measured into OUT pin
IOUTL1
OUT Sink Current (no OV)
0.5
0.5
Output Drive OUT, NCH Open Drain Active LOW Versions Only
(V5–V4), (V4–V3), (V3–V2), (V2–V1), or
(V1–VSS) > VOV, VDD = 18 V, IOL = 100 µA
measured into OUT pin
Output Drive Voltage, Active
Low
VOUT2
IOUTH2
IOUTL2
250
400
14
mV
mA
nA
(V5–V4), (V4–V3), (V3–V2), (V2–V1), or
(V1–VSS) > VOV, VDD = 18 V. OUT = VDD.
Measured into OUT pin
OUT Sink Current (during OV)
OUT Source Current (no OV)
(V5–V4), (V4–V3), (V3–V2), (V2–V1), and
(V1–VSS) < VOV, VDD = 18 V. OUT = VDD.
Measured out of OUT pin
100
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
Delay Timer
BQ771800, BQ771824
3.2
2.4
4
3
4.8
3.6
s
s
BQ771801, BQ771807, BQ771823
tDELAY
OV Delay Time
BQ771802, BQ771803, BQ771811,
BQ771815, BQ771818
0.8
4.4
1
5.5
15
1.2
6.6
s
s
Preview option only. Contact TI.
Fault Detection Delay Time during
Customer Test Mode
XCTMDELAY
See Section 8.4.3.
ms
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7.7 Typical Characteristics
4.40
0.316
0.315
0.314
0.313
0.312
Mean
4.39
Min
4.38
4.37
4.36
4.35
4.34
4.33
4.32
4.31
4.30
Max
−50
−25
0
25 50
Temperature (°C)
75
100
125
−50
−25
0
25 50
Temperature (°C)
75
100
125
G001
G002
Figure 7-1. Overvoltage Threshold (OVT) vs.
Temperature
Figure 7-2. Hysteresis VHYS vs. Temperature
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−50
−25
0
25 50
Temperature (°C)
75
100
125
−50
−25
0
25 50
Temperature (°C)
75
100
125
G003
G004
Figure 7-3. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 7-4. ICELL vs. Temperature
at VCELL= 9.2 V
−3.68
−3.70
−3.72
−3.74
−3.76
−3.78
−3.80
−3.82
−3.84
−3.86
−3.88
8
7
6
5
4
3
2
1
0
−50
−25
0
25 50
Temperature (°C)
75
100
125
0
5
10
15
20
25
30
VDD (V)
G005
G006
Figure 7-5. Output Current IOUT vs.
Temperature
Figure 7-6. VOUT vs. VDD
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8 Detailed Description
8.1 Overview
In the BQ7718xy family of devices, each cell is monitored independently and an external delay timer is initiated if
an overvoltage condition is detected on any cell.
For quicker production-line testing, the device provides a Customer Test Mode with greatly reduced delay time.
8.2 Functional Block Diagram
PACK+
R
VD
C
VD
VDD
R
IN
V5
V4
V3
V2
C
IN
R
IN
REG
C
IN
R
IN
INT_EN
V
OV
Delay
Timer
C
IN
R
IN
OUT
C
IN
R
IN
V1
OSC
C
IN
VSS
–
PACK
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
In the BQ7718xy device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. When the timer expires, the OUT pin goes from inactive to active state.
For NCH Open Drain Active Low configurations, the OUT pin pulls down to VSS when active (OV present) and is
high impedance when inactive (no OV).
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VOV
VOV–VHYS
tDELAY
OUT (V)
Figure 8-1. Timing for Overvoltage Sensing
8.3.1 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
8.3.2 Output Drive, OUT
This pin serves as the fault signal output, and may be ordered in either active HIGH or LOW options.
8.3.3 Supply Input, VDD
This pin is the unregulated input power source for the IC. A series resistor is connected to limit the current, and a
capacitor is connected to ground for noise filtering.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.
The device monitors the differential cell voltages connected across (V1 – VSS), (V2 – V1), (V3 – V2), (V4 – V3),
and (VC4 – VC5). The OUT pin is inactive and if configured:
The OUT pin is inactive and if configured:
•
•
Active high is low.
Active low is being externally pulled up and is an open drain.
8.4.2 OVERVOLTAGE Mode
OVERVOLTAGE mode is detected if any of the cell voltages exceeds the overvoltage threshold, VOV for
configured OV delay time. The OUT pin is activated after a delay time set by the capacitance in the CD pin. The
OUT pin will either pull high internally, if configured as active high, or will be pulled low internally, if configured as
active low. When all of the cell voltages fall below the (VOV – VHYS), the device returns to NORMAL mode.
8.4.3 Customer Test Mode
Customer Test Mode (CTM) helps to reduce test time for checking the overvoltage delay timer parameter once
the circuit is implemented in the battery pack. To enter CTM, VDD should be set to at least 10 V higher than V5
(see Figure 8-2). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal
operation. To exit Customer Test Mode, remove the VDD to a V5 voltage differential of 10 V so that the decrease
in this value automatically causes an exit.
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CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into Customer
Test Mode. Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (V5–
V4), (V4–V3), (V4–V3), (V3–V2), (V2–V1), and (V1–VSS). Stressing the pins beyond the rated limits
may cause permanent damage to the device.
Figure 8-2 shows the timing for the Customer Test Mode.
10 V
V
OV
V
V
–
OV HYS
> 10 ms
OUT (V)
Figure 8-2. Timing for Customer Test Mode
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
In the case of an Open Drain Active Low configuration, an external pull-up resistor is required on the OUT pin.
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements.
C
VD
VDD
V5
OUT
VSS
R
VD
R
R
C
C
IN
IN
IN
IN
Cell5
Cell4
V4
V3
V1
V2
R
R
R
IN
IN
IN
Cell3
Cell2
Cell1
C
C
IN
IN
C
IN
Copyright © 2016, Texas Instruments Incorporated
Figure 9-1. Application Configuration
9.1.1 Design Requirements
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements. Figure 9-1 shows
each external component.
Table 9-1. Parameters
PARAMETER
Voltage monitor filter resistance
EXTERNAL COMPONENT
MIN
900
0.01
100
NOM
MAX
1100
0.1
UNIT
Ω
RIN
CIN
1000
Voltage monitor filter capacitance
Supply voltage filter resistance
Supply voltage filter capacitance
CD external delay capacitance
µF
Ω
RVD
CVD
1K
0.1
0.1
µF
µF
1
OUT Open drain version pull-up resistance to
PACK+
100
kΩ
Copyright © 2021 Texas Instruments Incorporated
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
Note
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
9.1.2 Detailed Design Procedure
Figure 9-2 shows the measurement for current consumption for the product for both VDD and Vx.
ICC
OUT
VSS
V1
VDD
V5
IIN
Cell5
Cell4
IIN
V4
IIN
V3
V2
Cell3
Cell2
Cell1
IIN
IIN
Copyright © 2016, Texas Instruments Incorporated
Figure 9-2. Configuration for IC Current Consumption Test
Copyright © 2021 Texas Instruments Incorporated
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BQ7718
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
9.1.2.1 Application Curves
4.40
0.316
0.315
0.314
0.313
0.312
Mean
4.39
Min
4.38
4.37
4.36
4.35
4.34
4.33
4.32
4.31
4.30
Max
−50
−25
0
25 50
Temperature (°C)
75
100
125
−50
−25
0
25 50
Temperature (°C)
75
100
125
G001
G002
Figure 9-3. Overvoltage Threshold (OVT) vs.
Temperature
Figure 9-4. Hysteresis VHYS vs. Temperature
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−50
−25
0
25 50
Temperature (°C)
75
100
125
−50
−25
0
25 50
Temperature (°C)
75
100
125
G003
G004
Figure 9-5. IDD Current Consumption vs.
Temperature at VDD = 16 V
Figure 9-6. ICELL vs. Temperature
at VCELL= 9.2 V
−3.68
−3.70
−3.72
−3.74
−3.76
−3.78
−3.80
−3.82
−3.84
−3.86
−3.88
8
7
6
5
4
3
2
1
0
−50
−25
0
25 50
Temperature (°C)
75
100
125
0
5
10
15
20
25
30
VDD (V)
G005
G006
Figure 9-7. Output Current IOUT vs.
Temperature
Figure 9-8. VOUT vs. VDD
Copyright © 2021 Texas Instruments Incorporated
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
9.2 Systems Examples
In these application examples, an external pull-up resistor is required on the OUT pin to configure for an Open
Drain Active Low operation.
C
C
VD
VD
OUT
VSS
V1
OUT
VSS
VDD
V5
VDD
V5
R
R
VD
VD
V4
V3
V1
V2
V4
R
IN
Cell4
C
IN
V3
V2
R
R
IN
IN
C
C
Cell3
Cell2
Cell1
Cell3
Cell2
Cell1
IN
IN
R
R
IN
IN
IN
C
C
IN
IN
R
R
C
IN
C
IN
IN
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 9-10. 3-Series Cell Configuration with Fixed
Delay
Figure 9-9. 4-Series Cell Configuration
C
VD
VDD
V5
OUT
VSS
V1
R
VD
V4
V5
V2
R
IN
C
IN
Cell2
Cell1
R
IN
C
IN
Copyright © 2016, Texas Instruments Incorporated
Figure 9-11. 2-Series Cell Configuration with Internal Fixed Delay
10 Power Supply Recommendations
The maximum power of this device is 25 V on VDD.
Copyright © 2021 Texas Instruments Incorporated
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
11 Layout
11.1 Layout Guidelines
•
•
Ensure the RC filters for the V1 and VDD pins are placed as close as possible to the target terminal.
The VSS pin should be routed to the CELL– terminal.
11.2 Layout Example
Place the RC filters close to the
Power Trace Line
device terminals
Pack +
OUT
VDD
VC5
OUT
VSS
VCELL5
Pack -
VC4
VC3
VC1
VCELL4
VCELL3
VCELL2
VCELL1
PWPD
VC2
Figure 11-1. Example Layout
Copyright © 2021 Texas Instruments Incorporated
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BQ7718
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SLUSAX1L – DECEMBER 2012 – REVISED JUNE 2021
12 Device and Documentation Support
12.1 Documentation Support
For additional information, see the BQ7718 technical documentation, including the documentation available to
aid functional safety system design.
12.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ771800DPJR
BQ771800DPJT
BQ771801DPJR
BQ771801DPJT
BQ771802DPJR
BQ771802DPJT
BQ771803DPJR
BQ771803DPJT
BQ771806DPJR
BQ771806DPJT
BQ771807DPJR
BQ771807DPJT
BQ771808DPJR
BQ771808DPJT
BQ771809DPJR
BQ771809DPJT
BQ771811DPJR
BQ771811DPJT
BQ771815DPJR
BQ771815DPJT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
771800
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
771800
771801
771801
771802
771802
771803
771803
771806
771806
771807
771807
771808
771808
771809
771809
771811
771811
771815
771815
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ771817DPJR
BQ771817DPJT
BQ771818DPJR
BQ771818DPJT
BQ771823DPJR
BQ771824DPJR
BQ771825DPJR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 110
-40 to 110
-40 to 85
771817
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
771817
771818
771818
771823
771824
771825
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ771800DPJR
BQ771800DPJT
BQ771801DPJR
BQ771801DPJT
BQ771802DPJR
BQ771802DPJR
BQ771802DPJT
BQ771802DPJT
BQ771803DPJR
BQ771803DPJR
BQ771803DPJT
BQ771803DPJT
BQ771806DPJR
BQ771806DPJT
BQ771807DPJR
BQ771807DPJT
BQ771808DPJR
BQ771808DPJT
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ771809DPJR
BQ771809DPJR
BQ771809DPJT
BQ771809DPJT
BQ771811DPJR
BQ771811DPJR
BQ771811DPJT
BQ771811DPJT
BQ771815DPJR
BQ771815DPJT
BQ771817DPJR
BQ771817DPJR
BQ771817DPJT
BQ771817DPJT
BQ771818DPJR
BQ771818DPJR
BQ771818DPJT
BQ771818DPJT
BQ771823DPJR
BQ771824DPJR
BQ771825DPJR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
3000
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
3000
3000
250
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
3000
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ771800DPJR
BQ771800DPJT
BQ771801DPJR
BQ771801DPJT
BQ771802DPJR
BQ771802DPJR
BQ771802DPJT
BQ771802DPJT
BQ771803DPJR
BQ771803DPJR
BQ771803DPJT
BQ771803DPJT
BQ771806DPJR
BQ771806DPJT
BQ771807DPJR
BQ771807DPJT
BQ771808DPJR
BQ771808DPJT
BQ771809DPJR
BQ771809DPJR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
367.0
210.0
367.0
210.0
367.0
367.0
210.0
210.0
367.0
367.0
210.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
367.0
185.0
367.0
185.0
367.0
367.0
185.0
185.0
367.0
367.0
185.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
3000
250
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ771809DPJT
BQ771809DPJT
BQ771811DPJR
BQ771811DPJR
BQ771811DPJT
BQ771811DPJT
BQ771815DPJR
BQ771815DPJT
BQ771817DPJR
BQ771817DPJR
BQ771817DPJT
BQ771817DPJT
BQ771818DPJR
BQ771818DPJR
BQ771818DPJT
BQ771818DPJT
BQ771823DPJR
BQ771824DPJR
BQ771825DPJR
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
DPJ
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
250
250
210.0
210.0
367.0
367.0
210.0
210.0
367.0
210.0
367.0
367.0
210.0
210.0
367.0
367.0
210.0
210.0
367.0
367.0
367.0
185.0
185.0
367.0
367.0
185.0
185.0
367.0
185.0
367.0
367.0
185.0
185.0
367.0
367.0
185.0
185.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
250
3000
250
3000
3000
250
250
3000
3000
250
250
3000
3000
3000
Pack Materials-Page 4
PACKAGE OUTLINE
DPJ0008A
WSON - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2.3 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
4
5
SYMM
9
2X 1.95
6X 0.65
8
1
0.3
8X
PIN 1 ID
0.2
0.6
0.4
0.1
C A B
8X
0.05
4218853/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DPJ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.3)
8X (0.7)
SEE SOLDER MASK
DETAIL
SYMM
1
8X (0.25)
6X (0.65)
8
9
SYMM
(0.9)
(R0.05) TYP
4
5
(
0.2) TYP
VIA
(0.9)
(3.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218853/A 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DPJ0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.61)
8X (0.7)
4X ( 1.02)
8X (0.25)
8
1
(0.61)
9
SYMM
6X (0.65)
(R0.05) TYP
5
4
SYMM
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 9
79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4218853/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Copyright © 2021, Texas Instruments Incorporated
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