BQ77216_V01 [TI]
BQ77216 Voltage and Temperature Protection for 3-Series to 16-Series Cell Li-Ion Batteries with Internal Delay Timer;
| 型号： | BQ77216_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BQ77216 Voltage and Temperature Protection for 3-Series to 16-Series Cell Li-Ion Batteries with Internal Delay Timer |
| 文件： | 总23页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ77216
SLUSE36 – AUGUST 2020
BQ77216 Voltage and Temperature Protection for 3-Series to 16-Series Cell Li-Ion
Batteries with Internal Delay Timer
1 Features
3 Description
•
•
3-series cell to 16-series cell protection
High-accuracy over voltage protection
– ± 10 mV at 25°C
– ± 20 mV from 0°C to 60°C
Overvoltage protection options from 3.55 V to 5.1
V
Undervoltage protection with options from 1.0 V to
3.5 V
Open-wire connection detection
Overtemperature protection
Random cell connection
The BQ77216 family of products provides a range of
voltage and temperature monitoring including
overvoltage (OVP), undervoltage (UVP), open wire
(OW), and overtemperature (OT) protection for li-ion
battery pack systems. Each cell is monitored
independently for overvoltage, undervoltage, and
open-wire conditions. With the addition of an external
NTC thermistor, the device can detect
•
•
overtemperature conditions.
•
•
•
•
•
•
•
In the BQ77216 device, an internal delay timer is
initiated upon detection of an overvoltage,
undervoltage, open-wire, or overtemperature
condition. Upon expiration of the delay timer, the
respective output is triggered into its active state
(either high or low, depending on the configuration).
Functional safety-capable
Fixed internal delay timers
Fixed detections thresholds
Fixed output drive type for each of COUT and
DOUT
– Active high or active low
– Active high drive to 6 V
– Open drain with ability to be pulled up
externally to VDD
The overvoltage triggers the COUT pin if a fault is
detected, and undervoltage triggers the DOUT pin if a
fault is detected. If an overtemperature or open-wire
fault is detected, then both the DOUT and COUT will
be triggered. For quicker production-line testing, the
BQ77216 device provides a Customer Test Mode
(CTM) with greatly reduced delay time.
•
•
•
Low power consumption ICC ≈ 1 µA
(VCELL(ALL) < VOV
)
Device Information Table
Low leakage current per cell input < 100 nA with
open wire detection disabled
Package footprint options:
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.40 mm x 7.80 mm
(6.40 mm x 7.80 mm,
including leads)
BQ7721600(1)
TSSOP (24)
– Leaded 24-pin TSSOP with 0.65-mm lead pitch
2 Applications
(1) Contact TI for more information.
PACK+
Fuse or
Back-to-Back FETs
•
Protection for li-ion battery packs used in:
– Handheld garden tools
CVD
– Handheld power tools
VDD
– Cordless vacuum cleaners
– UPS battery backup
RIN
V16
CIN
DOUT
– Light electric vehicles (eBike, eScooter, pedal
assist bicycles)
RIN
RIN
RIN
V3
CIN
V2
CIN
V1
CIN
VSS
RDOUT
GND
COUT
RCOUT
RNTC
TS
PACK-
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
BQ77216
SLUSE36 – AUGUST 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
24-Lead Pin Functions......................................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 DC Characteristics......................................................5
7.6 Timing Requirements..................................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................10
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Systems Example..................................................... 14
10 Power Supply Recommendations..............................15
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Trademarks.............................................................17
12.2 Electrostatic Discharge Caution..............................17
12.3 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Date
Revision
Notes
August 2020
*
Advance Information
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5 Device Comparison Table
Package
Designator
OV Hysteresis
(V)
Output
Delay
UV Hysteresis
(V)
Output
Drive
TA
Part Number
Package
OVP (V)
UVP (V)
OT (°C)
Tape and Reel
–40°C to
110°C
24-Pin
TSSOP
BQ7721600
PW
4.325
0.100
0.100
1 s
1 s
2.25
0.100
0.100
70
Active Low
BQ7721600PWR
Active
High, 6-V
Drive
–40°C to
110°C
24-Pin
TSSOP
BQ7721602
PW
4.325
2.25
70
BQ7721602PWR
6 Pin Configuration and Functions
NC
VDD
V16
V15
V14
V13
V12
V11
V10
V9
1
24
23
22
21
20
19
18
17
16
15
14
13
TS
2
DOUT
COUT
VSS
V1
3
4
5
6
V2
7
V3
8
V4
9
NC
10
11
12
NC
V8
V5
V7
V6
Not to scale
Figure 6-1. PW Package 24-Pin
24-Lead Pin Functions
NO. NAME
TYPE DESCRIPTION
1
2
NC
—
P
I
Not electrically connected and can be left floating
Power supply
VDD
V16
V15
V14
V13
V12
V11
V10
V9
3
Sense input for positive voltage of the sixteenth cell from the bottom of the stack
Sense input for positive voltage of the fifteenth cell from the bottom of the stack
Sense input for positive voltage of the fourteenth cell from the bottom of the stack
Sense input for positive voltage of the thirteenth cell from the bottom of the stack
Sense input for positive voltage of the twelfth cell from the bottom of the stack
Sense input for positive voltage of the eleventh cell from the bottom of the stack
Sense input for positive voltage of the tenth cell from the bottom of the stack
Sense input for positive voltage of the ninth cell from the bottom of the stack
Sense input for positive voltage of the eighth cell from the bottom of the stack
Sense input for positive voltage of the seventh cell from the bottom of the stack
Sense input for positive voltage of the sixth cell from the bottom of the stack
Sense input for positive voltage of the fifth cell from the bottom of the stack
Not electrically connected and can be left floating
4
I
5
I
6
I
7
I
8
I
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
I
V8
I
V7
I
V6
I
V5
I
NC
—
—
I
NC
Not electrically connected and can be left floating
V4
Sense input for positive voltage of the fourth cell from the bottom of the stack
Sense input for positive voltage of the third cell from the bottom of the stack
Sense input for positive voltage of the second cell from the bottom of the stack
Sense input for positive voltage of the lowest cell in the stack
V3
I
V2
I
V1
I
VSS
COUT
P
O
Electrically connected to IC ground and negative terminal of the lowest cell in the stack
Output drive for overvoltage, open wire, and overtemperature. It can be left floating if not used.
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NO. NAME
TYPE DESCRIPTION
23
24
DOUT
TS
O
I
Output drive for undervoltage, open wire, and overtemperature. It can be left floating if not used.
Temperature sensor input. If not used, connect directly to VSS.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
VDD - VSS
range
–0.3
85
V
Vn - VSS where n = 1 to 16
TS
–0.3
–0.3
85
V
V
Input voltage
range
1.5
Output voltage
range
COUT - VSS, DOUT - VSS
–0.3
–40
85
V
Functional
temperature,
TFUNC
110
°C
Storage
temperature,
TSTG
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following
sentence optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following
sentence optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5
NOM
MAX
75
UNIT
V
VDD
VIN
Supply voltage
Input voltage range of Vn - Vn-1 where n = 2 to 16 and V1 - VSS
TS
0
5
V
0
1.5
13
V
VCTM
CTS
TA
Customer Test Mode Entry VDD > V16 + VCTM
Total capacitance on the TS Pin
Ambient temperature
12
V
200
85
pF
°C
°C
–40
–65
TJ
Junction temperature
150
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7.4 Thermal Information
DEVICE
PW (TSSOP)
24 PINS
97.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
40.5
53.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.3
ΨJB
52.7
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 DC Characteristics
Typical values stated where TA = 25°C and VDD = 58 V, MIN/MAX values stated where TA = –40°C to 85°C and
VDD = 5 V to 75 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVER VOLTAGE PROTECTION (OV)
VOV
OV Detection Range
3.55
5.1
V
VOV_STEP OV Detection Steps
25
mV
VOV
100
–
mV
mV
mV
mV
mV
VOV_HYS OV Detection Hysteresis
VOV
200
–
TA = 25℃
OV Detection Accuracy
–10
–20
–50
10
20
50
0℃ ≤ TA ≤ 60℃
VOV_ACC OV Detection Accuracy
-40℃ ≤ TA ≤ 110℃
OV Detection Accuracy
UNDER VOLTAGE PROTECTION (UV)
VUV
UV Detection Range
1.0
3.5
V
VUV_STEP UV Detection Steps
50
mV
VUV
100
+
mV
mV
VUV_HYS UV Detection Hysteresis
VUV
200
+
UV Detection Accuracy
VUV_ACC
TA = 25℃
–20
–50
450
20
50
mV
mV
mV
UV Detection Accuracy
-40 ≤ TA ≤ 110℃
VUV_MIN UV Detection Disabled Threshold
Vn - Vn-1 where n = 2 to 16 and V1 - VSS
500
550
OVER TEMPERATURE PROTECTION (OT)
Available options: 62°C, 65°C, 70°C,
75°C, 80°C, 83°C
TOT
OT Detection Range
62.0
83.0
°C
Ω
3000
2570
2195
1915
1651
1525
ROT_EXT OT Detection External Resistance
OT Detection External Resistance
ROT_ACC
Accuracy
–2%
2%
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Typical values stated where TA = 25°C and VDD = 58 V, MIN/MAX values stated where TA = –40°C to 85°C and
VDD = 5 V to 75 V (unless otherwise noted).
PARAMETER
TOT_HYS OT Detection Hysteresis
TOT_ACC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–10
°C
4186
3530
Ω
Ω
OT Detection Accuracy
–5
5
°C
(1)
RNTC
Internal Pull Up Resistor
After TI Factory Trim
19.5
20
20.5
kΩ
OPEN WIRE PROTECTION (OW)
Vn < Vn-1 where n = 2 to 16
V1 - VSS
–200
200
mV
mV
mV
mV
mV
VOW
OW Detection Threshold(1)
VOW_HYS OW Detection Hysteresis
Vn < Vn-1 where n = 1 to 16
TA = 25℃
100
OW Detection Accuracy
VOW_ACC
–12
–25
12
25
OW Detection Accuracy
-40 ℃ ≤ TA ≤ 110℃
SUPPLY AND LEAKAGE CURRENT
ICC
Supply Current
No fault detected.
1
2
µA
µA
Vn - Vn-1 and V1 - VSS = 4V, where n =
2 to 16
–0.2
–0.1
0.2
IIN
Input Current at Vx Pins
Vn - Vn-1 and V1 - VSS = 4V, where n =
2 to 16
0.1
µA
OUTPUT DRIVE, COUT and DOUT, CMOS ACTIVE HIGH VERSIONS ONLY
Vn - Vn-1 or V1 - VSS > VOV, where n = 2
to 16, VDD = 58 V, IOH = 100 µA
measured into COUT, DOUT pin.
6
0
V
V
VDD - VCOUT or VDOUT, Vn - Vn-1 or V1 -
VSS > VOV, where n = 2 to 16, IOH = 10
µA measured into COUT, DOUT pin.
1
1
1.5
1.5
Output Drive Voltage for COUT and
DOUT, Active High
VOUT_AH
VDD - VCOUT or VDOUT, If 15 of 16 cells
are short circuited and only one cell
remains powered and > VOV, VDD = Vx
(cell voltage), IOH = 100 µA,
0
V
Vn - Vn-1 and V1 - VSS < VOV, where n =
2 to 16, VDD = 58 V, IOH = 100 µA
measured into pin
250
100
400
120
4.5
mV
kΩ
ROUT_AH Internal Pull Up Resistor
IOUT_AH_
80
Vn - Vn-1 or V1 - VSS > VOV, where n = 2
to 16, VDD = 58 V, OUT = 0V. Measured
out of COUT, DOUT pin
OUT Source Current (during OV)
mA
H
Vn - Vn-1 and V1 - VSS < VOV, where n =
2 to 16, VDD = 58 V, OUT = VDD.
Measured into COUT, DOUT pin
IOUT_AH_L OUT Sink Current (no OV)
0.3
3
mA
OUTPUT DRIVE, COUT and DOUT, NCH OPEN DRAIN ACTIVE LOW VERSIONS ONLY
Vn - Vn-1 or V1 - VSS > VOV, where n = 2
Output Drive Voltage for COUT and
DOUT, Active Low
VOUT_AL
to 16, VDD = 58 V, IOH = 100 µA
measured into COUT, DOUT pin.
250
400
3
mV
mA
nA
Vn - Vn-1 or V1 - VSS > VOV, where n = 2
to 16, VDD = 58 V, OUT = VDD.
Measured into COUT, DOUT pin.
IOUT_AL_L OUT Source Current (during OV)
IOUT_AL_H OUT Sink Current (no OV)
0.3
Vn - Vn-1 and V1 - VSS < VOV, where n =
2 to 16, VDD = 58 V, OUT = VDD.
Measured out of COUT, DOUT pin.
100
(1) Open wire may not work properly if the cell voltage is below 2.8 V.
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7.6 Timing Requirements
Typical values stated where TA = 25°C and VDD = 58 V, MIN/MAX values stated where TA = –40°C to 85°C and
VDD = 5 V to 85 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25
0.5
1
MAX
UNIT
s
s
s
s
s
s
s
s
s
s
tOV_DELAY OV Delay Time
2
4
0.25
0.5
1
tUV_DELAY UV Delay Time
tOT_DELAY OT Delay Time
2
4
tOW_DELA
OW Delay Time
4
s
Y
tDELAY_AC
Delay Time Accuracy
For 0.25s, 0.5s, 1s delays
–128
128
ms
C
For all delays other than 0.25s, 0.5s, 1s
delays
tDELAY_DR Delay time drift across operating temp
–10%
10%
tCTM_DEL Fault Detection Delay Time during
See Customer Test Mode.
100
ms
Customer Test Mode
AY
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8 Detailed Description
8.1 Overview
The BQ77216 family of devices provides a range of voltage and temperature monitoring including overvoltage
(OVP), undervoltage (UVP), open wire (OW), and overtemperature (OT) protection for li- ion battery pack
systems. Each cell is monitored independently for overvoltage, undervoltage, and open-wire conditions. With the
addition of an external NTC thermistor, the device can detect overtemperature conditions. An internal delay timer
is initiated upon detection of an overvoltage, undervoltage, open-wire or overtemperature condition. Upon
expiration of the delay timer, the respective output is triggered into its active state (either high or low depending
on the configuration). The overvoltage triggers the COUT pin if a fault is detected, and undervoltage triggers the
DOUT pin if a fault is detected. If an undertemperature, overtemperature or open-wire fault is detected, then both
the DOUT and COUT are triggered.
For quicker production-line testing, the BQ77216 device provides a Customer Test Mode (CTM) with greatly
reduced delay time.
8.2 Functional Block Diagram
VDD
V16
Internal
Regulator
VSS
DOUT
Oscillator
Delay
Timer
V3
V2
Osc.
Monitor
VUV
VSS
+
œ
VSS
VOV
COUT
V1
VOT
Delay
Timer
VSS
VSS
TS
8.3 Feature Description
8.3.1 Voltage Fault Detection
In the BQ77216 device, each cell is monitored independently. Overvoltage is detected by comparing the actual
cell voltage to a protection voltage reference, VOV. If any cell voltage exceeds the programmed OV value, a timer
circuit is activated. When the timer expires, the COUT pin goes from inactive to active state. The timer is reset if
the cell voltage falls below the recovery threshold (VOV – VOV_HYS). Undervoltage is detected by comparing the
actual cell voltage to a protection voltage reference, VUV. If any cell voltage falls below the programmed UV
value, a timer circuit is activated. When the timer expires, the DOUT pin goes from inactive to active state. The
timer is reset if the cell voltage rises below the recovery threshold (VUV + VUV_HYS).
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VOV
VOV t VOV_HYS
tOV_DELAY
Active
Inacvtive
Figure 8-1. Timing for Overvoltage Sensing
VuV + VuV_HYS
VUV
tUV_DELAY
Active
Inacvtive
Figure 8-2. Timing for Undervoltage Sensing
8.3.2 Open Wire Fault Detection
In the BQ77216 device, each cell input is monitored independently to determine if the input is connected to a cell
or not by applying a 50-μA pull down current to ground that is activated for 128 μs every 128 ms. If the device
detects that Vn < Vn-1 – VOW V, then a timer is activated. When the timer expires, the COUT and DOUT pins go
from an inactive to active state. The timer is reset if the cell input rises above below the recovery threshold (VOW
+ VOW_HYS).
8.3.3 Temperature Fault Detection
In the BQ77216 device, the TS pin is ratiometrically monitored with an internal pull up resistance RNTC
.
Overtemperature is detected by evaluating the TS input voltage to determine the external resistance falls below
a protection resistance, ROT_EXT. If the resistance falls below the programmed OT value, a timer circuit is
activated. When the timer expires, the COUT and DOUT pins go from inactive to active state. The timer is reset
if the resistance rises above the recovery threshold (ROT + ROT_HYS). If external capacitance is added to the TS
pin, it needs to be within the spec limit shown in recommended operating conditions.
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Note
Texas Instruments does not recommend adding an external capacitor to the TS pin. The capacitance
on this pin will affect the TS measurement accuracy if greater than CTS.
8.3.4 Oscillator Health Check
The device can detect if the internal oscillator slows down below the fOSC_FAULT threshold. When this occurs then
the COUT and DOUT go from inactive to active state. If the oscillator returns to normal then the fault recovers.
8.3.5 Sense Positive Input for Vx
This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for
each input is required for noise filtering and stable voltage monitoring.
8.3.6 Output Drive, COUT and DOUT
These pins serve as the fault signal outputs, and may be ordered in either active HIGH with drive to 6V or active
LOW options configured through internal OTP.
The COUT and DOUT will respond per the following table when a fault is detected, if the specific fault is enabled.
Table 8-1. Fault Detection vs COUT and DOUT Action
FAULT Detected
Overvoltage
COUT
Active
Inactive
Active
Active
Active
DOUT
Inactive
Active
Active
Active
Active
Undervoltage
Open Wire
Over Temperature
Oscillator Health
8.3.7 The LATCH Function
The device can be enabled to latch the fault signal, which effectively disables the recovery functions of all fault
detections. The only way to recover from a fault state when the latch is enabled is a POR of the device.
8.3.8 Supply Input, VDD
This pin is the unregulated input power source for the IC. A series resistor is connected to limit the current, and a
capacitor is connected to ground for noise filtering.
8.4 Device Functional Modes
8.4.1 NORMAL Mode
When COUT and DOUT are inactive (no fault detected) the device operates in NORMAL mode and device is
monitoring for voltage, open wire and temperature faults.
The COUT and DOUT pins are inactive and if configured:
•
•
Active high is low.
Active low is being externally pulled up and is an open drain.
8.4.2 FAULT Mode
FAULT mode is entered if the COUT or DOUT pins are activated. The OUT pin will either pull high internally, if
configured as active high, or will be pulled low internally, if configured as active low. When COUT and DOUT are
deactivated the device returns to NORMAL mode.
8.4.3 Customer Test Mode
Customer Test Mode (CTM) helps to reduce test time for checking the delay timer parameter once the circuit is
implemented in the battery pack. To enter CTM, VDD should be set to at least VCTM higher than V16 (see Figure
8-3). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal operation. To
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exit Customer Test Mode, remove the VDD to a V16 voltage differential of 10 V so that the decrease in this value
automatically causes an exit.
CAUTION
Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into Customer
Test Mode. Also avoid exceeding Absolute Maximum Voltages for the individual cell voltages (VCn–
VCn-1) and (V1–VSS). Stressing the pins beyond the rated limits may cause permanent damage to
the device.
Figure 8-3 shows the timing for the Customer Test Mode.
VCTM
VOV
VOV t VOV_HYS
tCTM_DELAY
Active
Inacvtive
Figure 8-3. Timing for Customer Test Mode
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements.
QDSG
QCHG
PACK+
CVD
VDD
RIN
V16
CIN
DOUT
RIN
RIN
RIN
V3
V2
V1
RDOUT
CIN
CIN
CIN
GND
COUT
RCOUT
VSS
TS
RNTC
PACK-
GND
Figure 9-1. Application Configuration
9.1.1 Design Requirements
Changes to the ranges stated in Table 9-1 will impact the accuracy of the cell measurements. Figure 9-1 shows
each external component.
Table 9-1. Parameters
PARAMETER
Voltage monitor filter resistance
EXTERNAL COMPONENT
MIN
NOM
MAX
UNIT
RIN
900
1000
1100
Ω
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Table 9-1. Parameters (continued)
PARAMETER
EXTERNAL COMPONENT
MIN
0.01
100
NOM
MAX
0.1
1K
UNIT
µF
Voltage monitor filter capacitance
CIN
Supply voltage filter resistance
Supply voltage filter capacitance
RVD
CVD
300
0.1
Ω
0.05
1
µF
COUT and DOUT Open drain version pull-up
resistance to PACK+
80
100
120
kΩ
Note
The device is calibrated using an RIN value = 1 kΩ. Using a value other than this recommended value
changes the accuracy of the cell voltage measurements and VOV trigger level.
9.1.2 Detailed Design Procedure
Figure 9-2 shows the measurement for current consumption for the product for both VDD and Vx.
PACK+
ICC
VDD
V16
IIN
CELL16
DOUT
IIN
V3
CELL3
V2
IIN
CELL2
V1
IIN
COUT
CELL1
VSS
TS
RNTC
PACK-
GND
Figure 9-2. Configuration for IC Current Consumption Test
9.1.2.1 Cell Connection Sequence
The BQ77216 device can be connected to the array of cells in any order without damaging the device.
During cell attachment, the device could detect a fault if the cells are not connected within a fault detection delay
period. If this occurs, then COUT and/or DOUT could transition from inactive to active. Both COUT and DOUT
can be tied to VSS or VDD to prevent any change in output state during cell attach.
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9.2 Systems Example
In this application example, the choice of a FUSE or FETs is required on the COUT and DOUT pins configured
as an Active High drive to 6-V outputs.
PACK+
Fuse or
Back-to-Back FETs
CVD
VDD
V16
V15
RIN
V14
CIN
RIN
V13
CIN
DOUT
RIN
V3
RDOUT
CIN
RIN
GND
V2
CIN
RIN
V1
CIN
COUT
RCOUT
VSS
TS
RNTC
PACK-
GND
Figure 9-3. 14-Series Cell Configuration with Active High 6-V Option
When paring with BQ769x2 or BQ76940, the top cell must be used. For BQ77216 to drive the CHG and DSG
FETs, the active high 6-V option is preferred. Its COUT and DOUT are controlling two NCH FETs to jointly control
the CHG and DSG FETs with the monitor device.
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FUSE
PCHG
PDSG
PACK+
COUT
DOUT
CAN
TRANSCEIVER
5V
COMM TO
SYSTEM
DOUT
V16
V15
V14
V13
V12
V11
V10
V9
+
+
+
+
COMM
VC15
VC14
VC13
VC12
VC11
VC10
VC9
REGIN
REG1
3.3V
VDD
REG2
GPIO
RST_SHUT
DDSG
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
DSG Logic Out
CHG Logic Out
:
:
:
:
:
:
:
:
MCU
DCHG
DOUT
COUT
COUT
GPIO
GPIO
DFETOFF
CFETOFF
HDQ
VC8
V8
VC7
V7
SDA
SCL
INT
SDA
VC6
V6
SCL
VC5
V5
+
+
ALERT
VC4
V4
V3
GND
V2
V1
VSS
TS
TS1
+
TS2
TS1
+
+
TS3
PACK-
Figure 9-4. BQ77216 with BQ76952
10 Power Supply Recommendations
The maximum power of this device is 85 V on VDD.
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11 Layout
11.1 Layout Guidelines
•
•
Ensure the RC filters for the Vn and VDD pins are placed as close as possible to the target terminal.
The VSS pin should be routed to the CELL– terminal.
11.2 Layout Example
Place the RC filters close to the device
terminals
Power Trace
VDD
V16
Pack +
COUT
VSS
COUT
Pack -
VCELL16
V4
V3
V1
V2
VCELL4
VCELL3
VCELL2
VCELL1
Figure 11-1. Example Layout
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12 Device and Documentation Support
12.1 Trademarks
All other trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.3 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7721600PWR
BQ7721602PWR
PBQ7721600PWR
PREVIEW
PREVIEW
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
24
24
24
2000
2000
2000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
PBQ7721602PWR
ACTIVE
TSSOP
PW
24
2000
TBD
Call TI
Call TI
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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