BQ7790509PWR [TI]
3 至 5 节串联锂离子和锂磷酸盐超低功耗堆叠式电池保护器 | PW | 20 | -40 to 85;
| 型号： | BQ7790509PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 至 5 节串联锂离子和锂磷酸盐超低功耗堆叠式电池保护器 | PW | 20 | -40 to 85 电池 光电二极管 |
| 文件： | 总49页 (文件大小：2241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
BQ77904、BQ77905 3-20 节串联超低功耗电压、电流、温度和断线可堆叠锂离
子电池保护器
此器件可通过集成的独立 CHG 和 DSG 低侧 NMOS
FET 驱动器实现电池组保护，这些驱动器可通过两个
控制引脚禁用。这些控制引脚还能够以简单经济的方式
1 特性
• 正常模式：6µA（bQ77904 和bQ77905）
• 整套电压、电流和温度保护功能
• 电池节数可扩展，支持从3 节串联到20 节或更多
节数串联
为更多节串联电池（6 节以上）提供电池保护解决方
案。为此，只需将上级器件的 CHG 和 DSG 输出级联
到下级器件控制引脚。为减少元件数量，所有保护故障
均使用内部延迟计时器。
• 电压保护（精度为±10mV）
– 过压：3V 至4.575V
– 欠压：1.2V 至3V
• 开路电池和断线检测(OW)
• 电流保护
器件信息
器件型号(1)
BQ77904
BQ77905
封装尺寸（标称值）
封装
TSSOP (20)
6.50mm × 4.40mm
– 过流放电1：-10mV 至-85mV
– 过流放电2：-20mV 至+170mV
– 短路放电：-40mV 至+340mV
– 整个温度范围内，电压≤20mV 时的精度为
±20%，电压> 20mV 时的精度为±30%
• 温度保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
PACK+
VDD
VTB
VC5
TS
– 过热充电：45°C 至50°C
– 过热放电：65°C 至70°C
– 欠温充电：-5°C 至0°C
bq77094/5
LD
Vss
SRP SRN
DSG
CHGU
CTRC
– 低温放电：-20°C 或-10°C
• 附加特性
CTRD
– 独立充电(CHG) 和放电(DSG) FET 驱动器
– 每节电池输入的绝对最大额定电压为36V
– 内置自检功能，实现高可靠性
• 关断模式：0.5µA（最大值）
• 提供功能安全
VDD
VTB
TS
VC5
bq77094/5
LD
Vss
SRP
SRN
DSG
CHG
– 可帮助进行功能安全系统设计的文档
PACK-
2 应用
Copyright © 2017, Texas Instruments Incorporated
Copyright © 2017, Texas Instruments Incorporated
• 电动工具、园艺工具
• 启停电池组
简化版原理图
• 铅酸(PbA) 备用电池
• 轻型电动车辆
• 储能系统、不间断电源(UPS)
• 10.8V 至72V 电池组
3 说明
BQ77904 和 BQ77905 器件为低功耗电池组保护器，
无需微控制器 (MCU) 控制即可实现一系列电压、电流
和温度保护。该器件的可堆叠接口可进行简单扩展，支
持从 3 节串联到 20 节或更多节数串联的电池应用。保
护阈值和延迟均为出厂编程设定，有多种配置可供选
用。为提升灵活性，还提供了单独的过热和欠温放电阈
值（OTD 和 UTD）以及过热和欠温充电阈值（OTC
和UTC）。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCM3
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................26
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 32
9.3 System Examples..................................................... 36
10 Power Supply Recommendations..............................36
11 Layout...........................................................................37
11.1 Layout Guidelines................................................... 37
11.2 Layout Example...................................................... 37
12 Device and Documentation Support..........................38
12.1 Documentation Support.......................................... 38
12.2 Receiving Notification of Documentation Updates..38
12.3 Support Resources................................................. 38
12.4 Trademarks.............................................................38
12.5 Electrostatic Discharge Caution..............................38
12.6 Glossary..................................................................38
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................4
6 Pin Configuration and Functions...................................5
Pin Functions.................................................................... 5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements................................................10
7.7 Typical Characteristics.............................................. 11
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
Information.................................................................... 38
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision J (April 2020) to Revision K (July 2020)
Page
• Add the BQ7790521 evice in the Device Comparison table...............................................................................4
Changes from Revision I (December 2019) to Revision J (February 2020)
Page
• Changed the BQ7790518 device to a catalog device in the Device Comparison table......................................4
Changes from Revision H (September 2018) to Revision I (December 2019)
Page
• Added the BQ7790522 device to the Device Comparison table.........................................................................4
Changes from Revision G (September 2017) to Revision H (September 2018)
Page
• 为简洁明了，更改了整个数据表中的一些措辞....................................................................................................1
• Added the BQ7790518 device to the BQ77905 Device Comparison table........................................................ 4
Changes from Revision F (May 2017) to Revision G (September 2017)
Page
• Added BQ7790511 and BQ7790512 to the Device Comparison table...............................................................4
Changes from Revision E (March 2017) to Revision F (May 2017)
Page
• Changed the BQ7790400 setting: OV delay from 1 s to 2 s. UV from 2800 mV to 2200 mV, UV delay from 1 s
to 2 s, UV Hyst from 200 to 400 mV, UV load recovery from N to Y. OCD2 from 80 mV to 60 mV, OCD2 delay
from 700 to 350 ms. SCD from 160 mV to 100 mV.............................................................................................4
• Added BQ7790508 and BQ7790509 to the Device Comparison table...............................................................4
Changes from Revision D (March 2017) to Revision E (March 2017)
Page
• Added BQ7790505 to the Device Comparison table..........................................................................................4
• Changed UTC(REC) at 5°C typ from 68.8 to 69.73 %VTB. Changed UTC(REC) at 10°C typ from 64.23 to
65.52 %VTB........................................................................................................................................................7
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Changes from Revision C (February 2017) to Revision D (March 2017)
Page
• Changed VOTD, VOTD(REC), VOTC, VOTC(REC), VUTD, VUTD(REC), VUTC, VUTC(REC) MIN and MAX
specification values.............................................................................................................................................7
Changes from Revision B (November 2016) to Revision C (February 2017)
Page
• Added values in the Thermal Information table to align with JEDEC standards.................................................7
Changes from Revision A (June 2016) to Revision B (November 2016)
Page
• 更改了特性中所列项的顺序................................................................................................................................1
• 表5-1 and 表5-2, Changed OTC To: UTC in last column under Temperature. Changed BQ7790400 and
BQ7790503 to Production Data. Updated the BQ7790503 configuration ......................................................... 4
• Changed pin number from 16-pin to 20-pin .......................................................................................................5
• Corrected max value on the UTD at –20°C spec..............................................................................................7
• Changed comparator flowcharts with new flowcharts.......................................................................................14
• Corrected CTRC and CTRD delay time entries................................................................................................18
Changes from Revision * (June 2016) to Revision A (June 2016)
Page
• 将器件从“产品预发布”更改为“量产”...........................................................................................................1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
5 Device Comparison
NUMBER OF
TYPICAL NORMAL
MODE CURRENT (µA)
DEVICE
CELLS
PROTECTIONS
PACKAGE
BQ77904
BQ77905
3, 4
OV, UV, OW, OTD, OTC, UTD, UTC, OCD1,
OCD2, SCD, CTRC, CTRD
6
20-TSSOP
3, 4, 5
Unless otherwise specified, the devices in 表5-1 and 表5-2 come, by default, with the state comparator enabled
with a 2-mV threshold. Filtered fault detection is used by default. Contact Texas Instruments for new
configuration options or devices in preview.
表5-1. BQ77904 Device Comparison
OV
Delay(s)
UV
OW
OCD1
Threshold
Part Number
Thresh
(mV)
Load Removal
Recovery (Y/N)
Threshold (mV)
Hyst (mV)
Delay(s)
Hyst (mV)
400
Current (nA)
0 (disable)
Delay (ms)
(mV)
BQ7790400
4225
2
100
2200
2
Y
40
1420
OCD2
Delay (ms)
350
SCD
Threshold (mV)
100
Current Fault Recovery
Method
Temperature (°C)(1)
Part Number
Delay (s)
OTD
OTC
UTD
UTC
BQ7790400
0
Load Removal
70
50
–20
–5
(1) These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. The circuit is based on the 103AT NTC thermistor connected to TS and VSS, and a 10-kΩresistor connected to VTB and
TS. Actual thresholds must be determined in mV. Refers to the overtemperature and undertemperature mV threshold in the Electrical
Characteristics table.
表5-2. BQ77905 Device Comparison
OV
UV
OW
OCD1
Load
Removal
Recovery
(Y/N)
Part Number
Threshold
(mV)
Thresh
(mV)
Threshold
(mV)
Delay(s)
Hyst (mV)
Delay(s)
Hyst (mV)
Current (nA)
Delay (ms)
BQ7790500
4200
4250
4200
4250
3900
4250
4250
4175
4250
3700
4250
0.5
1
100
200
100
200
200
100
200
100
100
200
100
2600
2700
2700
2700
2000
2500
2700
2800
2750
2500
2800
1
1
2
1
1
1
1
1
1
1
1
400
200
400
200
400
400
200
400
200
200
200
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
100
100
100
0
30
85
80
60
50
50
50
75
70
70
80
1420
700
1420
10
BQ7790502
BQ7790503
BQ7790505
BQ7790508
BQ7790509
BQ7790511
BQ7790512
BQ7790518
BQ7790521
BQ7790522
1
1
1
100
100
100
100
100
100
100
700
700
350
1420
180
180
700
1
1
1
1
1
1
OCD2
SCD
Current Fault Recovery
Temperature (°C)(1)
Threshold
(mV)
Part Number
Delay (ms)
Threshold (mV)
Delay (s)
Method
OTD
70
70
70
65
70
70
65
65
70
70
70
OTC
50
50
50
45
50
50
45
45
50
50
50
UTD
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
UTC
BQ7790500
BQ7790502
BQ7790503
BQ7790505
BQ7790508
BQ7790509
BQ7790511
BQ7790512
BQ7790518
BQ7790521
BQ7790522
50
700
350
350
5
120
240
320
100
200
200
280
300
300
320
300
1
Load Removal + Delay
Load Removal
0
120
160
80
–5
–5
0
—
—
9
Load Removal
Load Removal + Delay
Load Removal + Delay
Load Removal + Delay
Load Removal
100
100
120
150
140
140
100
90
1
–5
–5
0
90
1
90
—
1
350
20
Load Removal + Delay
Load Removal
0
1
0
20
1
Load Removal
0
350
1
Load Removal
–5
(1) These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. Circuit is based on 103AT NTC thermistor connected to TS and VSS, and a 10-kΩresistor connected to VTB and TS. Actual
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
thresholds must be determined in mV. Refers to the overtemperature and undertemperature mV threshold in the Electrical
Characteristics table.
6 Pin Configuration and Functions
VDD
AVDD
VC5
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DVSS
CTRD
CTRC
CCFG
VTB
VC4
VC3
VC2
TS
VC1
LD
AVSS
SRP
SRN
CHG
CHGU
DSG
Not to scale
图6-1. PW Package 20-Pin TSSOP Top View
Pin Functions
PIN
NAME
I/O(1)
DESCRIPTION
NO.
2
AVDD
O
P
I
Analog supply (only connect to a capacitor)
Analog ground
AVSS
8
CCFG
17
Cell in series-configuration input
CHG FET driver. Use on a single device or on the bottom device of a stack
configuration.
CHG
13
12
O
O
CHG FET signal. Use for the upper device of a stack configuration to feed the CHG
signal to the CTRC pin of the lower device.
CHGU
CTRC
CTRD
DSG
DVSS
LD
18
19
11
20
14
10
9
I
I
CHG and DSG override inputs
O
P
I
DSG FET driver
Digital ground
PACK–load removal detection
SRN
SRP
I
Current sense input connecting to the PACK–side of sense resistor
Current sense input connecting to the battery side of sense resistor
I
Thermistor measurement input. Connect a 10-kΩresistor to AVSS pin if the function is
not used.
TS
15
I
VC1
VC2
VC3
VC4
VC5
VDD
VTB
7
6
I
I
Cell voltage sense inputs
5
I
4
I
3
I
Cell voltage sense inputs (Pin 3 must be connected to Pin 4 on the BQ77904 device.)
1
P
O
Supply voltage
16
Thermistor bias output
(1) I = Input, O = Output, P = Power
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). All values are referenced to VSS unless otherwise
noted.(1)
MIN
–0.3
–30
–0.3
–0.3
–30
–0.3
MAX
36
20
3.6
20
20
3.6
500
1
UNIT
VDD, VC5, VC4, VC3, VC2, VC1, CCFG, CTRD, CTRC
V
VI
Input voltage
LD
V
SRN, SRP, TS, AVDD, CCFG
V
DSG, CHGU
CHG
V
VO
Output voltage range
V
VTB
V
II
Input current
Input current
Output current
Output current
LD, CHG
CHGU, DSG
CHG
µA
mA
mA
mA
°C
II
IO
IO
1
CHGU, DSG
1
Storage temperature, Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VBAT
Supply voltage
VDD
3
25
5
V
VC5-VC4, VC4-VC3, VC3-VC2, VC2-VC1,
VC1-VSS
0
CTRD, CTRC
CCFG
0
(VDD + 5)
0
–0.2
0
AVDD
0.8
16
VI
Input voltage
V
SRN, SRP
LD
TS
0
VTB
16
CHG, CHGU, DSG
VTB, AVDD
0
VO
TA
Output voltage
V
0
3
Operating free-range temperature
85
°C
–40
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
7.4 Thermal Information
bq77904
bq77905
THERMAL METRIC(1)
UNITS
PW (TSSOP)
20 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
98.4
37
°C/W
°C/W
°C/W
°C/W
°C/W
49.3
2.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
48.7
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Typical values stated at TA = 25°C and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA = –
40°C to +85°C and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
V(POR)
POR threshold
VDD rising, 0 to 6 V
4
3.25
3.25
V
V
V
V(SHUT)
Shutdown threshold
AVDD voltage
VDD falling, 6 to 0 V
C(VDD) = 1 µF
2
V(AVDD)
2.1
2.5
SUPPLY AND LEAKAGE CURRENT
NORMAL mode current
(bq77904/bq77905)
Cell1 through Cell5 = 4 V,
VDD = 20 V (bq77905)
ICC
6
8
9
µA
I(CFAULT)
IOFF
Fault condition current
State comparator on
12
µA
µA
SHUTDOWN mode current VDD < VSHUT
0.5
Input leakage current at VCx All cell voltages = 4 V,
ILKG(OW_DIS)
ILKG(100nA)
ILKG(200nA)
ILKG(400nA)
0
110
210
425
100
175
315
640
nA
nA
nA
nA
–100
30
pins
Open-wire disable configuration
Open-wire sink current at
VCx pins
All cell voltages = 4 V,
100-nA configuration
Open-wire sink current at
VCx pins
All cell voltages = 4 V,
200-nA configuration
95
Open-wire sink current at
VCx pins
All cell voltages = 4 V,
400-nA configuration
220
PROTECTION ACCURACIES
Overvoltage programmable
threshold range
VOV
VUV
3000
1200
4575
3000
mV
mV
Undervoltage programmable
threshold range
TA = 25°C, OV detection accuracy
TA = 25°C, UV detection accuracy
TA = 0 to 60°C
10
18
26
40
mV
mV
mV
mV
–10
–18
–28
–40
V(VA)
OV, UV, detection accuracy
TA = –40 to 85°C
OV hysteresis
programmable threshold
range
VHYS(OV)
VHYS(UV)
VOTD
0
400
800
mV
mV
UV hysteresis programmable
threshold range
200
Overtemperature in
discharge programmable
Threshold for 65°C(1)
Threshold for 70°C (1)
19.71%
17.36%
20.56%
18.22%
21.86%
19.51%
V
VTB
threshold (ratio of VTB
)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Typical values stated at TA = 25°C and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA = –
40°C to +85°C and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Recovery threshold at 55°C for
when VOTD is at 65°C(1)
25.24%
26.12%
27.44%
VTB
Overtemperature in
discharge recovery (ratio of
VTB
VOTD(REC)
Recovery threshold at 60°C for
when VOTD is at 70°C(1)
)
22.12%
23.2%
24.24%
VTB
Overtemperature in charge
programmable threshold
Threshold for 45°C(1)
32.14%
29.15%
32.94%
29.38%
34.54%
31.45%
VTB
VTB
VOTC
Threshold for 50°C(1)
(ratio of VTB
)
Recovery threshold at 35°C when
VOTD is at 45°C(1)
38.63%
36.18%
40.97%
36.82%
40.99%
38.47%
VTB
VTB
Overtemperature in charge
VOTC(REC)
recovery (ratio of VTB
)
Recovery threshold at 40°C when
VOTD is at 50°C(1)
Threshold for –20°C(1)
Threshold for –10°C(1)
Undertemperature in
discharge programmable
threshold (ratio of VTB
86.41%
80.04%
87.14%
80.94%
89.72%
83.10%
VTB
VTB
VUTD
)
Recovery threshold at –10°C
when VUTD is at –20°C(1)
80.04%
71.70%
80.94%
73.18%
83.10%
74.86%
VTB
VTB
Undertemperature in
VUTD(REC)
discharge recovery (ratio of
VTB
Recovery threshold at 0°C when
VUTD is at –10°C(1)
)
Threshold for –5°C(1)
Undertemperature in charge
programmable threshold
75.06%
71.70%
77.22%
73.18%
78.32%
74.86%
VTB
VTB
VUTC
Threshold for 0°C(1)
(ratio of VTB
)
Recovery threshold at 5°C when
68.80%
64.67%
69.73%
65.52%
71.71%
67.46%
VTB
VTB
VUTC is at –5°C(1)
Undertemperature in Charge
Recovery (ratio of VTB
VUTC(REC)
)
Recovery threshold at 10°C when
VUTC is at 0°C(1)
Overcurrent discharge 1
programmable threshold
range,
VOCD1
mV
–85
–20
–10
(VSRP –VSRN
)
Overcurrent discharge 2
programmable threshold
range,
VOCD2
mV
mV
–170
(VSRP –VSRN
)
Short circuit discharge programmable threshold range, (VSRP
–
VSCD
–40
–30%
–20%
–340
30%
VSRN
)
OCD1 detection accuracy at
lower thresholds
VCCAL
VCCAH
VOCD1 > –20 mV
OCD1 ≤–20 mV; all OCD2 and
OCD1, OCD2, SCD
detection accuracy
V
20%
SCD threshold ranges
Open-wire fault voltage
threshold at VCx per cell
with respect to VCx-1
Voltage falling on VCx, 3.6 V to
0 V
VOW
450
500
100
550
mV
mV
Voltage rising on VCx, 0 V to
3.6 V
VOW(HYS)
Hysteresis for open wire fault
CHARGE AND DISCHARGE FET DRIVERS
11
12
14
VDD
0.5
V
V
V
VDD ≥12 V, CL = 10 nF
V(FETON)
CHG/CHGU/DSG on
CHG/CHGU/DSG off
VDD < 12 V, CL = 10 nF
VDD –1
V(FETOFF)
No load when CHG/CHGU/DSG is
off.
CHG off for > tCHGPDN and pin held
at 2 V
R(CHGOFF)
CHG off resistance
0.5
10
kΩ
R(DSGOFF)
CHGU/DSG off resistance
CHG clamp current
CHGU/DSG off and pin held at 2 V
CHG off and pin held at 18 V
16
Ω
ICHG(CLAMP)
450
µA
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Typical values stated at TA = 25°C and VDD = 16 V (bq77904) or 20 V (bq77905). MIN and MAX values stated with TA = –
40°C to +85°C and VDD = 3 to 20 V (bq77904) or VDD = 3 to 25 V (bq77905) unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
18
50
2
MAX
20.5
150
75
UNIT
V
VCHG(CLAMP)
tCHGON
CHG clamp voltage
ICHG(CLAMP) = 300 µA
16
CHG on rise time
CL = 10 nF, 10% to 90%
CL = 10 nF, 10% to 90%
CL = 10 nF, 90% to 10%
CL = 10 nF, 90% to 10%
µs
tDSGON
CHGU/DSG on rise time
CHG off fall time
µs
tCHGOFF
tDSGOFF
15
5
30
µs
CHGU/DSG off fall time
15
µs
CTRC AND CTRD CONTROL
With respect to VSS. Enabled <
MAX
VCTR1
Enable FET driver (VSS)
0.6
V
VCTR2
Enable FET driver (Stacked) Enabled > MIN
VDD + 2.2
2.04
V
V
VCTR(DIS)
Disable FET driver
Disabled between MIN and MAX
ICTR = 600 nA
VDD + 0.7
VDD + 5
CTRC and CTRD clamp
voltage
VCTR(MAXV)
tCTRDEG_ON)
tCTRDEG_OFF
VDD + 2.8
VDD + 4
V
CTRC and CTRD deglitch
for ON signal
(2)
(2)
7
7
ms
ms
CTRC and CTRD deglitch
for OFF signal
CURRENT STATE COMPARATOR
Discharge qualification
V(STATE_D1)
Measured at SRP-SRN
Measured at SRP-SRN
mV
mV
ms
–3
–2
–1
3
threshold1
Charge qualification
threshold1
V(STATE_C1)
1
2
State detection qualification
time
(2)
tSTATE
1.2
LOAD REMOVAL DETECTION
VLD(CLAMP)
ILD(CLAMP)
VLDT
LD clamp voltage
I(LDCLAMP) = 300 µA
16
18
20.5
450
V
µA
V
LD clamp current
LD threshold
V(LDCLAMP) = 18 V
Load removed < when VLDT
1.25
160
1
1.3
250
1.5
1.35
LD input resistance when
enabled
RLD(INT)
Measured to VSS
375
2.3
kΩ
tLD_DEG
LD detection deglitch
ms
CCFG PIN
CCFG threshold low (ratio of
V(CCFGL)
V(CCFGH)
V(CCFGHZ)
3-cell configuration
4-cell configuration
10%
100%
45%
V
V
VAVDD
CCFG threshold high (ratio
of VAVDD
)
65%
25%
)
CFG threshold high-Z (ratio 5-cell configuration, CCFG floating,
33%
6
V
of VAVDD
CCFG deglitch
CUSTOMER TEST MODE (CTM)
)
internally biased
(2)
tCCFG_DEG
ms
Customer test mode entry
voltage at VDD
V(CTM)
VDD > VC5 + V(CTM), TA = 25°C
VDD > VC5 + V(CTM), TA = 25°C
TA = 25°C
8.5
50
10
V
Delay time to enter and exit
Customer Test Mode
(3)
(3)
tCTM_ENTRY
tCTM_DELAY
ms
ms
Delay time of faults while in
Customer Test Mode
200
100
Fault recovery time of
OCD1, OCD2, and SCD
faults while in Customer Test
Mode
(3)
tCTM_OC_REC
1 s and 8 s options, TA = 25°C
ms
(1) Based on a 10-KΩpull-up and 103AT thermistor
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
(2) Not production tested parameters. Specified by design
(3) The device is in a no fault state prior to entering Customer Test Mode.
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
PROTECTION DELAYS (2)
0.5-s delay option
0.4
0.8
1.8
4
0.5
1
0.8
1.4
2.7
5.2
1.5
2.7
5.5
10.2
5.3
1-s delay option
tOVn_DELAY
Overvoltage detection delay time
s
2-s delay option
4.5-s delay option
1-s delay option
2-s delay option
4.5-s delay option
9-s delay option
2
4.5
1
0.8
1.8
4
2
tUVn_DELAY
Undervoltage detection delay time
Open-wire detection delay time
s
4.5
9
8
tOWn_DELAY
tOTC_DELAY
3.6
4.5
s
s
Overtemperature charge detection
delay time
3.6
3.6
3.6
3.6
4.5
4.5
4.5
4.5
5.3
5.3
5.3
5.3
Undertemperature charge detection
delay time
tUTC_DELAY
tOTD_DELAY
tUTD_DELAY
s
s
s
Overtemperature discharge
detection delay time
Undertemperature discharge
detection delay time
10-ms delay option
20-ms delay option
45-ms delay option
90-ms delay option
180-ms delay option
350-ms delay option
700-ms delay option
1420-ms delay option
5-ms delay option
10-ms delay option
20-ms delay option
45-ms delay option
90-ms delay option
180-ms delay option
350-ms delay option
700-ms delay option
360-µs delay option
1-s option
8
17
10
20
15
26
36
45
52
78
90
105
205
405
825
1620
8
tOCD1_DELAY
Overcurrent 1 detection delay time
ms
155
320
640
1290
4
180
350
700
1420
5
8
10
15
17
20
26
36
45
52
tOCD2_DELAY
Overcurrent 2 detection delay time
Short-circuit detection delay time
ms
78
90
105
205
405
825
610
1.4
10.2
155
320
640
220
0.8
8
180
350
700
400
1
tSCD_RELAY
tCD_REC
µs
s
Overcurrent 1, Overcurrent 2, and
Short-circuit recovery delay time
9-s option
9
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
7.7 Typical Characteristics
7.5
7
0.25
0.2
6.5
6
0.15
0.1
5.5
5
0.05
4.5
4
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (èC)
D002
Temperature (èC)
D001
图7-2. Shutdown Current
图7-1. NORMAL Mode Current
15
10
5
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (èC)
Temperature (èC)
D003
D004
图7-3. OV Error at 4.25-V Threshold
图7-4. UV Error at 2.8-V Threshold
0.1
0.05
0
0.2
2.5
2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
-0.05
-0.1
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
1.5
1
-0.15
-0.2
-0.25
-0.3
0.5
0
Error (in mV)
Error (in %)
Error (in mV)
Error (in %)
-0.35
0
20
40
60
80
0
20
40
60
80
œ40
œ20
œ40
œ20
Temperature (ºC)
Temperature (ºC)
C001
C002
图7-5. OCD1 Error at 40-mV Threshold
图7-6. OCD2 Error at 60-mV Threshold
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
2.5
2
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
1
0.5
0
Error (in mV)
Error (in %)
0
20
40
60
80
œ40
œ20
Temperature (ºC)
C003
图7-7. SCD Error at 160-mV Threshold
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The BQ77904 and BQ77905 families are full-feature stackable primary protectors for Li-ion/Li-Polymer batteries.
The devices implement a suite of protections, including:
• Cell voltage: overvoltage, undervoltage
• Current: Overcurrent discharge 1 and 2, short circuit discharge
• Temperature: overtemperature and undertemperature in charge and discharge
• PCB: cell open-wire connection
• FET body diode protection
Protection thresholds and delays are factory-programmed and available in a variety of configurations.
The BQ77904 supports 3-series-to–4-series cell configuration and BQ77905 supports 3-series-to–5-series cell
configuration. Up to four devices can be stacked to support ≥6-series cell configurations, providing protections
up to 20-series cell configurations.
The device has built-in CHG and DSG drivers for low-side N-channel FET protection, which automatically open
up the CHG and/or DSG FETs after protection delay time when a fault is detected. A set of CHG/DSG overrides
is provided to allow disabling of CHG and/or DSG driver externally. Although the host system can use this
function to disable the FETs' control, the main use of these pins is to channel down the FET control signal from
the upper device to the lower device in a cascading configuration in ≥6-series battery packs.
8.1.1 Device Functionality Summary
In this and subsequent sections, a number of abbreviations are used to identify specific fault conditions. The
fault descriptor abbreviations and their meanings are defined in 表8-1.
表8-1. Device Functionality Summary
FAULT DESCRIPTOR
FAULT DETECTION THRESHOLD and DELAY OPTIONS
FAULT RECOVERY METHOD and SETTING OPTIONS
OV
UV
Overvoltage
3 V to 4.575 V (25-mV step)
0.5, 1, 2, 4.5 s
1, 2, 4.5, 9 s
Hysteresis
0, 100, 200, 400 mV
1.2 V to 3 V
(100-mV step for < 2.5 V,
50-mV step for ≥2.5 V)
Hysteresis OR
Hysteresis + Load Removal
Undervoltage
200, 400 mV
Open wire (cell to pcb
disconnection)
0 (disabled), 100, 200, or 400
nA
OW
4.5 s
4.5 s
4.5 s
4.5 s
4.5s
Restore bad VCx to pcb connection
Hysteresis
VCx > VOW
10°C
Overtemperature during
discharge
OTD(1)
OTC(1)
UTD(1)
UTC (1)
OCD1
65°C or 70°C
45°C or 50°C
Overtemperature during
charge
Hysteresis
10°C
Undertemperature during
discharge
Hysteresis
10°C
–20°C or –10°C
–5°C or 0°C
Undertemperature during
charge
Hysteresis
10°C
Overcurrent1 during
discharge
10, 20, 45, 90, 180, 350, 700,
1420 ms
10 mV to 85 mV (5-mV step)
Delay OR
Delay + Load Removal OR
Load Removal
Overcurrent1 during
discharge
5, 10, 20, 45, 90, 180, 350, 700
ms
1 s or 9 s
OCD2
SCD
20 mV to 170 mV (10-mV step)
40 mV to 340 mV (20-mV step)
Short circuit discharge
360 µs
Disable via external control or
via CHGU signal from the upper
device in the stack
Enable via external control or via CHGU
signal from the upper device in the stack
configuration.
CTRC
CTRD
CHG signal override control
tCTRDEG_ON
tCTRDEG_OFF
configuration.
Disable via external control or
via DSG signal from the upper
device in the stack
Enable via external control or via DSG
signal from the upper device in the stack
configuration.
DSG signal override control
tCTRDEG_ON
tCTRDEG_OFF
configuration.
(1) These thresholds are target based on temperature, but they are dependent on external components that could vary based on customer
selection. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩresistor connected to VTB and TS.
Actual thresholds must be determined in mV. Refers to the overtemperature and undertemperature mV threshold in the Electrical
Characteristics table.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
8.2 Functional Block Diagram
VDD
AVDD
CCFG
VDIG
REGULATOR
AND
VTB
TS
BG
REFERENCE
BIAS
CONFIG
LOGIC
POR
SHUTDOWN
VC5
VC4
EEPROM
COMPARE
1
VC3
MUX
CTRC
CTRD
VC2
VC1
STACK
INTERFACE
CONTROL
LOGIC
OPEN
WIRE
CHG
CHG
DRIVER
CHGU
MUX
COMPARE
DSG
DRIVER
DSG
LD
2
SRP
SRN
LOAD
DETECTION
STATE
COMPARE
CLOCK
and
WDT
AVSS
DVSS
Copyright © 2018, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Protection Summary
The BQ77904 and BQ77905 have two comparators. Both are time multiplexed to detect all protection fault
conditions. Each of the comparators runs on a time-multiplexed schedule and cycles through the assigned
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
protection-fault checks. Comparator 1 checks for OV, UV, and OW protection faults. Comparator 2 checks for
OCD1, OCD2, SCD, OTC, OTD, UTC, and UTD protection faults. For OV, UV, and OW protection faults, every
cell is checked individually in round-robin fashion, starting with cell 1 and ending with the highest-selected cell.
The number of the highest cell is configured using the CCFG pin.
Devices can be ordered with various timing and hysteresis settings. See the 节 5 section for a summary of
options available per device type.
Check OV VCELL1
Check OV VCELL2
n = the highest call
configured by CCFG pin
Check OV VCELLn
NO
NO
Time to check
UV?
Time to check
OW?
YES
YES
x starts
from 1
at POR
Check OW VCELLx,
x = x +1
Check UV VCELL1
Check UV VCELL2
Check UV VCELLn
Reset x = 1, if x >
the highest cell
configured via
CCFG pin
Turn off Comp1 until
next cycle start
图8-1. Comparator 1 Flowchart
Check SCD
NO
NO
NO
NO
Time to check
OCD1?
Time to check
OCD2?
Time to check
OT?
Time to check
UT?
YES
YES
Check UT
YES
YES
Check
OCD1
Check
OCD2
Check OT
图8-2. Comparator 2 Flowchart
8.3.2 Fault Operation
8.3.2.1 Operation in OV
An OV fault detection is when at least one of the cell voltages is measured above the OV threshold, VOV. The
CHG pin is turned off if the fault condition lasts for a duration of OV Delay, tOVn_DELAY. The OV fault recovers
when the voltage of the cell in fault is below the (OV threshold – OV hysteresis, VHYS_OV) for a time of OV
Delay.
The BQ77904 and BQ77905 assume OV fault after device reset.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
8.3.2.2 Operation in UV
An UV fault detection is when at least one of the cell voltages is measured below the UV threshold, VUV. The
DSG is turned off if the fault condition lasts for a duration of UV Delay, tUVn_DELAY. The UV fault recovers when:
• The cell voltage in fault is above the (UV threshold + UV hysteresis, VHYS_UV) for a time of UV Delay only OR
• The cell voltage in fault is above the (UV threshold + UV hysteresis) for a time of UV Delay AND load removal
is detected.
If load removal is enabled as part of the UV recovery requirement, the CHG FET RGS value should change to
around 3 MΩ. Refer to the 节 9.1.1.4 section of this document for more detail. This requirement applies to load
removal enabled for UV recovery only. Therefore, if load removal is selected for current fault recovery, but not for
the UV recovery, a lower CHG FET RGS value (typical of 1MΩ) can be used to reduce the CHG FET turn off
time.
To minimize supply current, the device disables all overcurrent detection blocks any time the DSG FET is turned
off (due to a fault or CTRD being driven to the DISABLED state). Upon recovery from a fault or when CTRD is no
longer externally driven, all overcurrent detection blocks reactivate before the DSG FET turns back on.
8.3.2.3 Operation in OW
An OW fault detection is when at least one of the cell voltages is measured below the OW threshold, VOW. Both
CHG and DSG are turned off if the fault condition lasts for a duration of OW Delay, tOWn_DELAY. The OW fault
recovers when the cell voltage in fault is above the OW threshold + OW hysteresis, VOW_HYS for a time of OW
Delay.
The tOWn_DELAY time starts when voltage at a given cell is detected below the VOW threshold and is not from the
time that the actual event of open wire occurs. During an open-wire event, it is common that the device detects
an undervoltage and/or overvoltage fault before detecting an open-wire fault. This may happen due to the
differences in fault thresholds, fault delays, and the VCx pin filter capacitor values. To ensure both CHG and
DSG return to normal operation mode, the OW, OV, and UV faults recovery conditions must be met.
8.3.2.4 Operation in OCD1
An OCD1 fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN),
is measured below the OCD1 voltage threshold, VOCD1. Both CHG and DSG are turned off if the fault condition
lasts for a duration of OCD1 Delay, tOCD1_DELAY
.
The OCD1 fault recovers when:
• Load removal is detected only, VLD < VLDT OR
• Overcurrent Recovery Timer, tCD_REC, expiration only OR
• Overcurrent Recovery Timer expiration and load removal are detected.
8.3.2.5 Operation in OCD2
An OCD2 fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN),
is measured below the OCD2 voltage threshold, VOCD2. Both CHG and DSG are turned off if the fault condition
lasts for a duration of OCD2 Delay, tOCD2_DELAY
.
The OCD2 fault recovers when:
• Load removal detected only, VLD < VLDT OR
• Overcurrent Recovery Timer, tCD_REC, expiration only OR
• Overcurrent Recovery Timer expiration and load removal are detected.
8.3.2.6 Operation in SCD
An SCD fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP-VSRN),
is measured below the SCD voltage threshold, VSCD. Both CHG and DSG are turned off if the fault condition
lasts for a duration of SCD Delay, tSCD_DELAY
.
The SCD fault recovers when:
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
• Load removal detected only, VLD < VLDT OR
• Overcurrent Recovery Timer, tCD_REC, expiration only OR
• Overcurrent Recovery Timer expiration and load removal are detected.
8.3.2.7 Overcurrent Recovery Timer
The timer expiration method activates an internal recovery timer as soon as the initial fault condition exceeds the
OCD1/OCD2/SCD time. When the recovery timer reaches its limit, both CHG and DSG drivers are turned back
on. If the combination option of timer expiration AND load removal is used, then the load removal condition is
only evaluated upon expiration of the recovery timer, which can have an expiration period of tCD_REC
.
8.3.2.8 Load Removal Detection
The load removal detection feature is implemented with the LD pin (see 表8-2). When no undervoltage fault and
current fault conditions are present, the LD pin is held in an open-drain state. Once any UV, OCD1, OCD2, or
SCD fault occurs and load removal is selected as part of the recovery conditions, a high impedance pull-down
path to VSS is enabled on the LD pin. With an external load still present, the LD pin will be externally pulled high:
It is internally clamped to VLDCLAMP and should also be resistor-limited through RLD externally to avoid
conducting excessive current. If the LD pin exceeds VLDT, this is interpreted as a load present condition. When
the load is eventually removed, the internal high-impedance path to VSS should be sufficient to pull the LD pin
below VLDT for tLD_DEG. This is interpreted as a load removed condition and is one of the recovery mechanisms
selectable for undervoltage and overcurrent faults.
PACK+
bq77094/5
When load detect is
VLDT
enabled, the LD pin is
connected to Vss via the
RLD_INT.
Load Detect
block
LD
pin
RLD_INT
The load, RLD and RLD_INT
create a resister divider,
which the load detect
LOAD
RLD
circuit is used to detect
when the load is removed.
PACK-
图8-3. Load Detection Circuit for Current Faults Recovery
表8-2. Load State
LD PIN
≥VLDT
LOAD STATE
Load present
Load removed
< VLOT for tLD_DEG
8.3.2.9 Load Removal Detection in UV
During a UV fault, only the DSG FET driver is turned off while the CHG FET driver remains on. When load
removal is selected as part of the UV recovery condition, the active CHG FET driver would alter the resistor
divider ratio of the load detection circuit. To ensure the load status can still be detected properly, it is required to
increase the CHG FET external RGS value to about 3 MΩ. Refer to the 节 9.1.1.4 section for more detail. Note
that if load removal is only selected for the current fault recovery (and is not used for UV recovery), it is not
required to use a larger CHG FET RGS value.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
8.3.2.10 Operation in OTC
An OTC Fault occurs when the temperature increases such that the voltage across an NTC thermistor goes
below the OTC voltage threshold, VOTC. CHG is turned off if the fault condition lasts for an OTC delay time,
tOTC_DELAY. The state comparator is turned on when CHG is turned off. If a discharge current is detected, the
device immediately switches the CHG back on. The response time of the state comparator is typically in 700 µs
and should not pose any disturbance in the discharge event. The OTC fault recovers when the voltage across
thermistor gets above OTC recovery threshold, VOTC_REC, for OTC delay time.
8.3.2.11 Operation in OTD
An OTD fault is when the temperature increases such that the voltage across an NTC thermistor goes below the
OTD voltage threshold, VOTD. Both CHG and DSG are turned off if the fault condition lasts for an OTD delay
time, tOTD_DELAY. The OTD fault recovers when the voltage across thermistor gets above OTD recovery
threshold, VOTD_REC, a time of an OTD delay.
8.3.2.12 Operation in UTC
A UTC fault occurs when the temperature decreases such that the voltage across an NTC thermistor gets above
the UTC voltage threshold, VUTC. CHG is turned off if the fault condition lasts for a time of a UTC delay,
tUTC_DELAY. The state comparator is turned on when CHG is turned off. If a discharge current is detected, the
device will immediately switch CHG back on. The response time of the state comparator is typically in 700 µs
and should not pose any disturbance in the discharge event. The UTC fault recovers when the voltage across
thermistor gets below UTC recovery threshold, VUTC_REC, a time of a UTC delay.
8.3.2.13 Operation in UTD
A UTD fault occurs when the temperature decreases such that the voltage across an NTC thermistor goes
above the UTD voltage threshold, VUTD. Both CHG and DSG are turned off if the fault condition lasts for a UTD
delay time. The UTD fault recovers when the voltage across the thermistor gets below the UTD recovery
threshold, VUTD_REC, a time of the UTD delay.
8.3.3 Protection Response and Recovery Summary
表 8-3 summarizes how each fault condition affects the state of the DSG and CHG output signals, as well as the
recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output drivers
are enabled only when no respective fault conditions are present. When multiple simultaneous faults (such as an
OV and OTD) are present, all faults must be cleared before the FET can resume operation.
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
表8-3. Fault Condition, State, and Recovery Methods
RECOVERY
DELAY
FAULT
CTRC disabled
CTRD disabled
OV
FAULT TRIGGER CONDITION CHG
DSG
RECOVERY METHOD
TRIGGER DELAY
CTRC disabled for deglitch
delay time
OFF
CTRC must be enabled for deglitch delay time
—
tCTRDEG_ON
tCTRDEG_OFF
CTRD disabled for deglitch
delay time
OFF CTRD must be enabled for deglitch delay time
V(Cell) drops below VOV –VHYS_OV for delay
—
V(Cell) rises above VOV for
delay time
OFF
tOVn_DELAY
tUVn_DELAY
tOWn_DELAY
—
V(Cell) drops below VUV for
delay time
UV
OFF V(Cell) rises above VUV + VHYS_UV for delay
—
VCX –VCX–1 < VOW for delay
time
Bad VCX recovers such that VCX –VCX–1 >
VOW + VOW_HYS for delay
OW
OFF
OFF
(VSRP - VSRN) < VOCD1,
VOCD2, or VSCD for delay
time
Recovery delay expires OR
OFF LD detects < VLDT OR
tOCD1_DELAY,
tOCD2_DELAY,
tSCD_DELAY,
OCD1, OCD2,
SCD
OFF
tCD_REC
Recovery delay expires + LD detects < VLDT
Temperature rises above TOTC
for delay time
OTC(1)
OTD(1)
UTC(1)
UTD(1)
OFF
OFF
OFF
OFF
tOTC_DELAY
tOTD_DELAY
tUTC_DELAY
tUTD_DELAY
Temp drops below TOTC –TOTC_REC for delay
—
Temperature rises above TOTD
for delay time
OFF
Temp drops below TOTD –TOTD_REC for delay
Temperature drops below TUTC
for delay time
Temperature rises above TUTC + TUTC_REC for
delay
—
Temp drops below TUTD for
delay time
OFF Temp rises above TUTD + TUTD_REC for delay
(1) TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected
thermistor resistance.
For BQ77904 and BQ77905 devices to prevent CHG FET damage, there are times when the CHG FET may be
enabled even though an OV, UTC, OTC, or CTRC low event has occurred. See the State Comparator section for
details.
8.3.4 Configuration CRC Check and Comparator Built-In-Self-Test
To improve reliability, the device has built in CRC check for all the factory-programmable configurations, such as
the thresholds and delay time setting. When the device is set up in the factory, a corresponding CRC value is
also programmed to the memory. During normal operation, the device compares the configuration setting against
the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the CRC fault
counter. The digital reset forces the device to reload the configuration as an attempt to correct the
configurations. A correct CRC check reduces the CRC fault counter. Three CRC faults counts will turn off both
the CHG and DSG drivers. If FETs are opened due to a CRC error, only a POR can recover the FET state and
reset the CRC fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, and each comparator is checked for a period of time. If a fault is detected for the entire check period,
the particular comparator is considered at fault, and both the CHG and DSG FETs is turned off. The BIST
continues to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver
resumes normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not a
specific indication when a CRC or BIST error is detected besides turning off the CHG and DSG drivers. If there
is no voltage, current, or temperature fault condition present, but CHG and DSG drivers remain off, it is possible
that either a CRC or BIST error is detected. Users can power-on reset (POR) the device.
8.3.5 Fault Detection Method
8.3.5.1 Filtered Fault Detection
The device detects a fault once the applicable fault is triggered after accumulating sufficient trigger sample
counts. The filtering scheme is based on a simple add/subtract. Starting with the triggered sample count cleared,
the counts go up for a sample that is taken across the tested condition (for example, above the fault threshold
when looking for a fault) and the counts go down for a sample that is taken before the tested condition (that is,
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
below the fault threshold). 图 8-4 shows an example of a signal that triggers a fault when accumulating five
counts above the fault threshold. Once a fault has been triggered, the triggered sample counts reset, and counts
are incremented for every sample that is found to be below the recovery threshold.
Note
With a filtered detection, when the input signal falls below the fault threshold, the sample count does
not reset, but only counts down as shown in 图 8-4. Therefore, it is normal to observe a longer delay
time if a signal is right at the detection threshold. The noise can push the delay count to be counting
up and down, resulting a longer time for the delay counter to reach its final accumulated trigger target.
Based on Fault Trigger After 5 Counts
Fault Threshold
Recovery Threshold
FAULT
FAULT
Sample
0
1 2 3 4 3 2 1 2 3 4 5 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 2 3 4 5 0 0 0
Triggered Sample Count
Looking for a Fault
Looking for a Recovery
Looking for a Fault
图8-4. Fault Trigger Filtering
8.3.6 State Comparator
A small, low-offset analog state comparator monitors the sense-resistor voltage (SRP-SRN) to determine when
the pack is in a DISCHARGE state less than a minimum threshold, VSTATE_D or a CHARGE state greater than a
maximum threshold, VSTATE_C. The state comparator is used to turn the CHG FET on to prevent damage or
overheating during discharge in fault states that call for having only the CHG FET off, and vice versa for the DSG
FET during charging in fault states that call for having only the DSG FET off.
表 8-4 summarizes when the state comparator is operational. The state comparator is only on during faults
detected that call for only one FET driver to be turned off.
表8-4. State Comparator Operation Summary
STATE COMP
OFF
CHG
DSG
MODE
ON
ON
Normal
VSTATE_C Detection
VSTATE_D Detection
OFF
ON
OFF
ON
UV, CTRD
OFF
OFF
OV, UTC, OTC, CTRC
OFF
OCD1, OCD2, SCD, UTD, OTD, OW
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
PACK IS CHARGING
PACK IS DISCHARGING
SRP - SRN
VSTATE_D
VSTATE_C
0 V
图8-5. State Comparator Thresholds
8.3.7 DSG FET Driver Operation
The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, and CTRD
are disabled) are present. It is a fast switching driver with a target on resistance of about 15–20 Ω and an off
resistance of RDSGOFF. It is designed to allow users to select the optimized RGS value to archive the desirable
FET rise and fall time per the application requirement and the choice of FET characteristics. When the DSG FET
is turned off, the DSG pin drives low and all overcurrent protections (OCD1, OCD2, SCD) are disabled to better
conserve power. These resume operation when the DSF FET is turned on. The device provides FET body diode
protection through the state comparator if one FET driver is on and the other FET driver is off.
The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge
inhibit fault condition is present. This is done with the state comparator. The state comparator (with the VSTATE_C
threshold) remains on for the entire duration of a DSG fault with no CHG fault event.
• If (SRP-SRN) ≤VSTATE_C and no charge event is detected, the DSG FET output will remain OFF due to the
present of a DSG fault.
• If (SRP-SRN) > VSTATE_C and a charge event is detected, the DSG FET output will turn ON for body diode
protection.
See the 节8.3.6 section for details.
The presence of any related faults, as shown in 图8-6, results in the DSGFET_OFF signal .
DSGFET_OFF_UVn
DSGFET_OFF_OCD1
DSGFET_OFF_OCD2
DSGFET_OFF_SCD
DSGFET_OFF
DSGFET_OFF_UTD
DSGFET_OFF_OTD
OWn
CTRD
图8-6. Faults that Can Qualify DSGFET_OFF
8.3.8 CHG FET Driver Operation
The CHG and CHGU pins are driven high only when no related faults (OV, OW, OTC, UTC, OTD, UTD, OCD1,
OCD2, SCD, and CTRC are disabled) are present or the pack has a discharge current where (SRP-SRN) <
VSTATE_D1 . The CHG pin drives the CHG FET, which is for use on the single device configuration or by the
bottom device in a stack configuration. The CHGU pin has the same logic state as the CHG pin and is for use in
the upper device (in a multi-stack configuration) to provide the drive signal to the CTRC pin of the lower device.
The CHGU pin should never connect to the CHG FET directly.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG pin is designed to
switch on quickly and the target on resistance is about 2 kΩ. When the pin is turned off, the CHG driver pin is
actively driven low and will fall together with PACK–.
The CHG FET may be turned on to protect the FET's body diode if the pack is discharging, even if a charging
inhibit fault condition is present. This is done through the state comparator. The state comparator (with the
VSTATE_D threshold) remains on for the entire duration of a DSG fault with no CHG fault event.
• If (SRP-SRN) > VSTATE_D and no discharge event is detected, the CHG FET output will remain OFF due to
the present of a CHG fault.
• If (SRP-SRN) ≤VSTATE_D and a charge event is detected, the CHG FET output will turn ON for body diode
protection.
The CHGFET_OFF signal is a result of the presence of any related faults, as shown in 图8-7.
CHGFET_OFF_OVn
CHGFET_OFF_UTC
CHGFET_OFF_OTC
CHGFET_OFF_OCD1
CHGFET_OFF_OCD2
CHGFET_OFF
CHGFET_OFF_SCD
CHGFET_OFF_UTD
CHGFET_OFF_OTD
OWn
CTRC
图8-7. Faults That Can Qualify CHGFET OFF
8.3.9 External Override of CHG and DSG Drivers
The device allows direct disabling of the CHG and DSG drivers through the CTRC and CTRD pins, respectively.
The operation of the CTRC and CTRD pins is shown in 图 8-8. To support the simple-stack solution for higher-
cell count packs, these pins are designed to operate above the device’s VDD level. Simply connect a 10-MΩ
resistor between a lower device CTRC and CTRD input pins to an upper device CHGU and DSG output pins
(see the schematics in 节8.3.11.
CTRC only enables or disables the CHG pin, while CTRD only enables or disables the DSG pin. When the CTRx
pin is in the DISABLED region, the respective FET pin will be off, regardless of the state of the protection
circuitry. When the CTRx pin is in either ENABLED region, the protection circuitry determines the state of the
FET driver.
Both CTRx pins apply the fault-detection filtered method to improve the robustness of the signal detection: The
counter counts up if an ENABLED signal is sampled; the counter counts down if a DISABLED signal is sampled.
When the counter counts up from 0% to > 70% of its full range, which takes about 7 ms typical of a solid signal,
the CTRx pins take the signal as ENABLED. If the counter counts down from 100% to < 30%, of its full range,
which takes about 7 ms typical of a solid signal, the CTRx pins take the signal as DISABLED. From a 0 count
counter (solid DISABLE), a solid ENABLE signal takes about tCTRDEG_ON time to deglitch. From a 100% count
(solid ENABLE), a solid DISABLE signal takes about tCTRDEG_OFF time to deglitch. Although such a filter scheme
provides a certain level of noise tolerance, it is highly recommended to shield the CTRx traces and keep the
traces as short as possible in the PCB layout design. The CTRx deglitch time will add onto the FET response
timing on the OV, UV, and OW faults in a stack configuration. The tCTRDEG_OFF time adds an additional delay to
the fault detection timing and the tCTRDEG_ON time adds an additional delay to the fault recovery timing.
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
ENABLED
VCTR2
VCTRDIS (max)
VDD
DISABLED
(FET OFF)
VCTRDIS (min)
VCTR1
ENABLED
VSS
CHG driver set by CTRC
DSG driver set by CTRD
图8-8. External Override of CHG and DSG Drivers
8.3.10 Configuring 3-S, 4-S, or 5-S Mode
The BQ77904 supports 3-S and 4-S packs, while the BQ77905 supports 3-S, 4-S, and 5-S packs. To avoid
accidentally detecting a UV fault on unused (shorted) cell inputs, the device must be configured for the specific
cell count of the pack. This is set with the configuration pin, CCFG, which is mapped as in 表 8-5. The device
periodically checks the CCFG status and takes tCCFG_DEG time to detect the pin status.
表8-5. CCFG Configurations
CCFG
CONFIGURATION
CONNECT TO
AVSS
< VCCFGL for tCCFG_DEG
Within VCCFGM for tCCFG_DEG
> VCCFGH for tCCFG_DEG
3 cells
4 cells
AVDD
5 cells
Floating
The CCFG pin should be tied to the recommended net from 表 8-5. The device compares the CCFG input
voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration is
for 5 S, leave the CCFG pin floating. The internal pin bias is approximately 30% of the AVDD voltage for the 5-S
configuration. Note that the BQ77904 should not be configured in 5-S mode, as this results in a permanent UV
fault.
8.3.11 Stacking Implementations
Higher than 5-S cell packs may be supported by daisy-chaining multiple devices. Each device ensures OV, UV,
OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions automatically
disable the global CHG and/or DSG FET driver. Note that upper devices do not provide OCD1, OCD2, or SCD
protections, as these are based on pack current. For the BQ77904 and BQ77905 devices used on the upper
stack, the SRP and SRN pins should be shorted to prevent false detection.
表8-6. Stacking Implementation Configurations
CONFIGURATION
Bottom or single device
Upper stack
CHG PIN
CHGU PIN
Connect to CHG FET
Leave unconnected
Leave unconnected
Connect to CTRC of the lower device
To configure higher-cell packs, follow this procedure:
• Each device must have a connection on at least three lowest-cell input pins.
• TI recommends to connect a higher-cell count to the upper devices (for example, for a 7-S configuration,
connect four cells on the upper device and three cells on the bottom device). This provides a stronger CRTx
signal to the bottom device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
• Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (three, four,
or five cells).
• For the bottom device, the CHG pin should be used to drive the CHG FET and leave the CHGU pin
unconnected. For the upper device, the CHGU pin should be used to connect to lower device’s CTRC pin
with a RCTRx and leave the CHG pin unconnected.
• Connect the upper DSG pins with a RCTRx to the immediate lower device CTRD pin.
• All upper devices should have the SRP and SRN to its AVSS pin.
• If load removal is not used for UV recovery, connect the upper device LD pin to its AVSS pin, as shown in 图
8-9 and 图8-10. Otherwise, refer to 图9-7 for proper LD connection.
PACK+
RVDD
CVDD
VDD
AVDD
VC5
DVSS
CVDD
CTRD
CTRC
CCFG
VTB
RIN
CIN
VC4
RTS_PU
VC3
RTS
RIN
RIN
RIN
bq77905
CIN
VC2
TS
LD
VC1
CIN
CHG
AVSS
SRP
CHGU
DSG
CIN
SRN
RIN
CIN
RVDD
CVDD
CVDD
VDD
AVDD
VC5
DVSS
RCTRD
CTRD
CTRC
CCFG
VTB
RCTRC
RIN
CIN
VC4
RTS_PU
VC3
RIN
RIN
RIN
RTS
bq77905
CIN
TS
VC2
VC1
LD
CHG
CIN
AVSS
SRP
RCHG
CHGU
DSG
CIN
SRN
RDSG
RLD
RIN
CIN
RGS_DSG
RGS_CHG
RSNS
PACK-
图8-9. 10S Pack Using Two BQ77905 Devices
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
PACK+
RVDD
CVDD
VDD
AVDD
VC5
DVSS
CVDD
RIN
RIN
RIN
RIN
CIN
CTRD
CTRC
CCFG
VTB
CIN
CIN
VC4
RTS_PU
VC3
RTS
bq77905
VC2
TS
LD
VC1
CIN
AVSS
SRP
CHG
CHGU
DSG
RIN
SRN
CIN
RVDD
CVDD
VDD
AVDD
VC5
DVSS
CVDD
RCTRD
CTRD
CTRC
CCFG
VTB
RCTRC
RIN
RIN
RIN
RIN
CIN
VC4
RTS_PU
VC3
RTS
bq77905
CIN
VC2
TS
LD
VC1
CIN
AVSS
SRP
CHG
CHGU
DSG
CIN
SRN
RIN
CIN
RVDD
VDD
AVDD
VC5
DVSS
CVDD
RCTRD
CVDD
CTRD
CTRC
RCTRC
CCFG
VTB
VC4
RTS_PU
VC3
RTS
bq77905
VC2
TS
VC1
LD
CHG
RIN
RIN
RIN
CIN
AVSS
SRP
RCHG
CHGU
DSG
CIN
SRN
RDSG
RLD
CIN
RGS
RGS
RSNS
PACK-
图8-10. 13S Pack Using Three BQ77905 Devices
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
8.3.12 Zero-Volt Battery Charging Inhibition
Once the device is powered up, it can pull the CHG pin up if the VDD ≥VSHUT, which varies from about 1 V per
cell on a 3-S configuration to about 0.6 V per cell on a 5-S configuration. If the battery stack voltage falls below
VSHUT, the device is in SHUTDOWN mode and the CHG driver is no longer active and charging is not allowed
unless VDD rises above VPOR again.
8.4 Device Functional Modes
8.4.1 Power Modes
8.4.1.1 Power-On Reset (POR)
The device powers up when VDD ≥VPOR. At POR, the following events occur:
• A typical 5-ms hold-off delay applies to both CHG and DSG drivers, keeping both drivers in the OFF state.
This provides time for the internal LDO voltage to ramp up.
• CTRC and CTRD deglitch occurs. During the deglitch time, the CHG and DSG driver remains off. Note that
deglitch time masks out the 5-ms hold-off delay.
• The device assumes OV fault at POR; thus, the CHG driver is off for OV recovery time if all the cell voltages
are < (VOV –VHYS_OV). The OV recovery time starts after the 5-ms hold-off delay. If the device reset occurs
when any cell voltage is above the OV hysteresis range, the CHG driver will remain off until an OV recovery
condition is met.
8.4.1.2 FAULT Mode
If any configured protection fault is detected, the device enters the FAULT mode. In this mode, the CHG and/or
DSG driver can be turned off depending on the fault. Refer to the fault response summary, 节 8.4.1.2, for detail.
When one of the FET drivers (either CHG or DSG) is turned off, while the other FET driver is still on, the state
comparator is activated for FET body diode protection.
8.4.1.3 SHUTDOWN Mode
This is the lowest power consumption state of the device when VDD falls below VSHUT. In this mode, all fault
detections and theCHG and DSG drivers are disabled. The device will wake up and enter NORMAL mode when
VDD rises above VPOR
.
8.4.1.4 Customer Fast Production Test Modes
The BQ7790x device supports the ability to greatly reduce production test time by cutting down on protection
fault delay times. To shorten fault times, place the BQ7790x device into Customer Test Mode (CTM). CTM is
triggered by raising VDD to VCTM voltage above the highest cell input pin (that is, VC5) for tCTM_ENTRY time.
The CTM is expected to be used in single-chip designs only. CTM is not supported for stacked designs. Once
the device is in CTM, all fault delay and non-current fault's recovery delay times reduce to a value of tCTM_DELAY
The fault recovery time for overcurrent faults (OCD1, OCD2, and SCD) is reduced to tCTM_OC_REC
.
.
Verification of protection fault functionality can be accomplished in a reduced time frame in CTM. Reducing the
VDD voltage to the same voltage applied to the highest-cell input pin for tCTM_ENTRY will exit CTM.
In CTM, with reduced time for all internal delays, qualification of all faults will be reduced to a single instance.
Thus in this mode, fault condition qualification is more susceptible to transients, so take care to have fault
conditions clearly and cleanly applied during test mode to avoid false triggering of fault conditions during CTM.
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The BQ77904 and BQ77905 devices are low-power stackable battery pack protectors with an integrated low-
side NMOS FET driver. The BQ77904 and BQ77905 devices provide voltage, current, temperature, and open-
wire protections. All the devices protect and recover without MCU control. The following section highlights
several recommended implementation when using these devices.
9.1.1 Recommended System Implementation
9.1.1.1 CHG and DSG FET Rise and Fall Time
The CHG and DSG FET drivers are designed to have fast switching time. Users should select a proper gate
resistor (RCHG and RDSG in the reference schematic) to set to the desired rise/fall time.
DSG
CHG
Select proper gate
resistor to adjust
the desired rise/fall
time
R
R
DSG
CHG
R
GS_DSG
R
GS_CHG
Q2 Q1
R
SNS
PACK-
图9-1. Select Proper Gate Resistor for FET Rise and Fall Time
The CHG FET fall time is generally slower, because it is connected to the PACK– terminal. The CHG driver will
pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or
Vgsth, the PACK– will start to fall below ground and the CHG signal will follow suit in order to turn off the CHG
FET. This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel,
and the value of gate-source resistor (RGS_CHG).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Strong pull down by the CHG driver
when the device is initially signaled to
turn off CHG.
Once the CFET gate voltage reach PACK-, PACK-
voltage starts to fall below ground. The gate
voltage is then relying on RGS_CHG to fall with
PACK- to keep the CHG FET off.
图9-2. CHG FET Fall Time
9.1.1.2 Protecting CHG and LD
Because both CHG and LD are connected to the PACK– terminal, these pins are specially designed to sustain
an absolute max of –30 V. However, the device can be used in a wide variety of applications, and it is possible
to expose the pins lower than –30 V absolute max rating.
To protect the pins, TI recommends to put a PMOS FET in series of the CHG pin and a diode in series of the LD
pin as shown below.
DSG
CHG
LD
Q3 and the LD pin diode are used to
keep CHG and LD away from any
voltages below VSS. Apply these
components when CHG and LD pins can
be exposed beyond the absolute -30V.
Q3
RDSG
RCHG
RLD
Q3 will allow RGS_CHG to keeps Q1 OFF,
since all voltages below this FET can
^(}oo}Á_ t!/Y- as it goes below VSS.
RGS_DSG
RGS_CHG
Q2 Q1
RSNS
PACK-
图9-3. Protecting CHG and LD
9.1.1.3 Protecting CHG FET
When the CHG driver is off, CHG is pulled to VSS, the PACK–terminal can be pullup to the PACK+ level when a
load is connected. This can put the gate-source voltage above the absolute max of the MOSFET rating. Hence,
it is common to place a Zener diode across the CHG FET’s gate-source to protect the CHG FET. Additional
components are added when a Zener is used to limit current going into the CHG pin, as well as reducing the
impact on rise time. See 图9-4 for details.
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
DSG
CHG
This diode allows CHG to
pull the Q1 gate high,
bypassing the path through
RCHG and RGS_CHG which will
divide down the CHG ON
voltage
RCHG drops the voltage and limits the
current going into the CHG pin when
PACK- is pulled high and zener across Q1
RCHG
(1MΩ ) Vgs is used.
RDSG
This zener clamp may be
needed to prevent the Vgs of Q1
excesses absolute max rating.
RGS_CHG
16V
RGS_DSG
(>=1MΩ)
Q2
Q1
RSNS
PACK-
图9-4. Protect CHG FET from a High Voltage on PACK–
LD
DSG
CHG
Q3
RCHG
(1MΩ )
RLD
RDSG
RGS_CHG
(>=1MΩ)
16V
RGS_DSG
Q2 Q1
RSNS
PACK-
图9-5. Optional Components Combining Protecting CHG and LD and Protecting CHG FET Protections
9.1.1.4 Using Load Detect for UV Fault Recovery
A larger CHG FET gate-source resistor is required if load removal is enabled as part of the UV recovery criteria.
When the load removal circuit is enabled, the device is internally connected to Vss. Because in a UV fault the
CHG driver remains on, it creates a resistor divider path to the load detect circuit.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
PACK+
bq77094/5
VLDT
Load Detect
block
LD
pin
RLD_INT
LOAD
CHG
pin
FET driver
block
VFETON
RCHG
RLD
16V
RGS_CHG
CFET
PACK-
图9-6. Load Detect Circuit During UV Fault
To ensure load removal is detected properly during a UV fault, TI recommends to use 3.3 MΩ for RGS_CHG
(instead of a typical of 1 MΩ when load removal is NOT required for UV recovery). RCHG can stay in 1 MΩ as
recommended when using CHG FET protection components. The CHG FET rise time impact is minimized as
described in the Protecting CHG FET section. On a stacked configuration, connect the LD pin, as shown in 图
9-7 if load removal is used for a UV fault recovery. If load detection is not required for a UV fault recovery, a
larger value of RGS_CHG can be used (that is, 10 MΩ) and the LD pin on the upper devices can be left floating.
Ra is used to keep the LD pin pull
bq77094/5
down when load detect circuit is
not activated
LD
pin
Upper
device
Ra
(1M)
Vss
Must have block
diode on the upper
pin
device.
RLD
bq77094/5
LD
pin
Diode for the bottom
device is optional.
Bottom
Use if the LD pin will
be exposed lower
than -30V.
device
Vss
pin
RLD
PACK-
图9-7. Simplified Circuit: LD Connection on Upper Device When Using for UV Fault Recovery
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
9.1.1.5 Temperature Protection
The device detects temperature by checking the voltage divided by RTS_PU and RTS, with the assumption of
using 10-KΩ RTS_PU and 103AT NTC for RTS. System designers should always check the thermistor resistance
characteristics and refer to the temperature protection threshold specifications in the Electrical Characteristics
table to determine if a different pullup resistor should be used. If a different temperature trip point is required, it is
possible to scale the threshold using this equation: Temperature Protection Threshold = RTS / (RTS + RTS_PU).
Example: Scale OTC trip points from 50°C to 55°C
The OTC protection can be set to 45°C or 50°C. When the device's OTC threshold is set to 50°C, it is referred to
configure the VOTC parameter to 29.38% of VTB (typical), with the assumption of RTS_PU = 10 KΩ and RTS
=
103AT or similar NTC (which the NTC resistance at 50°C = 4.16 KΩ). The VOTC specification is the resistor
divider ratio of RTS_PU and RTS.
The VOTC, VOTD, VUTC, and VUTD configuration options are fixed in the device; thus, the actual temperature trip
point can only adjust by using a different B-value NTC and/or using a different RTS_PU
.
In this example, the 103AT NTC resistance at 55°C is 3.536 KΩ. By changing the RTS_PU from 10 KΩ to 8.5
KΩ, users can scale the actual OTC temperature trip point from 50°C to 55°C. Because the RTS_PU value is
smaller, this change affects all the other temperature trip points and scales OTD, UTC, and UTD to ~5°C higher
as well.
9.1.1.6 Adding Filter to Sense Resistor
Current fault is sense through voltage across a sense resistor. Optional RC filters can be added to the sense
resistor to improve stability.
SRP
SRN
0.1 µF
0.1 µF
0.1 µF
100 Ω
100 Ω
PACK-
RSNS
图9-8. Optional Filters Improve Current Measurement
9.1.1.7 Using a State Comparator in an Application
The state comparator does not have built-in hysteresis. It is normal to observe the FET body diode protection
toggling on and off with the VSTATE_C1 or VSTATE_D1 accuracy range. In a typical application, the sense resistor is
selected according to the application current, which usually is not close to the state comparator threshold.
9.1.1.7.1 Examples
As an example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor
is 3 mΩ or less. The typical current to turn on the FET body diode protection is 667 mA using this example.
Because there is no built-in hysteresis, noise can reset the state comparator counter and toggle off the FET body
diode protection and vice versa; thus, it is normal to observe the device toggles the FET body diode protection
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
on or off within a 1-mV to 3-mV range. With a 3-mΩsense resistor, it is about 330 mA to 1 A. As this behavior is
due to noise from the system, the FET toggling behavior usually occurs right at the typical 2-mV state
comparator threshold. As current increases or decreases from the typical value, the detection is more solid and
has less frequent FET toggling. Using this example, either charge or discharge should provide a solid FET body
diode protection detection.
Look at the device behavior during an OV event (and no other fault is detected). In an OV event, CHG FET is off
and DSG FET is on. If a discharge of > –1 A occurs, the device would turn on the CHG FET immediately to
allow the full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery
level, the OV fault is recovered and the CHG driver turns on (or remains on in this scenario) and the state
comparator is turned off.
If the discharge current is < 1 A when the device is still in an OV fault, the CHG FET may toggle on and off until
the overcharged cell voltage is reduced down to the OV recovery level. When the OV fault recovers, the CHG
FET is solidly turned on and the state comparator is off.
Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can
only pass through the CHG FET body diode until the OV fault is recovered. This increases the risk of damaging
the CHG FET if the MOSFET is not rated to sustain this amount of current through its body diode. It also
increases the FET temperature as current is now carried through the body diode.
9.2 Typical Application
PACK+
RVDD
CVDD
CVDD
VDD
AVDD
VC5
DVSS
CTRD
CTRC
CCFG
VTB
VC4
RIN
RTS_PU
bq77905
bq77904
VC3
RTS
CIN
VC2
TS
LD
RIN
RIN
RIN
VC1
CIN
AVSS
SRP
CHG
CHGU
DSG
RCHG
CIN
SRN
RDSG
RLD
CIN
RGS
RGS
RSNS
PACK-
Copyright © 2016, Texas Instruments Incorporated
图9-9. BQ77904 and BQ77905 with Four Cells
9.2.1 Design Requirements
For this design example, use the parameters shown in 表9-1.
表9-1. Design Parameters
PARAMETER
DESCRIPTION
VALUES
1 kΩ±5%
0.1 µF ±10%
1 kΩ±5%
RIN
Cell voltage sensing (VCx pins) filter resistor
CIN
Cell voltage sensing (VCx pins) filter capacitor
Supply voltage filter resistor
RVDD
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
表9-1. Design Parameters (continued)
PARAMETER
CVDD
DESCRIPTION
VALUES
1 µF ±20%
Supply voltage filter capacitor
NTC thermistor
RTS
103AT, 10 kΩ±3%
RTS_PU
Thermistor pullup resistor to VTB pin, assuming using 103AT NTC or NTC with similar
resistance-temperature characteristics
10 kΩ±1%
RGS_CHG
CHG FET gate-source Load removal is enabled for UV recovery.
3.3 MΩ±5%
1 MΩ±5%
1 MΩ±5%
resistor
Load removal is disabled for UV recovery.
RGS_DSG
RCHG
DSG FET gate-source resistor
CHG gate resistor
System designers should adjust this parameter to meet the
desired FET rise/fall time.
1 kΩ±5%
1 MΩ±5%
4.5 kΩ±5%
If additional components are used to protect the CHG FET
and/or to enable load removal detection for UV recovery.
RDSG
DSG gate resistor, system designers should adjust this parameter to meet the desired
FET rise/fall time.
RCRTC and RCTRD
CTRC and CTRD current limit resistor
LD resistor for load removal detection
10 MΩ±5%
450 KΩ±5%
RLD
RSNS
Current sense resistor for current protection. System designers should change this
parameter according to the application current protection requirements.
1 mΩ±1%
9.2.2 Detailed Design Procedure
The following is the detailed design procedure.
1. Based on the application current, select the proper sense resistor value. The sense resistor should allow
detection of the highest current protection, short circuit current.
2. Temperature protection is set with the assumption of using a 103AT NTC (or NTC with similar specification).
If a different type of NTC is used, a different RTS_PU may be used for the application. Refer to the actual
temperature detection threshold voltage to determine the RTS_PU value.
3. Connect the CCFG pin correctly based on the number of cells in series.
4. Review the Recommended Application Implementation to determine if optional components should be added
to the schematic.
9.2.2.1 Design Example
To design the protection for a 36-V Li-ion battery pack using 4.2-V LiCoO2 cells with the following protection
requirements:
Voltage Protection
• OV at 4.3 V, recover at 4.1 V
• UV at 2.6 V, recover at 3 V and when load is removed.
Current Protection
• OCD1 at 40 A with 300-ms–400-ms delay
• OCD2 at 80 A with the shortest delay option
• SCD at 100 A with < 500-µs delay
• Requires load removal for recovery
Temperature Protection
• Charge –OTC at 50°C, UTC at –5°C
• Discharge –OTD at 70°C, UTD at –10°C
To start the design:
1. Start the schematic.
• A 36-V pack using LiCoO2 cells requires 10-S configuration; thus, two BQ77905 devices in a stackable
configuration is needed.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
• Follow the 10-S reference schematic in this document. Follow the recommended design parameters
listed in the 节9.2.1 section of this document.
• The power FET used in this type of application usually has an absolute of 20 V Vgs. For a 36-V pack
design, TI recommends to use the additional components to protect the CHG FET Vgs. See the 节
9.1.1.4 section for details.
• Because load removal for UV recovery is required, a 3-MΩRGS_CHG should be used for the schematic.
2. Decide the value of the sense resistor, RSNS
.
• When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available
current protection threshold range.
• In this example, select RSNS = 1 mΩ(any value ≤2 mΩwill work in this example).
3. Determine all of the BQ77905 protection configurations (see 表9-2).
4. Review the available released or preview devices in the 节5 section to determine if a suitable option is
available. If not, contact TI representative for further assistance.
表9-2. Design Example Configuration
Protection
OV
Threshold
4.3 V
Hysteresis
Delay
Recovery Method
200 mV
1 s (default setting)
1 s (default setting)
Hysteresis
UV
2.6 V
400 mV
Hysteresis + load removal
100 nA
(default setting)
OW
(VCx –VCx–1) > 600 mV (typical)
—
—
OCD1
OCD2
SCD
OTC
OTD
UTC
40 mV
80 mV
100 mV
50°C
350 ms
5 ms
Load removal only
Load removal only
Load removal only
Hysteresis
—
—
Fixed at 360 µs
4.5 s
—
10°C
10°C
70°C
4.5 s
Hysteresis
10°C
10°C
4.5 s
Hysteresis
–5°C
–10°C
UTD
4.5 s
Hysteresis
9.2.3 Application Curves
DSG remains on
DSG remains on
CHG recovers after
2nd OV fault is removed
CHG falls due to
detection of 1st OV fault
2nd Fault removed
1st Fault removed
1st OV Fault
图9-10. OV Fault Protection
图9-11. OV Fault Recovery
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
Device is set to recovery after
current recovery delay. Both
CHG/DSG turns back on, but
device detects OCD2 fault and
turns off both FET driver again
State comparator detects discharge and
turns CHG back on even OV fault is present
Both CHG/DSG are
off in OCD2 fault
CHG falls due to OV fault.
State comparator is on to detect any
discharge activity
OCD2 fault inserted
OV fault
图9-13. Detect OTC Fault While in 30-A Discharge
图9-12. OV and OCD2 Faults Protection
In real application, OV and UV are usually
triggered first in an open wire event, masking out
the OW protection. This capture is to demonstrate
the OW protection by observing the CHG delay
time
DSG falls due to
UV fault on VC2
DSG falls after ~ 1s due to
UV fault on VC2
CHG falls after
~5s due to OW
CHG falls after ~ 1s due to
OV fault on VC3
Relay opens œ open cell2 to pcb connection
VC2 ramped to 0V, while other cell
voltages stay in normal
In real application, an open wire event will deplete the filter
capacitor connects to the device cell voltage sensing pin. The
depleted capacitor will trigger the UV fault. It also causes the
cell voltage sensing pin to see a sum of 2 cell voltages, which
trigger an OV fault.
OV and UV delays are shorter than OW delay, hence, the OV
UV will triggered before OW protection activates.
图9-14. OW Fault Protection—Open Cell2 To PCB
图9-15. OW Fault Protection—Ramping Down
Connection
Cell2 Voltage
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
9.3 System Examples
PACK+
RVDD
CVDD
CVDD
VDD
AVDD
VC5
DVSS
CTRD
CTRC
CCFG
VTB
RIN
CIN
VC4
RTS_PU
VC3
RIN
RTS
bq77905
CIN
VC2
TS
LD
VC1
RIN
RIN
CIN
AVSS
SRP
CHG
CHGU
DSG
RCHG
CIN
SRN
RDSG
RLD
RIN
CIN
RGS
RGS
RSNS
PACK-
Copyright © 2016, Texas Instruments Incorporated
图9-16. BQ77905 with Five Cells
10 Power Supply Recommendations
The recommended cell voltage range is up to 5 V. If three cells in series are connecting to BQ77905, the unused
VCx pins should be shorted to the highest unused VCx pin. The recommended VDD range is from 3 V–25 V.
This implies the device is still operational when cell voltage is depleted down to approximately 1.5-V range.
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
1. Match SRN and SRP traces.
2. RIN filters, VDD, AVDD filters, and the CVDD capacitor should be placed close to the device pins.
3. Separate the device ground plane (low current ground) from the high current path. Filter capacitors should
reference to the low current ground path or device Vss.
4. In a stack configuration, the RCTRD and RCTRC should be placed closer to the lower device CTRD and CTRC
pins.
5. RGS should be placed near the FETs.
11.2 Layout Example
PACK+
High current Path
Please filters
DVSS
close to IC pins
VDD
Connect AVSS and DVSS
to device ground plane
AVDD
VC5
:
:
RC
Filters
Low current, local
ground for each device
VC1
CHGU
DSG
AVSS
Connect the device ground at
šZꢀ o}ÁꢀŒ ꢁꢀoo[• ꢁꢀoo- on each
cell group
Please filters
close to IC pins
DVSS
VDD
Please CTRs
CTRD
CTRC
resistors close to
the lower device
AVDD
VC5
:
RC
:
Filters
Low current, local
device ground.
Separate from high
power path
VC1
AVSS
Connect the bottom
device ground at BAT-.
Using BAT- as the mutual
point to connect high
and low current path
PACK-
图11-1. Layout Example
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: BQ77904 BQ77905
BQ77904, BQ77905
ZHCSF60K –JUNE 2016 –REVISED JULY 2020
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
BQ77904
BQ77905
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: BQ77904 BQ77905
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7790400PW
BQ7790400PWR
BQ7790500PW
BQ7790500PWR
BQ7790502PW
BQ7790502PWR
BQ7790503PW
BQ7790503PWR
BQ7790505PW
BQ7790505PWR
BQ7790508PW
BQ7790508PWR
BQ7790509PW
BQ7790509PWR
BQ7790511PW
BQ7790511PWR
BQ7790512PW
BQ7790512PWR
BQ7790518PW
BQ7790518PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
B7790400
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
B7790400
B7790500
B7790500
B7790502
B7790502
B7790503
B7790503
B7790505
B7790505
B7790508
B7790508
B7790509
B7790509
B7790511
B7790511
B7790512
B7790512
B7790518
B7790518
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7790521PW
BQ7790521PWR
BQ7790522PW
BQ7790522PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
20
20
20
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
B7790521
2000 RoHS & Green
70 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
B7790521
B7790522
B7790522
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ7790400PWR
BQ7790500PWR
BQ7790502PWR
BQ7790503PWR
BQ7790505PWR
BQ7790508PWR
BQ7790509PWR
BQ7790511PWR
BQ7790512PWR
BQ7790518PWR
BQ7790521PWR
BQ7790522PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
20
20
20
20
20
20
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ7790400PWR
BQ7790500PWR
BQ7790502PWR
BQ7790503PWR
BQ7790505PWR
BQ7790508PWR
BQ7790509PWR
BQ7790511PWR
BQ7790512PWR
BQ7790518PWR
BQ7790521PWR
BQ7790522PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
20
20
20
20
20
20
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
356.0
356.0
356.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
356.0
356.0
356.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
BQ7790400PW
BQ7790500PW
BQ7790502PW
BQ7790503PW
BQ7790505PW
BQ7790508PW
BQ7790509PW
BQ7790511PW
BQ7790512PW
BQ7790518PW
BQ7790521PW
BQ7790522PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
20
20
20
20
20
20
20
20
20
20
20
20
70
70
70
70
70
70
70
70
70
70
70
70
530
530
530
530
530
530
530
530
530
530
530
530
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明