BQ7791500PWT [TI]
具有电池自主平衡功能的 3 节至 5 节串联可堆叠超低功耗初级保护器 | PW | 24 | -40 to 85;型号: | BQ7791500PWT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有电池自主平衡功能的 3 节至 5 节串联可堆叠超低功耗初级保护器 | PW | 24 | -40 to 85 电池 |
文件: | 总56页 (文件大小:1859K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BQ77915
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
具有电池自主平衡功能和休眠模式的 BQ77915 3 节至 5 节串联、可堆叠超低功
耗初级保护器
1 特性
3 说明
•
超低静态电流:8 µA 典型值(正常模式),2 µA
BQ77915 器件是一款低功耗电池组保护器,它实现了
一整套的电压、电流和温度保护功能以及智能电池平衡
算法,无需微控制器 (MCU) 控制。该器件的可堆叠接
口可进行简单扩展,支持从 3 节串联到 20 节或更多
节数串联的电池应用。保护阈值和延迟均为出厂编程设
定,有多种配置可供选用。为提升灵活性,还提供了单
独的过热和欠温放电阈值(OTD 和 UTD)以及过热和
欠温充电阈值(OTC 和 UTC)。
(休眠模式)
•
•
•
•
整套电压、电流和温度保护功能
智能电池被动平衡功能可消除电池间的不平衡
可将电池节数从 3 节扩展到 20 节或更多
电压保护(过压精度为 ±10mV,欠压精度为
±18mV)
– 过压:3V 至 4.575V
– 欠压:1.2V 至 3V
器件信息
•
•
开路电池和断线检测 (OW)
器件型号 (1)
BQ77915
封装
封装尺寸(标称值)
电流保护
TSSOP–24
7.70mm × 4.40mm
– 过流放电 1:-10mV 至 -85mV
– 过流放电 2:-20mV 至 -170 mV
– 短路放电:-40mV 至 -340 mV
温度保护
– 过热充电:45°C 至 50°C
– 过热放电:65°C 至 70°C
其他特性:
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
•
•
PACK+
VDD
VTB
TS
CTRD
CTRC
VC5
+
–
– 独立充电 (CHG) 和放电 (DSG) FET 驱动器
– 通过集成式 FET(平衡电流高达 50mA)实现了
智能电池平衡算法,此外还支持通过外部 FET
实现更高的电池平衡电流
bq77915
LD
PRES
LPWR
+
–
VC0
VSS
– 超低功耗休眠模式
CBO
CBI
– 每节电池输入的绝对最大额定电压高达 36V
– 过流 (OCD1/2) 延迟可通过电阻器进行编程
关断模式:0.5 µA(最大值)
提供功能安全
CHG
SRP
SRN
DSG
•
•
– 有助于进行功能安全系统设计的文档
2 应用
VTB
TS
VDD
VC5
CTRD
CTRC
+
–
•
•
•
•
电动工具、园艺工具
清洁机器人、真空吸尘器、悬浮滑板
电动自行车
bq77915
LD
PRES
LPWR
CBO
10.8V 至 72V 电池组
+
–
VC0
VSS
CHG
SRP
SRN
DSG
CBI
PACK–
简化版原理图
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings........................................ 5
8.2 ESD Ratings............................................................... 5
8.3 Recommended Operating Conditions.........................5
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................7
8.6 Typical Characteristics..............................................12
9 Detailed Description......................................................12
9.1 Overview...................................................................12
9.2 Functional Block Diagram.........................................14
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................31
10 Application and Implementation................................33
10.1 Application Information........................................... 33
10.2 Typical Application.................................................. 39
11 Power Supply Recommendations..............................44
12 Layout...........................................................................45
12.1 Layout Guidelines................................................... 45
12.2 Layout Example...................................................... 46
13 Device and Documentation Support..........................47
13.1 第三方产品免责声明................................................47
13.2 Documentation Support.......................................... 47
13.3 接收文档更新通知................................................... 47
13.4 支持资源..................................................................47
13.5 Trademarks.............................................................47
13.6 静电放电警告.......................................................... 47
13.7 术语表..................................................................... 47
14 Mechanical, Packaging, and Orderable
Information.................................................................... 47
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision J (March 2022) to Revision K (July 2023)
Page
•
Added the BQ7791514 device to the Device Comparison Table .......................................................................3
Changes from Revision I (September 2020) to Revision J (March 2022)
Page
•
•
根据最新德州仪器 (TI) 和行业数据表标准对本文档进行了更新。...................................................................... 1
Added the BQ7791513 device to the Device Comparison Table .......................................................................3
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
2
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
5 说明(续)
此器件可通过集成的独立 CHG 和 DSG 低侧 NMOS FET 驱动器实现电池组保护,这些驱动器可通过两个控制引
脚禁用。这些控制引脚还能够以简单经济的方式为更多节串联电池(6 节及以上)提供电池保护解决方案。为此,
只需将上级器件的 CHG 和 DSG 输出级联到下级器件控制引脚。为实现更大的灵活性,放电过流保护延迟可以通
过从 OCDP 引脚连接至 VSS 的电阻器进行编程。
BQ77915 保护器通过可实现高达 50mA 电池平衡电流的集成式 FET,实现了智能被动电池平衡算法。对于更高的
电池平衡电流要求,可通过连接外部 FET 的方式实现。旨在用于电池组运输和贮存之目的的休眠模式可支持超低
功耗运行。
BQ77915 保护器可用于无需主机监控的电池组。
6 Device Comparison Table
Unless otherwise specified, the device has, by default, a state comparator enabled with a 1.875-mV threshold. A
filtered fault detection is used by default.
表 6-1. Device Comparison Table
OV
UV
OW
OCD1
OCD2
SCD
OCC
Load
Remo-
val
Thre-
shold Delay Hyst
Thre-
shold
(mV)
Reco-
very
(Y/N)
Thre-
shold
(mV)
Delay
(s)
Hyst
(mV)
Current
(nA)
Delay
(ms)
Threshold
(mV)
Threshold
Delay
(ms)
Threshold
(mV)
Part Number
BQ7791500
BQ7791501
BQ7791502
BQ7791504
BQ7791506
BQ7791508
BQ7791513
(mV)
4200
4250
4200
4275
3800
4200
4300
(s)
(mV)
200
200
200
100
200
100
100
Delay (ms)
180
(mV)
120
120
120
1
2900
2800
2900
2000
2500
3000
1800
1
1
400
400
400
200
400
200
200
Y
Y
Y
N
Y
Y
N
100
100
100
60
35
70
180
180
180
60
0.96
0.96
0.96
60
20
70
1
60
180
1
1
70
180
1
1
Disabled
1
1
100
100
50
70
700
100
140
350
700
300
300
0.4
0.4
60
60
4.5
4.5
4.5
9
1420
Disabled
350
BQ7791514
3650
1
100
2500
1
200
Y
100
50
700
100
200
0.4
50
表 6-2. Device Comparison Table (continued)
Current Fault Recovery
Temperature (°C)(1)
Cell Balancing
VSTEP (VCBTH
–
Delay
(ms)
VHYST (VOV
VFC) (mV)
–
VCBTL
(mV)
)
Part Number
Method
OTD
OTC
UTD
UTC
VSTART (V)
BQ7791500
N/A
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
45
–10
0
3.8
100
100
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
BQ7791501
N/A
70
65
50
45
–20
–10
0
0
3.8
100
100
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
BQ7791502
BQ7791504
BQ7791506
N/A
Disabled
N/A
3.8
3.5
3.5
100
50
100
50
N/A
Disabled
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
65
50
50
–10
–20
0
100
50
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
BQ7791508
500
–5
3.8
100
50
BQ7791513
BQ7791514
Disabled N/A
N/A
Disabled
50
3.8
3.5
150
100
50
50
Load removal only (OCD1, OCD2, SCD)/load
detection only (OCC)
65
-10
0
(1) These thresholds are targets, based on temperature, but they are dependent on external components that could vary based on
customer selection. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to
VTB and TS. Actual thresholds must be determined in mV; refers to the overtemperature and undertemperature mV threshold in the
Electrical Characteristics table.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
7 Pin Configuration and Functions
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
VC0
VSS
SRP
SRN
DSG
1
24
23
22
21
20
19
18
17
16
15
14
13
CTRD
CTRC
PRES
CBO
CCFG
VTB
2
3
4
5
6
7
TS
8
OCDP
CBI
9
10
11
12
LPWR
LD
CHG
Not to scale
图 7-1. PW Package 24-Pin TSSOP Top View
表 7-1. Pin Functions
NUMBER
NAME
VDD
I/O
DESCRIPTION
1
2
P(1)
Supply voltage
AVDD
VC5
VC4
VC3
VC2
VC1
VC0
VSS
SRP
SRN
DSG
CHG
LD
O
I
Analog supply (only connect to a capacitor)
3
4
I
5
I
Cell voltage sense inputs
6
I
7
I
8
I
9
P
I
Analog ground
10
11
12
13
14
Current sense input connecting to the battery side of the sense resistor
Current sense input connecting to the pack side of the sense resistor
DSG FET driver output
I
O
O
I
CHG FET driver output
PACK– load removal detection
HIBERNATE mode communication pin. Connect to the PRES pin of the lower device in a stack
configuration. For a single device, leave the LPWR pin floating.
15
16
LPWR
CBI
O
I
Cell balancing input. Leave the CBI pin floating to disable cell balancing, and do not drive
with an external supply. Drive the pin low to enable cell balancing. In a stacked configuration,
connect the CBI pin of an upper device to the CBO pin of the immediate lower device.
Connecting a resistor from this pin to VSS programs the OCD1/2 fault detection delay. Connect
to a 10-MΩ resistor to VSS for the upper devices in a stack.
17
18
OCDP
TS
I
I
Thermistor measurement input. Connect a 10-kΩ resistor to the VSS pin if the function is not
used.
19
20
VTB
O
I
Thermistor bias output
CCFG
Cell in-series configuration input
Cell balancing output. Connect through a 10-k resistor to the CBI pin of the upper device in a
stacked configuration. For a single device, leave the CBO pin floating.
21
22
CBO
O
I
HIBERNATE mode input. Drive high for NORMAL mode operation. Leave the PRES pin
floating for HIBERNATE mode. Connect to the LPWR pin of the upper device in a stack
configuration.
PRES
Copyright © 2023 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
表 7-1. Pin Functions (continued)
NUMBER
NAME
CTRC
CTRD
I/O
DESCRIPTION
23
24
I
I
CHG and DSG override inputs
(1) I = Input, O = Output, P = Power
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). All values are referenced to VSS unless otherwise
noted.(1)
MIN
–0.3
–30
MAX
UNIT
VDD, VC5, VC4, VC3, VC2, VC1, CTRD, CTRC
36
V
LD
20
V
VI
Input voltage
PRES
–0.3
–0.3
–0.3
–30
36
V
VC0, SRN, SRP, TS, AVDD, CCFG, CBI
3.6
20
V
DSG
V
CHG
20
V
VO
Output voltage
CBO
–0.3
–30
36
V
LPWR
3.6
3.6
500
1
V
VO
II
Output voltage
Input current
VTB, OCDP
–0.3
V
LD, CHG
µA
mA
mA
mA
°C
°C
DSG
IO
IO
Output current
Output current
CHG, DSG
1
Cell Balancing current (VC5, VC4, VC3, VC2, VC1, VC0)
50
Lead temperature (soldering, 10 s), TSOLDER
Storage temperature, Tstg
300
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime.
8.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VBAT
Supply voltage
VDD
3
25
V
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.3 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VC5-VC4, VC4-VC3, VC3-
0
5
VC2, VC2-VC1, VC1-VC0
CTRD, CTRC
CCFG, CBI
PRES
0
0
(VDD + 5)
AVDD
16
VI
Input voltage range
V
0
SRN, SRP
LD
–0.2
0
0.8
16
TS
0
VTB
16
CHG, DSG
VTB, AVDD, LPWR
CBO
0
VO
Output voltage range
0
3
V
0
VDD
85
TOPR
RINE
Operating free-range temperature
–40
°C
Cell monitor filter resistance (External Cell
balancing)
± 5% tolerance
± 10% tolerance
1
kΩ
Cell monitor filter capacitance (External Cell
balancing)
CINE
RINI
CINI
0.1
µF
Ω
Cell monitor filter resistance (Internal Cell
balancing. 50-mA balancing current at 4.2-V
cell voltage)
± 5% tolerance
± 10% tolerance
33
1
Cell monitor filter capacitance (Internal Cell
balancing)
µF
RVDD
CVDD
RTS
Supply voltage filter resistance
Supply voltage filter capacitance
Thermistor
± 5% tolerance
± 20% tolerance
103AT, ± 3% tolerance
± 1% tolerance
± 5% tolerance
± 5% tolerance
1
1
kΩ
µF
10
10
1
kΩ
kΩ
MΩ
MΩ
RTS_PU
Thermistor pullup resistor to VTB
RGS_CHG CHG FET gate-source resistor
RGS_DSG DSG FET gate-source resistor
1
DSG gate resistor, System designers should
adjust this parameter to meet the desirable FET ± 5% tolerance
rise/fall time.
RDSG
4.5
1
kΩ
kΩ
± 5% tolerance. System
designers should adjust this
parameter to meet the
desirable FET rise/fall time.
RCHG
CHG gate resistor
± 5% tolerance. If additional
components are used to
protect the CHG FET and/or to
enable load removal detection
for UV recovery.
1
MΩ
RCTRC
RCTRD
RLD
CTRC current limit resistor
± 5% tolerance
± 5% tolerance
± 5% tolerance
10
10
MΩ
MΩ
kΩ
CTRD current limit resistor
LD resistor for load removal detection
470
Resistor between CBO of lower device and CBI
of upper device
RCB
± 5% tolerance
± 5% tolerance
10
10
kΩ
kΩ
Resistor between LPWR of upper device and
PRES of upper device
RHIB
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
6
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.3 Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Current sense resistor for current protection.
System designers should change this
parameter according to the application current
protection requirement.
RSNS
± 1% tolerance
1
mΩ
8.4 Thermal Information
Over operating free-air temperature range (unless otherwise noted)
BQ77915
PW (TSSOP)
24 PINS
THERMAL METRIC
UNIT(1)
RΘJA
RΘJC(top)
RΘJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
88.9
26.5
43.5
1.1
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
43
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953 SPRA953.
8.5 Electrical Characteristics
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25
V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VPOR
POR threshold
Shutdown threshold
AVDD voltage
VDD rising, 0 to 6 V
4
3.25
3.6
V
V
V
VSHUT
VAVDD
VDD falling, 6 to 0 V
CVDD = 1 µF
2
2.1
SUPPLY AND LEAKAGE CURRENT
Cell1 through Cell5 = 4 V, VDD = 20
V, No cell balancing
8
15
µA
ICC
NORMAL mode current
Cell balancing cells 3, 4 or 5
48
2
80
3
µA
μA
IHIB
Cell1 through Cell5 = 4 V, VDD = 20
V, HIBERNATE mode
HIBERNATE mode current
ICFAULT
IOFF
Fault condition current
State comparator on
10
0
15
µA
µA
SHUTDOWN mode current
VDD < VSHUT, CTRC/CTRD floating
0.5
All cell voltages = 4 V, open-wire
disable configuration
ILKG_OW_DIS
Input leakage current at VCx pins
Open-wire sink current at VCx pins
Open-wire sink current at VCx pins
Open-wire sink current at VCx pins
–100
100
nA
All cell voltages = 4 V, 100-nA
configuration
ILKG_100nA
ILKG_200nA
30
95
110
210
175
315
nA
nA
All cell voltages = 4 V, 200-nA
configuration
ILKG_400nA
All cell voltages = 4 V, 400-nA
configuration
220
425
640
nA
PROTECTION ACCURACIES
Overvoltage programmable
threshold range
VOV
VUV
3000
1200
4575
3000
mV
mV
Undervoltage programmable
threshold range
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25
V unless otherwise noted.
PARAMETER
TEST CONDITIONS
TA = 25°C, OV detection accuracy
TA = 25°C, UV detection accuracy
TA = 0 to 60°C
MIN
–10
–18
–28
–40
TYP
MAX
UNIT
10
mV
18
mV
VVA
OV, UV, detection accuracy
26
mV
TA = –40 to +85°C
40
mV
OV hysteresis programmable
threshold range
VHYS_OV
VHYS_UV
0
0
400
800
mV
mV
UV hysteresis programmable
threshold range
Threshold for 65°C based on a 10k
pullup and 103AT thermistor
19.69%
17.28%
20.56%
18.22%
21.86%
19.51%
VTB
VTB
Overtemperature in discharge
programmable threshold
VOTD
Threshold for 70°C based on a 10k
pullup and 103AT thermistor
Recovery threshold at 55°C for
when VOTD is at 65°C based on a
10k pullup and 103AT thermistor
25.18%
22.05%
26.12%
23.2%
27.44%
24.24%
VTB
VTB
Overtemperature in discharge
recovery
VOTD_REC
Recovery threshold at 60°C for
when VOTD is at 70°C based on a
10k pullup and 103AT thermistor
Threshold for 45°C based on a 10k
pullup and 103AT thermistor
32.14%
29.15%
32.94%
29.38%
34.54%
31.45%
VTB
VTB
Overtemperature in charge
programmable threshold
VOTC
Threshold for 50°C based on a 10k
pullup and 103AT thermistor
Recovery threshold at 35°C for
when VOTD is at 45°C based on a
10k pullup and 103AT thermistor
38.63%
36.18%
40.97%
36.82%
40.99%
38.47%
VTB
VTB
Overtemperature in charge
recovery
VOTC_REC
Recovery threshold at 40°C for
when VOTD is at 50°C based on a
10k pullup and 103AT thermistor
Threshold for –20°C based on a 10k
pullup and 103AT thermistor
86.41%
80.04%
87.14%
80.94%
89.72%
83.10%
VTB
VTB
Undertemperature in discharge
programmable threshold
VUTD
Threshold for –10°C based on a 10k
pullup and 103AT thermistor
Recovery threshold at –10°C for
when VUTD is at –20°C based on a
10k pullup and 103AT thermistor
80.04%
80.94%
83.10%
VTB
Undertemperature in discharge
recovery
VUTD_REC
Recovery threshold at 0°C for when
VUTD is at –10°C based on a 10k
pullup and 103AT thermistor
71.70%
75.06%
73.18%
77.22%
74.86%
78.32%
VTB
VTB
Threshold for –5°C based on a 10k
pullup and 103AT thermistor
Undertemperature in charge
programmable threshold
VUTC
Threshold for 0°C based on a 10k
pullup and 103AT thermistor
71.70%
68.80%
73.18%
69.73%
74.86%
71.71%
VTB
VTB
VUTC_REC
Recovery threshold at 5°C for when
VUTC is at –5°C based on a 10k
pullup and 103AT thermistor
Undertemperature in Charge
Recovery
Recovery threshold at 10°C for
when VUTC is at 0°C based on a 10k
pullup and 103AT thermistor
64.67%
65.52%
67.46%
VTB
VOCC
Overcurrent charge programmable
5
80
mV
mV
threshold range, (VSRP-VSRN
)
Overcurrent discharge 1
programmable threshold range
VOCD1
–85
–10
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
8
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25
V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Overcurrent discharge 2
programmable threshold range
VOCD2
VSCD
VCCAL
VCCAH
–170
–20
mV
Short circuit discharge
programmable threshold range
–340
–30 %
–20 %
–40
30 %
20 %
mV
OCD1 detection accuracy at lower
thresholds
VOCD1 ≤ 20 mV
OCC, OCD1, OCD2, SCD
detection accuracy
VOCD1 > 20 mV; all OCC, OCD2
and SCD threshold ranges
Open-wire fault voltage threshold
at VCx per cell with respect to
VCx-1
VOW
Voltage falling on VCx, 3.6 V to 0 V
Voltage rising on VCx, 0 V to 3.6 V
450
500
100
550
mV
mV
VOW_HYS
Hysteresis for open wire fault
PROTECTION DELAYS
0.5-s delay option
1-s delay option
2-s delay option
4.5-s delay option
1-s delay option
2-s delay option
4.5-s delay option
9-s delay option
0.4
0.8
1.8
4
0.5
1
0.8
1.4
2.7
5.2
1.5
2.7
5.5
10.2
5.3
tOVn_DELAY
Overvoltage detection delay time
s
s
2
4.5
1
0.8
1.8
4
2
tUVn_DELAY
Undervoltage detection delay time
Open-wire detection delay time
4.5
9
8
tOWn_DELAY
tOTC_DELAY
3.6
4.5
s
s
Overtemperature charge detection
delay time
3.6
3.6
3.6
3.6
4.5
4.5
4.5
4.5
5.3
5.3
5.3
5.3
Undertemperature charge
detection delay time
tUTC_DELAY
tOTD_DELAY
tUTD_DELAY
s
s
s
Overtemperature discharge
detection delay time
Undertemperature discharge
detection delay time
10-ms delay option
20-ms delay option
45-ms delay option
90-ms delay option
180-ms delay option
350-ms delay option
700-ms delay option
1420-ms delay option
5-ms delay option
8
17
10
20
15
26
36
45
52
78
90
105
205
405
825
1620
8
Overcurrent discharge 1 detection
delay time
tOCD1_DELAY
ms
155
320
640
1290
4
180
350
700
1420
5
10-ms delay option
20-ms delay option
45-ms delay option
90-ms delay option
180-ms delay option
350-ms delay option
700-ms delay option
8
10
15
17
20
26
36
45
52
Overcurrent discharge 2 detection
delay time
tOCD2_DELAY
ms
78
90
105
205
405
825
155
320
640
180
350
700
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25
V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
528
220
TYP
960
400
MAX
1450
610
UNIT
tSCD_DELAY
tSCD_DELAY
Short-circuit detection delay time
Short-circuit detection delay time
960-µs delay option
us
400-µs delay option
µs
Overcurrent charge detection
delay time
tOCC_DELAY
8
10
12
ms
Overcurrent discharge 1,
Overcurrent discharge 2,
Overcurrent charge and short-
circuit recovery delay time
250-ms option
500-ms option
225
250
275
tCD_REC
ms
450
500
550
CHARGE AND DISCHARGE FET DRIVERS
VDD ≥ 12 V, CL = 10 nF
VDD < 12 V, CL = 10 nF
11
12
14
VDD
0.5
V
V
V
VFETON
CHG/DSG on
CHG/DSG off
VDD – 1.5
VFETOFF
1-mA resistive load, CHG clamped
to ground when CHG/DSG is off.
tCHGON
CHG on rise time
DSG on rise time
CHG off fall time
DSG off fall time
CHG off resistance
DSG off resistance
CL = 10 nF, 10% to 90%
CL = 10 nF, 10% to 90%
CL = 10 nF, 90% to 10%
CL = 10 nF, 90% to 10%
CHG off and pin held at 2V
DSG off and pin held at 100 mV
50
2
150
75
µs
µs
µs
µs
kΩ
Ω
tDSGON
tCHGOFF
tDSGOFF
RCHGOFF
RDSGOFF
15
5
30
15
0.3
0.5
10
0.75
16
CELL BALANCING
VHYST Hysteresis between overvoltage
TA = 25°C
TA = 25°C
50
50
200
200
mV
mV
and full charge voltage range
(VOV – VFC, 4 steps of 50 mV)
VSTEP
Difference between the
cell balancing threshold
voltages (VCBTH – VCBTL, 4
steps of 50 mV)
VCBIL
CBI low threshold
CBI deglitch period
0.5
20
V
tCBI_DEG
100
12
ms
Cell balancing internal FET
resistance
Cell1 through Cell5 = 4 V, VDD = 20
V
RBAL
8
Ω
DBAL
tBAL
Cell balancing duty cycle
Only one cell balanced in the stack
90 %
521
Odd and even cell group balancing
duration
ms
HIBERNATE MODE
VPRESH
PRES High Threshold
1.25
1.5
4.5
1.75
V
s
tPRES_DEG_ENT
PRES deglitch time (hibernate
entry)
tPRES_DEG_EXT
PRES deglitch time (hibernate exit)
10
ms
CTRC AND CTRD CONTROL
With respect to VSS. Enabled <
MAX
VCTR1
Enable FET driver (VSS)
0.6
V
VCTR2
Enable FET driver (Stacked)
Disable FET driver
Enabled > MIN
VDD + 2.2
2.04
V
V
V
VCTRDIS
VCTRMAXV
Disabled between MIN and MAX
ICTR = 600 nA
VDD + 0.7
VDD + 5
CTRC and CTRD clamp voltage
VDD + 2.8
VDD + 4
8
CTRC and CTRD deglitch for ON
signal
tCTRDEG_ON
ms
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
10
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.5 Electrical Characteristics (continued)
Typical values stated at TA = 25°C and VDD = 20 V. MIN and MAX values stated with TA = –40°C to 85°C and VDD = 3 to 25
V unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CTRC and CTRD deglitch for OFF
signal
tCTRDEG_OFF
8
ms
CURRENT STATE COMPARATOR
VSTATE_D
Discharge qualification threshold1 Measured at SRP-SRN
–1.875
–1.25
1.875
1.25
mV
mV
mV
mV
ms
Discharge qualification threshold1
Measured at SRP-SRN
hysteresis
VSTATE_D_HYS
VSTATE_C
VSTATE_C_HYS
tSTATE
Charge qualification threshold1
Measured at SRP-SRN
Measured at SRP-SRN
Charge qualification threshold1
hysteresis
State detection qualification time
1.2
LOAD DETECTION AND LOAD REMOVAL DETECTION
VLDCLAMP
ILDCLAMP
VLDT
LD clamp voltage
LD clamp current
LD threshold
ILDCLAMP = 300 µA
VLDCLAMP = 18 V
16
1.25
1
19
20
450
V
µA
V
OPEN pack terminals
1.3
200
1.5
1.35
RLD_INT
tLD_DEG
CCFG PIN
LD input resistance when enabled Measured to VSS
LD detection de-glitch
kΩ
ms
2.3
CCFG threshold low (ratio of
3-cell configuration
VCCFGL
VCCFGH
10%
100%
45%
AVDD
AVDD
VAVDD
)
CCFG threshold high (ratio of
VAVDD
4-cell configuration
65%
25%
)
CFG threshold high-Z (ratio of
VAVDD
5-cell configuration, CCFG floating,
internally biased
VCCFGHZ
33%
6
AVDD
ms
)
tCCFG_DEG
CCFG deglitch
CUSTOMER TEST MODE
Customer test mode entry voltage
at VDD
VCTM
VDD > VC5 + VCTM, TA = 25°C
VDD > VC5 + VCTM, TA = 25°C
TA = 25°C
8.5
50
10
V
Delay time to enter and exit
customer test mode
tCTM_ENTRY
tCTM_DELAY
ms
ms
Delay time of faults while in
customer test mode
200
100
Fault recovery time of OCD1,
OCD2, and SCD faults while in
customer test mode
250-ms and 500-ms options, TA
25°C
=
tCTM_OC_REC
ms
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
8.6 Typical Characteristics
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-4
0
4
8
12
16
20
24
28
32
-30
-25
-20
-15
-10
-5
0
5
Voltage Applied to Pin (V)
Voltage applied (V)
D001
D002
图 8-1. Current into the PRES Pin
图 8-2. LPWR Current
0.7
1.2
1.1
1
CTRC Current
CTRD Current
Bal
No bal
0.6
0.5
0.4
0.3
0.2
0.1
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
0
2.5
5
7.5
10
12.5
15
17.5
20
22.5
-0.6
0
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
Applied Voltage (V)
V CBO - Top of Stack (V)
D003
D004
图 8-3. CTRC and CTRD Current
80
图 8-4. CBO Current Input at 18 V
3.28
ICBI
70
3.2
AVDD
60
50
3.12
3.04
2.96
2.88
2.8
40
30
20
10
2.72
2.64
2.56
2.48
2.4
0
-10
-20
-30
-40
-50
-60
-70
-80
2.32
2.24
2.16
2.08
2
-0.3
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
3
3.3 3.6
V CBI
D005
图 8-5. CBI Input Current vs. VCBI
9.1 Overview
The BQ77915 device is a full-feature stackable primary protector for li-ion/li-polymer batteries with a smart
cell-balancing algorithm. The device implements a suite of protections including:
•
Cell voltage: overvoltage, undervoltage
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
12
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
•
•
•
•
Current: overcurrent charge, overcurrent discharge 1 and 2, short circuit discharge
Temperature: overtemperature and undertemperature in charge and discharge
PCB: cell open-wire connection
FET body diode protection
Protection thresholds and delays are factory-programmed and available in a variety of configurations.
The BQ77915 device supports 3-series to 5-series cell configurations. Up to four devices can be stacked to
support ≥6-series cell configurations, providing protections up to a 20-series cell configuration. It is possible to
support greater than 20-series cell configurations, but with careful consideration of delays.
The device has an ultra-low current HIBERNATE mode for shipping and storage. The device also features a
smart cell-balancing algorithm to minimize cell-to-cell imbalance. The device has built-in CHG and DSG drivers
for low-side N-channel FET protection, which automatically opens up the CHG and/or DSG FETs after protection
delay time when a fault is detected. A set of CHG/DSG overrides is provided to allow disabling of the CHG
and/or DSG driver externally. Although the host system can use this function to disable the FET control, the main
usage of these pins is to channel down the FET control signal from the upper device to the lower device in a
cascading configuration in ≥6-series battery packs.
9.1.1 Device Functionality Summary
表 9-1. Device Functionality Summary
FAULT DESCRIPTOR
FAULT DETECTION THRESHOLD and DELAY OPTIONS
FAULT RECOVERY METHOD and SETTING OPTIONS
OV
UV
Overvoltage
3 V to 4.575 V (25-mV step)
0.5, 1, 2, 4.5 s
Hysteresis
0, 100, 200, 400 mV
1.2 V to 3 V
(100-mV step for < 2.5 V,
50-mV step for ≥ 2.5 V)
Undervoltage
1, 2, 4.5, 9 s
Load Removal + Hysteresis
0, 200, 400, 800 mV
Open wire (cell to pcb
disconnection)
0 (disabled), 100 nA, 200 nA,
400 nA
OW
4.5 s
4.5 s
4.5 s
4.5 s
4.5 s
10 ms
Restore bad VCx to pcb connection
Hysteresis or Load Removal + Hysteresis
Hysteresis
VCx > VOW
10°C
Overtemperature during
discharge
OTD(1)
OTC(1)
UTD(1)
UTC (1)
OCC
65°C or 70°C
Overtemperature during
charge
45°C or 50°C
10°C
Undertemperature during
discharge
–20°C or –10°C
Hysteresis
10°C
Undertemperature during
charge
–5°C or 0°C
Hysteresis
10°C
Timer auto-release and load detection, timer
auto-release only, load detection only
Overcurrent during charge
5 mV to 80 mV (5-mV step)
–10 mV to –85 mV (5-mV step)
Overcurrent1 during
discharge
10, 20, 45, 90, 180, 350, 700,
1420 ms
OCD1
OCD2
SCD
250 ms or 500 ms
Overcurrent1 during
discharge
–20 mV to –170 mV (10-mV
step)
5, 10, 20, 45, 90, 180, 350,
700 ms
Timer auto-release and load removal, timer
auto-release only, load removal only
–40 mV to –340 mV (20-mV
step)
Short circuit discharge
400, 960 µs
Disable via external control or
CHG signal override control via CHG signal from the upper tCTRDEG_ON
device in stack configuration
Enable via external control or via CHG signal
from the upper device in stack configuration
CTRC
CTRD
tCTRDEG_OFF
Disable via external control or
DSG signal override control via DSG signal from the upper tCTRDEG_ON
device in stack configuration
Enable via external control or via DSG signal
from the upper device in stack configuration
tCTRDEG_OFF
(1) These thresholds are target-based on temperature, but they are dependent on external components that could vary based on
customer selections. The circuit is based on a 103AT NTC thermistor connected to TS and VSS, and a 10-kΩ resistor connected to
VTB and TS. Actual thresholds must be determined in mV; refers to the over- and undertemperature mV threshold in the Electrical
Characteristics table.
表 9-2. Cell Balancing Threshold Summary
NAME
Description
Options
VSTART
Start threshold for cell balancing
3.5 V, 3.8 V
Hysteresis between overvoltage and full charge voltage range (VOV
– VFC)
VHYST
VSTEP
50 mV, 100 mV, 150 mV, 200 mV
50 mV, 100 mV, 150 mV, 200 mV
Difference between the cell balancing threshold voltages (VCBTH –
VCBTL)
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
9.2 Functional Block Diagram
CCFG
VDD
AVDD
Configuration
Logic
BG
Reference
Bias
VDIG Regulator
& Shutdown
VTB
POR
VC5
VC4
VC3
TS
Compare
1
EEPROM
MUX
VC2
VC1
CTRC
CTRD
Stack
Interface
VC0
Open
Wire
Bq77915
Control
Logic
CHG
Driver
CHG
DSG
CBI
Cell
Balancing
CBO
DSG Driver
MUX
Load
Detection
LD
Compare
2
OCD½
Delay
OCDP
SRP
SRN
State
Compare
LPWR
PRES
Hibernate
Mode
Clock
And
WDT
VSS
9.3 Feature Description
9.3.1 Protection Summary
Two comparators are time-multiplexed to detect all of the protection fault conditions, and to measure cell
voltages for balancing. Each of the comparators runs on a time-multiplexed schedule and cycles through the
assigned protection fault checks and voltage measurements. Comparator 1 checks for OV, UV, OW, OTC, OTD,
UTC, and UTD protection faults and measure individual cell voltages for balancing. Comparator 2 checks for
OCD1, OCD2, SCD, and OCC protection faults. For OV, UV, and OW protection faults and cell balancing, every
cell is checked individually in a round-robin fashion, starting with cell 1 and ending with the highest selected cell.
The number of the highest cell is configured using the CCFG pin.
Devices can be ordered with various timing and hysteresis settings. See 表 9-1 for more details.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
14
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
9.3.2 Fault Operation
9.3.2.1 Operation in OV
An OV fault detection occurs when at least one of the cell voltages is measured above the OV threshold, VOV for
a time of OV delay, tOVn_DELAY. The CHG FET is turned off. The OV fault recovers when the voltage of the cell in
fault is below the (OV threshold – OV hysteresis, VHYS_OV) for a time of OV delay.
The device assumes an OV fault after reset, and clears automatically after an OV delay if all cell voltages are
below the OV threshold minus hysteresis. In the event of an overvoltage fault condition on a particular cell, the
balancing FET corresponding to that cell is turned on until the cell voltage drops to the full charge voltage or until
the cell has recovered from overvoltage fault condition, whichever occurs earlier. See Cell Balancing for more
details.
The state comparator is turned on when CHG is turned off. If a discharge current is detected, the device
immediately switches the CHG back on. The response time of the state comparator is typically in 700 µs and
should not pose any disturbance in the discharge event.
9.3.2.2 Operation in UV
A UV fault detection is when at least one of the cell voltages is measured below the UV threshold, VUV, for a
duration of a UV delay, tUVn_DELAY. The DSG FET is turned off. The UV fault recovers when:
•
•
The voltage of the cell in fault goes above the (UV threshold + UV hysteresis, VHYS_UV) for a time of a UV
delay OR
The voltage of the cell in fault goes above the (UV threshold + UV hysteresis, VHYS_UV) for a time of a UV
delay and the load is removed.
The state comparator might turn on the DSG FET before the cell voltage recovers to protect the body diode.
To minimize device supply current when a UV fault has occurred or CTRD was driven to the DISABLED state,
the BQ77915 device disables all discharge overcurrent detection blocks. Upon recovery from the fault or when
CTRD is no longer externally driven, all discharge overcurrent detection blocks are reactivated.
9.3.2.3 Operation in OW
An OW fault detection is when at least one of the cell voltages is measured below the OW threshold, VOW, for a
duration of OW delay, tOWn_DELAY. CHG and DSG are turned off. The OW fault recovers when the cell voltage in
fault is above the OW threshold + OW hysteresis, VOW_HYS, for a time of OW delay.
The tOWn_DELAY time starts when the voltage at a given cell is detected below the VOW threshold and is not from
the time that the actual event of an open wire occurs. During an open-wire event, it is common that the device
detects an undervoltage and/or overvoltage fault before detecting an open-wire fault. This may occur due to the
differences in fault thresholds, fault delays, and the VCx pin filter capacitor values. To ensure that CHG and DSG
return to normal operation mode, the OW, OV, and UV faults' recovery conditions must be met.
9.3.2.4 Operation in OCD1
An OCD1 fault is when the discharge load is high enough that the voltage across the RSNS resistor (VSRP–VSRN
)
is measured below the OCD1 voltage threshold, VOCD1, for a duration of OCD1 delay, tOCD1_DELAY. CHG and
DSG are turned off.
The OCD1 fault recovers when:
•
•
•
Load removal is detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
9.3.2.5 Operation in OCD2
An OCD2 fault is when the discharge load is high enough that the voltage across the RSNS resistor (VSRP–VSRN
)
is measured below the OCD2 voltage threshold, VOCD2, for a duration of OCD2 delay, tOCD2_DELAY. CHG and
DSG are turned off.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
The OCD2 fault recovers when:
•
•
•
Load removal detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
9.3.2.6 Programming the OCD1/2 Delay Using the OCDP Pin
OCD1 and OCD2 detection delays are programmed by the resistor connected from the OCDP pin to VSS. The
device checks for the resistor value at power-up. For the bottom device in a stack, 表 9-3 shows how the resistor
values should be chosen.
表 9-3. OCD1/2 Delay Using OCDP Pin
Resistor Value
750 kΩ±1%
604 kΩ±1%
487 kΩ±1%
383 kΩ±1%
294 kΩ±1%
196 kΩ±1%
100 kΩ±1%
OCD1 Delay
1420 ms
700 ms
350 ms
180 ms
90 ms
OCD2 Delay
700 ms
350 ms
180 ms
90 ms
45 ms
20 ms
45 ms
EEPROM Delay Options (EC Table)
The OCD2 delay is roughly half of the OCD1 delay when any of the first six resistors are connected from the
OCDP pin to VSS. However, if a 100-kΩ resistor is connected, the OCD1 and OCD2 delays are independent of
each other and can be chosen to have any value provided in the EC table.
For any device other than the bottom device in a stacked configuration, a 10-MΩ resistor must be connected
from the OCDP pin of that device to the VSS pin of the device.
If the OCDP pin is left open, the OCD1 and OCD2 delays are determined by the EEPROM settings.
9.3.2.7 Operation in SCD
An SCD fault is when the discharge load is high enough that the voltage across the RSNS resistor, (VSRP–VSRN),
is measured below the SCD voltage threshold, VSCD, for a duration of SCD delay, tSCD_DELAY. CHG and DSG are
turned off.
The SCD fault recovers when:
•
•
•
Load removal detected only, VLD < VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load removal is detected.
9.3.2.8 Operation in OCC
An OCC fault is when the charging current is high enough that the voltage across the RSNS resistor, (VSRP
–
VSRN), is measured above the OCC voltage threshold, VOCC, for a duration of OCC delay, tOCC_DELAY. CHG and
DSG are turned off.
The OCC fault recovers when:
•
•
•
Load detected only, VLD > VLDT, OR
Overcurrent Recovery Timer, tCD_REC, expiration only OR
Overcurrent Recovery Timer expiration and load is detected.
9.3.2.9 Overcurrent Recovery Timer
The timer expiration method activates an internal recovery timer as soon as the initial fault condition exceeds
the OCD1/OCD2/SCD/OCC time. When the recovery timer reaches its limit, both of the CHG and DSG drivers
are turned back on. If the combination option of the timer expiration AND load removal/detection is used, then
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
16
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
the load removal/detection condition is only evaluated upon expiration of the recovery timer, which can have an
expiration period of tCD_REC
.
9.3.2.10 Load Detection and Load Removal Detection
The load detection and removal detection features are implemented with the LD pin. When no undervoltage fault
and current fault conditions are present, the LD pin is held in an open-drain state. Once any UV, OCD1, OCD2,
OCC, or SCD fault occurs and load removal or detection is selected as device of the recovery conditions, a high
impedance pulldown path to VSS is enabled on the LD pin. With an external load still present, the LD pin will
be externally pulled high: It is internally clamped to VLDCLAMP and should also be resistor-limited through RLD
externally to avoid conducting excessive current. If the LD pin voltage exceeds VLDT for tLD_DEG, it is interpreted
as a load present condition and is one of the recovery mechanisms selectable for an OCC fault. When the
load is eventually removed, the internal high-impedance path to VSS should be sufficient to pull the LD pin
below VLDT for tLD_DEG. This is interpreted as a load removed condition and is one of the recovery mechanisms
selectable for UV, OCD1, OCD2, and SCD faults.
表 9-4. Load State
LD PIN
LOAD STATE
Load present
Load removed
≥ VLDT for tLD_DEG
< VLDT for tLD_DEG
9.3.2.11 Operation in OTC
An OTC fault is when the temperature increases such that the voltage across an NTC thermistor goes below
the OTC voltage threshold, VOTC, for an OTC delay time, tOTC_DELAY. CHG is turned off. The state comparator is
turned on when CHG is turned off. If a discharge current is detected, the device immediately switches the CHG
back on. The response time of the state comparator is typically in 700 µs and should not pose any disturbance
in the discharge event. The OTC fault recovers when the voltage across the thermistor goes above the OTC
recovery threshold, VOTC_REC, for an OTC delay time.
9.3.2.12 Operation in OTD
An OTD fault is when the temperature increases such that the voltage across an NTC thermistor goes below the
OTD voltage threshold, VOTD, for an OTD delay time, tOTD_DELAY. CHG and DSG are turned off.
The OTD fault recovers when:
•
•
The voltage across thermistor gets above OTD recovery threshold, VOTD_REC, for a time of OTD delay OR
The voltage across thermistor gets above OTD recovery threshold, VOTD_REC, for a time of OTD delay and
load is removed.
9.3.2.13 Operation in UTC
A UTC fault occurs when the temperature decreases such that the voltage across an NTC thermistor gets above
the UTC voltage threshold, VUTC, for a time of a UTC delay, tUTC_DELAY. CHG is turned off. The state comparator
is turned on when CHG is turned off. If a discharge current is detected, the device will immediately switch
the CHG back on. The response time of the state comparator is typically in 700 µs and should not pose any
disturbance in the discharge event. The UTC fault recovers when the voltage across thermistor gets below UTC
recovery threshold, VUTC_REC, for a time of UTC delay.
9.3.2.14 Operation in UTD
A UTD fault occurs when the temperature decreases such that the voltage across an NTC thermistor goes
above the UTD voltage threshold, VUTD, for a UTD delay time, tUTD_DELAY. CHG and DSG are turned off. The
UTD fault recovers when the voltage across thermistor gets below UTD recovery threshold, VUTD_REC, for a time
of UTD delay.
9.3.3 Protection Response and Recovery Summary
表 9-5 summarizes how each fault condition affects the state of the DSG and CHG output signals, as well as the
recovery conditions required to resume charging and/or discharging. As a rule, the CHG and DSG output drivers
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
are enabled only when no respective fault conditions are present. When multiple simultaneous faults (such as an
OV and OTD) are present, all faults must be cleared before the FET can resume operation.
表 9-5. Fault Condition, State, and Recovery Methods
RECOVERY
DELAY
FAULT
CTRC disabled
CTRD disabled
OV
FAULT TRIGGER CONDITION CHG
DSG
RECOVERY METHOD
TRIGGER DELAY
CTRC disabled for deglitch
delay time
OFF
—
CTRC must be enabled for deglitch delay time
tCTRDEG_ON
tCTRDEG_OFF
CTRD disabled for deglitch
delay time
—
OFF CTRD must be enabled for deglitch delay time
V(Cell) rises above VOV for
delay time
OFF
—
V(Cell) drops below VOV – VHYS_OV for delay
tOVn_DELAY
tUVn_DELAY
tOWn_DELAY
V(Cell) drops below VUV for
delay time
DSG FET turned on after Load is removed and
V(Cell) rises above VUV + VHYS_UV for delay.
UV
—
OFF
OFF
VCX – VCX–1 < VOW for delay
time
Bad VCX recovers such that VCX – VCX–1
VOW + VOW_HYS for delay
>
OW
OFF
Recovery delay expires, OR
OFF LD detects > VLDT, OR
(VSRP – VSRN) > VOCC for
delay time
OCC
OFF
tOCC_DELAY
tCD_REC
Recovery delay expires + LD detects > VLDT
(VSRP – VSRN) < VOCD1,
VOCD2, or VSCD for delay
time
Recovery delay expires, OR
OFF LD detects < VLDT, OR
tOCD1_DELAY
tOCD2_DELAY
tSCD_DELAY
,
,
OCD1, OCD2,
SCD
OFF
OFF
tCD_REC
Recovery delay expires + LD detects < VLDT
Temperature rises above TOTC
for delay time
OTC(1)
OTD(1)
—
OFF
—
Temp drops below TOTC – TOTC_REC for delay
tOTC_DELAY
Temp drops below TOTD – TOTD_REC for delay,
OR
Temp drops below TOTD – TOTD_REC for delay
and Load is removed
Temperature rises above TOTD
for delay time
OFF
tOTD_DELAY
Temperature drops below TUTC
for delay time
Temperature rises above TUTC + TUTC_REC for
delay
UTC(1)
UTD(1)
OFF
OFF
tUTC_DELAY
tUTD_DELAY
Temp drops below TUTD for
delay time
OFF Temp rises above TUTD + TUTD_REC for delay
(1) TUTC, TUTD, TUTC_REC, and TUTD_REC correspond to the temperature produced by VUTC, VUTD, VUTC_REC, and VUTD_REC of the selected
thermistor resistance.
To prevent FET damage, there are times when the CHG FET or DSG FET may be enabled even though a fault
event has occurred. See the State Comparator section for details.
9.3.4 Cell Balancing
Cell balancing is performed by comparing the cell voltages with respect to cell balancing threshold voltages,
evaluating the results of the comparison and controlling the cell balancing FET, which over a period of time will
allow for closer cell voltages, thereby extending battery pack life. The conditions for performing cell balancing
are: CBI is connected to VSS, no device in the stack is in a fault condition, and the pack is charging. The State
Comparator section lists the conditions for the device's charging state.
CBI is the cell balancing input pin. It enables cell balancing function for the device.
•
•
Leave the CBI pin floating to disable cell balancing. An internal circuit pulls up the CBI pin to AVDD in this
case.
Connect CBI to VSS to enable cell balancing.
In a single device, cell balancing of all the odd numbered cells can happen at the same time, and balancing of
all the even numbered cells can also happen at the same time, but odd and even cells are not balanced at the
same time. When devices are stacked on top of each other, it must be ensured in the PCB layout that the trace
from VC5 pin to a cell and the trace from the VC0 pin of the next upper device to the immediately higher cell are
kept separate.
All cell balancing FETs are turned off during voltage measurements. If odd numbered and even numbered cells
need balancing at the same time, one single cycle time tBAL is dedicated for odd numbered cells alone followed
by the next tBAL dedicated for even numbered cells alone. See an example of adjacent cell balancing in 图 9-1.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
18
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
图 9-1. Balancing Cells 1, 2, and 3
In a stacked configuration, the CBO pin of the bottom device should be connected to the CBI pin of the next
upper device through a 10-kΩ resistor and so forth.
When a cell is in OV, its corresponding balancing FET will be turned on if CBI is connected to VSS and if there
are no discharge faults anywhere in the stack. The balancing FET will be ON until the cell voltage drops to VFC
or VOV – VHYS_OV, whichever occurs earlier.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
VOV
VFC
CV5
VCBTH
CV3
CV1
CV4
VCBTL
CV2
VSTART
图 9-2. Cell-Balancing Algorithm
VCBTL is the lower cell balancing threshold and VCBTH is the upper cell balancing threshold. In 图 9-2, the
balancing FET will be turned on only for the cell CV5. The BQ77915 VSTART is set at 3.8 V; therefore, cell
balancing starts only when individual cell voltages exceed 3.8 V. The difference between VCBTH and VCBTL can
be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV. The difference between
the VOV and VFC can also be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV.
When using the integrated MOSFETs for cell balancing, the cell monitor filter resistance RINI controls the amount
of cell balancing current the device can supply to the cells. Internal cell balancing should be used for cell
balancing currents up to 50 mA. External MOSFETs have to be used if higher cell balancing currents are
required. In the case of external balancing, the balancing current is controlled by the resistor RCB in series with
the external MOSFET, as shown in 图 9-3. The pin filter resistance RINE should be 1 kΩ and the capacitance
CINE should be 0.1 µF. The gate bias voltage necessary to turn on the FET connected to Cell(n) is generated by
the resistor RINE connected to the VC(n–1) pin. The external MOSFET must be selected with a threshold voltage
less than 1.7 V.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
20
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
RVDD
PACK+
CVDD
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
RINE
PRES
CBO
RCB
RCB
RCB
RCB
RCB
VC4
VC3
CBO
CINE
CCFG
RTS_PU
VC2
VC1
VTB
TS
RTS
bq77915
RINE
ROCD
CBI
VC0
VSS
OCDP
CBI
CINE
SRP
SRN
DSG
LPWR
LD
RINE
RINE
RINE
CHG
CINE
RDSG
RCHG
CINE
RLD
CINE
RGS
RGS
RINE
CINE
RSNS
PACKœ
图 9-3. Cell Balancing with External MOSFETs
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
9.3.5 HIBERNATE Mode Operation
Tool
Trigger
PACK+
System /
Charger
R2
PRES
VDD
+
Internal Weak
Pull-Down
œ
bq77915
+
LPWR
PRES
œ
VSS
R3
VDD
+
Internal Weak
Pull-Down
œ
bq77915
+
LPWR
œ
VSS
DSG
CHG
Q2
Q3
PACKœ
图 9-4. HIBERNATE Mode Simplified Schematic 1
PACK+
System /
Charger
R2
PRES
VDD
+
Internal Weak
Pull-Down
œ
bq77915
+
LPWR
PRES
œ
VSS
VDD
R3
+
Internal Weak
Pull-Down
œ
bq77915
+
LPWR
œ
VSS
DSG
CHG
Q2
Q3
PACKœ
图 9-5. HIBERNATE Mode Simplified Schematic 2
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
22
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
The BQ77915 device has two dedicated pins (PRES and LPWR) for HIBERNATE mode operation. Most of the
internal circuitry is turned off in HIBERNATE mode to save power. Charge and discharge FETs are turned off and
all fault protections are disabled.
The PRES pin has an internal pulldown connected to the pin, which pulls PRES low. When the PRES pin is
left floating (the system or charger is not connected to the pack), the load is not connected, and the device is
not in any fault condition, the device enters HIBERNATE mode after tPRES_DEG_ENT time. Once in HIBERNATE
mode, the system or the charger should drive this pin high (>VPRESH) through the resistor R2 for NORMAL mode
operation. When the battery pack (in HIBERNATE mode) is inserted to the tool/system or when a charger is
connected to the pack, the system has to provide a pull-up to the PRES pin, which puts the device back to
NORMAL mode. The device will exit HIBERNATE mode after a tPRES_DEG_EXT deglitch time.
In a stacked configuration, connect the LPWR pin of an upper device to the PRES pin of a lower device through
the resistor R3.
9.3.6 Configuration CRC Check and Comparator Built-In-Self-Test
To improve reliability, the device has a built-in CRC check for all the factory-programmable configurations, such
as the thresholds and delay time settings. When the device is set up in the factory, a corresponding CRC
value is also programmed to the memory. During normal operation, the device compares the configuration
setting against the programmed CRC periodically. A CRC error will reset the digital circuitry and increment the
CRC fault counter. The digital reset forces the device to reload the configuration as an attempt to correct the
configurations. A correct CRC check reduces the CRC fault counter. Three CRC fault counts will turn off both the
CHG and DSG drivers. If FETs are opened due to a CRC error, only a POR can recover the FET state and reset
the CRC fault.
In addition to the CRC check, the device also has built-in-self-test (BIST) on the comparators. The BIST runs in a
scheduler, and each comparator is checked for a period of time. If a fault is detected for the entire check period,
the particular comparator is considered at fault, and the CHG and DSG FETs are turned off. The BIST continues
to run by the scheduler even if a BIST fault is detected. If the next BIST result is good, the FET driver resumes
normal operation.
The CRC check and BIST check do not affect the normal operation of the device. However, there is not specific
indication when a CRC or BIST error is detected besides turning off the CHG and DSG drivers. If there is no
voltage, current, or temperature fault condition present, but CHG and DSG drivers remain off, it is possible either
CRC or BIST error is detected. Users can POR the device to reset the device.
9.3.7 Fault Detection Method
9.3.7.1 Filtered Fault Detection
The device detects a fault once the applicable fault is triggered after accumulating sufficient trigger sample
counts. The filtering scheme is based on a simple add/subtract. Starting with the triggered sample count cleared,
the counts go up for a sample that is taken across the tested condition (for example, above the fault threshold
when looking for a fault) and the counts go down for a sample that is taken before the tested condition (that
is, below the fault threshold). 图 9-6 shows an example of a signal that triggers a fault when accumulating five
counts above the fault threshold. Once a fault has been triggered, the trigger sample counts reset.
备注
With a filtered detection, when the input signal falls below the fault threshold, the sample count does
not reset but only counts down, as shown in 图 9-6. Therefore, it is normal to observe a longer delay
time if a signal is right at the detection threshold. The noise can push the delay count to be counting
up and down, resulting in a longer time for the delay counter to reach its final accumulated trigger
target.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
Based on fault trigger after 5 counts
Fault Threshold
Recovery Threshold
FAULT
FAULT
Sample
Triggered Sample Count
0
1
2
3
4
0
0
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
1
2
0
1
2
3
4
5
0
0
Looking for a fault
Looking for a recovery
Looking for a fault
图 9-6. Filtered Fault Detection
9.3.8 State Comparator
A small, low-offset analog state comparator monitors the sense resistor voltage (SRP–SRN) to determine when
the pack is in a DISCHARGE state less than a minimum threshold, VSTATE_D, or a CHARGE state greater
than a maximum threshold, VSTATE_C. The state comparator is used to turn the CHG FET on to prevent damage/
overheating during discharge in fault states that call for having only the CHG FET off, and vice versa for the DSG
FET during charging in fault that call for having only the DSG FET off. Also, the state comparator is turned on in
NORMAL mode (CHG and DSG FETs on) during cell balancing to ensure that cell balancing is performed only
when the pack is charging.
表 9-6 summarizes when the state comparator is operational. The state comparator is only on during faults
detected that call for only one FET to be turned off, and also in NORMAL mode during cell balancing to ensure
that cell balancing is performed only when the pack is charging.
表 9-6. State Comparator Operation Summary in Fault Conditions
MODE
NORMAL mode, no cell balancing
NORMAL mode, cell balancing
UV, CTRD
CHG
DSG
STATE COMP
ON
ON
OFF
ON
ON
VSTATE_C detection
VSTATE_C detection
VSTATE_D detection
OFF
ON
OFF
ON
OV, UTC, OTC, CTRC
OFF
OFF
OCD1, OCD2, SCD, OCC, UTD, OTD, OW
OFF
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
24
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
VSTATE_D_HYS
VSTATE_C_HYS
PACK IS DISCHARGING
PACK IS CHARGING
PACK IS CHARGING
PACK IS DISCHARGING
SRP - SRN
0 V
VSTATE_D
VSTATE_C
图 9-7. State Comparator Thresholds
Any time a CHG fault is present and a DSG fault is not present, the device will enable the state comparator. If
the pack is in a fault state where charging is prohibited but discharging is permitted (OV, OTC, UTC, and CTRC),
a discharge may occur. When this happens, the CHG FET driver will be turned on to avoid damage, as it will
otherwise carry the discharge current through its body diode. The state comparator (with the VSTATE_D threshold
and VSTATE_D_HYS hysteresis) remains on for the entire duration of a CHG fault with no DSG fault event.
If there is a DSG fault under CTRD conditions, the DSG FET would be turned on if charge is detected. The state
comparator (with VSTATE_C threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG
fault with no CHG fault event.
9.3.9 DSG FET Driver Operation
The DSG pin is driven high only when no related faults (UV, OW, OTD, UTD, OCD1, OCD2, SCD, OCC, and
CTRD disabled) are present and the device is not in HIBERNATE mode of operation. It is a fast switching driver
with a target on resistance of about 15 Ω–20 Ω and an off resistance of RDSGOFF. It is designed to enable
customers to select the optimized RGS value to archive the desirable FET rise and fall time per the application
requirement and the choice of FET characteristics. When the DSG FET is turned off, the DSG pin drives low and
all discharge overcurrent protections (OCD1, OCD2, SCD) are disabled to better conserve power. These resume
operation when the DSG FET is turned on. The device provides FET body diode protection through the state
comparator if one FET driver is on and the other FET driver is off.
The DSG driver may be turned on to prevent FET damage if the battery pack is charging while a discharge
inhibit fault condition is present. This is done by the state comparator. The state comparator (with VSTATE_C
threshold and VSTATE_C_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault
event.
•
If (SRP–SRN) ≤ (VSTATE_C – VSTATE_C_HYS) and no charge event is detected, the DSG FET output will remain
OFF due to the presence of a DSG fault.
•
If (SRP–SRN) > VSTATE_C and a charge event is detected, the DSG FET output will turn ON for body diode
protection.
See the 节 9.3.8 section for details.
The presence of any related faults, as shown in 图 9-8, results in the DSGFET_OFF signal.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
DSGFET_OFF_UVn
DSGFET_OFF_OCD1
DSGFET_OFF_OCD2
DSGFET_OFF_OCC
HIBERNATE
DSGFET_OFF
DSGFET_OFF_SCD
DSGFET_OFF_UTD
DSGFET_OFF_OTD
OWn
CTRD
图 9-8. Faults that Can Qualify DSGFET_OFF
9.3.10 CHG FET Driver Operation
The CHG pin is driven high only when no related faults (OV, OW, OTC, UTC, OTD, UTD, OCD1, OCD2, SCD,
OCC, and CTRC disabled) are present and the pack is not in HIBERNATE mode of operation. The CHG pin
is used to drive the CHG FET, which is designed to be used on the single device configuration or used by the
bottom device in a stack configuration.
Turning off the CHG pin has no influence on the overcurrent protection circuitry. The CHG pin is designed to turn
on very quickly; the internal on resistance is about 2 kΩ. The CHG FET turn off relies on the external resistor
connected in parallel to the gate-source nodes of the NCH power FET.
The CHG FET may be turned on to protect the FET's body diode if the pack is charging, even if a charging
inhibit fault condition is present. This is done through the state comparator. The state comparator (with VSTATE_D
threshold and VSTATE_D_HYS hysteresis) remains on for the entire duration of a DSG fault with no CHG fault
event.
•
If (SRP–SRN) > (VSTATE_D + VSTATE_D_HYS) and no discharge event is detected, the CHG FET output will
remain OFF due to the presence of a CHG fault.
•
If (SRP–SRN) ≤ VSTATE_D and a discharge event is detected, the CHG FET output will turn ON for body diode
protection.
The CHGFET_OFF signal is a result of the presence of any related faults as shown in 图 9-9.
CHGFET_OFF_OVn
CHGFET_OFF_UTC
CHGFET_OFF_OTC
CHGFET_OFF_OCD1
CHGFET_OFF_OCD2
CHGFET_OFF_OCC
CHGFET_OFF
HIBERNATE
CHGFET_OFF_SCD
CHGFET_OFF_UTD
CHGFET_OFF_OTD
OWn
CTRC
图 9-9. Faults that Can Qualify CHGFET OFF
9.3.11 External Override of CHG and DSG Drivers
The device allows direct disabling of the CHG and DSG drivers through the CTRC and CTRD pins, respectively.
图 9-10 shows the operation of the CTRC and CTRD pins. To support the simple-stack solution for higher-cell
count packs, these pins are designed to operate above the device’s VDD level. Connect a 10-MΩ resistor
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
26
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
between a lower device CTRC and CTRD input pins to an upper device's CHG and DSG output pins (see the
schematics in 节 9.3.13).
CTRC only enables or disables the CHG pin, while CTRD only enables or disables the DSG pin. When the
CTRx pin is in the DISABLED region, the respective FET pin will be off, regardless of the state of the protection
circuitry. When the CTRx pin is in either ENABLED region, the protection circuitry determines the state of the
FET driver.
备注
In any event where CTRC is disabled, CTRD is enabled, no DSG FET related faults are present, and
(SRP–SRN) < VSTATE_D, the CHG output pin will be held high regardless. In any event where CTRD
is disabled, CTRC is enabled, no charge FET related faults present, and (SRP–SRN) > VSTATE_C, the
DSG output pin will be held high regardless.
Both CTRx pins apply the fault-detection filtered method to improve the robustness of the signal detection. The
counter counts up if an ENABLED signal is sampled; the counter counts down if a DISABLED signal is sampled.
When the counter counts up from 0% to > 70% of its full range, which takes about 7-ms typical of a solid signal,
the CTRx pins take the signal as ENABLED. If the counter counts down from 100% to < 30% of its full range,
which takes about 7-ms typical of a solid signal, the CTRx pins take the signal as DISABLED. From a 0 count
counter (solid DISABLE), a solid ENABLE signal takes about tCTRDEG_ON time to deglitch. From a 100% count
(solid ENABLE), a solid DISABLE signal takes about tCTRDEG_OFF time to deglitch. Although such a filter scheme
provides a certain level of noise tolerance, it is highly recommended to shield the CTRx traces and keep the
traces as short as possible in the PCB layout design. The CTRx deglitch time will add onto the FET response
timing on OV, UV, and OW faults in a stack configuration. The tCTRDEG_OFF time adds an additional delay to the
fault detection timing and the tCTRDEG_ON time adds an additional delay to the fault recovery timing.
ENABLED
VCTR2
VCTRDIS (max)
VDD
DISABLED
(FET OFF)
VCTRDIS (min)
VCTR1
ENABLED
VSS
CHG driver set by CTRC
DSG driver set by CTRD
图 9-10. CTRC, CTRD Voltage Levels
9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
The BQ77915 device supports 3-series, 4-series, or 5-series packs. To avoid accidentally detecting a UV fault on
unused (shorted) cell inputs, the device must be configured for the specific cell count of the pack. This is set with
the configuration pin, CCFG, which is mapped as shown in 表 9-7. The device periodically checks the CCFG
status and takes tCCFG_DEG time to detect the pin status.
表 9-7. CCFG Configurations
CCFG
CONFIGURATION
CONNECT TO
VSS
< VCCFGL for tCCFG_DEG
Within VCCFGM for tCCFG_DEG
> VCCFGH for tCCFG_DEG
3 cells
4 cells
AVDD
5 cells
Floating
The CCFG pin should be tied to the recommended net from 表 9-7. The device compares the CCFG input
voltage to the AVDD voltage and should never be set above the AVDD voltage. When the device configuration
is for 5 series, leave the CCFG pin floating. The internal pin bias is approximately 33% of the AVDD voltage for
5-series configuration.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
RVDD
PACK+
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
CVDD
RHIB
RTS_PU
VC4
VC3
CBO
CCFG
VC2
VC1
VTB
TS
RTS
bq77915
RIN
RIN
RIN
ROCD
VC0
VSS
OCDP
CBI
SRP
SRN
DSG
LPWR
LD
CHG
CIN
RDSG
RCHG
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK–
图 9-11. 3-Series Configuration with Cell Balancing and HIBERNATE Mode Disabled
RVDD
PACK+
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
CVDD
PRES
RIN
VC4
VC3
CBO
CCFG
RTS_PU
CIN
RIN
VC2
VC1
VTB
TS
RTS
bq77915
ROCD
RCB
VC0
VSS
OCDP
CBI
CIN
RIN
SRP
SRN
DSG
LPWR
LD
CHG
CIN
RDSG
RCHG
RIN
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK–
图 9-12. 4-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
28
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
RVDD
PACK+
CVDD
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
RIN
PRES
VC4
VC3
CBO
CIN
CCFG
RTS_PU
RIN
VC2
VC1
VTB
TS
RTS
bq77915
ROCD
RCB
CIN
VC0
VSS
OCDP
CBI
RIN
SRP
SRN
DSG
LPWR
LD
CIN
CHG
RIN
RDSG
RCHG
CIN
RIN
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACK–
图 9-13. 5-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
9.3.13 Stacking Implementations
Higher than 5-series cell packs may be supported by daisy-chaining multiple devices. Each device ensures
OV, UV, OW, OTC, OTD, UTC, and UTD protections of its directly monitored cells, while any fault conditions
automatically disable the global CHG and/or DSG FET driver.
备注
Upper devices do not provide OCC, OCD1, OCD2, or SCD protections, as these are based on pack
current. For the BQ77915 device used on the upper stack, the SRP and SRN pins should be shorted
to prevent false detection.
To configure higher-cell packs, follow this procedure:
•
•
Each device must have a connection on at least each of its three lowest cell input pins.
It is highly recommended to connect higher cell count to the upper devices (for example, for a 7-series
configuration, connect four cells on the upper device and three cells on the bottom device). This is to provide
stronger CTRx signal to the bottom device.
•
Ensure that each device’s CCFG pin is configured appropriately for its specific number of cells (that is, three,
four, or five cells).
•
•
•
•
•
•
Connect the upper CHG pins with an RCTRx to the immediate lower device CTRC pin.
Connect the upper DSG pins with an RCTRx to the immediate lower device CTRD pin.
All upper devices should have their SRP and SRN pins shorted to their VSS pins.
Connect the upper CBI pins with an RCB to the immediate lower device CBO pin.
Connect the upper LPWR pins with an RHIB to the immediate lower device PRES pin.
Connect the upper OCDP pins with a 10-MΩ resistor to VSS. Use the lower OCDP pin to program the
OCD1/2 delay.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
RVDD
PACK+
CVDD
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
RIN
PRES
VC4
VC3
CBO
CIN
CCFG
RTS_PU
RIN
VC2
VC1
VTB
TS
RTS
bq77915
10 MΩ
CIN
VC0
VSS
OCDP
CBI
RIN
SRP
SRN
DSG
LPWR
LD
CIN
CHG
RIN
RCTRC
RCTRD
CIN
RIN
R2
CIN
RLD
CIN
RIN
RHIB
RVDD
RCB
CVDD
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
RIN
VC4
VC3
CBO
CIN
CCFG
RTS_PU
RIN
VC2
VC1
VTB
TS
RTS
bq77915
ROCD
RCB
CIN
VC0
VSS
OCDP
CBI
RIN
SRP
SRN
DSG
LPWR
LD
CIN
CHG
RIN
RDSG
RCHG
CIN
RIN
CIN
RLD
CIN
RIN
RGS
RGS
RSNS
PACKœ
图 9-14. 10-Series Configuration with Internal Cell Balancing and HIBERNATE Mode Enabled
9.3.14 Zero-Volt Battery Charging Inhibition
Once the device is powered up, it can pull the CHG pin up if the VDD ≥ VSHUT, which varies from about 1 V per
cell on a 3-series configuration to about 0.6 V per cell on a 5-series configuration. If the battery stack voltage
falls below VSHUT, the device is in SHUTDOWN mode and the CHG driver is no longer active and charging is not
allowed unless VDD rises above VPOR again.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
30
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
9.4 Device Functional Modes
9.4.1 Power Modes
9.4.1.1 Power On Reset (POR)
The device powers up when VDD ≥ VPOR. At POR, the following events occur:
•
•
•
A typical of 5-ms hold-off delay applies to both CHG and DSG drivers, keeping both drivers in the OFF state.
This is to provide time for the internal LDO voltage to ramp up.
The CTRC and CTRD deglitch occurs. During the deglitch time, the CHG and DSG driver remains off. Note
that the deglitch time masks out the 5-ms hold-off delay.
The device assumes an OV fault at POR; thus, the CHG driver is off for OV recovery time if all the cell
voltages are < (VOV – VHYS_OV). The OV recovery time starts after the 5-ms hold-off delay. If device reset
occurs when any cell voltage is above the OV hysteresis range, the CHG driver will remain off until an OV
recovery condition is met.
9.4.1.2 NORMAL Mode
This is the normal operation mode. All configured protections are active, no fault is detected, and both CHG
and DSG drivers are enabled. HIBERNATE mode is deactivated. While the device is in NORMAL mode, cell
balancing occurs if all the necessary conditions for balancing are valid. Refer to the Cell Balancing section for
details.
9.4.1.3 FAULT Mode
If any configured protection fault is detected, the device enters the FAULT mode. In this mode, the CHG and/or
DSG driver can be turned off depending on the fault. Refer to Fault Condition, State, and Recovery Methods for
details. When one of the FET drivers (either CHG or DSG) is turned off, while the other FET driver is still on, the
state comparator is activated for FET body diode protection.
9.4.1.4 HIBERNATE Mode
If the PRES pin is left floating, the device enters HIBERNATE mode operation. In this mode, all fault detection
and cell balancing is deactivated and the CHG and DSG drivers are turned off to reduce power consumption to
ultra-low levels. This mode of operation is recommended when the battery packs are in shipping or storage. The
device can be brought back to NORMAL mode by driving PRES high.
9.4.1.5 SHUTDOWN Mode
This is the lowest power consumption state of the device when VDD falls below VSHUT. In this mode, all fault
detections, CHG and DSG drivers are disabled. The device will wake up and enter NORMAL mode when VDD
rises above VPOR
.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
VDD falls below shutdown voltage threshold
VDD falls below shutdown voltage threshold
Shutdown Mode
Normal Mode
VDD falls below shutdown voltage threshold
PRES is floating, part enters hibernate
mode after 4.5 seconds
Detect any of the following: OV, UV, OW,
OCD1/2, SCD, OCC, OTC/D, UTC/D, CTRC/D
- Protections ON
- FET Drivers ON
- Cell Balancing allowed
Meet the corresponding fault
recovery condition
PRES is pulled high, part exits
hibernate mode after 10ms
PRES is floating, part enters hibernate mode
after 4.5 seconds
Fault Mode
- Protections ON
- One or both FET Drivers OFF
- Cell Balancing disabled
-CB FETs ON in OV (depending on conditions)
Hibernate Mode
- Protections OFF
- Both FET Drivers OFF
- Cell Balancing disabled
- Minimal Circuit is ON
图 9-15. Various Operational Modes
9.4.1.6 Customer Fast Production Test Modes
The BQ77915 device supports the ability to greatly reduce production test time by cutting down on protection
fault delay times. To shorten fault times, place the BQ77915 device into Customer Test Mode (CTM). CTM is
triggered by raising VDD to VCTM voltage above the highest cell input pin (that is, VC5) for tCTM_ENTRY time.
The CTM is expected to be used in single-chip designs only. CTM is not supported for stacked designs.
Once the device is in CTM, all fault delays and non-current fault's recovery delay times reduce to a value
of tCTM_DELAY. The fault recovery time for overcurrent faults (OCD1, OCD2, OCC, and SCD) is reduced to
tCTM_OC_REC
.
Verification of protection fault functionality can be accomplished in a reduced timeframe in CTM. Reducing the
VDD voltage to the same voltage applied to the highest-cell input pin for tCTM_ENTRY will exit CTM.
In CTM, with reduced time for all internal delays, qualification of all faults will be reduced to a single instance.
Thus, in this mode, fault-condition qualification is more susceptible to transients, so take care to have fault
conditions clearly and cleanly applied during test mode to avoid false triggering of fault conditions during CTM.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
32
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
10 Application and Implementation
备注
Information in the following applications sections is not device of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The BQ77915 device is a low power stackable battery pack protector with integrated low-side NMOS FET
drivers. The device protects and recovers without MCU control. The following section highlights several
recommended implementation when using the device.
10.1.1 Recommended System Implementation
10.1.1.1 CHG and DSG FET Rise and Fall Time
The CHG and DSG FET drivers are designed to have fast switching time. Customers should select a proper gate
resistor (RCHG and RDSG in the reference schematic) to set to the desired rise/fall time.
DSG
CHG
Select proper gate
resistor to adjust
the desired rise/fall
time
R
R
DSG
CHG
R
GS_DSG
R
GS_CHG
Q2 Q1
R
SNS
PACK-
图 10-1. Select Proper Gate Resistor for FET Rise and Fall Time
The CHG FET fall time is generally slower because it is connected to the PACK– terminal. The CHG driver will
pull to VSS quickly when the driver is signaled to turn off. Once the gate of the CHG FET reaches ground or
Vgsth, the PACK– will start to fall below ground, the CHG signal will follow suit in order to turn off the CHG FET.
This portion of the fall time is strongly dependent on the FET characteristic, the number of FETs in parallel, and
the value of the gate-source resistor (RGS_CHG).
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
Strong pull down by the CHG driver
when the device is initially signaled to
turn off CHG.
Once the CFET gate voltage reach PACK-, PACK-
voltage starts to fall below ground. The gate
voltage is then relying on RGS_CHG to fall with
PACK- to keep the CHG FET off.
图 10-2. CHG FET Fall Time
10.1.1.2 Protecting CHG and LD
Because both CHG and LD are connected to PACK– terminal, these pins are specially designed to sustain an
absolute max of –30 V. The device can be used in a wide variety of applications, and it is possible to expose the
pins lower than –30-V absolute max rating.
To protect the pins, TI recommends to put a PMOS FET in series of the CHG pin, and a diode in series of the LD
pin, as shown below.
DSG
CHG
LD
Q3 and the LD pin diode are used to
keep CHG and LD away from any
voltages below VSS. Apply these
components when CHG and LD pins can
be exposed beyond the absolute -30V.
Q3
RDSG
RCHG
RLD
Q3 will allow RGS_CHG to keeps Q1 OFF,
since all voltages below this FET can
^(}oo}Á_ t!/Y- as it goes below VSS.
RGS_DSG
RGS_CHG
Q2 Q1
RSNS
PACK-
图 10-3. Protecting the CHG and LD Pins Below Absolute Minimum
10.1.1.3 Protecting the CHG FET
When the CHG driver is off, CHG is pulled to VSS, the PACK– terminal can be pulled up to the PACK+ level
when a load is connected. This can put the gate-source voltage above the absolute max of the MOSFET
rating. Thus, it is common to place a Zener diode across the CHG FET’s gate source to protect the CHG FET.
Additional components are added when a Zener is used to limit current going into the CHG pin, as well as
reducing the impact on rise time. See 图 10-4 for details.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
34
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
DSG
CHG
This diode allows CHG to
pull the Q1 gate high,
bypassing the path through
RCHG and RGS_CHG which will
divide down the CHG ON
voltage
RCHG drops the voltage and limits the
current going into the CHG pin when
PACK- is pulled high and zener across Q1
RCHG
(1MΩ ) Vgs is used.
RDSG
This zener clamp may be
needed to prevent the Vgs of Q1
excesses absolute max rating.
RGS_CHG
16V
RGS_DSG
(>=1MΩ)
Q2
Q1
RSNS
PACK-
图 10-4. Protecting the CHG FET from High Voltage on PACK–
LD
DSG
CHG
Q3
RCHG
(1MΩ )
RLD
RDSG
RGS_CHG
(>=1MΩ)
16V
RGS_DSG
Q2 Q1
RSNS
PACK-
图 10-5. Optional Components Combining and Protections
10.1.1.4 Using Load Detect for UV Fault Recovery
A larger CHG FET gate-source resistor is required if load removal is enabled as a device of the UV recovery
criteria. When the load removal circuit is enabled, the device is internally connected to Vss. Because in a UV
fault, the CHG driver remains on, it creates a resistor divider path to the load detect circuit.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
PACK+
bq77915
VLDT
Load Detect
block
LD
pin
RLD_INT
LOAD
CHG
pin
FET driver
block
VFETON
RCHG
RLD
16V
RGS_CHG
CFET
PACK-
图 10-6. Load Detect Circuit During UV Fault
To ensure load removal is detected properly during a UV fault, TI recommends to use 3.3 MΩ for RGS_CHG
(instead of a typical 1 MΩ when load removal is NOT required for UV recovery). RCHG can stay in 1 MΩ as
recommended when using CHG FET protection components. The CHG FET rise time impact is minimized, as
described in Protecting the CHG FET. On a stacked configuration, connect the LD pin as shown in 图 10-7 if
load removal is used for a UV fault recovery. If load detection is not required for a UV fault recovery, a larger
value of RGS_CHG can be used (that is, 10 MΩ), and the LD pin on the upper devices can be left floating.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
36
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
Ra is used to keep the LD pin pull
down when load detect circuit is
not activated
bq77915
LD
pin
Upper
device
Ra
(1M)
Vss
pin
Must have block
diode on the upper
device.
RLD
bq77094/5
LD
pin
Diode for the bottom
device is optional.
Use if the LD pin will
be exposed lower
than -30V.
Bottom
device
Vss
pin
RLD
PACK-
图 10-7. Simplified Circuit: LD Connection On Upper Device When Using for UV Fault Recovery
10.1.1.5 Temperature Protection
The device detects temperature by checking the voltage divided by RTS_PU and RTS, with the assumption of
using 10 KΩ RTS_PU and 103AT NTC for RTS. System designers should always check the thermistor resistance
characteristic and refer to the temperature protection threshold specification in the Electrical Characteristics table
to determine if a different pull up resistor should be used. If a different temperature trip pint is required, it is
possible to scale the threshold using this equation: Temperature Protection Threshold = RTS/(RTS + RTS_PU).
Example: Scale OTC trip points from 50°C to 55°C
The OTC protection can be set to 45°C or 50°C. When the device's OTC threshold is set to 50°C, it is referred
to configure the VOTC parameter to 29.38% of VTB (typical), with the assumption of RTS_PU = 10 KΩ and RTS
= 103AT or similar NTC (which the NTC resistance at 50°C = 4.16KΩ). The VOTC specification is the resistor
divider ratio of RTS_PU and RTS.
The VOTC, VOTD, VUTC, and VUTD configuration options are fixed in the device. Hence, the actual temperature trip
point can only adjust by using a different B-value NTC and/or using a different RTS_PU
.
In this example, the 103AT NTC resistance at 55°C is 3.536 KΩ. By changing the RTS_PU from 10 KΩ to 8.5 KΩ,
we can scale the actual OTC temperature trip point from 50°C to 55°C. Because the RTS_PU value is smaller, this
change affects all the other temperature trip points and scales OTD, UTC, and UTD with the largest impact to
OTD.
10.1.1.6 Adding RC Filters to the Sense Resistor
Current fault is sensed through voltage across sense resistor. Optional RC filters can be added to the sense
resistor to improve stability.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
SRP
SRN
0.1 µF
0.1 µF
0.1 µF
100 Ω
100 Ω
PACK-
RSNS
图 10-8. Optional Filters Improve Current Measurement
10.1.1.7 Using the State Comparator in an Application
The state comparator has built-in hysteresis and tSTATE qualification time. In a typical application, the sense
resistor is selected according to the application current, which is not usually close to the state comparator
threshold. Current variation slowly through the hysteresis range causes the FET body diode protection to toggle
on and off.
10.1.1.7.1 Examples
As an example, using a 5-Ah battery, with 1C-rate (5 A) charge and 2C-rate (10 A) discharge, the sense resistor
is mostly 3 mΩ or less.
The typical current to turn on the FET body diode protection is 625 mA using this example. The typical current
to turn off the FET body diode protection with the 3-mΩ sense resistor is 417 mA. Using this example, a > 1
A current, either charge or discharge should provide a solid FET body diode protection detection. A momentary
drop through the hysteresis threshold will not cause the body diode protection to drop, but drops of 2 ms or more
will cause the FET to toggle.
Observe the device behavior during an OV event (and no other fault is detected). In an OV event, the CHG FET
is off and the DSG FET is on. If a discharge of >1 A occurs, the device would turn on the CHG FET to allow the
full discharge current to pass through. Once the overcharged cell is discharged to the OV recovery level, the OV
fault is recovered and CHG driver turns on (or remains on in this scenario) and the state comparator is turned
off.
If the discharge current drops below the V(STATE_D_HYS) threshold for longer than tSTATE when the device is still in
an OV fault, the CHG FET may toggle on and off until the overcharged cell voltage is reduced down to the OV
recovery level. When the OV fault recovered, the CHG FET will be turned on solidly and the state comparator is
off.
Without the FET body diode protection, if a discharge occurs during an OV fault state, the discharge current can
only pass through the CHG FET body diode until the OV fault is recovered. This increases the risk of damaging
the CHG FET if the MOSFET is not rated to sustain such current through its body diode. It also increases the
FET temperature as current is now carried through the body diode.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
38
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
10.2 Typical Application
RVDD
PACK+
CVDD
CVDD
VDD
AVDD
VC5
CTRD
CTRC
PRES
RIN
RHIB
PRES
VC4
VC3
CBO
CIN
CCFG
RTS_PU
RIN
VC2
VC1
VTB
TS
RTS
bq77915
ROCD
CIN
VC0
VSS
OCDP
CBI
RIN
SRP
SRN
DSG
LPWR
LD
CIN
CS
CHG
RIN
CS
RDSG
RCHG
CIN
RIN
CIN
RCHG2
CS
RLD
CIN
RIN
RS
RS
RGS
RGS
RSNS
PACKœ
图 10-9. The BQ77915 Device with Five Cells
10.2.1 Design Requirements
For this design example, use the parameters shown in 表 10-1.
表 10-1. Design Parameters
PARAMETER
DESCRIPTION
VALUES
RIN
Cell voltage sensing (VCx pins) filter resistor. System designers should change this
parameter to adjust the cell balance current.
1 kΩ ±5%
CIN
Cell voltage sensing (VCx pins) filter capacitor
Supply voltage filter resistor
0.1 µF ±10%
1 kΩ ±5%
RVDD
CVDD
RS
Supply voltage filter capacitor
Current sensing input filter resistor
Current sensing input filter capacitor
NTC thermistor
1 µF ±20%
100 Ω ±5%
0.1 µF ±10%
CS
RTS
103AT, 10 kΩ ±3%
10 kΩ ±1%
RTS_PU
Thermistor pullup resistor to VTB pin, assuming using 103AT NTC or NTC with similar
resistance-temperature characteristic
RGS_CHG
CHG FET gate-source Load removal is enabled for UV recovery.
3.3 MΩ ±5%
1 MΩ ±5%
1 MΩ ±5%
resistor
Load removal is disabled for UV recovery.
RGS_DSG
DSG FET gate-source resistor
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
表 10-1. Design Parameters (continued)
PARAMETER
DESCRIPTION
VALUES
RCHG
CHG gate resistor
System designers should adjust this parameter to meet the
desired FET rise/fall time.
1 kΩ ±5%
1 MΩ ±5%
4.5 kΩ ±5%
If additional components are used to protect the CHG FET
and/or to enable load removal detection for UV recovery
RDSG
DSG gate resistor. System designers should adjust this parameter to meet the desired
FET rise/fall time.
RCTRC and RCTRD
CTRC and CTRD current limit resistor
PRES pullup resistor for NORMAL mode
10 MΩ ±5%
10 kΩ ±5%
RHIB
ROCD
OCDP discharge overcurrent protection delay pulldown resistor. System designers
should change this parameter for the desired delay.
100 kΩ ±1%
RCB
RLD
CBI pulldown resistor between stacked devices to enable balancing
LD resistor for load removal detection
10 kΩ ±5%
450 KΩ ±5%
RSNS
Current sense resistor for current protection. System designers should change this
parameter according to the application current protection requirement.
1 mΩ ±1%
10.2.2 Detailed Design Procedure
The following is the detailed design procedure:
1. Select the number of devices needed for the number of cells in the system, and for the configuration of the
protection thresholds.
2. Select the proper sense resistor value based on the application current. The sense resistor should enable
detection of the highest current protection, as well as the short circuit current.
3. Set the temperature protection using a 103AT NTC (or an NTC with similar specifications). If using a different
type of NTC, a different RTS_PU may be used for the application. Refer to the actual temperature detection
threshold voltage to determine the RTS_PU value.
4. Connect the CCFG pin correctly for each device based on the number of cells in series.
5. Enable cell balancing if desired.
6. Select the configuration parameters and input filter resistors to set the current.
7. Review the Recommended System Implementation to determine if optional components should be added to
the schematic.
10.2.2.1 Design Example
This example shows how to design protection for an 18-V Li-ion battery pack using 4.2-V cells with the following
requirements:
•
•
•
•
•
•
•
•
•
•
•
•
•
The system will operate from 15 V to 21.5 V.
The battery must allow 4-A continuous current.
The battery must protect with 8-A discharge current > 500 ms.
The battery must have short circuit protection in < 2 ms.
The system is for operation in an office environment: 10°C to 30°C.
The cell normal charge voltage is 4.2 ±0.05 V to 0.05 C.
The cell cutoff voltage is 2.75 V.
The charge temperature is 0°C to 45°C.
A cell configuration is selected to provide 5 Ah over the system range of operation.
The cell assembly is capable of > 30-A short circuit current.
Cell balancing is desired with a current of 10% of termination current.
Low current drain is desired when the pack is removed from the system.
Load removal for fault recovery is required. Recovery by connecting the charger is acceptable.
To start the design:
1. Start the schematic:
•
An 18-V pack using 3.6-V nominal cells requires a 5-series configuration. A single BQ77915 device is
needed.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
40
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
•
Follow the 5-series reference schematic in this document. Follow the recommended design parameters in
Design Requirements.
•
•
Because a single device is needed, CTRC and CTRD are connected directly to GND.
The power FET used in this type of application usually has an absolute maximum of 20-V Vgs. For an
18-V pack design, transient voltage during an OCD may exceed 20 V, so the diode across the 1-MΩ
RCHG2 is used. RCHG helps to slow the charge FET from turning on.
•
Because a charger connection for UV recovery is acceptable, the condition in 节 10.1.1.4 is not a
concern. A 1-MΩ RGS_CHG can be used for the schematic.
•
•
The optional sense input filter is selected for the circuit.
Because low current storage is desired, the PRES pin is brought out of the pack for control by the
system. The standard recommended RHIB value is used.
•
Because cell balancing is required:
– Connect the CBI pin to VSS.
– Determine the resistance for the RIN filter resistors. Since the charge taper current will be 0.05 × 5 A
or 250 mA, 10% is 25 mA. With a 4.1-V cell, 25 mA would require 164-Ω resistance. This resistance
includes the internal RBAL resistance and two RIN resistors. 75-Ω resistors are selected for RIN.
2. Decide the value of the sense resistor, RSNS
.
•
When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available
current protection threshold range.
•
In this example, only one protection threshold is specified. The minimum available OCD threshold is the
–10-mV OCD1 threshold, but this would result in an odd value for RSNS and the tolerance of the threshold
is 30%. Using the –60-mV threshold of the BQ77915 configuration, a 10-mΩ sense resistor would give
a 6-A nominal OCD threshold. With the 20% tolerance, 4 A can pass without OCD and 8 A will always
cross the threshold.
•
•
A 30-A SCD with a 10-mΩ sense resistor would be a nominal 300-mV threshold. Tolerance must be
considered and the protection threshold can be lower than the battery capability. The 120-mV threshold of
the BQ77915 configuration with a 10-mΩ RSNS will give a 12-A nominal short circuit threshold.
Select RSNS = 10 mΩ for this example.
3. Determine the remaining BQ77915 protection configuration:
•
Charging the cells at a lower than maximum voltage allows a margin on setting the OV threshold. The
system could allow a 4.15-V OV, while the cells might allow a 4.3-V OV. Since the charge voltage will be
4.1 V/cell, this is the desired VFC point of the BQ77915 device. The 4200-mV OV threshold and 100 mV
VOV – VFC of the BQ77915 device are suitable.
•
•
OV hysteresis and delay values are not specified requirements. A 1-s delay will be selected. Some
hysteresis is desired to prevent cycling if the battery were to reach OV. 200 mV is acceptable.
The system will stop operation at a nominal 3 V per cell, while the cells could operate to 2.75 V. Some
margin below the 3 V should be allowed, because cell voltages may vary at low states of charge. A
2750-mV threshold option is available, but the existing BQ77915 configuration has the 2900 threshold.
UV hysteresis and delay are not specified requirements. A 1-s delay is selected. Generally, a larger
UV hysteresis will avoid system cycling from automatic recovery; however, in this design load, removal
is required and charger connection is expected for UV recovery. The value could vary, but 400 mV is
selected.
•
•
•
Open-wire protection is selected at the 100-nA level.
tOCD1 or tOCD2 could be programmed to 350 ms to protect in less than 500 ms, or the default BQ77915
180 ms is used. However, the 350 ms can be selected with ROCD. Use 604 kΩ 1% for ROCD
.
•
•
The 2-ms SCD response time allows either SCD delay selection.
Overcurrent charge protection is not specified in the requirements. The BQ77915 60-mV setting will allow
a 1C charge.
•
•
•
For temperature protections, the 0°C to 45°C charge temperature thresholds match the range for the
cells. Use the lower range for discharge.
The VCBTH – VCBTHL determines the voltage spread during constant current charge when balancing
will be allowed. 100 mV allows some spread without balancing.
See the summary in 表 10-2.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
4. Review the available release in the Device Comparison Table to determine if it is a suitable option. In
this example, the BQ7791500 configuration is suitable. If it is not suitable for your design, contact a TI
representative for further assistance and for information on BQ77915 PRODUCT PREVIEW devices.
表 10-2. Design Example Configuration
Protection
OV
Threshold
4.2 V
Hysteresis
Delay
Recovery Method
Hysteresis
200 mV
1 s (default setting)
1 s (default setting)
UV
2.9 V
400 mV
Hysteresis + load removal
100 nA
(default setting)
OW
—
—
—
—
(VCx – VCx–1) > 600 mV (typical)
Load removal only
OCD1
OCD2
60 mV
60 mV
180 ms
180 ms (350 ms using
Load removal only
ROCD
)
SCD
OCC
120 mV
60 mV
45°C
—
-—
960 µs
Load removal only
Load detection only
Hysteresis
Hysteresis
Hysteresis
Hysteresis
—
Fixed at 10 ms
OTC
10°C
10°C
10°C
10°C
—
4.5 s
4.5 s
4.5 s
4.5 s
—
OTD
65°C
UTC
0°C
UTD
–10°C
100 mV
100 mV
3.8 V
VOV – VFC
VCBTH – VCBTL
VSTART
—
—
—
—
—
—
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
42
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
10.2.3 Application Curves
图 10-10. OV Fault Protection
图 10-11. OV Fault Recovery
图 10-12. OV and OCD2 Faults Protection
图 10-13. Detect OTC Fault While in Discharge
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
图 10-14. OW Fault Protection—Open Cell1 To PCB 图 10-15. OW Fault Protection, Low Voltage—Open
Connection
Cell1 Connection
11 Power Supply Recommendations
The recommended cell voltage range is up to 5 V. If three cells in series are connecting to the BQ77915 device,
the unused VCx pins should be shorted to the highest unused VCx pin. The recommended VDD range is from 3
V to 25 V. This implies the device is still operational when cell voltage is depleted down to the ~1.5-V range.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
44
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
12 Layout
12.1 Layout Guidelines
1. Match SRN and SRP traces.
2. RIN filters, VDD, AVDD filters, and the CVDD capacitor should be placed close to the device pins.
3. Separate the device ground plane (low current ground) from the high current path. Filter capacitors should
reference to the low current ground path or device Vss.
4. In a stack configuration, the RCTRD and RCTRC should be placed closer to the lower device CTRD and CTRC
pins.
5. RGS should be placed near the FETs.
6. In a stacked configuration, it must be ensured in the PCB layout that the trace from the VC5 pin to a cell and
the trace from the VC0 pin of the next upper device to the immediately higher cell are kept separate.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
12.2 Layout Example
PACK+
High current Path
Place filters
close to IC pins
CTRD
CTRC
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
VC0
VSS
PRES
CBO
CCFG
VTB
RC
Filters
Low current, local
ground for each device
TS
OCDP
CBI
SRP
SRN
DSG
LPWR
LD
CHG
Place resistors
close to the input
pins
Connect the device
ground at the lower
ꢀꢁoo[• ꢀꢁoo- on each
cell group
Place filters
close to IC pins
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
VC0
VSS
CTRD
CTRC
PRES
CBO
CCFG
VTB
RC
Filters
TS
OCDP
CBI
Low current, local
device ground.
Separate from high
power path
SRP
LPWR
LD
CHG
SRN
DSG
Connect the bottom
device ground at BAT-.
Use BAT- as the mutual
point to connect high
and low current path
PACK-
图 12-1. Layout Example
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLUSCU0
46
Submit Document Feedback
Product Folder Links: BQ77915
BQ77915
www.ti.com.cn
ZHCSHU6K – MARCH 2018 – REVISED JULY 2023
13 Device and Documentation Support
13.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
BQ77915 3–5S Low-Power Protector Evaluation Module User's Guide (SLUUBU2)
BQ77915 Functional Safety FIT Rate, FMD, and PinFMA Application Report (SLUAA46 )
13.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅 TI
的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: BQ77915
English Data Sheet: SLUSCU0
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ7791500PWR
BQ7791500PWT
BQ7791501PWR
BQ7791501PWT
BQ7791502PW
BQ7791502PWR
BQ7791504PW
BQ7791504PWR
BQ7791506PW
BQ7791506PWR
BQ7791508PW
BQ7791508PWR
BQ7791513PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
24
24
24
24
24
24
24
24
24
24
24
24
24
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
BQ77915
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
BQ77915
7791501
7791501
7791502
7791502
7791504
7791504
7791506
7791506
7791508
7791508
7791513
250
60
RoHS & Green
RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
60 RoHS & Green
2000 RoHS & Green
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ7791500PWR
BQ7791500PWT
BQ7791501PWR
BQ7791501PWT
BQ7791502PWR
BQ7791504PWR
BQ7791506PWR
BQ7791508PWR
BQ7791513PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
24
24
24
24
24
24
24
24
24
2000
250
330.0
180.0
330.0
180.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
6.95
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2000
250
2000
2000
2000
2000
2000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ7791500PWR
BQ7791500PWT
BQ7791501PWR
BQ7791501PWT
BQ7791502PWR
BQ7791504PWR
BQ7791506PWR
BQ7791508PWR
BQ7791513PWR
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
PW
24
24
24
24
24
24
24
24
24
2000
250
356.0
210.0
356.0
210.0
356.0
356.0
356.0
356.0
356.0
356.0
185.0
356.0
185.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
2000
250
2000
2000
2000
2000
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
BQ7791502PW
BQ7791504PW
BQ7791506PW
BQ7791508PW
PW
PW
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
24
24
24
24
60
60
60
60
530
530
530
530
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3.5
3.5
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023,德州仪器 (TI) 公司
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明