BQ79612-Q1_技术文档

BQ79616-Q1, BQ79614-Q1, BQ79612-Q1

ZHCSR27D –AUGUST 2020 –REVISED SEPTEMBER 2022

BQ79616-Q1、BQ79614-Q1、BQ79612-Q1 功能安全合规型汽车类16/14/12 节串

联电池监测器、平衡器和集成硬件保护器

1 特性

2 应用

• 符合汽车应用要求

• 具有符合AEC-Q100 标准的下列特性：

– 器件温度等级1：–40°C 至+125°C 环境工作

温度范围

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 符合功能安全标准

• 混合动力和电动动力总成系统中的电池管理系统

(BMS)

• 带有电池管理系统的储能电池组

3 说明

BQ79612-Q1、BQ79614-Q1 和 BQ79616-Q1 可在不

到200μs 的时间内为 HEV/EV 中高压电池管理系统中

的 12S、14S 和 16S 电池模块提供高精度电池电压测

量。该系列监控器在同一封装类型中提供不同的通道选

项，同时提供引脚对引脚兼容性，并支持在任何平台上

高度重复使用既有的软件和硬件。借助集成式前端滤波

器，可以在电池输入通道上使用简单、低额定电压的差

分 RC 滤波器来实施系统。集成式后 ADC 低通滤波器

可以执行经过滤波、类似于直流电的电压测量，以便更

好地计算荷电状态 (SOC)。此器件支持自主内部电池

平衡，并通过监测温度来自动暂停和恢复平衡，以免出

现过热条件。

– 专为功能安全应用开发

– 可帮助进行ISO 26262 系统设计的文档

– 系统可满足ASIL D 级要求

– 硬件可满足ASIL D 要求

• +/- 1.5mV ADC 精度

• 兼容引脚/封装和软件的器件系列：

– 可堆叠监测器16S（BQ79616-Q1、BQ79656-

Q1）、14S（BQ79614-Q1、BQ79654-Q1）和

12S（BQ79612-Q1、BQ79652-Q1）

– 独立式监测器48V 系统(BQ75614-Q1)

• 用于电压、温度诊断的内置冗余路径

• 可以在128µs 内对所有电池通道执行高度精确的电

池电压测量

器件信息

器件型号⁽¹⁾

BQ79612-Q1

BQ79614-Q1

BQ79616-Q1

封装尺寸（标称值）

封装

• 集成式后ADC 可配置数字低通滤波器

• 支持汇流条连接和测量

10.00mm x 10.00mm

HTQFP（64 引脚）

• 主机控制的内置硬件复位功能，可模拟类似于POR

的器件复位

• 支持内部电池平衡

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Battery

Modules

– 240mA 的平衡电流

+

12

V

– 内置平衡热管理，具有自动暂停和恢复控制功能

• 隔离式差分菊花链通信，采用可选的环形架构

• 通过通信线路传输的嵌入式故障信号和检测信号

• UART/SPI 主机接口/通信桥接器件BQ79600-Q1

• 内置SPI 主器件

Balance and Filter Components

DC-DC

To CAN

Bus

MCU

BQ79600

bq79600

BQ7961x

bq79600

BQ7961x

bq79600

NFAULT

UART or

SPI

UART or

SPI

COML

COMH

COML

COMH

COML

COMH

Capactive

Level-shifted Differential Interface

Isolation

Components

Optional Ring Connection

简化版系统图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSE81

BQ79616-Q1, BQ79614-Q1, BQ79612-Q1

ZHCSR27D –AUGUST 2020 –REVISED SEPTEMBER 2022

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Table of Contents

9.4 Device Functional Modes........................................104

9.5 Register Maps.........................................................113

10 Application and Implementation..............................192

10.1 Application Information......................................... 192

10.2 Typical Applications.............................................. 192

11 Power Supply Recommendations............................204

12 Layout.........................................................................205

12.1 Layout Guidelines................................................. 205

12.2 Layout Example.................................................... 208

13 Device and Documentation Support........................212

13.1 Device Support..................................................... 212

13.2 接收文档更新通知................................................. 212

13.3 支持资源................................................................212

13.4 Trademarks...........................................................212

13.5 Electrostatic Discharge Caution............................212

13.6 术语表................................................................... 212

14 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................4

6 Device Comparison Table...............................................5

7 Pin Configuration and Functions...................................6

8 Specifications................................................................ 11

8.1 Absolute Maximum Ratings...................................... 11

8.2 ESD Ratings..............................................................11

8.3 Recommended Operating Conditions.......................12

8.4 Thermal Information..................................................12

8.5 Electrical Characteristics...........................................12

8.6 Timing Requirements................................................17

8.7 Typical Characteristics..............................................21

9 Detailed Description......................................................23

9.1 Overview...................................................................23

9.2 Functional Block Diagram.........................................23

9.3 Feature Description...................................................25

Information.................................................................. 213

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (June 2021) to Revision D (September 2022)

Page

• 将“受限”更改为“公开”.................................................................................................................................1

• Additional supply current when TSREF is enabled...........................................................................................12

• DVDD output voltage........................................................................................................................................12

• NEG5V pin voltage........................................................................................................................................... 12

• Diagnostic measurements resolution................................................................................................................12

• Added paragraph to 节9.3.1.2 ........................................................................................................................ 25

• Changed 380μs to 1.35ms in 节9.3.1.6 .........................................................................................................26

• Added Note to 节9.3.2.1.3.1 ........................................................................................................................... 31

• Deleted as in the Main ADC path and added Note to 节9.3.2.2.1.1 ............................................................... 33

• Changed text in 节9.3.2.3 ...............................................................................................................................37

• Changed latch to load in 节9.3.3.3.3 .............................................................................................................. 43

• Added text to 节9.3.5 ......................................................................................................................................49

• Changed above to below in 图9-23 ................................................................................................................ 50

• Changed 图9-25 to show response frame start time is after TX_HOLF_OFF expiration time.........................52

• Changed Read to Write in 表9-9 .....................................................................................................................53

• Changed 图9-27 to the correct bit-width per byte............................................................................................56

• Added t_{prog_otp}= 100ms and During this time no data communications is allowed to step 4 in 表9-26 ..........81

• Changed BQ79606-Q1 to BQ7961X-Q1 in 节9.3.6.4 .....................................................................................82

• Deleted Rcb resistor in 图9-56 ......................................................................................................................101

• Multiple bits in 节9.5.4.3.11 updated with Bit is self-cleared and added text................................................. 130

• Changed bit setting 11 to Reserved in 节9.5.4.5.1 ....................................................................................... 135

• Changed bit 6 to Reserved and changed bit 5 to 0 = Dynamic Alignment in 节9.5.4.5.8 .............................137

• Added sourced from TSREF regulator voltage and Default Reset setting 4% to COOLOFF[2:0] and sourced

from TSREF regulator voltage and Default Reset setting 24% to OTCB_THR[3:0] in 节9.5.4.7.5 ...............156

• Added This bit is self clearing to BAL_TIME_GO in 节9.5.4.7.8 ...................................................................157

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• Added sourced from TSREF regulator voltage. and Default Reset setting 80% to UT_THR[2:0] and sourced

from TSREF regulator voltage. and Default Reset setting 39% to OT_THR[4:0] in 节9.5.4.8.5 ...................159

• Updated correct register names in 节9.5.4.13.3 ...........................................................................................171

• Added Note to UART_MIRROR_EN in 节9.5.4.14.2 .................................................................................... 179

• Changed cap value to 2.2 μF and fixed isolator pinout in 图10-1 ............................................................... 192

• Changed content, 图10-7, 图10-8, and 图10-9 in 节10.2.1.2.7.2 ...............................................................198

• Changed cap values to 2.2 μF in 图10-11 ...................................................................................................201

• Changed 图12-3 ........................................................................................................................................... 207

Changes from Revision B (April 2021) to Revision C (June 2021)

Page

• 将BQ79614-Q1 和BQ79612-Q1 从“产品预发布”更改为“量产数据”.........................................................1

Changes from Revision A (December 2020) to Revision B (April 2021)

Page

• Added ^{(2) (3)}......................................................................................................................................................11

• Added ⁽²⁾.......................................................................................................................................................... 11

• Added ⁽³⁾.......................................................................................................................................................... 11

• Added MAIN_ADC_CAL1, MAIN_ADC_CAL2 register to 节9.3.2.1.3.1 .........................................................31

• Changed CUST_CRC_LO reset value from 0x73 to 0xF3 in 节9.5.1 ........................................................... 113

• Added content to MAIN_MODE[1:0] description in 节9.5.4.5.7 ....................................................................137

• Added content to AUX_MODE[1:0] description in 节9.5.4.5.9 ......................................................................137

• Changed From: This bit is set if [MSK_COMP] = 1 To: This bit is set if [MSK_COMP] = 0 for

FAULT_COMP_ADC = in 节9.5.4.13.1 .........................................................................................................169

• Added content to Common-mode choke and ESD diode (optional) descriptions in 表10-4 ......................... 198

• Changed content for Transformer description and added content to ESD diode (optional) description in 表

10-5 ................................................................................................................................................................198

Changes from Revision * (August 2020) to Revision A (December 2020)

Page

• 将“预告信息”更改为“量产数据”.................................................................................................................. 1

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5 说明（续）

包含的隔离式双向菊花链端口支持通过电容器和变压器进行隔离，并允许使用最有效的组件实现 xEV 动力总成系

统中常见的集中式或分布式架构。此器件还包含八个GPIO 或辅助输入，可执行外部热敏电阻测量。

与 BQ7961x-Q1 系列器件的主机通信可通过以下方式进行连接：器件的专用 UART 接口或通信桥接器件

BQ79600。此外，隔离的差分菊花链通信接口允许主机通过单个接口与整个电池组进行通信。在通信线路中断的

情况下，菊花链通信接口可配置为环形架构，允许主机与堆栈两端的设备通信。

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6 Device Comparison Table

DEVICE

STATUS

DESCRIPTION

Supports 6S to 16S battery modules

Supports 6S to 14S battery modules

Supports 6S to 12S battery modules

BQ79616-Q1

BQ79614-Q1

BQ79612-Q1

Production Data

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ZHCSR27D –AUGUST 2020 –REVISED SEPTEMBER 2022

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7 Pin Configuration and Functions

PAP Package

64-Pin HTQFP

Top View

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

BAT

CB16

VC16

CB15

VC15

CB14

VC14

CB13

VC13

NPNB

LDOIN

CVSS

2

3

4

CVDD

5

NEG5V

COMHP

COMHN

COMLN

COMLP

AVSS

6

7

BQ79616-Q1

64-HTQFP (PAP)

10 mm x 10 mm

8

9

10

11

12

13

14

15

16

CB12

VC12

CB11

VC11

CB10

VC10

CB9

AVDD

REFHP

REFHM

VC0

CB0

VC1

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PAP Package

64-Pin HTQFP

Top View

1

48

BAT

NC

NPNB

2

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

LDOIN

CVSS

NC

3

4

NC

CVDD

5

NEG5V

COMHP

COMHN

COMLN

COMLP

AVSS

NC

6

CB14

VC14

CB13

VC13

7

BQ79614-Q1

64-HTQFP (PAP)

10 mm x 10 mm

8

9

10

11

12

13

14

15

16

CB12

VC12

CB11

VC11

CB10

VC10

CB9

AVDD

REFHP

REFHM

VC0

CB0

VC1

PAP Package

64-Pin HTQFP

Top View

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

BAT

NC

NPNB

LDOIN

CVSS

2

3

4

CVDD

5

NEG5V

COMHP

COMHN

COMLN

COMLP

AVSS

6

7

BQ79612-Q1

64-HTQFP (PAP)

10 mm x 10 mm

8

9

10

11

12

13

14

15

16

CB12

VC12

CB11

VC11

CB10

VC10

CB9

AVDD

REFHP

REFHM

VC0

CB0

VC1

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表7-1. Pin Functions

NAME

TYPE

DESCRIPTION

No.

BQ79616

BAT

BQ79614

BQ79612

BAT

1

P

Power supply input and top of module measurement input. Connect to the top cell of the

battery module.

NPNB

48

47

P

Connect to the base of an external NPN transistor.

LDOIN

6-V preregulated analog power supply input/sense pin. Connect to the emitter of the external

NPN transistor and connect a 0.1-µF decoupling capacitor to CVSS.

AVDD

AVSS

NEG5V

DVDD

DVSS

CVDD

AVDD

AVSS

NEG5V

DVDD

DVSS

CVDD

AVDD

AVSS

NEG5V

DVDD

DVSS

CVDD

38

39

44

49

50

45

P

GND

P

5-V regulated output. AVDD supplies the internal analog circuits. Bypass AVDD with a

capacitor to AVSS.

Analog ground. Ground connection for internal analog circuits. Connect DVSS, CVSS,

REFHM, and AVSS externally.

Negative 5-V charge pump used for daisy chain and Main ADC. Connect with a capacitor to

CVSS.

P

1.8-V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a

capacitor to DVSS.

GND

P

Digital ground. Ground connection for internal digital logics. Connect DVSS, CVSS, REFHM,

and AVSS externally.

5-V daisy chain communication and I/Os power supply. CVDD supplies the stack daisy chain

communication transceiver circuit and the I/O pins. This power supply also supports an

additional 10-mA external load in ACTIVE and SLEEP.

CVSS

46

51

GND

P

Daisy chain communication ground. Ground connection for internal daisy chain transceivers.

Connect DVSS, CVSS, REFHM, and AVSS externally.

TSREF

5-V bias voltage for NTC thermistor. Connect TSREF to the top of the NTC resistor divider

network to the GPIOs when they are configured for NTC temperature monitoring. Bypass

TSREF with a capacitor to CVSS.

REFHP

REFHM

REFHP

REFHM

REFHP

REFHM

37

36

P

Precision reference output pin. Bypass with a capacitor to REFHM.

GND

Precision reference ground. Ground connection for the internal precision reference. Connect

DVSS, CVSS, REFHM, and AVSS externally.

VC16

VC15

VC14

VC13

NC

3

5

7

9

I

Cell voltage sense input. Connect to the positive terminal of cell 16. Connect a differential

RC filter to VC15. Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in

Cell Connections.

NC

Cell voltage sense input. Connect to the positive terminal of cell 15. Connect a differential

RC filter to VC14.Tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in

Cell Connections.

VC14

VC13

Cell voltage sense input. Connect to the positive terminal of cell 14. Connect a differential

RC filter to VC13.Tie unused NC pins in BQ79612 to BAT pin as explained in Cell

Connections.

Cell voltage sense input. Connect to the positive terminal of cell 13. Connect a differential

RC filter to VC12. Tie unused NC pins in BQ79612 to BAT pin as explained in Cell

Connections.

VC12

VC11

VC10

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC12

VC11

VC10

VC9

VC8

VC7

VC6

VC5

VC4

VC3

VC12

VC11

VC10

VC9

VC8

VC7

VC6

VC5

VC4

VC3

11

13

15

17

19

21

23

25

27

29

I

Cell voltage sense input. Connect to the positive terminal of cell 12. Connect a differential

RC filter to VC11.

Cell voltage sense input. Connect to the positive terminal of cell 11. Connect a differential

RC filter to VC10.

Cell voltage sense input. Connect to the positive terminal of cell 10. Connect a differential

RC filter to VC9.

Cell voltage sense input. Connect to the positive terminal of cell 9. Connect a differential RC

filter to VC8.

Cell voltage sense input. Connect to the positive terminal of cell 8. Connect a differential RC

filter to VC7.

Cell voltage sense input. Connect to the positive terminal of cell 7. Connect a differential RC

filter to VC6.

Cell voltage sense input. Connect to the positive terminal of cell 6. Connect a differential RC

filter to VC5.

Cell voltage sense input. Connect to the positive terminal of cell 5. Connect a differential RC

filter to VC4.

Cell voltage sense input. Connect to the positive terminal of cell 4. Connect a differential RC

filter to VC3.

Cell voltage sense input. Connect to the positive terminal of cell 3. Connect a differential RC

filter to VC2.

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表7-1. Pin Functions (continued)

NAME

BQ79614

VC2

TYPE

DESCRIPTION

No.

BQ79616

VC2

BQ79612

VC2

31

I

Cell voltage sense input. Connect to the positive terminal of cell 2. Connect a differential RC

filter to VC1.

VC1

VC0

CB16

VC1

VC0

NC

VC1

VC0

NC

33

35

2

Cell voltage sense input. Connect to the positive terminal of cell 1. Connect a differential RC

filter to VC0.

I

Cell voltage sense input. Connect to the negative terminal of cell 1. Connect a differential

RC filter to AVSS.

I/O

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 16 with a differential RC filter to CB15. The filter

resistor also sets the internal balance current. Tie unused CB16 pin via RC to BAT pin and

tie unused NC pins in BQ79614 and BQ79612 to BAT pin as explained in Cell Connections.

CB15

CB14

CB13

NC

4

6

8

I/O

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 15 with a differential RC filter to CB14. The filter

resistor also sets the internal balance current. Tie unused NC pins in BQ79614 and

BQ79612 to BAT pin as explained in Cell Connections.

CB14

CB13

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 14 with a differential RC filter to CB13. The filter

resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin

as explained in Cell Connections.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 13 with a differential RC filter to CB12. The filter

resistor also sets the internal balance current. Tie unused NC pins in BQ79612 to BAT pin

as explained in Cell Connections.

CB12

CB11

CB10

CB9

CB8

CB7

CB6

CB5

CB4

CB3

CB2

CB1

CB0

CB12

CB11

CB10

CB9

CB8

CB7

CB6

CB5

CB4

CB3

CB2

CB1

CB0

CB12

CB11

CB10

CB9

CB8

CB7

CB6

CB5

CB4

CB3

CB2

CB1

CB0

10

12

14

16

18

20

22

24

26

28

30

32

34

I/O

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 12 with a differential RC filter to CB11. The filter

resistor also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 11 with a differential RC filter to CB10. The filter

resistor also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 10 with a differential RC filter to CB9. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 9 with a differential RC filter to CB8. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 8 with a differential RC filter to CB7. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 7 with a differential RC filter to CB6. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 6 with a differential RC filter to CB5. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 5 with a differential RC filter to CB4. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 4 with a differential RC filter to CB3. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 3 with a differential RC filter to CB2. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 2 with a differential RC filter to CB1. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect

this pin to the positive terminal of cell 1 with a differential RC filter to CB0. The filter resistor

also sets the internal balance current.

Cell balance connection. This pin is connected to the internal cell balancing FET. Connect to

the negative terminal of cell 1 with differential RC filter to AVSS. The filter resistor also sets

the internal balance current.

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表7-1. Pin Functions (continued)

NAME

TYPE

DESCRIPTION

No.

BQ79616

BBP

BQ79614

BQ79612

BBP

64

I

Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel

provides a differential input to the ADC measurement with a 5x gain.

BBN

RX

BBN

RX

BBN

RX

63

52

Bus bar connection. With BBP and BBN connecting to each end of a bus bar, this channel

provides a differential input to the ADC measurement with a 5x gain.

UART receiver input. Pull up to CVDD with an external resistor and connect the device RX

to the TX output of the host MCU. If unused (for example, for stack devices), connect RX to

CVDD.

TX

53

O

UART transmitter output. Connect device TX to RX input of the host MCU and will be pulled

up from the host side. If unused (for example, for stack devices), leave it floating.

COMHP

COMHN

COMHP

COMHN

COMHP

COMHN

43

42

I/O

Vertical bidirectional communication interface for daisy chain connection. High side (north

side) differential I/O. Will connect to the low side (south side) COMLP and COMLN of the

lower adjacent device in the daisy chain configuration. If unused, connect COMHP and

COMHN with a 1kΩresistor.

COMLP

COMLN

COMLP

COMLN

COMLP

COMLN

40

41

I/O

Vertical bidirectional communication interface for daisy chain connection. Low side (south

side) differential I/O. Will connect to the high side (north side) COMHP and COMHN of the

upper adjacent device in the daisy chain configuration. If unused, connect COMLP and

COMLN with a 1kΩresistor.

NFAULT

62

O

Fault indication output. Active low. If used on the base device, pull up NFAULT to CVDD with

a pullup resistor and connect NFAULT to host MCU GPIO. If unused, leave it unconnected.

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

61

60

59

58

57

56

55

54

I/O

General purpose input/output, configuration options are:

•

For external NTC thermistor connection, connect NTC thermistor to the pin and pull up

to TSREF. Used as input to ADC and OT and UT hardware comparators.

For external DC voltage measurement, configured as input to ADC.

Generic digital input/output.

•

Use as I/O for SPI master.

10

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

BAT, VC* (except VC0), CB* (except CB0),

100

V

–0.3

NFAULT, BBP, BBN to AVSS ^{(2) (3)}

Input Voltage

CB0, VC0 to AVSS

5.5

80

16

80

9

V

–0.3

–80

VCn to VCn-1, n = 1 to 16 ⁽²⁾

CBn to CBn-1, n = 1 to 16 ⁽³⁾

BBP to BBN

V

–0.3

–80

V

LDOIN to AVSS

V

–0.3

–5.5

–0.3

–20

NPNB to AVSS

10

5.5

1.98

6

V

AVDD to AVSS

V

DVDD to DVSS

V

CVDD to CVSS

V

TSREF to AVSS

5.5

0

V

REFHP to REFHM

V

NEG5V to AVSS

V

TX, RX to AVSS

6

V

COMHP, COMHN, COMLP, COMLN to CVSS

COMHP to COMHN, COMLP to COMLN

GPIO* to AVSS

20

5.5

240

10

V

–5.5

–0.3

V

CB* current

I/O current

Max of 8 cell in balancing at 75^oC ambient

GPIO*, RX, TX current

mA

Device will not start OTP programming above

this temperature

T_{OTP_PROG}

55

°C

T_A

Ambient temperature

Junction temperature

Storage temperature

130

150

°C

–40

–65

T_J

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) VC pin voltage has to meet criteria of both VCn to AVSS as well as VCn to VCn-1.

(3) CB pin voltage has to meet criteria of both CBn to AVSS as well as CBn to CBn-1.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Electrostatic

discharge

V_(ESD)

All Pins

V

Charged device model (CDM), per AEC

Q100-011

Other pins (1, 16, 17, 32, 33, 48, 49, 64)

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_{BAT_RANG}

Total module voltage, full functionality, no OTP programming

9

80

5

V

E

V_{BAT_OTP_R}

Total module voltage, full functionality, OTP programming allow

11

V

ANGE

V_{CELL_RAN}

VC_n- VC_n-1, where n = 2 to 16

–1

GE

VC1 - VC0

0

-0.3

3

5

V

VC0, CB0 to AVSS

VC1, VC2, CB1, CB2 to AVSS

VCn, CBn to AVSS, where n = 3 to 16

V_{BB_RANGE}V_BBP- V_BBN

80

V

80

V

-600

0

800

5

mV

V

V_{CB_RANGE}CB_n- CB_n-1, where n = 1 to 16

V_{IO_RANGE}RX, TX, NFAULT

0

CVDD

V

V_{GPIO_RAN}

GPIO_ninput, where n = 1 to 8

0.2

4.8

V

GE

I_IO

T_A

GPIO_n, RX, TX, where n = 1 to 8

Operation temperature

5

mA

°C

125

–40

8.4 Thermal Information

BQ7961x-Q1

THERMAL METRIC

PAP (HTQFP)

UNIT

64 PINS

21.6

8.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

7.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JT

7.8

ψ_JB

R_θJC(bot)

2.1

8.5 Electrical Characteristics

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

THERMAL SHUTDOWN

T_SHUT

Thermal shutdown (rising direction)

Thermal shutdown (falling direction)

130

112

137

152

129

°C

T_{SHUT_FALL}

Thermal shutdown (rising - falling

direction)

T_{SHUT_HYS}

20

°C

Thermal warning Threshold (rising

direction)

T_{WARN_RANGE}

85

115

Thermal warning hysteresis (falling

direction)

T_{WARN_HYS}

T_{WARN_ACC}

10

5

°C

Thermal warning accuracy (+/-)

SUPPLY CURRENTS

I_SHDNSupply current in SHUTDOWN mode Sum of both I_BATand I_LDOIN

16

23

µA

12

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8.5 Electrical Characteristics (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Sum of both I_BATand I_LDOIN

T_A= -20℃to 65℃

120

160

220

µA

Baseline supply current in SLEEP

mode. No fault, no protector

comparator, no cell balancing

I_SLP(IDLE)

Sum of both I_BATand I_LDOIN

T_A= -40℃to 125℃

Sum of both I_BATand I_LDOIN

No fault, no communication, no

protector comparator, no cell balancing

Baseline supply current in ACTIVE

mode

I_ACT(IDLE)

10.4

1

11.6

mA

At least 1 cell balancing FET is on,

OT_CBis enabled. Other functions are

inactive

Additional supply current when cell

balancing is on

I_{CB_EN}

1.5

60

Additional supply current when

protector comparator is on

Either OV/UV/OT/UT protector is

enabled. Other functions are inactive

I_PROTCOMP

I_TSREF

20

100

0.4

µA

SLEEP Mode, no load on TSREF pin

One ADC on, and conversion is in

progress. Other functions are inactive

0.6

0.9

mA

Additional supply current when ADC is

enabled

I_ADC

2 ADCs on, and conversion is in

progress. Other functions are inactive

0.6

mA

ACTIVE Mode

SLEEP Mode

150

25

5

µA

I_BAT

Supply current goes into BAT pin

SHUTDOWN Mode

Additional supply current during daisy- Use transformer isolation for daisy-

chain broadcast read of 128-byte data chain interface

I_COMT

10

mA

µA

Additional supply current during daisy- Use capacitor or capacitor and choke

chain broadcast read of 128-byte data isolation for daisy-chain interface

I_COMC

Sink current for open wire test, applies

to VC1 to VC16 and CB1 to CB 16

I_{OW_SINK}

I_{OW_SOURCE}

380

500

600

0.1

Source current for open wire test,

applies to VC0 and CB0

VC, CB pins with ADC off.

I_LEAK

Leakage current on VC, CB pins

Supplies (LDOIN)

No OTP programming

5.9

7.9

6

8

6.1

8.1

V

V_LDOIN

LDOIN voltage

OTP programming

Supplies (CVDD)

ACTIVE and SLEEP mode

4.9

5

5.1

6

V

SHUTDOWN mode, no external Iload

CVDD output voltage

3.95

V_CVDD

SHUTDOWN mode, max external

Iload = 5mA

3.4

–30

5.3

5.5

30

V

mV

V

ACTIVE/SLEEP mode, max external

V_{CVDD_LDRG}

V_{CVDD_OV}

CVDD load regulation

Iload = 10mA

ACTIVE/SLEEP mode, max external

CVDD OV threshold

Iload = 10mA

5.5

5.7

170

ACTIVE/SLEEP mode, max external

V_{CVDD_OVHYS}

CVDD OV Hystersis

Iload = 10mA

130

150

3.5

mV

V

SHUTDOWN mode

V_{CVDD_UV}

CVDD UV threshold

ACTIVE/SLEEP mode, max external

Iload = 10mA

4.3

35

4.45

4.65

85

V

V_{CVDD_UVHYS}

V_{CVDD_ILIMIT}

CVDD UV Hystersis

CVDD current limit

260

60

mV

mA

ACTIVE, SLEEP

Supplies (AVDD)

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MAX UNIT

8.5 Electrical Characteristics (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

C_SUPPLIES= 1µF, ACTIVE mode

C_SUPPLIES= 1µF

MIN

4.85

5.25

135

4.25

235

10

TYP

5

V_AVDD

AVDD output voltage

AVDD OV threshold

AVDD OV Hystersis

AVDD UV threshold

AVDD UV Hystersis

AVDD current limit

5.21

5.7

165

4.6

430

50

V

V_{AVDD_OV}

5.5

155

4.45

340

30

V_{AVDD_OVHYS}

V_{AVDD_UV}

mV

V

V_{AVDD_UVHYS}

V_{AVDD_ILIMIT}

Supplies (DVDD)

V_DVDD

mV

mA

C_SUPPLIES= 1µF, ACTIVE mode

1.72

1.95

40

1.8

2.1

65

1.88

2.3

120

1.71

73

V

V_{DVDD_OV}

DVDD OV threshold

DVDD OV Hystersis

DVDD UV threshold

DVDD UV Hystersis

DVDD current limit

V_{DVDD_OVHYS}

V_{DVDD_UV}

mV

V

1.623

15

1.65

50

V_{DVDD_UVHYS}

V_{DVDD_ILIMIT}

Supplies (TSREF)

V_TSREF

mV

mA

13

30

53

TSREF output voltage

TSREF load regulation

C_SUPPLIES= 1µF, ACTIVE mode

4.975

5

5.025

30

V

I_load= 4mA, C_SUPPLIES= 1µF, ACTIVE

mode

V_{TSREF_LDRG}

V_{TSREF_OV}

V_{TSREF_OVHYS}

V_{TSREF_UV}

V_{TSREF_UVHYS}

V_{TSREF_ILIMIT}

mV

–30

I_load= 4mA, C_SUPPLIES= 1µF, ACTIVE

mode

TSREF OV threshold

TSREF OV Hystersis

TSREF UV threshold

5.2

98

5.6

110

4.2

5.8

120

4.4

V

mV

V

I_load= 4mA, C_SUPPLIES= 1µF, ACTIVE

mode

I_load= 4mA, C_SUPPLIES= 1µF, ACTIVE

mode

4.0

I_load= 4mA, C_SUPPLIES= 1µF, ACTIVE

mode

TSREF UV Hystersis

TSREF current limit

300

15

350

30

400

52

mV

mA

Device in ACTIVE Mode

Negative Charge Pump (NEG5V)

V_NEG5V

C_NEG5V= 0.1µF

-5.0

-4.1

-4.3

-4.6

-3.5

-3.8

-4.5

-3.0

-3.3

V

V_{NEG5V_UV}

NEG5V UV threshold (rising)

V_{NEG5V_UVRECOV}

CELL BALANCE

NEG5V UV Recovery

VCn > 2.8V, where n = 1 to 16;

-40^oC<T_A<125^oC

R_DSON

Internal cell balance FET Rdson

1.45

2.45

18

4.6

4

Ω

V

VCB_DONE detection threhsold

setting range (not accuracy)

V_{CB_DONE}

V_{MB_DONE}

T_OTCB

Step of 25mV

Step of 1V

Step of 2%

VMB_DONE detection threhsold

setting range (not accuracy)

65

24

14

V

OTCB threshold setting range (not

accuracy)

10

%

COOLOFF threshold setting range

(not accuracy)

T_COOLOFF

4

T_{CB_WARN}

CB TWARN threshold

CB TWARN Hysteresis

105

10

^oC

T_{CB_WARN_HYS}

ADC Resolution

Main ADC Effective number of

bits

ENOB_MAIN

ENOB_AUX

16

14

bits

AUX ADC Effective number of bits

14

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8.5 Electrical Characteristics (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Main and AUX ADC Resolution for

VCELL measurement

V_{LSB_ADC}

V_{LSB_BB}

190.73

µV/LSB

Main and AUX ADC Resolution for

(BBP-BBN) measurement

30.52

0.025

3.05

µV/LSB

°C/LSB

mV/LSB

V_{LSB_MAIN_DIETEMP}

ADC measurement is centered with

0x000 = 0^oC

DieTemp1 resolution (Main ADC)

1

ADC measurement is centered with

0x000 = 0^oC

V_{LSB_AUX_DIETEMP2}DieTemp2 resolution (AUX ADC)

Applies to BAT voltage measurement

from AUX ADC

V_{LSB_AUX_BAT}

BAT resolution (AUX ADC)

GPIO resolution (Main & AUX

ADC)

V_{LSB_GPIO}

152.59

169.54

µV/LSB

V_{LSB_TSREF}

TSREF resolution (Main ADC)

REFL, VBG2, LPBG5, VCM,

AVAO_REF, AVDD_REF, HW protector

DAC

Diagnostic measurements resolution

V_{LSB_DIAG}

152.59

190.73

µV/LSB

OV_DAC, UV_DAC, VCBDONE_DAC

V_{LSB_DIAG}

ADC Accuracy

T_A= -20^oC to 65^oC

T_A= -40^oC to 105^oC

1.8

2

µA

VCn to VCn-1 input current

delta (when Main ADC is on)

I_{VC_DELTA}

VCn input current (when Main ADC is

on)

I_VC

8

12

µA

CB pin input impedance (when AUX

ADC is on)

R_{CB_INPUT}

16

MΩ

2V<V_CELL<4.5V; T_A=25^oC

-2.2

-3.0

-3.5

-3.7

-4.5

-7.5

-8.0

-9.0

-7.1

-7.8

-7.9

-0.20

-0.30

1.5

2.4

2.6

2.8

3.2

5.4

6.3

6.5

6.6

6.1

6.6

6.7

6.9

0.20

0.30

mV

%

2V<V_CELL<4.5V; -20^oC<T_A<65^oC

2V<V_CELL<4.5V; -40^oC<T_A<105^oC

2V<V_CELL<4.5V; -40^oC<T_A<125^oC

1V<V_CELL< 5V; -40^oC<T_A<125^oC

-2V<V_CELL< 5V; -40^oC<T_A<125^oC

2V<V_CELL<4.5V; T_A=25^oC

Total channel accuracy for main ADC

VCELL

measurement, LPF_VCELL[2:0] =

0x03 setting;

V_{ACC_MAIN_CELL}

V_{ACC_AUX_CELL}

V_(MAIN-AUX)

2V<V_CELL<4.5V; -20^oC<T_A<65^oC

2V<V_CELL<4.5V; -40^oC<T_A<105^oC

2V<V_CELL<4.5V; -40^oC<T_A<125^oC

1V<V_CELL< 5V; -40^oC<T_A<125^oC

0V<V_CELL< 5V; -40^oC<T_A<125^oC

2V<V_CELL<4.5V; T_A=25^oC

Total channel accuracy for AUX ADC

measurement (excluding BAT and

GPIO accuracy);

2V<V_CELL<4.5V; -20^oC<T_A<65^oC

2V<V_CELL<4.5V; -40^oC<T_A<105^oC

2V<V_CELL<4.5V; -40^oC<T_A<125^oC

1V<V_CELL< 5V; -40^oC<T_A<125^oC

0V<V_CELL< 5V; -40^oC<T_A<125^oC

0.08V<V_IN<0.2V, 85^oC<T_A<125^oC

0.2V<V_IN<4.6V, -40^oC<T_A<105^oC

4.6V<V_IN<4.8V, -40^oC<T_A<-20^oC

Main - AUX measurement during

VCELL and OVDAC Reference

diagnostic. Same input voltage to both

ADC under same T_A;

V_{ACC_MAIN_GPIO_RA}Measured GPIO from Main ADC/

%

measured TSREF from Main ADC;

TIO

%

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MAX UNIT

8.5 Electrical Characteristics (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

-0.20

-0.30

-4.00

-5.00

-4.00

-6.00

TYP

0.08V<V_IN<0.2V, 85^oC<T_A<125^oC

0.2V<V_IN<4.6V, -40^oC<T_A<105^oC

4.6V<V_IN<4.8V, -40^oC<T_A<-20^oC

0.08V<V_IN<0.2V, 85^oC<T_A<125^oC

0.2V<V_IN<4.6V, -40^oC<T_A<105^oC

4.6V<V_IN<4.8V, -40^oC<T_A<-20^oC

0.08V<V_IN<0.2V, 85^oC<T_A<125^oC

0.2V<V_IN<4.6V, -40^oC<T_A<105^oC

4.6V<V_IN<4.8V, -40^oC<T_A<-20^oC

0.20

0.30

4.00

3.00

4.00

6.00

%

V_{ACC_AUX_GPIO_RA}Measured GPIO from AUX ADC/

%

measured TSREF from AUX ADC;

TIO

%

mV

V_{ACC_MAIN_GPIO_AB}Total channel accuracy for GPIO

measurement (Main ADC);

S

V_{ACC_AUX_GPIO_AB}

Accuracy from AUX ADC on GPIO

S

Total channel accuracy for (BBP-BBN)

from Main ADC

V_{ACC_MAIN_BB}

LPF_BB[2:0] = 0x00

-1.1

-4

1.1

4

mV

Total channel accuracy for (BBP-BBN)

from AUXADC

V_{ACC_AUX_BB}

AUX ADC measurement accuracy for Vbat pack range: 32V to 72V, T_A

BAT pin

=

V_{ACC_AUX_BAT}

-225

135

-40^oC to 125^oC

V_{ACC_AUX_REFL}

V_{ACC_AUX_VBG2}

V_{ACC_AUX_VCM}

AUX ADC measurement result

1.092

2.400

1.1

2.5

1.106

2.550

V

V_{ACC_AUX_AVAO_RE}

AUX ADC measurement result

2.400

2.47

2.550

V

F

V_{ACC_AUX_AVDD_RE}

F

V_{ACC_AUX_OVDAC}

V_{ACC_AUX_UVDAC}

AUX ADC measurement result

Setting at 4.475V; T_A= -20^oC to 65^oC

Setting at 4.475V; T_A= -40^oC to 105^oC

Setting at 4.475V; T_A= -40^oC to 125^oC

Setting at 3.8V

4.450

4.445

3.770

2.970

3.095

4.500

3.825

3.030

3.150

V

Setting at 3V

Setting at 3.1V

3.1

4

V_{ACC_AUX_VCBDONE}

AUX ADC measurement result

Setting at 4V

3.950

4.050

V

DAC

V_{ACC_AUX_OTDAC}

V_{ACC_AUX_UTDAC}

AUX ADC measurement result

Setting at 39%

Setting at 80%

1.900

3.950

4.975

1.95

4

2.000

4.050

5.025

V

V_{ACC_MAIN_TSREF}Main ADC measurement result

5

V_{ACC_MAIN__DIETEM}Total channel accuracy for Die Temp1

3

6

℃

measurement (+/-)

P

Total channel accuracy for Die Temp2

V_{ACC_AUX_DIETEMP}

measurement (+/-)

Reference Voltages

V_REFH

REFHP to REFHM voltage

4.975

5

5.025

V

HW Voltage Comparator/Protector (CELL OV/UV)

Step of 25mV

2700

3600

4175

3000

3800

4500

mV

OV comparator detection

V_{OV_COMP_RANGE}

threshold setting range (not accuracy)

OV comparator hysteresis after

V_{OV_COMP_HYS}

detection

50

mV

T_A= -20^oC to 65^oC

T_A= -40^oC to 105^oC

-24

-28

24

28

mV

V_{OV_COMP_ACC}

OV comparator accuracy

16

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8.5 Electrical Characteristics (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

UV comparator detection threshold

setting range (not accuracy)

V_{UV_COMP_RANGE}

V_{UV_COMP_HYS}

Step of 50mV

1200

3100

mV

UV comparator hysteresis

after detection

50

T_A= -20^oC to 65^oC

T_A= -40^oC to 105^oC

-35

-50

35

50

mV

V_{UV_COMP_ACC}

UV comparator accuracy

HW Temperature Comparator/Protector (NTC OT/UT)

OT comparator

V_{OT_COMP_RANGE}detection threshold setting range (not

accuracy)

Step of 1%, ratiometric with respect to

TSREF

10

39

%

OT comparator hysteresis

V_{OT_COMP_HYS}

2

%

after detection

V_{OT_COMP_ACC}

OT comparator accuracy

-0.5

66

0.5

80

UT comparator detection threshold

range

Step of 2%, ratiometric with respect to

TSREF

V_{UT_COMP_RANGE}

UT comparator hysteresis

after detection

V_{UT_COMP_HYS}

V_{UT_COMP_ACC}

%

UT comparator accuracy

-0.5

0.5

0.3

Digital I/Os (TX, RX, GPIO, SPI master)

Output as logic level high (TX, GPIO

as output)

GPIO is configured as output. I_OUT

1mA

=

V_CVDD-0

.3

V_OH

V_OL

V_IH

V_IL

V

Output as logic level low (TX, NFAULT, GPIO is configured as output. I_OUT

GPIO as output) 1mA

Input as logic level high (RX, GPIO as GPIO is configured as input. I_OUT

fault input) 1mA

=

0.75 x

V_CVDD

Input as logic level low (RX, GPIO as GPIO is configured as input. I_OUT

fault input)

=

0.25 x

V_CVDD

1mA

R_{WK_PU}

GPIO weak pull-up resistance

GPIO weak pull-down resistance

20

37

40

60

KΩ

R_{WK_PD}

COML and COMH

Transmitter output impedance (COML

and COMH)

R_DCTX

18

45

Ω

kΩ

V

Common mode impedance (COML

and COMH)

R_DCCM

Common mode voltage (COML and

COMH)

V_DCCM

2.21

0.4

2.5

2.76

1.2

Receiver threshold range (V_COMP

-

V_{COMM_DATA1}

V_{COMM_TONE1}

CODE:0

V

V_COML) form communication

Receiver threshold range (V_COMP

V_COML) form Tone

-

0.4

1.2

V

8.6 Timing Requirements

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

POWER STATE TIMING

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MAX UNIT

8.6 Timing Requirements (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

Base device: From the end of WAKE

ping to the start of a forwading WAKE

tone

6

10

ms

µs

Startup from SHUTDOWN to ACTIVE

mode

t_{SU(WAKE_SHUT)}

Stack device: From the end of a

recevied WAKE tone to the start of a

forwading WAKE tone

6

Base device: From the end of

SLEEP2ACTIVE ping to the start of

the forwarding SLEEP2ACTIVE tone

230

1

Startup from SLEEP to ACTIVE mode

(with SLEEP2ACTIVE ping/tone)

t_SU(SLP2ACT)

Stack device: From the end of

SLEEP2ACTIVE tone to the start of

the forwarding SLEEP2ACTIVE tone

µs

Base device: From the end of WAKE

ping to the start of a forwading WAKE

tone

ms

Startup from SLEEP to ACTIVE mode

(with WAKE ping/tone)

t_{SU(WAKE_SLP)}

Stack device: From the end of a

recevied WAKE tone to the start of a

forwading WAKE tone

1

ms

µs

From receiving SLEEP entry condition

to enter in SLEEP mode

t_SLP

From ACTIVE to SLEEP mode

From ACTIVE to SHUTDOWN mode

Reset time during ACTIVE mode

100

From receiving SHUTDOWN entry

condition to enter in SHUTDOWN

mode (all LDOs in 10% of their

norminal value)

t_SHTDN

20

ms

CONTROL1[SOFT_RST] = 1 is sent to

a completion of the digital reset

t_RST

1

ms

The time device will be in HW reset,

after HW reset ping/tone issued

t_HWRST

75

SUPPLIES TIMING

t_{TSREF_ON}

TSREF ramp up time (10%-90%)

TSREF ramp down time (90%-10%)

C_TSREF= 1µF

6

ms

t_{TSREF_OFF}

8

PING SIGNAL TIMING

WAKE ping low time on RX pin; no

t_{HLD_WAKE}

2

7

2.5

10

ms

external load on CVDD

SHUTDOWN ping low time on RX pin;

no external load on CVDD

t_{HLD_SD}

SLEEPtoACTIVE ping low time on RX

t_UART(StA)

250

36

300

µs

t_{HLD_HWRST}

HW_RESET ping low time on RX pin

ms

COML and COMH (PULSE and TONE TIMING)

COMM: Pulse width of data (half bit

time) for communiction

t_{PW_DC}

250

4

ns

µs

COMM: data reclocking delay

per device from COMH to COML or

viceversa

t_{RECLK_DC}

5

Time between pulses of comm tones

(HFO based). Comm Tones are

WAKE, SLEEPtoACTIVE,

t_COMTONE

11

15

µs

SHUTDOWN, HWRST tones

The HIGH time of each comms pulse

(HFO base)

t_{COMMTONE_HI}

t_{COMMTONE_LO}

0.92

1

1.08

µs

The LOW time of each comms pulse

(HFO base)

18

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8.6 Timing Requirements (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

Time between pulses of FAULT Tone

(LFO based). Applies to FAULT Tone

and HEARTBEAT

t_FLTTONE

11.5

µs

The HIGH time of each pulse of the

tone couplete

t_{FLTTONE_HI}

t_{FLTTONE_LO}

n_WAKEDET

n_WAKE

1

µs

The LOW time of each pulse of the

tone couplete

µs

Number of pulses to detect as a

WAKE tone

60

pulses

Number of pulses to transit for a

WAKE tone

90

Number of pulses to detect as a

SHUTDOWN tone

n_SHDNDET

n_SHDN

180

270

20

Number of pulses to transit for a

SHUTDOWN tone

Number of pulses to detect as a

SLEEPtoACTIVE tone

n_SLPtoACTDET

n_SLPtoACT

n_HWRSTDET

n_HWRST

Number of pulses to transit for a

SLEEPtoACTIVE tone

30

Number of pulses to detect as a

HW_RESET tone

540

810

20

Number of pulses to transit for a

HW_RESET tone

HEARTBEAT: Number of pulses to

detect as a valid tone

n_HBDET

HEARTBEAT: Number of pulses

to transit for a tone

n_HB

30

HEARTBEAT: Period

between HEARTBEAT Burst (from the

beginning of a HEARTBEAT to the

beginning of the next HEARTBEAT)

t_{HB_PERIOD}

t_{HB_TIMEOUT}

t_{HB_FAST}

360

0.9

400

1

440

1.1

ms

s

HEARTBEAT: Timeout to

considered as not receving

HEARTBEAT

HEARTBEAT: If HEARTBEAT

is received within this time, it is

considered receving HEARTBEAT too

fast

200

ms

FAULT TONE: Number of pulses to

detect as a valid tone

n_FTONEDET

n_FTONE

60

90

pulses

FAULT TONE: Number of pulses

to transit for a tone

FAULT TONE: Period between

FAULT TONE Burst (from the

beginning of a FAULT TONE to the

beginning of the next

t_{FTONE_PERIOD}

50

ms

FAULT TONE)

From time a device receive the tone to

the time the same device detects and

generate its fault tone

t_{FTS_LATENCY}

Fault Tone latency in Stack Device

Fault Tone latency in Base Device

48

24

µs

From the time a device receive the

tone to the time the same device

detects and asserts NFAULT

t_{FTB_LATENCY}

MAIN and AUX ADC TIMING

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8.6 Timing Requirements (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

Single conversion time (both Main and

AUX ADCs)

t_{SAR_CONV}

8

µs

t_{MAIN_ADC_CYCLE}

t_{AUX_ADC_CYCLE}

Single round robin cycle (Main ADC)

Single round robin cycle (AUX ADC)

192

µs

Analog front end (Level shifters)

settling time whenever device enter

ACTIVE mode from SLEEP or

SHUTDOWN

t_{AFE_SETTLE}

4

ms

This includes mux round robin, ADC

conversions, and digital filters.

t_{ADC_ACC}

BALANCING TIMING

-1.5

-5

1.5

5

%

t_{BAL_ACC}

Balancing timer accuracy

HW COMPARATORS/PROTECTORS TIMING

t_{OV_CYCLE}

t_{UV_CYCLE}

OV round robin cycle

UV round robin cycle

8

ms

t_{OVUV_BIST_CYCLE}OV and UV BIST cycle

21.8

10.9

23

4

24.2

12.1

t_{OT_CYCLE}

t_{UT_CYCLE}

OT round robin cycle

UT round robin cycle

4

Time needed for the power supply

BIST to complete after the power BIST

go command

t_{PWR_BIST_CYCLE}

11.5

20

ms

t_{OTUT_BIST_CYCLE}

t_{HW_COMP_ACC}

OT and UT BIST cycle

19

-5

21

5

ms

%

OV,UV,OT,UT comparators

timing accuracy

I/O TIMING (TX, RX, GPIO, NFAULT)

V_CVDD> MIN V_CVDD, C_LOAD= 150pF,

GPIO in output mode

t_RISE

Rise Time

12

7

ns

V_CVDD> MIN V_CVDD, C_LOAD= 150pF,

GPIO in output mode

t_FALL

Fall Time (exclude NFAULT)

Fall Time on NFAULT

V_CVDD> MIN V_CVDD, C_LOAD= 150pF,

R_PULLUP= 10kΩ

t_{FALL_NFAULT}

100

UART TIMING

UART_BAUD

UART TX/RX Baud Rate

1

Mbps

%

UART RX baud rate error -

requirement on the external host

UART_{ERR_BAUD(RX)}

-1

-1.5

15

1

1.5

20

UART_{ERR_BAUD(TX)}UART TX baud rate error

%

bit

period

t_UART(CLR)

UART Clear low time

After COMM CLEAR, wait this time

before sending new frame

bit

period

t_{UART(RX_HIGH)}

OTP NVM TIMING

t_{CRC_CUST}

1

Time to complet a single cycle of CRC

check on the customer OTP space

175

1.6

µs

Time to complet a single cycle of CRC

check on the factory OTP space

t_{CRC_FACT}

ms

SPI MASTER TIMING

f_SCLK

SCLK frequency

SCLK duty cycle

450

500

50

550

kHz

%

t_HIGH,t_LOW

20

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8.6 Timing Requirements (continued)

over operating -40℃to 125℃free-air temperature range, VBAT = 9V to 80V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX UNIT

SS HIGH latency time. Time

from register write high to SS pin high

t_SS(HIGH)

t_SS(LOW)

t_SU(MISO)

4

µs

SS LOW latency time. Time

from register write low to SS pin low

4

µs

MISO input data setup time -

requirement for slave device

MISO stable before SCLK transition

MISO stable after SCLK transition

100

ns

t_HD(MISO)

OSCILLATOR

f_HFO

MISO input dat hold time

0

High frequency oscillator

Low frequency oscillator

31.52

248.9

32

32.48 MHz

f_LFO

262

275.1

kHz

8.7 Typical Characteristics

150

145

140

135

130

125

120

11.1

10.9

10.7

10.5

10.3

10.1

9.9

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

图8-1. ISLP (IDLE) vs Temperature

图8-2. IACT (IDLE) vs Temperature

0

-20

3.5

3.3

3.1

2.9

2.7

2.5

2.3

2.1

1.9

1.7

-40

-60

LPF 6.5Hz

LPF 13Hz

LPF 26Hz

LPF 53Hz

LPF 111Hz

LPF 240Hz

-80

-100

-120

1

10

100

1000 10000 100000 1000000

Frequency (Hz)

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

图8-4. Digital Low Pass Filter

图8-3. CBFET RDSON vs Temperature

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0

-20

0

-20

-40

-60

-80

AAF 0.7kHz

AAF 1.4kHz

AAF 2.9kHz

-100

-120

AAF 1.6kHz

-120

1

10

100

1000 10000 100000 1000000

Frequency (Hz)

1

10

100

1000 10000 100000 1000000

Frequency (Hz)

图8-5. MAIN ADC Filter

图8-6. AUX ADC Filter

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9 Detailed Description

9.1 Overview

The BQ7961x-Q1 device is a stackable battery monitor that measures cell voltages and temperature. The device

supports 6 to 16 series-connected (6S to 16S) battery cells. It allows up to 3 bus bar connections and

measurements using cell sensing input channels or a dedicated bus bar channel maximizing the device flexibility

to support various battery module sizes.

Multiple devices can be connected in a daisy chain. Each device has a pair of high (north) and low (south)

vertical differential communication ports, requiring only one twisted pair cable. The device supports either

capacitive only, capacitive and choke, or transformer isolation. Communication is reclocked on each daisy-

chained device, ensuring communication integrity for long distances. An optional RING connection is supported

to reverse the daisy chain communication direction in case of cable failure. Each device includes a SPI master

configured through the GPIOs.

The device is ASIL-D compliant on voltage and temperature measurements, and communication. The ADCs in

the daisy-chained devices can be configured to align the start of cell voltage measurements and all cell voltages

can be measured within 128 μs. Each cell sensing channel includes with a post-ADC digital low-pass filter

(LPF) for noise reduction as well as providing moving average measurement results. The device has 8 GPIOs,

all of which are configurable for NTC thermistor connections or use as general purpose I/O. All 8 GPIOs can be

measured within 1.6 ms.

The device supports passive balancing through an internal cell balancing MOSFET (CBFET) for each cell. The

balancing function runs autonomously without microcontroller (MCU) interaction. It includes an option to pause

and then resume balancing based on a programmable threshold detected by the external thermistor or if the die

temperature is too high (greater than 105°C). Once balancing starts, the device tracks the balancing time on

each cell. MCU can read out the remaining balancing time at any time.

The device includes a hardware OVUV comparator and an OTUT comparator with user configurable thresholds.

These can be used as a second-level protector for cell over- and undervoltage and thermistor over- and

undertemperature detections independent of ADC measurements.

The device provides an option to embed fault status information to the communication frame. When a device in

the daisy chain detects a fault condition, this information is embedded and travels along the communication

response frame to the bottom device which can be configured to trigger an NFAULT pin as an interrupt signal to

the system. This provides a way to reduce communication overhead without adding an additional twisted pair

cable and isolation for faster fault detection.

The device has SLEEP and SHUTDOWN modes for lower power consumption. All functions work in ACTIVE

mode, balancing and hardware comparators for OVUV and OTUT also work in SLEEP mode. While in

SHUTDOWN, all active functions are turned off. A HW reset function is available and can be activated by the

host MCU. The HW reset provides a POR-like event to the device without actual battery removal. This provides

a reliable, low cost, and recoverable option to improve overall system robustness.

9.2 Functional Block Diagram

The BQ79616 functional block diagram also applies to BQ79614 and BQ79612 but with fewer VC and CB input

channels.

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BBP

COMM/FAULT VIF

COMHP

COMHN

TSREF

DVDD

AVDD

Pre-reg

AVAO

CVDD

POR

BBN

COM VIF

North

VC16

COMLP

COMLN

VC15

COM VIF

SOUTH

Main ADC (SAR)

VC14

Die Temp1

Tone/Ping Detection

VC13

Digital

VC[0:16]

BBP

Filters

(BCI &

AAF),

LS

:

SAR

ADC

VC12

VC11

VC10

VC9

LPF

BBN

MUX

HW RESET

Detection

REF

Osc

GPIO1

:

MUX

GPIO8

VC8

AUX ADC (SAR)

Die Temp2

CB0

OV, UV, VCBDONE

VC0

VC7

VC6

Protectors

:

CB

MUX

CB16

BBP/BBN

GPIO1

Voltage

Comp

:

LS

MUX

Digital

VC5

Digtial

VC16

SAR

ADC

MUX

:

VC4

VC3

GPIO

MUX

OT, UT, OTCB

GPIO8

GPIO1

Diag ch1

Temp

Comp

:

LS

:

MUX

Digital

VC2

GPIO8

Diag ch 12

VC1

VC0

Cell Balance

CB16

NFAULT

CB16

CB15

CB14

CB13

CB12

CB11

CB10

CB9

Q_CB16

RX

TX

CB15

:

CB1

Digital

CB Control

GPIO1

GPIO2

Q_CB1

CB0

I/O

Charge Pump

TWARN

GPIO3

GPIO4

Registers

OTP

GPIO5

GPIO6

CB8

24

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9.3 Feature Description

9.3.1 Power Supplies

The device generates directly from the battery stack all required supplies for its operation. The following

subsections provide an overview of each internal supply block. See 节 10 for recommended component

connection. See 节9.3.6.4 for diagnostic control and fault detection on the power supplies block.

9.3.1.1 AVAO_REF and AVDD_REF

The AVAO_REF block (analog voltage always on) is powered from the BAT pin. It powers the always-on low-

current circuits that are required for all power modes. This block also generates a preregulated reference,

AVAO_REF. The AVAO_REF voltage passes through a load switch controlled by the SHUTDOWN mode. The

reference voltage after the load switch is AVDD_REF.

Always-On (AVAO) Block

AVAO_REF

AVDD_REF

Pre-

regulation

Switch

BAT

Reference

Systems

Shutdown

Logic

图9-1. AVAO Block

9.3.1.2 LDOIN

The device is powered from the battery module in which the current draw for each cell is the same. From the top

of the battery module, the device generates a 6-V regulated voltage (nominal) on the LDOIN pin through the

internal linear regulator and an external NPN transistor.

The NPNB pin controls the external NPN transistor of the regulator and a maximum current of 1.15mA can be

drawn from this pin.

The LDOIN output is the preregulated input to the rest of the internal low-dropout regulators (LDOs). During OTP

(One-Time Programmable) memory programming, the LDOIN pin will be regulated to 8 V (nominal) to supply the

programming voltage internally to the OTP programming. The LDOIN is turned off only during HW reset or a

POR event.

9.3.1.3 AVDD

The AVDD LDO is the supply for the analog circuits. It takes the input voltage from LDOIN and generates a

nominal 5 V. It will not be used to power any external circuit. This LDO is powered down in SHUTDOWN mode,

during HW reset, or a POR event.

9.3.1.4 DVDD

The DVDD LDO is the supply for the digital circuits. It takes the input voltage from LDOIN and generates a

nominal 1.8 V. It will not be used to power any external circuit. This LDO is powered down in SHUTDOWN

mode, during HW reset, or a POR event.

9.3.1.5 CVDD and NEG5V

The CVDD LDO is the supply for the daisy chain interface (or vertical interface, VIF) and the I/O pins (RX, TX,

NFAULT, and GPIOs). It takes the input voltage from LDOIN and generates a nominal 5V. Besides providing

power for internal usage, this LDO can support an extra 10mA external load in ACTIVE and SLEEP mode,

whereas extra 5mA external load in SHUTDOWN mode.

There is a –5V charge pump used for the daisy chain interface (or vertical interface, VIF) and Main ADC blocks.

The NEG5V pin has a –4.6V output (nominal). It will be in a low-power burst mode when the device is in SLEEP

or SHUTDOWN mode.

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9.3.1.6 TSREF

The TSREF is a 5-V buffered reference that can bias the external thermistor circuits, allowing the ADCs to

measure temperature and the OTUT protector to detect temperature faults. This reference is measurable by the

Main ADC. Both TSREF and GPIO measured by the Main ADC give a ratiometric measurement for best

temperature measurement.

The TSREF is capable of supplying up to I_{TSREF_ILMIT}and will not be used to power any external circuit other

than the thermistor bias. The TSREF is off by default and can be enabled or disabled through the

CONTROL2[TSREF_EN] bit. The startup time of TSREF is determined by the external capacitance. The MCU

ensures TSREF is stable before making any GPIO measurement or OTUT protector detection. After enabling

TSREF LDO, user shall wait 1.35ms before sending the next command.

9.3.2 Measurement System

There are two SAR ADCs in the device, a 16-bit Main ADC and a 14-bit AUX ADC; both use a precision

reference (REFH) for high-accuracy measurement. Each ADC has its own independent control and can be

enabled or disabled separately. The Main ADC is the main measurement for cell voltages (VCELL) and

temperature through thermistors connecting to the GPIOs. It also provides TSREF and die temperature

measurements. The AUX ADC is mainly used during diagnostic procedures such as providing measurements on

internal reference voltages or DAC output of the OVUV and OTUT comparators. It serves as a redundancy

measurement for cell voltage inputs and thermistor temperature input through the GPIOs.

The subsections below provide an overview of the Main and AUX ADCs measurement paths. See 节 10 for the

recommended external component connection. See 节 9.3.6.4 for the diagnostic control function and status of

this block.

9.3.2.1 Main ADC

There are total of 24 inputs (slots) multiplexed to the Main ADC (图 9-2). All inputs are measured in round robin

fashion (图 9-3). Each input takes 8 μs (nominal) to measure and a single round robin cycle completes in 192

μs (nominal). The inputs to the Main ADC are:

• Die temperature 1

• TSREF

• Cell1 to Cell16 voltages through differential VC_n–1to VC_n, where n = 1 to 16

• Bus bar input through differential BBP–BBN pins

• Multiplexed GPIO1 through GPIO8

• Spares (RSVD)

All measurements are reported in 16-bit hexadecimal in 2s complement. Results are reported to the

corresponding *_HI (high-byte) and *_LO (low-byte) registers. First, convert the hexadecimal results to decimal

values. Follow the equations in 表9-1 to translate the result to μV or °C.

When the Main ADC is enabled, all Main ADC-related result registers shown in 表 9-1 are reset to the default

value 0x8000. The measured result is populated to the result registers as the main ADC makes its conversion

along the round robin cycle. When MCU reads the *_HI register, the device will pause the data refresh to the

associated *_LO register until that *_LO register is read.

表9-1. Main ADC Measurement Conversion Equations

Main ADC Inputs

Result Registers

Conversion Equations

Result in °C = V_{LSB_MAIN_DIETEMP1}* Result in decimal

0x0000h is centered to 0°C.

Die Temperature 1

DIETEMP1_HI/LO

TSREF

TSREF_HI/LO

Result in μV = V_{LSB_TSREF}* Result in decimal

Result in μV = V_{LSB_ADC}* Result in decimal

Result in μV = V_{LSB_BB}* Result in decimal

Result in μV = V_{LSB_GPIO}* Result in decimal

Cell1 to Cell16

Bus Bar

VCELL*_HI/LO, where * = 1 to 16

BUSBAR_HI/LO

GPIO1 to GPIO8

GPIO*_HI/LO, where * = 1 to 8

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DieTemp1

TSREF

Die Temp1 register

TSREF register

If LFP is disabled

VC16

:

VC0

:

BCI

BCI filter

filter

Level

shifter

Level

SAR

ADC

AAF

VCELL1...16 registers

Digital

LPF

Digital

BBP

BBN

MUX

De-MUX

LPF

Busbar register

If LFP is disabled

GPIO8

:

GPIO MUX

GPIO1

GPIO1..8 registers

图9-2. Main ADC Measurement Path

MAIN ADC

Typ 192 µs

Typ 8 µs

. . .

Round robin 1

Round robin 8

DieTemp1

Spare

. . .

TSREF

Cell1

Cell16

Busbar

GPIO1

GPIO8

Spare

. . .

DieTemp1

. . .

Spare

Round robin N

图9-3. Main ADC Round Robin Measurements

9.3.2.1.1 Cell Voltage Measurements

9.3.2.1.1.1 Analog Front End

The cell voltage measurements of the Main ADC are taken from the VC0 through VC16 pins. The device allows

a minimum of 6 cells to a maximum of 16 cells to be measured. The VC0 through VC16 pins are connected to

the analog front end which consists of a BCI filter, level shifter, and an anti-aliasing filter (AAF) on each VC input

channel. The BCI filter has a cutoff frequency (f_cutoff) of 100 kHz and the AAF has f_cutoffof 1.6 kHz. This filters out

high-frequency noise on the VC input before going to the high-voltage multiplexer and measured by the Main

ADC. The level shifter block is turned off to save power in SLEEP and SHUTDOWN modes.

9.3.2.1.1.2 VC Channel Measurements

The VC pins are the input channels for cell voltage measurements from the Main ADC measured in the Cell1 to

Cell16 slots of the round robin. The round robin timing is always the same even if fewer than 16 cells are

connected to the device (图 9-4). That is, for the inactive (or unused) VC channel, the device ignores the

respective cell slot, but it does not remove the slot from the round robin cycle. This keeps a consistent

measurement timing regardless of the cell number configuration. It also provides a consistent sampling time to

the post-ADC digital LPF input.

To determine the number of active VCELL channels for ADC measurement, the ACTIVE_CELL[NUM_CELL3:0]

parameter sets the highest active channel number. The device assumes any VC channel below the setting is

also active. For example, when a 14S is connected to the device, the MCU sets the [NUM_CELL3:0] to 14S, the

Main ADC ignores channel 15 and channel 16 measurements and takes measurements on channels 1 through

14.

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The measurement results are reported in the corresponding VCELL*_HI (high-byte) and VCELL*_LO (low-byte)

registers, where * = 1 to 16. If the digital LPFs are disabled, the result registers are reported with the single ADC

conversion values; otherwise, the result registers are reported with filtered measurement values. For an inactive

VC channel, the respective _HI and _LO registers remain with the default value 0x8000.

MAIN ADC

Typ 192 µs

. . .

DieTemp1

. . .

Cell1

Cell14

Cell15

Cell16

. . .

Spare

ACTIVE_CELL[NUM_CELL3:0] = 14S,

Indicating —Cell15“ and —Cell16“ are

Inactive channels

Inactive slots remain in the round robin, but device does not make the measurement

图9-4. Same Round Robin Timing for 6S Through 16S

9.3.2.1.1.3 Post-ADC Digital LPF

Each differential VC channel measurement is equipped with a post-ADC LPF. The LPFs have much lower cutoff

frequency (f_cutoff). There are 7 f_cutoffoptions: 6.5 Hz, 13 Hz, 26 Hz, 53 Hz, 111 Hz, 240 Hz, and 600 Hz,

configurable through the ADC_CONF1[LPF_VCELL2:0] setting. Once an f_cutoffvalue is selected and the LPFs

are enabled by setting ADC_CTRL1[LPF_VCELL_EN] = 1, the same f_cutoffsetting applies to all VC channel

measurements.

The digital LPF is implemented as single-pole filter which responds very similarly as an analog RC circuit. This

means the Main ADC will be running in continuous mode for the digital LPFs to produce effective filtered results.

The MCU should take into account the digital filter settling time when there is a step change in the input DC

voltage level. Equation below gives a typical estimate of digital filter settling time to hit settling accuracy

threshold for a step in VC voltage.

Digital Filter Settling Time ~ [ ({log10 (Settling Accuracy Threshold [mV] / Voltage Step in Input Voltage [mV])} /

{log10(1 - Filter Coefficient)}) - 1] x 0.192 ms

Fcutoff (Hz)

600

240

111

53

26

13

6.5

Filter Coefficient 0.5

0.25

0.125

0.0625

0.03125

0.015625

0.007813

For example: If VC step by 15mV, and user has to accommodate ~27ms settling time to within 1 LSB of input

step for 26Hz LPF setting.

When the LPF starts, from disabled to enabled state, it jumps to its first input value and starts the filtering from

that point. As compared to starting from 0 V or some mid-level voltage, this implementation allows a fast settling

time for Main ADC and LFP is just starting.

9.3.2.1.1.4 BBP and BBN Measurements

The BBP and BBN pins are the inputs for bus bar measurement from the Main ADC. The intent of the BB

channel is to enable the system to share a bus bar with a cell to a single VC channel, as the example shows in

图9-5. Hence, similar to the VC inputs, the BBP/N inputs also have the BCI, Level-Shifters, and AAF filters in the

front end. The differential BB channel measurement also has an option to pass-through a post-ADC digital LPF.

With the same f_cutoffoption as for the VC channel by using different configuration and enable control,

ADC_CONF1[LPF_BB2:0]and ADC_CTRL1[LPF_BB_EN].

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+

VC6

CB6

+

CELL6

BusBar

BBP

BBN

VC5

CB5

+

图9-5. Simplified BBP and BBN Connections

The BB channel measurement is reported in the BUSBAR_HI (high-byte) and BUSBAR_LO (low-byte) registers.

If the digital LPF is disabled, the result registers are reported with the single ADC conversion value; otherwise,

the result is reported in the filtered measurement value. In 图 9-5, to obtain the actual Cell6 measurement, the

MCU takes the difference of (VCELL6_HI/LO measurement – BUSBAR_HI/LO measurement). If the BBP and

BBN pins are not used (floating), the BUSBAR_HI/LO register values are meaningless. The MCU will ignore

these register values.

9.3.2.1.2 Temperature Measurements

9.3.2.1.2.1 DieTemp1 Measurement

There are 2 die temperature sensors, DieTemp1 and DieTemp2. The DieTemp1 is routed to the Main ADC and it

is also used for the Main ADC gain and offset correction internally. The measurement is reported in the

DIETEMP1_HI (high-byte) and DIETEMP1_LO (low-byte) registers. The 0°C measurement is centered to hex

value 0x0000h, so a positive value represents a positive temperature and a negative value represents a

negative temperature. The measurement is also capped off to +200°C and –100°C.

9.3.2.1.2.2 GPIOs and TSREF Measurements

There are eight GPIOs. All GPIO inputs are available to be used for thermistor connections for temperature

measurements and be used as a simple, single-ended, voltage input measurement.

Device

TSREF

1 µF

R₁

R_filter

(optional)

GPIO1

R₂

(OPTIONAL)

C_filter

(optional)

图9-6. Thermistor Connection

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图9-6 shows the thermistor circuit when GPIO is enabled for thermistor measurements. MCU ensures TSREF is

enabled by setting CONTROL2[TSREF_EN] = 1 and settled before taking the measurement value.

The GPIOs are multiplexed to one of the Main ADC MUX inputs. That is, in a single round robin cycle, only one

GPIO is measured. To complete all eight GPIO measurements, it takes eight round robin cycles.

To enable the GPIO for ADC measurement, the corresponding GPIO_CONFn[GPIO*2:0] (where n = 1 to 4, * = 1

to 8 for the corresponding GPIO) register is configured to ADC input or ADC and OTUT input. For example, to

enable GPIO1 for ADC measurement only, set GPIO_CONF1[GPIO12:0] to ADC input. See 节 9.3.5 for more

details. If a GPIO is not configured for any ADC measurement, the device will ignore the corresponding GPIO

slot but does not remove the slot from the round robin cycle. See 图 9-7 for an example when GPIO2 is

configured for non-ADC measurement.

MAIN ADC

Round robin 1

Round robin 2

Round robin 3

DieTemp1

. . .

GPIO1

GPIO2

GPIO3

. . .

Spare

GPIO2 is inactive. ADC

measurement is ignored in this

slot

Round robin 8

Round robin 9

DieTemp1

. . .

GPIO8

GPIO1

. . .

Spare

. . .

Round robin 10

DieTemp1

. . .

GPIO2

. . .

Spare

图9-7. GPIO2 Not Configured for ADC Measurement

The measurements are reported in the corresponding GPIO*_HI (high-byte) and GPIO*_LO (low-byte) registers,

where * = 1 to 8. The measurement result is in μV. To achieve better temperature accuracy, the MCU can use a

ratiometric measurement by using both TSREF and GPIO measurement with the following formula: (GPIO_ADC/

TSREF_ADC) = RNTC/(RNTC + R1), where

• GPIO_ADC = ADC measurement on GPIO

• TSREF_ADC = ADC measurement on TSREF

• RNTC = NTC thermistor resistance

• ACTIVE_CELL register: Determine the inactive VC channel(s) and keep the result registers to default value

0x8000.

• R1 is the pull-up resistor as shown in 图9-6 with the assumption the R2 is not used

For an inactive GPIO channel, the respective _HI and _LO registers remain with the default value 0x8000.

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9.3.2.1.3 Main ADC Operation Control

9.3.2.1.3.1 Operation Modes and Status

To start the Main ADC, the host MCU sets ADC_CTRL1[MAIN_GO] = 1. When the device receives the GO

command, it first samples the following settings to determine Main ADC configuration and then operates the

Main ADC accordingly. Any change of the settings below requires the MCU to resend another GO command to

implement the new settings.

• ADC_CTRL1[MAIN_MODE1:0]: three run modes. See 表9-2 for details.

• ADC_CTRL1[LPF_VCELL_EN]: LPF for VC channels. Set to ADC_CONF1[LFP_VCELL2:0] f_cutoffif enabled.

• ADC_CTRL1[LPF_BB_EN]: LPF for BB channel. Set to ADC_CONF1[LFP_BB2:0] f_cutoffif enabled.

• ADC_CONF2[ADC_DLY5:0]: Delay the start of the Main ADC. Use to align the ADC start time among the

daisy-chained devices.

• ACTIVE_CELL register: Determine the inactive VC channel(s) and keep the result registers to default value

0x8000.

• GPIO_CONF1 to GPIO_CONF4: Determine the inactive GPIO channel(s) and keep the result registers to

default value 0x8000.

• MAIN_ADC_CAL1, MAIN_ADC_CAL2, CS_ADC_CAL1, CS_ADC_CAL2, ADC_CTRL1[CS_DR] register

备注

When using the MAIN ADC with the LPF Filter enabled and an ADC reset is desired, it is important

that the LPF_VCELL_EN bit, LPF_BB_EN bit and MAIN_GO bit is set to 0 and again set to 1 before

running the MAIN ADC again, due to needed re-initialization of the internal LPF buffer. If this

procedure is ommited then an LPF_FAIL status bit can occur on the following MAIN ADC activation.

There are two status bits to indicate the Main ADC status:

• DEV_STAT[MAIN_RUN]: indicates if the Main ADC is running or not.

• ADC_STAT1[DRDY_MAIN_ADC]: set when at least eight round robin cycles have completed indicating all

active GPIO channels and all other Main ADC inputs have at least one measurement completed.

表9-2. Summary of Main ADC Run Modes

[MAIN_MODE1:0]

Run Mode

Description

0b00

Stop Main ADC

Stop the Main ADC

Main ADC runs for eight round robin cycles then stops. This gives a single

measurement on all cell voltages and all GPIO inputs to the system. Filtered

measurements are not effective under run mode. For example, use as a quick

burst read when MCU is periodically awake during system idle state.

8 RR Run (eight round

robin cycles)

0b01

0b10

Main ADC runs in continuous mode and stops if [MAIN_MODE1:0] = 0b00 and a

GO is sent. For example, must use this mode if LPF is enabled. Also use in

diagnostic operation.

Continuous Run

The level shifter is enabled for the number of channels specified in the ACTIVE_CELL[NUM_CELL3:0] when

device enters ACTIVE mode. MCU shall wait for t_{AFE_SETTLE}time before starting the Main ADC whenever the

device enters ACTIVE mode or when [NUM_CELL3:0] setting is changed.

The Main ADC operates in ACTIVE mode only. If the ADC is running while the device goes into SLEEP, the Main

ADC will be “frozen” (that is, ADC is stopped but device still remembers the operational state). When the

device returns to ACTIVE mode without any digital reset event, the Main ADC will restart and continues from its

“pre-frozen” state. In this condition, the cell voltage measurements are off during the t_{AFE_SETTLE}time

because input voltage to the ADC is not settled yet. MCU can ignore these measurements or send a new GO

command to restart the Main ADC after t_{AFE_SETTLE}

.

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9.3.2.2 AUX ADC

There are a total of 24 inputs (slots) multiplexed to the AUX ADC (图9-8). All inputs are measured in round robin

fashion (图 9-9). Each input takes 8 μs (nominal) to measure and a single round robin cycle completes in 192

μs (nominal). The inputs to AUX ADC are:

• Die temperature 2

• Multiplexed differential CB_n–1to CB_n(AUXCELL1 to AUXCELL16), where n = 1 to 16 and differential bus bar

input through the BBP to BBN pins.

• MISC measurements:

– BAT pin

– REFL, internal reference

– VBG2, internal bandgap

– VCM, common voltage on Main ADC

– AVAO_REF, always-on block reference

– AVDD_REF

– OV DAC from OV protector

– UV DAC from UV protector

– VCBDONE DAC from UV protector

– OT or OTCB DAC from OT protector

– UT DAC from UT protector

• Multiplexed GPIO1 to GPIO8

• Spares (RSVD)

All measurements are reported in 16-bit hexadecimal in 2s complement. Results are reported to the

corresponding *_HI (high-byte) and *_LO (low-byte) registers. It first converts the hexadecimal results to decimal

values. Follow the equations in 表9-3 to translate the result to μV or °C.

When the AUX ADC is enabled, all AUX ADC related result registers shown in 表 9-3 are reset to the default

value 0x8000. The measured result is populated to the result registers as the AUX ADC makes its conversion

along the round robin cycle. When MCU reads the *_HI register, the device will pause the data refresh to the

associated *_LO register until that *_LO register is read.

表9-3. AUX ADC Measurement Conversion Equations

AUX ADC inputs

Die Temperature 2

Result Registers

Conversion Equations

Result in °C = V_{LSB_AUX_DIETEMP2}* Result in decimal

Note: 0x0000h is centered to 0°C.

DIETEMP2_HI/LO

Multiplexed AUXCELL1 to

AUXCELL16 and BB channel

AUX_CELL_HI/LO, when CB MUX is

locked to a single channel

Result in μV = V_{LSB_ADC}* Result in decimal

Result in μV = V_{LSB_AUX_BAT}* Result in decimal

BAT

AUX_BAT_HI/LO

REFL

AUX_REFL_HI/LO

VBG2

AUX_VBG2_HI/LO

VCM

AUX_VCM_HI/LO

AVAO_REF

AVDD_REF

OV DAC

AUX_AVAO_REF_HI/LO

AUX_AVDD_REF_HI/LO

AUX_OV_DAC_HI/LO

AUX_UV_DAC_HI/LO

AUX_VCBDONE_DAC_HI/LO

AUX_OT_OTCD_DAC_HI/LO

AUX_UT_DAC_HI/LO

AUX_GPIO_HI/LO

Result in μV = V_{LSB_AUX_DIAG}* Result in decimal

UV_DAC

VCBDONE DAC

OT or OTCD DAC

UT DAC

Multiplexed GPIO1 to GPIO8

Result in μV = V_{LSB_GPIO}* Result in decimal

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DieTemp2

Die Temp2 register

CB16

CB0

:

AUX_CELL register

Level

shifter

CB

MUX

BCI filter

AAF

BBP

BBN

SAR

ADC

AUX

ADC

MUX

De-MUX

AUX_SETTLE options

MISC1 to MISC12

registers

MISC1 to MISC12

inputs

:

GPIO8

GPIO1

GPIO MUX

AUX_GPIO register

图9-8. AUX ADC Measurement Path

Typ 192 µs

AUX ADC

Typ 8 µs

Round

robin 1

. . .

DieTemp2

3 Spare slots

CB MUX output

MISC 1

MISC 12

GPIO1

6 Spare slots

. . .

Round

robin 8

DieTemp2

3 Spare slots

CB MUX output

MISC 1

MISC 12

GPIO8

GPIOn

6 Spare slots

. . .

Round

robin n

3 Spare slots

CB MUX output

MISC 1

MISC 12

6 Spare slots

t_{AUXCB_SETTLE}

ADC_CONF1[AUX_SETTLE1:0]

Configured through [AUX_CELL_SEL4:0] bits

0x00 = cycle through the active cells

0x01 = lock to Busbar (BBP-BBN)

0x02 = lock to AUXCELL 1

0x03 = lock to AUXCELL 2

:

The MISC channels are:

MISC1 = BAT

MISC2 = REFL

MISC3 = VBG2

MISC4 = Spare

MISC5 = VCM

0x11 = lock to AUXCELL 16

MISC6 = AVAO_REF

MISC7 = AVDD_REF

MISC8 = OV DAC (HW protector)

MISC9 = UV DAC (HW protector)

MISC10 = VCBDONE DAC (HW protector)

MISC11 = OT or OTCB DAC (HW protector)

MISC12 = UT DAC (HW protector)

图9-9. AUX ADC Round Robin Measurements

9.3.2.2.1 AUX Cell Voltage Measurements

9.3.2.2.1.1 AUX Analog Front End

The AUX ADC path serves as a redundancy path to the Main ADC measurement on cell voltage measurements

and bus bar measurements. It also has the front end filters of a BCI filter and an AAF filter in the AUX ADC path.

The AUXCELL channel and differential BB channel (taken from BBP and BBN pins) in the AUX path are

multiplexed (shown as the CB MUX in 图 9-8) to share a single BCI filter and AAF filter. The CB MUX output

after the front end filters is then going into one of the AUX ADC MUX and to the AUX ADC for measurement.

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Because the front end filters are shared, the device has to wait for the AAF filter to settle before making any valid

CB channel (AUXCELL) or BBP and BBN channel measurement. The default AAF f_cutoffis 1.64 kHz which

translates to additional 4.3ms settling time to complete a single CB or BB channel measurement. The device

provides

3

AAF settling time options, 4.3ms (default), 2.3ms, and 1.3ms, configured by the

ADC_CONF1[AUX_SETTLE1:0] bits. The BCI filter f_cutoffis 100 kHz as in the Main ADC path.

备注

In order to achieve best measurement accuracy through the AUX ADC it is recommended to reset the

ADC every time a new CB channel is locked through the AUX_CELL_SEL bits. This will ensure that

the common mode error calibration routine is re-run and the measured result is compensated for

common mode error.

9.3.2.2.1.2 CB and BB Channel Measurements

One slot, the CB MUX output slot, is assigned in the AUX ADC round robin cycle for the CB channels

(differential CB_n–1– CB_n, where n = 1 to 16) and BB (differential BBP – BBN)channel measurement because

these channels are multiplexed to a single input to the AUX ADC multiplexer. For a single CB or BB channel

measurement, it takes multiple round robin cycles because the device has to wait for the AAF settling time as

well.

Because of the need to wait for the AAF to settle, the AUX ADC would only measure CB and BB channels that

are active and are selected by the MCU; inactive or unselected channels are skipped.

Active CB channels are determined by the ACTIVE_CELL[NUM_CELL3:0] setting. These bits set the highest

active channel number. For example, when a 14S is connected to the device, the MCU sets the

ACTIVE_CELL[NUM_CELL3:0] to 14S, the device assumes CB channels 1 through 14 are active; CB channels

15 and 16 are inactive and will be skipped by the AUX ADC.

MCU can control which CB and BB channels to be measured through the AUX ADC. The

ADC_CTRL2[AUX_CELL_SEL4:0] gives the options to run through all the active CB channel and BB channels

or to lock to a single CB channels or lock to the BB channel.图 9-10 shows the example of how the AUXCELL

slot is implemented with different [AUX_CELL_SEL4:0] setting.

It is recommend to run AUX ADC in continuous mode and all AUX ADC to measure through all the active CB

channel once. This enables the device to reduce the common mode error in AUX ADC measurement. MCU shall

perform this procedure before running ADC comparison related diagnostic or locking to a single CB or BB

channel measurement.

There is no post-ADC LPF in the AUX ADC path. When the AUX ADC measurements are used during

diagnostics, the AUX CELL (CB channel) measurements are compared against the Main ADC prefiltered

measurements. While the device performs VCELL (from Main ADC) to AUX CELL (from AUX ADC)

measurement comparison internally, the AUX BB comparison is performed by the host instead. See 节 9.3.6.4

for more details.

The device makes the CB or BB channel measurement available to read only when the [AUX_CELL_SEL4:0]

bits are set to lock on a single CB (must be active) or BB channel. The measurement is reported in the

AUX_CELL_HI (high-byte) and AUX_CELL_LO (low-byte) registers. The result registers will be updated after the

AAF settling time is passed. For any other conditions, including lock to an inactive CB channel, the result

registers remain with the default value 0x8000.

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CB MUX stays at the selected channel for the AUX ADC AAF settling time,

but the measurement during this time is discarded

Round

robin 1

. . .

AUXCELL5

. . .

Round

robin 1

. . .

AUXCELL1

. . .

Round

robin 2

. . .

Round

robin 2

. . .

Round

robin n

Round

robin n

. . .

AUXCELL5

. . .

AUXCELL1

AUXCELL2

. . .

Round

robin n+1

Round

robin n+1

Start valid AUX ADC

measurement

. . .

AUXCELL5

. . .

AUX ADC makes the

measurement after AAF is

settled

Round

robin n+2

Round

robin n+2

CB MUX switches to next

active channel

Round

robin n+3

Round

robin m

. . .

AUXCELL2

. . .

Lock at the selected active channel until

AUX ADC stop/restart with a different

selection

Round

robin m+1

. . .

Looping through all the active AUXCELL

(CB channels) until AUX ADC stop/restart

with a different selection

(a) [AUX_CELL_SEL4:0] = loop through all active CB channels

(b) [AUX_CELL_SEL4:0] = Lock to CB channel 5 (AUXCELL5)

图9-10. CB MUX Output Slot with Different [AUX_CELL_SEL4:0] Setting

9.3.2.2.2 AUX Temperature Measurements

9.3.2.2.2.1 DieTemp2 Measurement

There are 2 die temperature sensors, DieTemp1 and DieTemp2. The DieTemp2 is routed to the AUX ADC and is

also used for the AUX ADC gain and offset correction internally. The measurement is reported in the

DIETEMP2_HI (high-byte) and DIETEMP2_LO (low-byte) registers. The 0°C measurement is centered to hex

value 0x00, so a positive value represents positive temperature and a negative value represents negative

temperature. The measurement is also capped off to +200°C and –100°C.

9.3.2.2.2.2 AUX GPIO Measurements

The AUX GPIO path is the same as the main GPIO path. All eight GPIOs are multiplexed to a single AUX ADC

MUX input. There is only one GPIO slot in the AUX ADC round robin cycle. That is, in a single AUX ADC round

robin cycle, only one GPIO will be measured. To complete all eight GPIO measurements, it takes eight round

robin cycles. If GPIO is connected to the thermistor network, the MCU enables TSREF by setting

CONTROL2[TSREF_EN] = 1 and ensures TSREF is stable before starting the AUX ADC measurement.

When AUX ADC is enabled, the GPIO slot in the 1st round robin cycle is GPIO1, 2nd round robin cycle is

GPIO3, and so on. For the AUX ADC to make a measurement on a GPIO, the GPIO must be configured as ADC

input or ADC and OTUT input in the corresponding GPIO_CONFn[GPIO*2:0] bits, where n = 1 to 4, * = 1 to 8 for

the respective GPIO channel. See 节 9.3.5 for more details. If the GPIO is inactive for the ADC measurement,

the device ignores the corresponding GPIO slot but does not remove the slot from the AUX ADC round robin

cycle.

By default, the AUX ADC loops through all GPIO channels and the measurements do not report out to the result

registers. However, if MCU locks to a single GPIO channel, the locked GPIO measurement is reported to the

AUX_GPIO*_HI (high-byte) and AUX_GPIO*_LO (low-byte) registers. This channel lock can be set by the

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ADC_CTRL3[AUX_GPIO_SEL3:0] bits. The result registers will report

a

GPIO measurement if

[AUX_GPIO_SEL3:0] is locked to single GPIO channel, any other condition will show default value 0x8000.

Round robin. .1.

Round robin. .2.

GPIO1

GPIO2

. . .

Round robin.1. .

Round robin.2. .

GPIO3

. . .

Round robin.8. .

Round robin.9. .

GPIO8

GPIO1

. . .

Round robin.8. .

Round robin.9. .

GPIO3

. . .

Looping through all the GPIO channels

Lock at the selected GPIO channel

(a) [AUX_GPIO_SEL3:0] = loop through all GPIO channels

(b) [AUX_GPIO_SEL3:0] = Lock to GPIO3

图9-11. GPIO Slot with Different [AUX_GPIO_SEL3:0] Setting

9.3.2.2.3 MISC Measurements

There are 12 MISC measurements listed at the beginning of the AUX ADC section. When the AUX ADC is

enabled, these inputs are measured in every round robin cycle. 表9-3 shows the corresponding result registers.

The DAC inputs of the OVUV and OTUT protectors reflect the real-time DAC values of the device which shows

the OVUV and OTUT detection or recovery threshold currently in use in the protectors. It is normal to observe a

change of the DAC measurements if there are unused channels or if any cell or GPIO channels detect a fault.

See 节 9.3.4 for description of the protector architecture and see 节 9.3.6.4 for the protector DAC measurement

configuration.

9.3.2.2.4 AUX ADC Operation Control

To start the AUX ADC, the host MCU sets ADC_CTRL3[AUX_GO] = 1. When the device receives the GO

command, it first samples the following settings to determine the AUX ADC configuration, then operates the AUX

ADC accordingly. Any change to the settings below requires the MCU to send another GO command to

implement the new settings.

• ADC_CTRL3[AUX_MODE1:0]: Four run modes. See 表9-4 for details.

• ADC_CTRL2[AUX_CELL_SEL4:0]: Selects which CB channels are measured by AUX ADC.

• ADC_CONF1[AUX_SETTLE1:0]: Configures the AUX ADC AAF settling time.

• ADC_CTRL3[AUX_GPIO_SEL3:0]: Selects which GPIO channels are measured by AUX ADC.

• ACTIVE_CELL register: Determines the inactive CB channel(s).

• GPIO_CONF1 to GPIO_CONF4: Determines the inactive GPIO channel(s).

There are four status bits to indicate the AUX ADC status:

• DEV_STAT[AUX_RUN]: indicates if the AUX ADC is running or not.

• ADC_STAT1[DRDY_AUX_MISC]: set when all MISC inputs are measured at least once.

• ADC_STAT1[DRDY_AUX_CELL]: set when the CB or BB channels selected by [AUX_CELL_SEL4:0] are

measured at least once.

• ADC_STAT1[DRDY_AUX_GPIO]: set when all GPIO channels (active or inactive) have been measured once.

Inactive channel measurements will be ignored by the device.

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表9-4. Summary of AUX ADC Run Modes

[AUX_MODE1:0]

Run Mode

Description

0b00

Stop AUX ADC

Stop the AUX ADC

AUX ADC runs for one round robin cycle then stops. This gives a single

measurement on all MISC inputs. For example, use as a quick burst read for just

the MISC inputs without the need to issue a stop command to the AUX ADC.

Single Run (1 round robin

cycle)

0b01

AUX ADC runs in continuous mode and stops if [AUX_MODE1:0] = 0b00 and a GO

command is sent. For example, must use this mode when ADC diagnostic

comparison operation is used. See 节9.3.6.4 for details.

0b10

0b11

Continuous Run

8 RR Run (eight round

robin cycles)

AUX ADC runs for eight round robin cycles then stops. This gives a single

measurement on all active GPIO inputs.

The AUX ADC operates in ACTIVE mode only. If the ADC is running while the device goes into SLEEP mode,

the AUX ADC will be “freezed”; that is, the ADC stops but the device still remembers the operational state.

When the device returns to ACTIVE mode without any digital reset event, the AUX ADC will restart and continue

from its “prefreeze”state.

9.3.2.3 Synchronization between MAIN and AUX ADC Measurements

When AUX_CELL_ALIGN = 0x0 in ADC_CTRL2 register the device aligns AUX Cell Measurement (CB MUX -

Slot 5) with the target VC channel slot on MAIN cell. DieTemp2 starts without any delay, and AUX cell CB MUX

slot #5 moves dynamically accordingly to match the selected MAIN cell and the remaining AUX ADC slots adjust

accordingly. This ensures that there is no time skew between MAIN VC and AUX CB ADCs sampling. This

feature helps improve the ASIL-D accuracy significantly.

When AUX_CELL_ALIGN = 0x1, then the dynamic alignment is disabled and the AUX Cell Measurement (CB

MUX Slot #5) is always aligned to Main ADC Cell 8 Measurement (MAIN ADC Slot #12).

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Typ 192 µs

Typ 8 µs

MAIN ADC

DieTemp1

[slot1]

Spare

[slot2]

Spare

[slot3]

TSREF

[slot4]

Cell1

[slot5]

Cell2

[slot6]

Cell3

. . .

[slot7]

Cell16

[slot20]

Busbar

[slot21]

GPIO1

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

Typ 8 µs

AUX ADC

DieTemp2

[slot1]

Spare

[slot2]

Spare

[slot3]

Spare

[slot4]

CB MUX

[slot5]

Diag1

[slot6]

Diag2

. . .

[slot7]

Spare

[slot20]

Spare

[slot21]

Spare

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

a) [AUX_CELL_SEL] = 00h t Running all active cell channels set by ACTIVE_CELL_CONF register. Ch1 conversion.

Typ 192 µs

Typ 8 µs

MAIN ADC

DieTemp1

[slot1]

Spare

[slot2]

Spare

[slot3]

TSREF

[slot4]

Cell1

[slot5]

Cell2

[slot6]

Cell3

. . .

[slot7]

Cell16

[slot20]

Busbar

[slot21]

GPIO1

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

Typ 8 µs

AUX ADC

DieTemp2

[slot1]

Spare

[slot2]

Spare

[slot3]

Spare

[slot4]

Diag1

[slot6]

CB MUX

[slot5]

Diag2

. . .

[slot7]

Spare

[slot20]

Spare

[slot21]

Spare

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

b) [AUX_CELL_SEL] = 00h t Running all active cell channels set by ACTIVE_CELL_CONF register. Ch2 conversion.

Typ 192 µs

Typ 8 µs

MAIN ADC

DieTemp1

[slot1]

Spare

[slot2]

Spare

[slot3]

TSREF

[slot4]

Cell1

[slot5]

Cell2

[slot6]

Cell3

. . .

[slot7]

Cell16

[slot20]

Busbar

[slot21]

GPIO1

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

Typ 8 µs

AUX ADC

DieTemp2

[slot1]

Spare

[slot2]

Spare

[slot3]

Spare

[slot4]

Diag1

[slot6]

Diag2

[slot7]

CB MUX

. . .

[slot5]

Spare

[slot20]

Spare

[slot21]

Spare

[slot22]

Spare

[slot23]

Spare

[slot24]

. . .

c) [AUX_CELL_SEL] = 04h t Lock to AUX CELL 3. Ch3 conversion.

图9-12. Synchronization between MAIN and AUX ADC Sampling

9.3.3 Cell Balancing

The device integrates internal cell balancing MOSFET (CBFET) across each CB channel to enable passive cell

balancing. The balancing current is determined by the cell voltage, the external resistor in series with the CB pin,

and the internal CBFET Rdson, R_DSONparameter. The following equations calculate the effective balancing

current with or without adjacent CBFETs being on. Cell balancing can run in ACTIVE or SLEEP mode.

• Balancing with no consecutive CBFET on (图9-13 (a)): I_CB= VCell / ((2 × R_CB) + Rdson_QCB

)

• Balancing with two consecutive CBFETs on (图9-13 (b)): I_CB= (Sum of two VCELL) / ((2 × R_CB) + Rdson_QCBn

+ Rdson(_QCBn-1) )

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Device

R_VC

V_Cn

VCELL ADC

signal path

R_VC

V_Cn

VCELL ADC

signal path

R_CB

CB_n

R_CB

CB_n

VC_n

C_CB

C_VC

I_CB

+

C_CB

C_VC

I_CB

+

Q_CBn

R_VC

VC_n-1

CB_n-1

VCELL ADC

signal path

Q_CBn

R_VC

VC_n-1

CB_n-1

VCELL ADC

signal path

R_CB

VC_n-1

+

CB Control

Q_CBn-1

CB Control

Q_CBn-1

R_CB

CB_n-2

(b) Cell balancing with 2 consecutive CBFETs on

(a) Cell balancing with internal CBFET

图9-13. Internal Cell Balancing and the Flow of Balancing Current

9.3.3.1 Set Up Cell Balancing

There are three steps to set up cell balancing. Each step is described in detail in the following subsections. The

host MCU follows the steps to configure the balancing control before starting cell balancing. Balancing starts by

setting BAL_CTRL2[BAL_GO] = 1. The BAL_STAT[CB_RUN] = 1 indicates the cell balancing is actively running.

Note that channels not selected by ACTIVE_CELL[NUM_CELL3:0] are bypassed during cell balancing.

1. Determine which channel to enable for cell balancing.

2. Select the cell balancing control methods, auto or manual balancing control.

3. Decide the additional control configuration:

a. Will the thermal management based on thermistor measurement be enabled?

b. Is cell balancing stop based on cell voltage?

c. Will cell balancing terminate if any unmasked fault is detected?

9.3.3.1.1 Step 1: Determine Balancing Channels

The device provides an individual balancing timer for each channel. The balancing timer is the primary control

setting to start and stop the cell balancing on a channel. The balancing timer is configured by CB_CELL*_CTRL

registers, where * = 1 to 16 corresponding to CBFET 1 (CB channel 1) to CBFET 16 (CB channel 16). A non-

zero value in these registers sets up the corresponding channels for balancing, but the CBFETs will not turn on

until MCU issues the BAL_CTRL2[BAL_GO] = 1. When a channel balancing timer expires, cell balancing on that

channel stops. Cell balancing can also stop with other conditions, like cell voltage below a certain threshold,

unmasked fault is detected, or a forced stop by the host. 节 9.3.3.3 summarizes the cell balancing stop

conditions.

9.3.3.1.2 Step 2: Select Balancing Control Methods

The cell balancing runs autonomously once it is configured. The cell balancing control can be configured in two

ways using the BAL_CTRL2[AUTO_BAL] bit.

• Auto balancing control ([AUTO_BAL] = 1): With this method, host MCU can enable balancing on any channel.

Once the host sends a [BAL_GO] = 1, balancing starts and the device will automatically duty cycle all

enabled CBFETs in an odd and even manner. The duty cycle is configured by BAL_CTRL1[DUTY2:0] bits.

– Example 1: MCU sets up all 16 channels for cell balancing.

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Example: Both odd and even CB_CELL*_CTRL registers have non-zero setting

t_{CB_DUTY}

By [DUTY2:0]

t_{CB_DUTY}

By [DUTY2:0]

Cycle continues until any stop

condition is met

Odd CBFETs

Even CBFETs

Odd CBFETs

Even CBFETs

. . .

time

Start CB

[AUTO_BAL] = 1, AND

[BAL_GO] = 1

图9-14. Auto Balancing Control, Example 1

– Example 2: MCU sets up odd or even channels only for cell balancing. The BAL_CTRL1[DUTY2:0] bits

setting is ineffective because the device is not switched between odd or even channels.

Example: Odd CB_CELL*_CTRL registers have non-zero value

Even CB_CELL*_CTRL registers are all zero

t_{CB_DUTY}

By [DUTY2:0]

t_{CB_DUTY}

By [DUTY2:0]

Cycle continues until any stop

condition is met

. . .

Odd CBFETs

Start CB

[AUTO_BAL] = 1, AND

time

图9-15. Auto Balancing Control, Example 2

• Manual balancing control ([AUTO_BAL] = 0): With this method, the device will turn on the CBFETs that have

non-zero balancing timer settings once [BAL_GO] = 1 is received. There is no odd and even channel

switching during the cell balancing and the BAL_CTRL1[DUTY2:0] setting does not apply under this control.

Host MCU can enable two consecutive CBFETs with this method and a maximum of eight CBFETs can be

enabled. When two consecutive CBFETs are enabled with both channels connected to battery cells, the

balancing current is significantly different compared to no adjacent CBFET being on (图9-13). The

DEV_CONF[NO_ADJ_CB] bit is provided to avoid inadvertent enabling of an adjacent CBFET for a system

that is not intended to have an adjacent channel on for balancing. In this control method, the device is relying

on the MCU to enable the proper channels. If the MCU sends [BAL_GO] = 1 but the CBFETs are enabled

with an invalid condition, the device will not start balancing and will set BAL_STAT[INVALID_CBCONF] = 1.

Invalid configurations are either:

– More than eight channels are enabled for balancing (that is, more than eight CB_CELL*_CTRL registers

have non-zero settings),

– DEV_CONF[NO_ADJ_CB] = 1, but adjacent channels are enabled for balancing,

– DEV_CONF[NO_ADJ_CB] = 0, but more than two consecutive channels are enabled for balancing:

• Example: Enabling CBFET 1, 2, 4, 5, 7, 10, 12, and 14 is valid.

• Example: Enabling CBFET 1, 2, and 3 is invalid.

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CBFETs with non-zero value in the

CB_CELL*_CTRL timer registers are on

Cycle continues until any stop

condition is met

. . .

time

Start CB

[AUTO_BAL] = 0, AND

[BAL_GO] = 1

图9-16. Manual Balancing Control

9.3.3.1.3 Step 3a: Balancing Thermal Management

With passive balancing, heat is generated through the internal CBFETs and the external balancing resistors. This

creates 2 hotspots on the PCB, the device and the balancing resistors area. The device is designed to support

up to 240mA at 75°C ambient. Higher balancing current can be supported with lower ambient temperature.

Nevertheless, the device provides two thermal management functions to avoid overheating the die as well as

managing the PCB temperature. Both functions monitor temperature, either die temperature or thermistor

temperature, to automatically pause balancing if temperature exceeds a pause threshold. When temperature

falls below a recovery threshold, balancing will automatically resume. In the cell balancing pause state, all

balancing timers and balancing settings are “freezed”, balancing will resume with the same configuration

when the device is out of the pause state.

• CB TWARN Balancing Pause: There are die temperature sensors built near the internal CBFETs. When

[BAL_GO] = 1 is sent, these temperature sensors are enabled. If any of the sensors detect a die temperature

> than the T_{CB_TWARN}threshold (105°C nominal), balancing on all channels is paused. The device sets the

BAL_STAT[CB_INPAUSE] = 1 and BAL_STAT[OT_PAUSE_DET] = 1. When all sensors detect die

temperature < (T_{CB_TWARN}–T_{CB_HYS}), cell balancing will resume on the balancing enabled channels.

• Thermistor OTCB Balancing Pause: To manage thermal increases due to external balancing resistors, the

device has an option to pause cell balancing on all channels if any of the active thermistors connected to

GPIOs detects a temperature greater than a threshold set by OTCB_THRESH[OTCB_THR3:0]. Once a

OTCB detection is triggered, the BAL_STAT[CB_INPAUSE] = 1 and BAL_STAT[OT_PAUSE_DET] = 1. The

balancing on all enabled channels will resume once all active thermistors detect a temperature less than a

recovery threshold set by (OTCB_THRESH[OTCB_THR3:0] + OTCB_THRESH[COOLOFF2:0]). The OTCB

detection is performed through the integrated OT protector. The protector must be turned on and running in

round robin mode before cell balancing starts. See 节9.3.4 for the protector control details. To use the OTCB

function, MCU follows the setup sequence state below:

– Before enabling OT protector:

• GPIO used for this function will be configured to ADC and OTUT inputs.

• [OTCB_THR3:0] and [COOLOFF2:0] are configured.

– Enable the OT protector in round robin mode.

– Set [OTCB_EN] and [BAL_GO] to 1.

Failure to do so may result in no OTCB pausing action or pausing at the wrong temperature. If a different

OTCB or COOLOFF threshold is needed, MCU configures the new threshold values and then re-starts the

OT protector to latch in the new setting. It is not required to resend the [BAL_GO] = 1.

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Cell Balancing

function

BAL OFF

. . .

BAL OFF

BAL ON

. . .

PAUSE PERIOD

BAL ON

. . .

BAL OFF

Check OT and

COOLOFF hysteresis

Check OT &

COOLOFF hysteresis

Check OT & OTCB

. . .

Check OT & OTCB

OT comparator

OTCB result is not used by the

device Balancing block

OTCB result is not used by the

device Balancing block

r

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&

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图9-17. Cell Balancing Pause and Resume by OTCB Detection

9.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold

Besides the balancing timers, cell balancing can stop if the channel voltage is less than a threshold set by the

VCB_DONE_THRESH register with a non-zero value. This stop voltage threshold applies to all channels. When

this stop option is used, a channel will stop its balancing either if its balancing timer expires or its voltage level is

less than VCB_DONE_THRESH setting.

The detection of the VCB_DONE_THRESH setting is performed by the integrated UV protector. The protector

must be turned on and running in round robin mode before cell balancing starts. See 节 9.3.4 for the protector

control details.

When using the VCB_DONE detection function, the MCU follows the setup sequence state below:

• Configure the VCB_DONE_THRESH register

• Enable the UV protector in round robin mode

• Send [BAL_GO] to 1

Failure to do so may result in no VCB_DONE detection or cell balancing stops at a wrong channel voltage.

If different VCB_DONE thresholds are needed, MCU configures the new threshold values and then re-starts the

UV protector to latch in the new setting. It is not required to resend the [BAL_GO] = 1.

9.3.3.1.5 Step 3c: Option to Stop at Fault

The device provides an option to abort cell balancing if an unmasked fault is detected. To enable this option,

MCU sets BAL_CTRL2[FLTSTOP_EN] = 1 before starting cell balancing. If cell balancing is aborted under this

condition, the BAL_STAT[ABORTFLT] = 1.

9.3.3.2 Cell Balancing in SLEEP Mode

Cell balancing can be operated in both ACTIVE and SLEEP modes. To run cell balancing in SLEEP mode,

simply configure and start cell balancing in ACTIVE mode first. Once cell balancing is running, put the device in

SLEEP mode. Cell balancing will continue autonomously in SLEEP mode. See 节 9.4 for description of putting

device in SLEEP mode.

When cell balancing is completed with BAL_STAT[CB_DONE] = 1, there is an option to put the device in a

different power mode by using the BAL_CTRL2[BAL_ACT1:0]. For example, setting [BAL_ACT1:0] to 0b10

(SHUTDOWN mode) and start cell balancing, When cell balancing is completed in all balancing enabled

channels, the device will automatically enter SHUTDOWN mode without MCU interaction. When multiple devices

are connected in daisy chain structure, one device may complete its balancing but another may not. Using this

option can result with devices in different power states for some period of time. See 节 9.3.3.3 for details about

the BAL_STAT[CB_DONE] bit set conditions.

9.3.3.3 Pause and Stop Cell Balancing

9.3.3.3.1 Cell Balancing Pause

Cell balancing can be paused by one of three methods:

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• If die temperature during balancing > T_{CB_TWARN}

.

• If [OTCB_EN] = 1 when any thermistor detects a temperature greater than OTCB_THR.

• MCU sets BAL_CTRL2[CB_PAUSE] = 1.

The first two conditions are described in 节9.3.3.1.3. The third pause condition is a MCU-controlled pause action

usually used during a diagnostic check that involves the CB path. MCU can pause cell balancing through the

[CB_PAUSE] bit at any given time once balancing starts.

When the cell balancing is paused due to any of the pause methods, the pause activity is the same:

• Turn off CBFETs on all channels.

• All balancing timers are in hold or “freeze”state.

• BAL_STAT[CB_INPAUSE] = 1.

• Any unmasked fault detected during the pause state does not terminate cell balancing. This is because the

pause event can be used during diagnostic and fault insertion can be part of the diagnostic.

Once the device exits the cell balancing pause state, the cell balancing resumes. Cell balancing timers will

continue the count down. CB channels with non-zero values in their timers will continue with the balancing.

9.3.3.3.2 Cell Balancing Stop

Cell balancing stops in one of three conditions summarized in 表9-5.

表9-5. Cell Balancing Stop Conditions

Stop Condition

Cell balancing timer expires

CB channel voltage <

Apply to Individual Channel?

Set BAL_STAT[CB_DONE] = 1?

Yes, this stop condition is monitored

per channel

Yes, when all channels meet either stop condition 1 or stop

condition 2.

Yes, this stop condition is monitored

VCB_DONE_THRESH register value per channel

[FLTSTOP_EN] = 1 and unmasked

fault is detected

No, this stops cell balancing on all

channels

No, instead set BAL_STAT[ABORTFLT] = 1

Additionally, MCU can also force stop cell balancing on any particular channel or on all channels by either:

• Zeroing out the balancing timer setting and issuing [BAL_GO] = 1.

• Setting a voltage greater than the CB channel voltage in the VCB_DONE_THRESH register and issuing

[BAL_GO] = 1.

Because the cell balancing timer is the primary control to start cell balancing, if the MCU resets all balancing

timers to 0 with [BAL_GO] = 1, the device does not start balancing and BAL_STAT[CB_DONE] remains 0.

On the other hand, if any of the cell balancing timers is non-zero but the VCB_DONE_THRESH register is set to

a threshold greater than all CB channel voltages with [BAL_GO] = 1, the device starts cell balancing because of

non-zero values on the balancing timers, but immediately stops because of the VCB_DONE_THRESH stop

condition. The BAL_STAT[CB_DONE] is set to 1 for this condition.

9.3.3.3.3 Remaining CB Time

Each channel has a balancing timer, when balancing starts, the timers start counting down from the configured

balancing time set by CB_CELLn_CTRL registers, where n= 1 to 16. When balancing is pause, these timers are

paused.

To read the remaining CB time, MCU set [BAL_TIME_SEL3:0] to select a single channel, then issue

[BAL_TIME_GO] = 1 which will load the remaining CB time of the selected channel to the BAL_TIME register.

Repeat the steps to read other remaining CB time on other channels. This timer information is only valid if CB is

running, in pause state or in a valid CB stop condition.

If BAL_TIME register reports 0x7F or 0xFF, which is not a valid value. This indicates the balancing configuration

is keeping the balancing in a stop state, such as [BAL_GO] = 1 with all balancing timer set to 0, or MCU never

issue [BAL_GO] = 1.

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表9-6. BAL_TIME Register Status

CB Stop Condition

Cell balancing timer expires

BAL_TIME Register

The selected CB channel reports 0-s

CB channel voltage < VCB_DONE_THRESH register

value

The selected CB channel reports the remaining CB time

[FLTSTOP_EN] = 1 and unmasked fault is detected

9.3.3.4 Module Balancing

A small current can sink through GPIO as a way to balance the module voltage. The host can connect a loading

resistor on the GPIO and configure the GPIO as digital output high which then loading current through CVDD

that is regulated from the module stack. Such control can be turned on or off manually by the host.

Alternatively, the device can control this loading path through a function called module balancing (MB). The

concept remains the same as depleting module voltage through a loading resistor connected to a GPIO (MB

takes over GPIO3 for this function). However, host can set a module balancing timer and a stop threshold to

automatically turn off the loading path through the module balancing function.

Sink current is limited

by the max GPIO

output current limit

Stack_N-1

GPIO3

R_LOAD

GND

Daisy Chain

Comm

Host set non-zero to MB_TIMER_CTRL

Register, device configures GPIO3 as

Output High and will be enable module timer

Stack_N-1

And monitor BAR voltage for the balancing

GPIO3

R_LOAD

图9-18. Module Balancing

9.3.3.4.1 Start Module Balancing

1. Set a non-zero value to the MB_TIMER_CTRL register.

2. Configure the stop MB voltage threshold in the VMB_DONE_THRESH register.

3. The stack module monitoring is performed through AUX ADC. So host starts AUX ADC in continuous.

4. Send BAL_CTRL2[BAL_GO] = 1.

5. GPIO3 will be taken over for this function and is set to digital output port and starts sinking current through a

loading resistor. BAL_STAT[MB_RUN] = 1

9.3.3.4.2 Stop Module Balancing

Once started, MB stops if one of the following occurs:

• Balancing timer reaches MB_TIMER_CTRL setting, device will set BAL_STAT[MB_DONE] = 1.

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• BAT voltage is less than VMB_DONE_THRESH setting (AUX ADC must be on), device will set

BAL_STAT[MB_DONE] = 1.

• Host stops the balancing by setting MB_TIMER_CTRL = 0 and sends BAL_CTRL2[BAL_GO] = 1.

BAL_STAT[MB_DONE] = 0.

• If BAL_CTRL[FLTSTOP_EN] = 1 and an unmasked fault is detected, BAL_STAT[MB_DONE] = 0

备注

• There is no pause control (manual pause or thermal pause) to module balancing.

• If AUX ADC stops (either stopped by the host or device enters SLEEP mode) during module

balancing, the device will not stop module balancing based on BAT voltage. Module balancing will

stop by the MB timer expiration condition.

• BAL_CTRL2[BAL_ACT1:0] setting applies to the module balancing function as well. When the

[MB_DONE] = 1 (and [CB_DONE] = 1 if CB is enabled), device can enter the power mode set by

the [BAL_ACT1:0] setting.

9.3.4 Integrated Hardware Protectors

The device integrates cell OV and UV protectors and thermistor OT and UT protectors with programmable

thresholds independent of the ADC functionality or the ADC measurements path. The OVUV and OTUT

protectors can operate in ACTIVE or SLEEP mode. The subsections below provide an overview of the

protectors. See 节9.3.6.4 for diagnostic control function and status of this block.

9.3.4.1 OVUV Protectors

A set window comparator provides cell voltage monitoring for all VC channels. This comparator function is

entirely separate from the ADC function and as such, even if the ADC function fails, the analog comparators still

flag the crossing of the overvoltage (OV) and undervoltage (UV) comparator thresholds. The programmed

thresholds are translated through DACs to the comparators.

OV

Comp

:

OVUV

MUX

:

FAULT_OV and FAULT_UV

registers

Digital

UV

Comp

VC0

:

MAINAD

CMUX

Main ADC

:

BCI filters

:

AAF + LS

:

VC16

图9-19. OV and UV Protectors

The OV and UV thresholds set by OV_THRESH and UV_THRESH registers are the same for all VC channels.

The active channels are defined by the ACTIVE_CELL[NUM_CELL3:0] bits. These bits set the highest active

channel number and the device assumes any lower channels are also active.

The UV_DISABLE1 and UV_DISABLE2 registers setting disable any individual channel for UV detection, such

as channel is connected to bus bar.

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Otherwise, the OV protector detects an OV fault on a particular channel if the VC channel voltage is greater than

the OV_THRESH setting. The UV protector detects a UV fault on a particular channel if the VC channel voltage

is less than the UV_THRESH setting.

9.3.4.1.1 OVUV Operation Modes

The OV and UV protectors have several operation modes controlled by OVUV_CTRL[OVUV_MODE1:0] and is

summarized in 表9-7. To start the OVUV protectors, MCU sets OVUV_CTRL[OVUV_GO] = 1.

表9-7. OVUV Protector Operation Modes

[OVUV_MOD1:0]

0b00

Operation Mode

Stop OV and UV protectors

Round robin run

Description

Stop OV and UV protectors

0b01

The OV and UV protectors are looping through all VC inputs. The active

channels are checked against the OV and UV thresholds (图9-19).

The round robin cycle timing is always the same regardless of the number of

the active channels. For the inactive VC channels, the digital logic simply

ignores the detection outcome.

The UV protector detects both UV_THRESH and VCB_DONE_THRESH.

0b10

0b11

OV and UV BIST run

(diagnostic use, see 节9.3.6.4 for

details)

A BIST (built-in self-test) cycle on the OV and UV comparators and the

detection paths.

VCELL (VC channels) ADC measurement from the Main ADC and the OV and

UV detections through the OVUV protectors are not available during this run.

MCU shall stop ADC measurement when performing OVUV BIST.

Single channel run

(diagnostic use, see 节9.3.6.4 for

details)

Use for checking the OV and UV DACs. The OV and UV comparator is locked

to a single VC input channel in this mode. Channel is locked by

OVUV_CTRL[OVUV_LOCK3:0].

If OVUV BIST run is in progress, but MCU start ADC, the ADC result registers will be held at 0x8000. ADC

measurements will resume once OVUV BIST is completed and after t_{AFE_SETTLE}time pass.

If ADC is running, but MCU start OVUV BIST, the ADC result registers will be held at its last measurement. ADC

measurement update resumes once OVUV BIST is completed and after t_{AFE_SETTLE}time pass

Note: The round robin cycle time is always the same regardless the number of active channel

Stop if [OVUV_MODE1:0] = 0b00,

AND

[OVUV_GO] = 1

OV

CELL1

OV

Round robin

OV

CELL16

. . .

OV CELL1

t_{OV_CYCLE}

UV and

VCB_DONE

Round robin

Stop if [OVUV_MODE1:0] = 0b00,

. . . AND

[OVUV_GO] = 1

UV

CELL1

UV

CELL16

VCB_DONE_THRESH

CELL1

UV

CELL1

VCB_DONE_THRESH

CELL16

. . .

t_{UV_CYCLE}

Time

Set [OVUV_MODE1:0] = 0b01, AND

Set [OVUV_GO] = 1

图9-20. OV and UV Round Robin Mode

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9.3.4.1.2 OVUV Control and Status

9.3.4.1.2.1 OVUV Control

To start the OV and UV protectors, MCU sets OVUV_CTRL[OVUV_GO] = 1. When the device receives the GO

command, it samples the following register settings and then starts the OVUV protectors accordingly. Any

change of the settings below requires the MCU to resend another GO command to implement the new settings.

• OV_THRESH register: Sets the OV threshold for all VC channels

• UV_THRESH register: Sets the UV threshold for all VC channels

• VCB_DONE_THRESH register: Sets the VCB_DONE threshold for cell balancing stop condition (if enabled)

• OVUV_CTRL[OVUV_MODE1:0]: OVUV operation mode selection

• ACTIVE_CELL register: Determines the inactive VC channel(s) and ignores the detection result accordingly

• UV_DISABLE1 and UV_DISABLE2 registers: Determines the inactive VC channel(s) and ignores the

detection result accordingly.

The OVUV protectors can also operate in SLEEP mode. MCU first starts the protector in ACTIVE mode, then

puts the device in SLEEP mode. The OVUV protectors will continue the operation until the MCU commands to

stop or if the device shuts down.

9.3.4.1.2.2 OVUV Status

The DEV_STAT[OVUV_RUN] = 1 indicates the OVUV protectors are running. The OV detection result is

reflected in the FAULT_OV1 and FAULT_OV2 registers; the UV detection result is reflected in the FAULT_UV1

and FAULT_UV2 registers.

The VCB_DONE detection is not a fault but a cell balancing stop condition. The result is reflected in a particular

channel stopping cell balancing. See 节9.3.3 for details.

9.3.4.2 OTUT Protector

A set window comparator provides temperature monitoring for all GPIO inputs with the external thermistor

network pulled up to TSREF. This comparator function is entirely separate from the ADC function and, as such,

even if the ADC function fails, the analog comparators still flag the crossing of the overtemperature (OT) and

undertemperature (UT) comparator thresholds. The programmed thresholds are translated through DACs to the

comparators.

Main

ADC

MUX

To Main

ADC

OT

Comp

GPIO[1:8]

FAULT_OT and FAULT_UT

registers

GPIO

MUX

Digital

UT

Comp

AUX

ADC

MUX

To AUX

ADC

图9-21. OT and UT Protectors

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The OT and UT thresholds set by OTUT_THRESH[OT_THR4:0] and OTUT_THRESH[UT_THR2:0] bits are the

same for all active GPIO inputs. The active GPIO inputs are defined by the GPIO_CONFn[GPIO*2:0] (where n =

1 to 4, * = 1 to 8 for the corresponding GPIO input). The GPIO has to be configured as ADC and OTUT inputs to

be considered as active GPIO inputs for the OTUT protectors.

The OTUT comparators use TSREF as reference, and so the detection is in ratiometric form. The OT protector

detects an OT fault on

a

particular GPIO if the (GPIO voltage/TSREF) is less than the

OTUT_THRESH[OT_THR4:0] setting. The UT protector detects a UT fault on a particular GPIO if the (GPIO

voltage/TSREF) is more than the OTUT_THRESH[UT_THR2:0] setting. The OTUT protectors assume the NTC

thermistor is used for temperature monitoring.

MCU ensures TSREF is enabled before starting the OTUT protectors. Failing to do so, the OTUT protectors will

flag all OT and UT faults on all GPIO inputs as an indication of abnormal detection.

9.3.4.2.1 OTUT Operation Modes

The OT and UT protectors have several operation modes controlled by OTUT_CTRL[OTUT_MODE1:0] and are

summarized in 表9-8. To start the OTUT protectors, the MCU sets OTUT_CTRL[OTUT_GO] = 1.

表9-8. OTUT Protector Operation Modes

[OTUT_MOD1:0]

0b00

Operation Mode

Stop OT and UT protectors

Round robin run

Description

Stop OT and UT protectors

0b01

The OT and UT protectors are looping through all GPIO inputs. The active

GPIO inputs are checked against the OT and UT thresholds (图9-22).

The round robin cycle timing is always the same regardless of the number of

the active GPIOs. For the inactive GPIO inputs, the digital logic simply ignores

the detection outcome.

The OT protector detects both OT threshold and OTCB threshold.

0b10

0b11

OT and UT BIST run

(diagnostic use, see 节9.3.6.4 for

details)

A BIST (built-in self-test) cycle on the OT and UT comparators and the

detection paths.

Temperature (GPIO channels) ADC measurement from the main or AUX ADC

and the OT and UT detections through the OTUT protectors are not available

during this run.

Single channel run

(diagnostic use, see 节9.3.6.4 for

details)

Used for checking the OT and UT DACs. The OT and UT comparator is locked

to a single GPIO input channel in this mode. Channel is locked by

OTUT_CTRL[OTUT_LOCK2:0].

Note: The round robin cycle time is always the same regardless of the number of active GPIO inputs

OT and OTCB

Round robin

OT

GPIO1

OT

GPIO8

OTCB

GPIO1

OTCB

GPIO8

Stop if [OTUT_MODE1:0] = 0b00, AND

[OTUT_GO] = 1

. . .

t_{OT_CYCLE}

UT

Round robin

UT

GPIO1

UT

GPIO8

UT

GPIO1

UT

GPIO8

Stop if [OTUT_MODE1:0] = 0b00, AND

[OTUT_GO] = 1

. . .

t_{UT_CYCLE}

Time

Set [OTUT_MODE1:0] = 0b01, AND

Set [OTUT_GO] = 1

图9-22. OT and UT Round Robin Modes

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9.3.4.2.2 OTUT Control and Status

9.3.4.2.2.1 OTUT Control

Ensure TSREF is enabled. To start the OT and UT protectors, host MCU sets OTUT_CTRL[OTUT_GO] = 1.

When the device receives the GO command, it samples the following register settings and then starts the OTUT

protectors accordingly. Any change of the settings below requires the MCU to send another GO command to

implement the new settings.

• OTUT_THRESH[OT_THR4:0]: Sets the OT threshold for all active GPIO inputs

• OTUT_THRESH[UT_THR2:0]: Sets the UT threshold for all active GPIO inputs

• OTCB_THRESH register: Sets the OTCB threshold and COOLOFF hysteresis (if enabled)

• OTUT_CTRL[OTUT_MODE1:0]: OTUT operation mode selection

• GPIO_CONF1 to GPIO_CONF4: Determines the inactive GPIO channel(s) and ignores the detection result.

The OTUT protectors can also operate in SLEEP mode. MCU first starts the protector in ACTIVE mode, then

puts the device in SLEEP mode. The OTUT protectors will continue the operation until the MCU commands

them to stop or if device shuts down.

9.3.4.2.2.2 OTUT Status

The DEV_STAT[OTUT_RUN] = 1 indicates the OTUT protectors are running. The OT detection result is reflected

in the FAULT_OT register; the UT detection result is reflected in the FAULT_UT register.

The OTCB detection is not a fault but a cell balancing pause condition. The result is reflected in a particular

channel pausing cell balancing. See 节9.3.3 for details.

9.3.5 GPIO Configuration

The device has eight GPIOs. Each GPIO can be programmed to be one of the configurations below through the

GPIO_CONF1 to GPIO_CONF4 registers. Note that when the device is in SHUTDOWN mode all GPIOs will

exibit a weak pull-down behaviour.

DISAB

LE

WEAK PULL-UP/

DOWN

INPUT

OUTPUT

SPECIAL

GPIO

ADC &

weak

pull-up pull-down

ADC &

weak

Module Balancing

MB_TIMER_CTRL

is not 0x00

Fault Input

[FAULT_IN_ EN] =

1

Digita ADC & ADC

SPI Master

[SPI_EN] = 1

High-Z

High Low

l

OTUT Only

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

√

√(output, HIGH)

√(SS)

√(MISO)

√(MOSI)

√(SCLK)

√(input, active low)

GPIO Configuration

Description

DISABLE

High-Z

Digital

This is the default GPIO configuration at reset if OTP is not programmed

When GPIO is configured as Digital Input, the device detects the input voltage level to determine a 1 or

0 with respect to its V_ILand V_IHlevels. The result is shown in the GPIO_STAT register.

The GPIO is configured to be measurable by the ADC (both main and AUX ADCs) and also as the input

to the OTUT protectors. Example: use this selection for GPIO used for thermistor connection.

INPUT

ADC and OTUT

ADC only

The GPIO is configured to be measurable by the ADC (both main and AUX ADCs) only. Example: use

this selection to measurement voltage on GPIO.

The GPIO is configured as digital output high (internally pull up to CVDD). The logic state is also shown

in the GPIO_STAT register.

High

Low

OUTPUT

The GPIO is configured as digital output low. The logic state is also shown in the GPIO_STAT register.

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GPIO Configuration

Description

ADC and Weak The GPIO is pull up internally and is configured to measured by the ADC (both main and AUX ADCs)

Pull-up

WEAK PULL-

UP/DOWN

ADC and Weak The GPIO is pull down internally and is configured to measured by the ADC (both main and AUX ADCs)

Pull-down

When the MB_TIMER_CTRL register is non-zero, GPIO3 will be taken over to be used in the module

balancing control. This configuration has higher priority over any of the INPUT/OUTPUT configurations

on GPIO3.

Module

Balancing

When GPIO_CONF1[SPI_EN] = 1, GPIO4 to GPIO7 are taken over as the SPI master communication

lines. This configuration has higher priority over any of the INPUT/OUTPUT configurations on GPIO4 to

GPIO7.

SPECIAL

SPI Master

Fault Input

When GPIO_CONF1[FAULT_IN_EN] = 1, GPIO8 is taken over as an input that if the GPIO was asserted

(active low), will set FAULT_SYS[GPIO] = 1 and assert NFAULT (if enabled).

9.3.6 Communication, OTP, Diagnostic Control

9.3.6.1 Communication

The device can operate as a standalone device in a multidrop configuration (DEV_CONF[MULTIDROP_EN] = 1)

or as a base/stack device in a daisy chain configuration (DEV_CONF[MULTIDROP_EN] = 0). In multidrop

configuration, the daisy chain communication is disabled and the host communicates only with a single device

through UART interface. This document will focus on the daisy chain communication.

In daisy chain configuration, each device is identified by a 6-bit device address; hence, up to 64 devices can be

connected in the daisy chain. In this configuration, a device is either defined to a base (interface with host

through UART) or a stack (interface through the daisy chain ports COMH/COML to the base device). The base

description in this document assumes the use of BQ7961x-Q1 as base device. If a communication extender

(also known as bridge device) is used as a base, user must refer to the bridge device’s datasheet for details.

9.3.6.1.1 Serial Interface

The device has a serial interface which uses UART protocol as the physical layer to communicate between base

device and host. The communication is specified in a proprietary frame structure.

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Half-duplex

Command Frame

Response Frame

Base device

MCU

TX

RX

TX

Both Command and Response Frames shall follow

the Transaction Frame Structure

Transaction Frame Structure (to/from system MCU to the base device):

A transaction frame consists of 5 types of information as shown below.

Data are all sent in byte, and each byte is sent through UART protocol.

INIT[7:0]

DEV ADR[7:0]

REG ADR[15:8]

REG ADR[7:0]

DATA MSB[7:0]

...

DATA LSB[7:0]

CRC[15:8]

CRC[7:0]

Each frame is sent through the UART Protocol

UART Protocol:

. . .

STOP

START

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

½ bit

period

bit

period

bit

period

bit period = 1/ baud rate

图9-23. UART Communication to Host

9.3.6.1.1.1 UART Physical Layer

The UART interface follows the standard serial protocol of 8-N-1, where it sends information as a START bit,

followed by eight data bits, and then one STOP bit. The STOP bit indicates the end of the byte. If a byte is

received that does not have the STOP bit set, the FAULT_COMM1[STOP_DET] bit is set, indicating there may

be a baud rate issue between the host and the device. The device supports 1-Mbps baud rate. Additionally,

during development, a slower baud rate is needed to debug the communication, an optional 250-kbps baud rate

can be enabled under communication debug mode.

The UART sends data on the TX pin and receives data on the RX pin. When idle, the TX and RX pins are high.

The UART interface requires that RX is pulled up to CVDD through a resistor on the base device. The RX is

pulled up on the device side. Do not leave RX unconnected. Ensure RX is connected directly to CVDD for stack

devices.

The TX pin is disabled in stack devices, but must be pulled high through a resistor on the host side on base

device to prevent triggering an invalid communications frame when the communication cable is not attached, or

during power-off or SHUTDOWN state when TX is high impedance. TX is always pulled to CVDD internally while

in ACTIVE or SLEEP mode, whether enabled or disabled. Leave TX unconnected if not used in stack devices.

The UART interface is strictly a half-duplex interface. While transmitting, any attempted communication on RX is

ignored. The only exception is COMM CLEAR signal on RX pin, which immediately terminates the

communication. See 节9.3.6.1.1.1.3 for details.

Using two STOP bits in UART:

The device can be set up with two stop bits (DEV_CONF[TWO_STOP_EN] = 1), the UART response frame

transmits from device to host will always return with two STOP bits as shown below. Host is not required to send

the command frame to the device with two STOP bits. The device is able to receive one or more stop bits with or

without this function enabled.

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2-bit period

. . .

START

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

STOP

bit period

½ bit

period

bit period = 1/ baud rate

图9-24. UART Response Frame with Two STOP Bits

Potential use of the two stop bits may be to:

• The host to gain extra time to process the data before receiving next data frame.

• The clock tolerance between device and host might cause the data detection out of sync. Having two STOP

bits allows re-synchronization of the communication; hence, improving communication robustness.

Although UART is only used by the base device, if the [TWO_STOP_EN] = 1, the stack devices also set the

[TWO_STOP_EN] = 1 even though UART is not used in stacks. It is because the stack devices will use the bit

setting to determine the proper gap applying between two communication frames.

9.3.6.1.1.1.1 UART Transmitter

The transmitter is configured to wait a specified number of bit periods after the last bit reception before starting

transmissions using the TX_HOLD_OFF register. This provides time for the host to switch the bus direction at

the end of its transmission. The UART transmitter is disabled by default in the stack devices.

TX_HOLD_OFF

data direction

device RX

device TX

Command frame

data direction

To MCU

Response frame

Time

图9-25. UART TX_HOLD_OFF

9.3.6.1.1.1.2 UART Receiver

While the device is transmitting data on TX, RX is ignored except when receiving a COMM CLEAR. To avoid

collisions during data transmission up the daisy-chain interface, the host must wait until all bytes of a

communication transmission are received from the device before attempting additional communication to the

device. If the host starts a transmitting without waiting to receive the preceding transaction's response, the

communication is not considered reliable and the host must send a COMM CLEAR to restore normal

communications to the base device.

9.3.6.1.1.1.3 COMM CLEAR

A COMM CLEAR is sent on the RX pin of the base device. It does not send to the stack devices. RX cannot be

disabled and a COMM CLEAR can be sent at any time regardless of the TX status. Ensure that the COMM

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CLEAR does not exceed the maximum value of t_UART(CLR)bit periods, as this may result in recognition of other

communication pings.

1 bit period

RX pin

Wait 1-bit period to start

the next communication

SLEEPtoACTIVE ping

COMM CLEAR

t_UART(CLR)

t_UART(StA)

图9-26. UART COMM CLEAR

Use the COMM CLEAR command to clear the receiver and instruct the UART engine to look for a new start of

frame. The next byte following the COMM CLEAR is always considered a start-of-frame byte. When detected, a

COMM CLEAR sets the FAULT_COMM1[COMMCLR_DET] flag. The host must wait at least t_UART(RXMIN)after

the COMM CLEAR to start sending a new frame. It should be noted that in addition to the [COMMCLR_DET]

flag, the FAULT_COMM1[STOP_DET] flag is also set because the COMM CLEAR timing violates the typical

byte timing and the STOP bit is seen as 0.

A SLEEPtoACTIVE ping/tone also clears the UART receiver. This ping/tone sets the [COMMCLR_DET] flag

when transiting from SLEEP to ACTIVE mode. If this ping/tone is sent during ACTIVE mode, the

[COMMCLR_DET] and [STOP_DET] flags are set.

COMM CLEAR sent during daisy chain communication:

When a read command is sent, but the response has not yet completely returned to the host, if a COMM CLEAR

is received in the base device at this condition, the device response is discarded. In addition, the stack devices

do not see the COMM CLEAR and continue to send their responses which are forwarded to the host, resulting in

host receiving unexpected response frames. Hence, host should avoid this condition by waiting until all

responses are received from the stack before sending a COMM CLEAR.

If the above condition occurs, the base device low-level communication debug register

DEBUG_UART_RR_TR[TR_WAIT]

(indicating

device

is

waiting

to

transmit

response)

or

DEBUG_UART_RR_TR[TR_SOF] (indicating a COMM CLEAR is received while device is transmitting data) bits

can be set depending on the timing in receiving the COMM CLEAR signal.

When using the multidrop configuration, a COMM CLEAR signal must be used before every frame to ensure

consistent communication.

9.3.6.1.1.2 Command and Response Protocol

The host initiates every transaction between the host and device. The device never transmits data without first

receiving a command frame from the host. A command frame is a communication frame sent from host to the

device; a response frame is a response (to a read command) from device to host. After a command frame is

transmitted, the host must wait for all expected responses to be returned (or a timeout in case of error) before

initiating a new command frame. The commands supported by the device are listed in 表9-9:

表9-9. Commands

Command

Single Device Read

Single Device Write

Stack Read

Description

To read a register(s) from a single device (base or stack)

To write a register(s) to a single device (base or stack)

To read a register(s) from the stack devices only. The device must be configured as a stack device with

COMM_CTRL[STACK_DEV] = 1 to respond to Stack Read commands..

Stack Write

To write a register(s) for only the stack devices. The device must be configured as a stack device with

COMM_CTRL[STACK_DEV] = 1 to respond to Stack Write commands.

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表9-9. Commands (continued)

Command

Broadcast Read

Broadcast Write

Description

To read a register(s) for all of the devices in the daisy chain, including base device.

To write a register(s) for all of the devices in the daisy chain, including base device.

Broadcast Write Reverse To send a broadcast write in the reverse direction set by CONTROL1[DIR_SEL] bit. This command is intended

Direction to be used for switching the communication direction with the RING interface.

9.3.6.1.1.2.1 Transaction Frame Structure

The protocol layer is made up of transaction frames. There are two basic types of transaction frames: command

frames (transactions from host) and response frames (transactions from device). The transaction frames are

made up of the following five field types:

• Frame initialization (INIT, 1-byte)

• Device address (DEV ADR, 1-byte)

• Register address (REG ADR, 2-byte)

• Data (DATA, various byte length)

• Cyclic redundancy check (CRC, 2-byte)

9.3.6.1.1.2.1.1 Frame Initialization Byte

The frame initialization byte is used in both command and response frames. It is always the first byte of the

frame. The frame initialization byte performs two functions. First, it defines the frame as either a command frame

(host) or a response frame (device). Second, it defines the length of the frame that follows after the frame

initialization byte. This provides the receiver an exact number of bytes to expect for a complete command or

response.

表9-10. Command Frame Initialization Byte Definition

Command Frame

Response Frame

Description

0 = Defines Response Frame

Bit

7

Bit Name

FRAME_TYPE

REQ_TYPE

Description

Bit Name

INIT

1 = Define Command Frame

FRAME_TYPE

6

000 = Single Device Read

001 = Single Device Write

010 = Stack Read

RESPONSE_BYTE Number of the data bytes

0x00 = 1 byte

0x01 = 2 bytes

:

5

4

011 = Stack Write

100 = Broadcast Read

101 = Broadcast Write

110 = Broadcast Write Reverse

111 = RSVD⁽¹⁾

0x7F = 128 bytes

3

2

1

0

RSVD

Reserved. This bit is ignored

DATA_SIZE

Number of data bytes of the command

frame, excluding device address,

register address or CRC

000 = 1 byte

001 = 2 bytes

:

111 = 8 bytes

(1) No function to this selection, however, selecting this setting will set the DEBUG_COMMH[RC_IERR] or DEBUG_COMMH[RC_IERR]

flag depends on which daisy chain interface receives the command frame.

9.3.6.1.1.2.1.2 Device Address Byte

The device address byte identifies the device targeted by the single device read/write command. This byte is

omitted for broadcast, stack, and broadcast reverse direction command frames. All response frames contain the

device address byte. In single device read/write commands, the device that contains a matching value in the

DIR0_ADDR (used for communication direction with CONTROL1[DIR_SEL] = 0) or in DIR1_ADDR (used for

communication direction with CONTROL1[DIR_SEL] = 1) responds to the command. If multiple devices have

matching values, all of those devices will respond and cause collision.

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DEV ADR

表9-11. Device Address Byte Definition

Command Frame

Response Frame

Description

Bit

7

Bit Name

RSVD

Description

Bit Name

RSVD

Should always write 0

6

RSVD

5 to 0 Device Address

Set the device address range from

0x00 to 0x3F

Device Address

Set the device address range from

0x00 to 0x3F

9.3.6.1.1.2.1.3 Register Address Bytes

Register addresses are two bytes in length. Any write command to an invalid register address is ignored. Any

read from an invalid register returns a 0x00 response. This is true for command frames sent to an individual

register with invalid address, or as part of command sent to multiple registers with invalid addresses. When read/

write addresses a block of registers with only some invalid addresses, the valid addresses respond as normal,

while the invalid addresses respond as previously described.

表9-12. Register Address Byte Definition

Command Frame

Description

7 to 0 Register Address Target or beginning of the register

(MSB) address

7 to 0 Register Address Target or beginning of the register

(LSB) address

Response Frame

Description

Register Address Target or beginning of the register

(MSB) address

Register Address Target or beginning of the register

(LSB) address

Bit

Bit Name

REG_ADR

9.3.6.1.1.2.1.4 Data Bytes

The number of data bytes and the relevant information they convey is determined by the type of command frame

sent and the target register specified in that command frame. When part of a command frame, the data bytes

contain the values to be written to the registers. When part of a response frame, the data bytes contain the

values returned from the registers.

表9-13. Data Bytes Definition

Command Frame

Response Frame

Description

Bit

7

Bit Name

Description

Bit Name

Data

For Write command:

Data

Data value return from the register(s) is

Byte[0] Data value to be written to the register(s) is

specified in the REG_ADR frame

For Read command:

Byte[0] specified in the REG_ADR frame

6

5

Specify the number of bytes need to be

returned by the read command.

0x00 = 1 byte

4

3

0x01 = 2 bytes

:

0x7F = 128 bytes

2

1

0

DATA

…

7

6

5

4

3

2

1

0

……

Data Byte Data value return from the register(s) is

[n] specified in the REG_ADR frame

……

Data Byte For Write command:

[n]

Data value to be written to the register(s) is

specified in the REG_ADR frame

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9.3.6.1.1.2.1.5 CRC Bytes

The device uses a CRC (cyclic redundancy check) to protect data integrity during transmission. The CRC

represents the remainder of a process analogous to polynomial long division, where the frame being checked is

divided by the generator. The CRC appended to the frame is the remainder. Because of this process, when the

device receives a frame, the CRC calculated by the receiver across the entire frame including the transmitted

CRC will be zero, indicating a correct transmission and reception. A non-zero result indicates a communication

error. Specifically, the device uses the CRC-16-IBM polynomial (x¹⁶+ x¹⁵+ x²+ 1 ) with 0xFFFF initialization.

The CRC value is checked as the first step after receiving the communication frame. If the CRC is incorrect, the

entire frame is discarded and not processed. Any additional frame errors are not checked and any errors are not

indicated other than CRC error. The bytes are still transferred up or down the stack, thus every device that

processed the frame will indicate a CRC error. This results in multiple devices indicating CRC faults on the same

communication frame.

9.3.6.1.1.2.1.6 Calculating Frame CRC Value

The CRC calculation by the transmitter is in bit-stream order across the entire transmission frame (except for the

CRC). When determining bit-stream order for implementing the CRC algorithm, it is important to note that

protocol bytes transmit serially, least-significant bit first. 图9-27 illustrates the bit-stream order concept.

MSB

7

LSB

0

MSB

7

LSB

0

MSB

7

LSB

0

6

5

4

3

2

1

6

5

4

3

2

1

6

5

4

3

2

1

Normal Order

MSB

0

LSB

7

MSB

0

LSB

7

MSB

0

LSB

7

1

2

3

4

5

6

1

2

3

4

5

6

1

2

3

4

5

6

Bit-stream Order

图9-27. Bit-Stream Order Explanation

The CRC (0x0000) is appended to the end of the bit-stream. This bit-stream is then initialized by XOR'ing with

0xFFFF to catch any leading 0 errors. This new bit-stream is then divided by the polynomial (0xC002) until only

the 2-byte CRC remains. During this process, the most significant 17 bits of the bit stream are XOR’d with the

polynomial. The leading zeroes of the result are removed and that result is XOR’d with the polynomial once

again. The process is repeated until only the 2-byte CRC remains. For example:

Example 1: CRC Calculation Using Polynomial Division

Command Frame = 0x80 00 02 0F 0B (0b1000 0000 0000 0000 0000 0010 0000 1111 0000 1011)

Command Frame in bit stream order

1101 0000)

= 0x01 00 40 F0 D0 (0b0000 0001 0000 0000 0100 0000 1111 0000

After Initialization (XOR with 0xFFFF) = 0b1111 1110 1111 1111 0100 0000 1111 0000 1101 0000

1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000 0000 0000 0000 #append 0x0000 for CRC

1100 0000 0000 0010 1 #XOR with polynomial

0011 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0000 0000 0000

11 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0000 0000 0000 #delete leading zeros from

previous result

11 0000 0000 0000 101 #XOR with polynomial

00 1110 1111 1101 0110 0000 1111 0000 1101 0000

……

1100 0110 0000 0001 0000 0000

1100 0000 0000 0010 1 #XOR with polynomial

0000 0110 0000 0011 1000 0000

110 0000 0011 1000 0000

110 0000 0000 0001 01 #XOR with polynomial

000 0000 0011 1001 0100

0000 0011 1001 0100 #CRC result in bit stream order

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1100 0000 0010 1001 #final CRC result in normal order

CRC final 0xC029

9.3.6.1.1.2.1.7 Verifying Frame CRC

There are several methods for checking the CRC of a frame. One method is to simply calculate the CRC for the

transmitted command except the last two bytes (CRC bytes) using the method described in the previous section,

and then compare that result with the transmitted CRC bytes. A more simple option is to run the entire

transmission through the CRC algorithm. If the CRC is correct, the result is 0000. In this case, the initial zero

padding of the bit-stream with 16 zeroes is not necessary. Using the previous result and running through the

algorithm produces the following results:

Example 1: CRC Verification Using Polynomial Division:

Command Frame = 0x80 00 02 0F 0B (0b1000 0000 0000 0000 0000 0010 0000 1111 0000 1011)

CRC to Check = 0xC029

Command Frame w/ CRC in bit stream order = 0x80 00 02 0F 0B C0 29 (0b1000 0000 0000 0000 0000 0010

0000 1111 0000 1011 0000 0011 1001 0100)

After Initialization (XOR with 0xFFFF) = 0b0 1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000

0011 1001 0100

1111 1110 1111 1111 0100 0000 1111 0000 1101 0000 0000 0011 1001 010 #delete leading zeros from

previous result

1100 0000 0000 0010 1 #XOR with polynomial

0011 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0011 1001 0100

11 1110 1111 1101 1100 0000 1111 0000 1101 0000 0000 0011 1001 0100 #delete leading zeros from

previous result

11 0000 0000 0000 101 #XOR with polynomial

00 1110 1111 1101 0110 0000 1111 0000 1101 0000 0000 0011 1001 0100

……

1100 0110 0000 0010 1001 0100

1100 0000 0000 0010 1 #XOR with polynomial

0000 0110 0000 0000 0001 0100

1 1000 0000 0000 0101 00

1 1000 0000 0000 0101 #XOR with polynomial

0 0000 0000 0000 0000 00

0x0000 #verfiy that CRC checks out valid

备注

The result of ‘0b0000 0000 0000 0000’for the CRC indicates a successful check.

9.3.6.1.1.2.2 Transaction Frame Examples

Transaction frames are created using the frame structure discussed in the previous sections. This section

outlines how the command and response frames are passing through the daisy chain. The CRC values in the

examples are correct and can be used to verify the customer CRC algorithm. The CRC is verified by the device

with every received command frame and the command is not executed unless the CRC is valid.

9.3.6.1.1.2.2.1 Single Device Read/Write

Single Device Read:

Device address must be set up before using this command. A single device read generates a response frame

whose length depends on the requested number of register bytes read. The command frame send by host must

contain the register address to start at (address field) and the number of bytes to return (number of registers to

read). The DATA_SIZE field in the initialization byte for the single device read command is always 0b000.

The command frame travels to all devices in the daisy chain, but only the device that matches the command

frame’s device address field will respond to the single device read command. The corresponding device will

respond with returned data request by the single device read, following the response frame format.

Single Device Write:

Device address must be set up before using this command. A write command for a single device enables the

customer to update up to eight consecutive registers with one command. The single device write command

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frame must contain the register address to start at (address field) and the data bytes to write to the registers. The

DATA_SIZE field in the initialization byte for the single device write command is the number of registers to

update.

The command frame travels to all devices in the daisy chain, but only the device that matches the command

frame’s device address field will execute the single device write command.

[DIR0_ADDR] = 3

[TOP_STACK] = 1

[DIR0_ADDR] = 3

[TOP_STACK] = 1

COMH

S3

COML

2

[DIR0_ADDR] = 2

[DIR0_ADDR] = 1

[DIR0_ADDR] = 0

[DIR0_ADDR] = 2

COMH

S2

COMH

S2

2

Only the addressed

device responds after

receiving the command

Only the addressed device

executes the command

COML

[DIR0_ADDR] = 1

COMH

S1

COMH

S1

1

COML

1

Host sends Single Read

command (addressing to S2)

[DIR0_ADDR] = 0

Host sends Single Write command

(addressing to S2)

COMH

B0

COMH

B0

RX

TX

MCU

TX

RX

TX

MCU

TX

RX

COML

RX

COML

(a) Single Read Command to S2

(b) Single Write Command to S2

图9-28. Single Device Read/Write

表9-14. Single Device Read/Write

Single Read Command Sent by Host

Single Write Command Sent by Host

Write OTP Unlock Code to OTP_PROG_UNLOCK1A to 1D

Registers

Example

Read 16 Cell Voltages from S2

Comments

Frame Field

Data

Comments

Initialization

Byte

0x80

Always 0x80

FRAME_TYPE = 1

REQ_TYPE = 0b000 = Single Read

DATA_SIZE = 0b000

0x93

0x90 for 1 byte data write, 0x91 for 2 bytes

data write, 0x92 for 3 bytes data write, and so

on.

For this example:

FRAME_TYPE = 1

REQ_TYPE = 0b001= Single Write

DATA_SIZE = 0b11 = 4 bytes

Device

0x02

Device address 0x02 (S2) in this example

0x02

Device address 0x02 (S2) in this example

Address

Register

Address

0x0568 Start address of the register block to read

(address of VCELL16_HI in this example)

0x0300

Start address of the register block to write

(address of OTP_PROG_UNLOCK1A in this

example)

Data

0x1F

Instruct the target device to return 32 bytes of

data (that is, from address 0x0568 to 0x0587),

assuming each VCELLn_HI = 0x80,

0x02B7 78BC The unlock value to OTP_PROG_UNLOCK1A

to OTP_PROG_UNLOCK1D

VCELLn_LO = 0x00, where n = 1 to 16.

CRC

0x5A6F

0xB8AE

9.3.6.1.1.2.2.2 Stack Read/Write

Stack Read:

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The device address, COMM_CTRL[STACK_DEV] bit and [TOP_STACK] bit must be configured before using this

command. A stack read command generates a number of response frames depending on the number of devices

in the stack (that is, device with COMM_CTRL[STACK_DEV] = 1), whose length depends on the requested

number of register bytes read. The stack read command frame must contain the register address to start at

(address field) and the number of bytes to return (number of registers to read). The DATA_SIZE field in the

initialization byte for the read command is always 0b000.

The command frame travels to all devices in the daisy chain, but only the device with

COMM_CTRL[STACK_DEV] = 1 will respond. During the response, the device with COMM_CTRL[TOP_STACK]

= 1 will return the response frame first. Each device (address N) in the stack waits until the device above

(address N+1) responds before appending its response frame. The CRC is validated while receiving the

responses. If a CRC error occurs in the response frame from address N+1, device N does not append its

message and an invalid CRC fault is generated.

Use 图 9-29 with the example of using reading 16 cell voltages from S1 to S3. The response to this command is

3 separate response frames (one response frame per device), each frame with a total length of 38 bytes (32

data bytes + 6 protocol bytes). Although the stack read command does not contain the device address field,

each response frame will contain the corresponding device address field associating the data to a particular

device. The host will receive a response frame from S3 first (ToS), following with a response frame from S2, and

finally the response frame from S1.

Stack Write:

The COMM_CTRL[STACK_DEV] must be configured before using this command. A stack write command

enables the host to update up to eight consecutive registers for the stack devices (that is, device with

COMM_CTRL[STACK_DEV] = 1) with one command. The command frame must contain the register address to

start at (address field) and the data bytes to write to the registers. The DATA_SIZE field in the initialization frame

is the number of registers to update.

The command frame travels to all devices in the daisy chain, but only the device with

COMM_CTRL[STACK_DEV] = 1 will execute the command.

2

[DIR0_ADDR] = 3

[TOP_STACK] = 1

COMH

[DIR0_ADDR] = 3

[TOP_STACK] = 1

COMH

Device in top of stack

responds first

S3

2

COML

After S2 receives

All the devices identified as

—stack“ execute the command

except B0 (as it is identified as

—base“)

[DIR0_ADDR] = 2

response from S3, S2

also responds and

process continues for

the rest of the device.

[DIR0_ADDR] = 2

COMH

S2

COMH

S2

COML

B0 (identified as base

device) only forward the

response and does not

return its own data

COML

[DIR0_ADDR] = 1

COMH

S1

COMH

S1

COML

1

COML

1

Host sends Stack

Read command

[DIR0_ADDR] = 0

Host sends Stack

Write command

COMH

B0

COMH

B0

RX

TX

MCU

TX

RX

TX

MCU

TX

RX

COML

RX

COML

(a) Stack Read Command

(b) Stack Write Command

图9-29. Stack Read/Write

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表9-15. Stack Read/Write

Stack Read Command Sent by Host

Read 16 Cell Voltages from S1 to S3

Comments

Stack Write Command Sent by Host

Write OTP Unlock Code to OTP_PROG_UNLOCK1A to 1D

Registers to S1, S2, and S3

Example

Frame Field

Data

Comments

Initialization

Byte

0xA0

Always 0xA0

FRAME_TYPE = 1

REQ_TYPE = 0b010 = Stack Read

DATA_SIZE = 0b000

0xB3

0xB0 for 1 byte data write, 0xB1 for 2 bytes

data write, 0xB2 for 3 bytes data write, and so

on.

For this example:

FRAME_TYPE = 1

REQ_TYPE = 0b011= Stack Write

DATA_SIZE = 0b011 = 4 bytes

Device

Address

N/A

No need to include the device address byte in

command frame

N/A

No need to include the device address byte in

command frame

Register

Address

0x0568 Start address of the register block to read

(address of VCELL16_HI in this example)

0x0300

Start address of the register block to write

(address of OTP_PROG_UNLOCK1A in this

example)

Data

0x1F

Instruct each device to return 32 bytes of data

(that is, from address 0x0568 to 0x0587),

assuming each VCELLn_HI = 0x80,

0x02B7 78BC The unlock value to OTP_PROG_UNLOCK1A

to OTP_PROG_UNLOCK1D

VCELLn_LO = 0x00, where n = 1 to 16.

CRC

0x5C2D

0x0BD7

9.3.6.1.1.2.2.3 Broadcast Read/Write

Broadcast Read:

The device address and [TOP_STACK] bit must be configured before using this command. A broadcast read

command generates a number of response frames depending on the number of devices in the daisy chain (both

stack and base devices), whose length depends on the requested number of register bytes read. The broadcast

read command frame must contain the register address to start at (address field) and the number of bytes to

return (number of registers to read). The DATA_SIZE field in the initialization byte for the read command is

always 0b000.

The command frame travels to all devices in the daisy chain, every device will respond. During the response, the

device with COMM_CTRL[TOP_STACK] = 1 will return the response frame first, each device (address N) in the

stack waits until the device above (address N+1) responds before appending its response frame. The CRC is

validated while receiving the responses. If a CRC error occurs in the response frame from address N+1, device

N does not append its message and an invalid CRC fault is generated.

Use 表 9-16 with the example of reading 16 cell voltages from B0 to S3. The response to this command is 4

separate response frames (one response frame per device), each frame with a total length of 38 bytes (32 data

bytes + 6 protocol bytes). Although the broadcast read command does not contain the device address field, each

response frame will contain the corresponding device address field, associated the data to a particular device.

The host will receive the response frame from S3 first (ToS), following with the response frame from S2, then S1,

and finally the response frame from B0.

Broadcast Write:

This command can be used without auto-addressing. A broadcast write command enables the host to update up

to eight consecutive registers for all devices in the daisy chain with one command. The command frame must

contain the register address to start at (address field) and the data bytes to write to the registers. The

DATA_SIZE field in the initialization frame is the number of registers to update.

The command frame travels to all the devices in the daisy chain, and every devices in the daisy chain will

execute the command.

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[DIR0_ADDR] = 3

[TOP_STACK] = 1

[DIR0_ADDR] = 3

[TOP_STACK] = 1

COMH

2

S3

Device in top of stack

responds first

2

COML

[DIR0_ADDR] = 2

All the devices execute the

command

[DIR0_ADDR] = 2

[DIR0_ADDR] = 1

[DIR0_ADDR] = 0

COMH

S2

After S2 receives

response from S3, S2

also responds.

COMH

S2

COML

Process continues until

all devices send their

response

[DIR0_ADDR] = 1

COMH

S1

COMH

S1

1

COML

1

Host sends broadcast

Read command

[DIR0_ADDR] = 0

Host sends Broadcast

Write command

COMH

B0

COMH

B0

RX

TX

RX

MCU

RX

TX

MCU

TX

COML

RX

COML

(a) Broadcast Read Command

(b) Broadcast Write Command

图9-30. Broadcast Read/Write

表9-16. Broadcast Read/Write

Broadcast Read Command Sent by Host

Broadcast Write Command Sent by Host

Write OTP Unlock Code to OTP_PROG_UNLOCK1A to 1D

Registers to B0, S1, S2, and S3

Example

Read 16 Cell Voltages from B0 to S3

Comments

Frame Field

Data

Comments

Initialization

Byte

0xC0

Always 0xC0

FRAME_TYPE = 1

REQ_TYPE = 0b100 = Broadcast Read

DATA_SIZE = 0b000

0xD3

0xD0 for 1 byte data write, 0xD1 for 2 bytes

data write, 0xD2 for 3 bytes data write, and so

on.

For this example:

FRAME_TYPE = 1

REQ_TYPE = 0b101= Broadcast Write

DATA_SIZE = 0b011 = 4 bytes

Device

Address

N/A

No need to include the device address byte in

command frame

N/A

No need to include the device address byte in

command frame

Register

Address

0x0568 Start address of the register block to read

(address of VCELL16_HI in this example)

0x0300

Start address of the register block to write

(address of OTP_PROG_UNLOCK1A in this

example)

Data

0x1F

Instruct each device to return 32-bytes of data

(that is, from address 0x0568 to 0x0587),

assuming each VCELLn_HI = 0x80,

0x02B7 78BC The unlock value to OTP_PROG_UNLOCK1A

to OTP_PROG_UNLOCK1D

VCELLn_LO = 0x00, where n = 1 to 16.

CRC

0x422D

0x6BD1

9.3.6.1.1.2.2.4 Broadcast Write Reverse Direction

Usually, device is expecting to receive communication based on the [DIR_SEL] setting. If a device receives

communication frame opposite to the [DIR_SEL] setting, such as receiving command frame from COMH while

[DIR_SEL] = 0, it will flag the communication as error. The broadcast write reverse direction is a command used

to change flip the [DIR_SEL] setting when host needs to switch the daisy chain communication direction. This

command is expected to receive from an opposite direction than the [DIR_SEL] setting during reverse

communication direction procedure. See 节9.3.6.1.3.4 for details.

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Although the broadcast write reverse direction is allowed to write any register value to the device, it is not

recommended to write any other register setting other than the CONTROL1[DIR_SEL] to avoid communication

collisions. Communication collisions are not detected and result in corrupted communication on the stack

interface.

[TOP_STACK] = 0

[DIR0_ADDR] = 3

COMH

S3

COML

[DIR0_ADDR] = 2

COMH

S2

COML

[DIR0_ADDR] = 1

COMH

S1

COML

Host sends Single Write command to change

1

B0 communication direction

[DIR0_ADDR] = 0

COMH

B0

TX

RX

TX

MCU

RX

COML

Host sends Reverse Broadcast Write

command to change stack devices

communication direction

2

Reverse Broadcast Write Command

图9-31. Broadcast Write Reverse Direction

表9-17. Broadcast Write Reverse Direction

Broadcast Write Reverse Direction Command Sent by Host

Set the [DIR_SEL] = 1 on All Devices in the Daisy Chain

Comments

Example

Frame Field

Data

Initialization Byte

0xE0

Always 0xE0

FRAME_TYPE = 1

REQ_TYPE = 0b110 = Broadcast Write Reverse Direction

DATA_SIZE = 0b000

Device Address

Register Address

Data

N/A

No need to include the device address byte in command frame

Address of CONTROL1 register

0x0309

0x80

Set CONTROL1[DIR_SEL] = 1

CRC

0xC014

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9.3.6.1.2 Daisy Chain Interface

The daisy chain communication is created using differential signaling to minimize Electro-Magnetic Susceptibility

(EMS) and Bulk Current Injection (BCI) immunity. The differential communication transmits true and complement

data on the COM*P and COM*N pins, respectively. In a multiple device stack, there are configurations where the

devices are physically located on the same board or located in entirely separate packs connected with twisted-

pair wiring.

The device supports the use of transformers or capacitors to electrically isolate the signals between devices in

the stack. For applications that have multiple devices on the same PCB, a single level-shifting capacitor is

connected between the COMH/L pins of the devices. For extremely noisy environments, additional filtering may

be necessary. For devices that are separated by cabling, additional isolation components are used. See 节 10

for specific details on selecting components.

9.3.6.1.2.1 Daisy Chain Transmitter and Receiver Functionality

The daisy chain is bi-directional and half duplex, and, therefore, has a transmitter (TX) and receiver (RX) on the

COMH and COML interfaces. The TX and RX functions are controlled automatically by the hardware based on

the device’s base/stack detection. When a WAKE ping/tone is received, the communication direction is set by

CONTROL1[DIR_SEL] and the COMM_CTRL[TOP_STACK] configurations. See 节 9.3.6.1.3 for details.

Additionally, a user overwrite to take over the complete control of the COMH and COML is available under

communication debug mode using the DEBUG_CTRL_UNLOCK, DEBUG_COMM_CTRL1, and

DEBUG_COMM_CTRL2 registers. See 节9.5.4.14 for details.

9.3.6.1.2.2 Daisy Chain Protocol

The differential daisy chain (vertical) interface uses an asynchronous 13-bit byte-transfer protocol. Data is

transferred LSB first and every bit is duplicated (with a complement) to ensure the transmission has no DC

content.

”1‘

”0‘

CVDD

COM*P

COM*N

CVSS

2 x t_{PW_DC}

t_{PW_DC}

COM*P œ COMP*N

t_{PW_DC}

图9-32. Daisy Chain Bit Definition

A byte starts with a Preamble, followed by two SYNC bits, a start-of-frame bit, eight data bits starting from the

LSB D0 to MSB D7 (D0 is transmitted just after State-Of-Frame and D7 comes last before the Byte Error and

Postamble).

The device extracts timing information using the Preamble and SYNC bits to decode the rest of the bit value in

the byte. If any of the following errors is detected, the byte is not processed and register error bit is set.

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• The Preamble and SYNC bits are known values, if the decoded value has error, the DEBUG_COMH/

L_BIT[SYNC1] = 1 depends on which COM port receives this data.

• If timing extracted from the Preamble and SYNC bits is outside of the expected range, the DEBUG_COMH/

L_BIT[SYNC2] = 1.

Once the two valid SYNC bits are received, the additional bits are decoded and sent to the command processor.

The device continues to detect any error on this byte, and if error is detected, the Byte Error (BERR) bit will be

set in this byte. The DEBUG_COMH/L_BIT[PERR] = 1 depends on which COM port detects the error. The

following condition will set the BERR bit in the byte.

• Not sufficient samples to indicate the logic level of a bit. That is, a bit is decoded as not a strong 1 or strong 0.

The DEBUG_COMH/L_BIT[BIT] = 1 depends on which COM port detects the error.

In the meantime, each bit is still being retransmitted to the next device. If the device is unable to decode a 1 or a

0 for the bit, it will retransmit with 0 with the BERR bit set in the byte. When the new device detects the BERR bit

is set to 1 in the receiving byte, it will ignore the questionable byte and set the DEBUG_COMH/

L_BIT[BERR_TAG] = 1, indicating a byte is received with BERR. The questionable byte being ignored is likely to

cause other communication errors and is likely to trigger the DEBUG_COMH/L_BIT[PERR] = 1 being set in the

new device as well. The questionable byte continues to be retransmitted up the daisy chain with BERR set and

the process continues.

Communication transmits

from UART

INIT[7:0]

DEV ADR[7:0]

Byte in daisy chain

transmission

DATA[7:0]

SYNC [1:0]

+1

COM*P œ COMP*N

-1

D7

D4

D6

D1

D3

D5

D0

D2

SYNC = 2'b00

Additional bits used for daisy chain transmission

SYNC [1:0]

DATA[7:0]

+1

COM*P œ COMP*N

-1

D7

D4

D6

D1

D3

D2

6.5us nominal

D5

D0

0.5 us of bus short

1.375 us of bus idle

SYNC = 2'b00

图9-33. Daisy Chain Byte Definition

表9-18. Daisy Chain Byte Definition

Bit Field

Description

Preamble (half-bit) Indicates a start of transaction, signaling the receiver to start sampling. This half-bit and the following two SYNC bits

are used to extra timing information.

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表9-18. Daisy Chain Byte Definition (continued)

Bit Field

Description

SYNC[1:0]

Always 0b00. The SYNC bits are used for the digital to assess the timing and noise level on the byte, improving the

detection of a 1 and 0 in a noisy environment.

Start-Of-Frame (1- The Start-Of-Frame (SOF) bit indicates the follow-on data byte is the initialization byte, a start of a communication

bit)

transaction frame. Stack device needs this information to process the communication.

For command frame transaction, the base device is responsible to set the SOF bit as it translates the UART

communication to the daisy chain communication.

The initialization byte contains data size information. Based on the data size information, the base device would count

the number of bytes received and set the next SOF bit accordingly.

The UART COMM CLEAR signal resets the UART receiver which includes the frame handling of the logic. Hence, the

next byte after COMM CLEAR must have SOF set to 1 because the COMM CLEAR indicates the system clears UART

and re-starts the communication.

Data[7:0]

The actual byte of the communication transaction frame

Byte Error BERR Indicates an error detected in this byte. When a device receives a byte with BERR set by the lower device, it will

(1-bit)

retransmit the byte also with BERR = 1.

Because each data bit is re-clocked from one device to the next, the next device may not detect a communication error.

However, the tag of the [BERR] bit would indicate this communication frame has an error during its previous

transaction.

Postamble (half-

bit)

Indicates the end of transaction

Each byte is transmitted at 2 MHz (250 ns per pulse or 500 ns per couplet). The time between each byte

depends on the UART baud rate (1 Mbps in normal operation), but the byte time is always the same. The

communication frame is defined with idle time between byte. In some rare cases, communication signal may not

terminate cleanly, leaving ringing at the end of a byte. In such case, increasing the byte to byte gap can improve

the communication robustness. The device allows additional byte gap insert between bytes in the response

frame through STACK_RESPONSE register setting.

Apply to response frame only:

Additional byte gap configured by

STACK_RESPONSE delay

Up to 8.375 µs for a byte

Byte

10.875 µs at 1Mbps

40.6us at 250Kbps (if comm debug is enable)

Nominal Response byte to byte delay is fixed by the UART

baud rate

图9-34. Daisy Chain Byte Transfer

9.3.6.1.3 Start Communication

From SHUTDOWN or after device reset, host follows the following steps to bring up the devices for

communication.

• Host sends a WAKE ping to reset or bring the devices to ACTIVE mode. In this process, the devices in the

daisy chain will configure their own COMH and COML ports based on their position in the daisy chain (base

device or stack device)

– After this step, the broadcast write is supported.

• Host performs auto-addressing to assign a device address to each device

– After this step, the broadcast read/write and single device read/write are supported.

• Host configures the COMM_CTRL[STACK_DEV] and [TOP_STACK] bits. The Top of Stack (ToS) device will

disable its transmitter of the COMH (or COML based on communication direction)

– After this step, all commands, broadcast read/write, single device read/write, and stack read/write are

supported.

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[STACK_DEV] = 1

[TOP_STACK] = 1

[DIR_SEL] = 0

COMH

S3

COMH

RX TX

COMH

S3

S3:

Based on [TOP_STACK]

& [DIR_SEL] setting, S3,

in this example, disables

its COMH TX

[DIR0_ADDR] = 3

S3

COML

S1 to S3:

Receive WAKE tone.

Identified itself as stack.

Both COML and COMH are enabled

[STACK_DEV] = 1

[TOP_STACK] = 0

[DIR_SEL] = 0

COMH

S2

COMH

S2

COMH

S2

[DIR0_ADDR] = 2

COML

[STACK_DEV] = 1

[TOP_STACK] = 0

[DIR_SEL] = 0

COMH

S1

COMH

S1

COMH

S1

[DIR0_ADDR] = 1

COML

B0: Receive WAKE ping.

Identified itself as base.

[DIR_SEL =0] (default): COML

(both TX and RX) is disable

[STACK_DEV] = 0

[TOP_STACK] = 0

Host:

Configure COMM_CTRL[STACK_DEV]

& [TOP_STACK] bits to each device

[DIR_SEL] = 0

Host:

Perform auto addressing

COMH

B0

COMH

B0

COMH

B0

WAKE ping

[DIR0_ADDR] = 0

RX

TX

RX

TX

MCU

TX

MCU

TX

RX

MCU

TX

UART

TX

UART

RX

COML

RX

COML

(a) Waking up device using WAKE ping/tone

(b) Perform auto addressing

(c) Set the [STACK_DEV] & [TOP_STACK]

图9-35. Configure Device for Communication

9.3.6.1.3.1 Identify Base and Stack

A WAKE ping/tone is used for the device to identify its position in the daisy chain.

• Base device: a device interfaces with host through UART

• Stack device: a device interfaces with the base device through COMH and COML

A base device will be woke up by a WAKE ping through RX pin, while a stack device will be woke up by WAKE

tone via the COMH/COML port. Hence, a device is using a WAKE ping or WAKE tone to identify itself as base or

stack. This information is stored in the AVAO_REF block which is available in all power modes and is refreshed

whenever a WAKE ping/tone is received.

Using the CONTROL1[DIR_SEL] setting, a base device will disable the unused daisy chain ports (transmitter

and receiver). If host changes the CONTROL1[DIR_SEL] setting, the base device will reconfigure its COMH/

COML.

备注

The host starts communication at least 100 µs after changing the [DIR_SEL] setting to ensure the

device finishes the COMH/COML reconfiguration.

9.3.6.1.3.2 Auto-Addressing

Every device must have a unique device address for the read protocol to work. If, for any reason, two devices

are assigned with the same device address, it is likely that broadcast and stack reads do not work. Additionally,

single device read to the doubled address results in destroyed communication.

The default device address, assuming the device address in OTP is not programmed, is 0x00. For a host to talk

to a standalone device (that is, a stack consisting with only one device), host can simply use the default 0x00

device address. Otherwise, device address follows the rules below:

• Base device address can start with any value, it is not necessary for it to be 0x00

• All device addresses must be sequential. That is, if base is 0x00, the next device must be 0x01, and next

must be 0x02, and so on.

Before starting the auto-addressing procedure, all devices must be in ACTIVE mode. In this state, the device will

only be able to process broadcast write command, which will be the command used for the auto-addressing

procedure. Based on the CONTROL1[DIR_SEL] setting, the auto-addressing procedure sets up the device

address to either DIR0_ADDR register (when [DIR_SEL] = 0) or DIR1_ADDR register (when [DIR_SEL] = 1).

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9.3.6.1.3.2.1 Setting Up the Device Addresses

The CONTROL1[ADDR_WR] bit enables the auto-addressing mode. In this mode, the device turns off its

COMH/COML (depends on the [DIR_SEL] setting) transmitter for one communication frame (following the auto-

addressing procedure, that will be its own device’s address), clear the CONTROL1[ADDR_WR] = 0. When the

next communication is received (following the auto-addressing procedure, it will be the next device’s address),

the device will forward the communication to the next device.

[ADDR_WR] = 1

COMH

S2

[DIR_SEL] = 0

[ADDR_WR] = 1

COMH

S2

COML

S1 transmits: DIR_ADDR = 0x02

[ADDR_WR] = 0

[ADDR_WR] = 1

COMH

COML

COMH

[ADDR_WR] = 1

[DIR_SEL] = 0

[DIR0_ADDR] = 1

S1

COMH

S1

COML

B0 retransmits:

DIR_ADDR = 0x01,

DIR_ADDR = 0x02

COML

S1 receives:

DIR_ADDR = 0x01,

DIR_ADDR = 0x02

Host sending:

[ADDR_WR] = 1

DIR_ADDR = 0x00,

DIR_ADDR = 0x01,

DIR_ADDR = 0x02

[ADDR_WR] = 0

[DIR_SEL] = 0

COMH

B0

COMH

B0

B0 receives:

[DIR0_ADDR] = 0

RX

MCU

TX

RX

TX

DIR_ADDR = 0x00,

DIR_ADDR = 0x01,

DIR_ADDR = 0x02

TX

UART

RX

COML

(a) Set [ADDR_WR] = 1 to all the devices and start sending in the

device addresses

(b)B0 takes the 1^stdevice address sent by host, clear [ADDR_WR]

and retransmit the rest

(c)S1 takes the 2^nddevice address sent by host, clear [ADDR_WR]

and retransmit the rest

图9-36. Auto-Addressing

9.3.6.1.3.2.2 Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]

The last procedure in the auto-addressing is to configure the COMM_CTRL[STACK_DEV] and [TOP_STACK]

settings. These bits need to be configured for the broadcast read and stack read/write to work properly.

• Base device: [STACK_DEV] = 0 and [TOP_STACK] = 0

• Stack devices (except ToS device): [STACK_DEV] = 1 and [TOP_STACK] = 0

• ToS device: [STACK_DEV] = 1 and [TOP_STACK] = 1

表 9-19 shows the auto-addressing steps, assuming CONTROL1[DIR_SEL] = 0 (that is, each device will be set

up to transmit command frame sent by host from its COML to COMH).

表9-19. Auto-Addressing

Step

Procedure

1

This step is required if a device reset has occurred before performing the auto-addressing procedure.

Dummy Write to synchronize all daisy chain devices DLL (delay-locked loop) ramp in write direction.

Host sends broadcast write to write 0x00 to ECC_DATA1 to ECC_DATA8 registers.

2

3

Enable auto-addressing procedure.

Host sends broadcast write to set CONTROL1[ADDR_WR] = 1.

Sending in the device addresses. Host sends broadcast write to set the consecutive addresses to

DIR0_ADDR[ADDRESS5:0]. With an example of a total of three devices in a daisy chain:

1. Send broadcast write to DIR0_ADDR register with data 0x00.

2. Send broadcast write to DIR0_ADDR register with data 0x01.

3. Send broadcast write to DIR0_ADDR register with data 0x02.

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表9-19. Auto-Addressing (continued)

Step

Procedure

4

Set up the COMM_CTRL[STACK_DEV] and [TOP_STACK] bits for each device.

Option 1: Host sends single device write to each device to set the proper [STACK_DEV] and [TOP_STACK] values.

Option 2 (less communication steps):

1. Host sends broadcast write to set [STACK_DEV] = 1 and [TOP_STACK] = 0.

2. Host sends single device write to base device (device address 0x00 in this example) with [STACK_DEV] = 0.

3. Host send single device write to the ToS device address 0x02 in this example) with [TOP_STACK] = 1.

5

This step is required if a device reset has occurred before performing the auto-addressing procedure.

Dummy read to synchronize all daisy chain devices DLL ramp in read direction.

Host sends broadcast read to read ECC_DATA1 to ECC_DATA8registers. Host may not receive all of the data as this step

synchronizes the DLL.

7

8

Recommended as good practice. Use broadcast read to read DIR0_ADDR registers to read back all device addresses to

ensure all devices are addressed properly.

If the dummy write and dummy read steps are performed to synchronize the DLL , it is normal if communication fault is

triggered. Clear the fault registers if that is the case.

9.3.6.1.3.2.3 Storing Device Address to OTP

The device uses DIR0_ADDR (used with [DIR_SEL] = 0) and DIR1_ADDR (used with [DIR_SEL] = 1) registers

for its device address. In the auto-addressing procedure, device address is written to one of these registers and

the new device address takes effect immediately.

The host has an option to program the device addresses for the [DIR_SEL] = 0 and 1 directions to the OTP,

allowing the programmed addresses to be loaded whenever the device is reset. To program the device address

to OTP, host writes the desired address to the OTP shadow registers, DIR0_ADDR_OTP (used when [DIR_SEL]

= 0) and DIR1_ADDR_OTP (used when [DIR_SEL] = 1) and performs OTP programming. These two shadow

registers only reflect the value programmed in OTP or use for the host to program the desired value to OTP.

These two shadow registers are not the device address setting during communication. See 节 9.3.6.3.2 for

programming details.

9.3.6.1.3.3 Synchronize Daisy Chain DLL

When device is reset or enter ACTIVE from SLEEP. MCU should perform dummy write and read to synchronize

the DLL on the daisy chain devices.

In the device reset case, if device address is not programmed in OTP. MCU must perform an auto-address. The

DLL synchronization is part of the step. If device address is programmed in OTP, auto-address is not required

after device reset. However, MCU should perform a dummy write and dummy read steps shown in 表 9-19,

step1 and step5 to synchronize the DLL.

When device goes from SLEEP to ACTIVE using SLEEPtoACTIVE signal, the device is not reset. However, it is

recommend to do a 1-data-byte dummy write and read to ensure robustness. Follow the similar dummy write

and read steps in Table 21, but only write and read to OTP_ECC_DATAIN1.

9.3.6.1.3.4 Ring Communication

The daisy chain communication for the device uses a Ring architecture. In this architecture, a cable break

between two devices does not prevent communication to all upstream devices as in a normal non-Ring scheme.

When the host detects a broken communication, the device allows the host to switch the communication

direction to communicate with devices on both sides of the break. This allows for safe operation until the break in

the lines is repaired.

The CONTROL1[DIR_SEL] controls the communication direction. The devices will reconfigure the COMH and

COML ports depending on the [DIR_SEL] and the [TOP_STACK] settings. Auto-addressing procedure is needed

to re-address the device address for the reverse communication direction.

Example to change the communication direction to [DIR_SEL] = 1 to the entire daisy chain:

1. Host sends Single Device Write to change the base device [DIR_SEL] = 1. The base device will disable its

COMH and enable its COML.

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2. Host sends Broadcast Write Reverse Direction to clear the COMM_CTRL register settings on all devices.

3. Host sends Broadcast Write Reverse Direction to change the rest of the devices’[DIR_SEL] = 1. In this

step, the entire daisy chain set up to transmitting communication in the [DIR_SEL] = 1 direction (that is, each

device set up to transmit command frames sent by host from its COMH to its COML).

4. Host performs auto-addressing procedure to set up device address in the DIR1_ADDR register. Unless the

devices have been reset, host can skip the dummy read/write steps to synchronize the DLL in the auto-

addressing procedure.

5. Host sets up the new Top of Stack device and the new ToS device will disable its COML transmitter.

[TOP_STACK] = 1

[TOP_STACK] = 0

[DIR_SEL] = 0

[DIR_SEL] = 1

COMH

RX TX

COMH

RX TX

COMH

RX TX

[DIR0_ADDR] = 3

[DIR1_ADDR] = 1

[DIR0_ADDR] = 3

S3

COML

[DIR_SEL] = 0

[DIR_SEL] = 1

COMH

S2

COMH

S2

COMH

S2

[DIR0_ADDR] = 2

[DIR1_ADDR] = 2

[DIR0_ADDR] = 2

COML

[DIR_SEL] = 0

[TOP_STACK] = 1

[DIR_SEL] = 1

COMH

S1

COMH

S1

COMH

S1

[DIR0_ADDR] = 1

[DIR1_ADDR] = 3

[DIR0_ADDR] = 1

COMH

RX TX

COML

Host:

Broadcast write reverse

direction to change the rest of

the devices [DIR_SEL] = 1

Host:

Sing device write to

change [DIR_SEL] = 1

[DIR_SEL] = 1

COMH

B0

COMH

B0

COMH

B0

[DIR0_ADDR] = 0

[DIR1_ADDR] = 0

[DIR0_ADDR] = 0

RX

TX

RX

TX

MCU

TX

MCU

TX

UART

RX

COML

(a) Change the communication direction on the base device

(b) Clear Top of Stack and change the communication

direction to the stack devices

(c) re-address the device addresses for the reverse

communication direction, and set the new Top of Stack

图9-37. Example to Change Communication Direction in Daisy Chain

Once the device address in both communication directions is set up, host can skip auto-address step when

switching communication direction.

In a broken cable case, host follows the same procedure to change the communication direction. To access all

devices in the daisy chain, host will have to communicate with [DIR_SEL] = 0 on some devices and

communicate with [DIR_SEL] = 1 on other devices in the daisy chain. The chain will also have two ToS devices,

one for each communication direction.

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[DIR_SEL] = 1

COMH

RX TX

S3

[DIR1_ADDR] = 1

COML

[TOP_STACK] = 1

[DIR_SEL] = 1

COMH

S2

COMH

S2

[DIR1_ADDR] = 2

COML

[TOP_STACK] = 1

[DIR_SEL] = 0

[TOP_STACK] = 1

COMH

S1

COMH

S1

[DIR0_ADDR] = 1

COMH

RX TX

[DIR_SEL] = 1

[DIR_SEL] = 0

COMH

B0

COMH

B0

[DIR0_ADDR] = 0

RX

TX

RX

TX

[DIR1_ADDR] = 0

COML

(a) Use [DIR_SEL] = 0 direction to communicate to S1

(a) Use [DIR_SEL] = 1 direction to communicate to S3 and S2

图9-38. Using Ring Architecture to Access All Devices in a Broken Cable Case

9.3.6.1.4 Communication Timeout

There are two programmable communication timeout thresholds, CTS timer and CTL timer, that monitor the

absence of a valid frame from either UART or daisy chain communication. A valid frame is defined as any frame

(response or command) that does NOT contain any errors that prevent the frame from being processed. The

communication timeouts are only actively counting while in ACTIVE mode. The counters are disabled and reset

during SHUTDOWN mode. In SLEEP mode, the last counter values are held frozen.

9.3.6.1.4.1 Short Communication Timeout

The short communication timeout acts like an alert to the host when triggered. The timeout period is

programmable through the COMM_TIMEOUT_CONF[CTS_TIME2:0] bits. If enabled, the timer is reset every

time a valid response or command frame is received. If the timer expires, the FAULT_SYS[CTS] bit is set.

9.3.6.1.4.2 Long Communication Timeout

The long communication timeout allows the host to put the device in SLEEP or SHUTDOWN mode for power

saving. The timeout period is programmable through COMM_TIMEOUT_CONF[CTL_TIME2:0] bits. If enabled,

the timer is reset every time a valid response or command frame is received. If the timer expires, host can

choose one of the following actions through COMM_TIMEOUT_CONF[CTL_ACT] bit.

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• Set FAULT_SYS[CTL] = 1 and enter SLEEP mode.

• Enter SHUTDOWN mode.

9.3.6.1.5 Communication Debug Mode

The device provides a communication debug mode to ease the initial development phase. To enter this debug

mode, host writes an unlock code 0xA5 to register DEBUG_CTRL_UNLOCK. Once the debug mode is unlocked,

the settings in DEBUG_COMM_CTRL1 and DEBUG_COMM_CTRL2 become effective.

To exit the debug mode simply write any value but 0xA5 (for example, writing 0x00) to the

DEBUG_CTRL_UNLOCK. The COMH, COML, and UART will return to their normal operation status regardless

of the settings in the DEBUG_COMM_CTRL1 and DEBUG_COMM_CTRL2 registers.

Once the communication debug mode is entered, the host gains control of the following:

表9-20. Communication Debug Mode Functions

Control Function

Enable Bit

Description

Full COMH/L transmitter and

receiver control

[USER_DAISY_EN] If [USER_DAISY_EN] = 1, device will enable or disable its COMH/L transmitter and

receiver based on the DEBUG_COMM_CTRL2 register setting.

If [USER_DAISY_EN] = 0, COMH/L will be in its normal operation status even

under communication debug mode.

Mirror out the data in daisy

chain onto UART

[USER_UART_EN] If [USER_UART_EN] = 1, host can set [UART_MIRROR_EN] = 1 to instruct the

device to translate the daisy chain onto the UART, allowing host to read the data

being received or forwarded in the daisy chain from the UART interface. Data will

be presented in UART communication frame format.

For stack devices, the UART TX is disabled by default. To use this feature, host

also sets [UART_TX_EN] = 1.

If [USER_UART_EN] = 0, any UART related debug functions are disabled. The

UART will be in its normal operation status regardless of the [UART_MIRROR_EN]

and [UART_TX_EN] settings.

Slow down UART baud rate to

250 kbps

[USER_UART_EN] If [USER_UART_EN] = 1, host can set [UART_BAUD] = 1 to change the UART

baud rate to 250 kbps. This will result in slow throughput rate on the daisy chain.

If [USER_UART_EN] = 0, UART baud rate will stay on 1 Mbps regardless of the

[UART_BAUD] setting.

The DEBUG_COMM_STAT register has status bits indicating if UART and COMH/L are under user or hardware

(device) control. The register also indicates the status of the COMH/L transmitter and receiver. This debug status

register is updated per device status and is readable with or without the communication debug mode enabled.

In fact, the read-only debug registers are all readable in ACTIVE mode without communication debug mode

enabled. Most of them are lower level communication fault status registers to provide extra information in a

communication failure event like the DEBUG_UART*, DEBUG_COMH*, and DEBUG_COML* registers. See 节

9.3.6.2 and 节9.5.4 for more details.

9.3.6.1.6 Multidrop Configuration

A multidrop configuration is a configuration of multiple devices in a system communicating through UART to the

host system. There is no daisy chain communication between devices. When [MULTIDROP] = 1, the device

COMH and COML ports are disabled. All the communication protocols, single device read/write, broadcast read/

write, stack read/write, reverse broadcast write are still supported as in daisy chain configuration (that is,

[MULTIDROP] = 0). However, in a multidrop configuration, it is unlikely to have a use of the stack and reverse

broadcast commands. If broadcast command is used, it is still required to set up the devices with sequential

device address and set the [TOP_STACK] bit on the device with highest device address. The device with

[TOP_STACK] = 1 will initiate the data return when a broadcast read command is received, and the device with

one lower device address will respond next, as in a daisy chain communication. Additionally, a COMM_CLR

must be used before every frame to ensure consistent communication in multidrop configuration.

9.3.6.1.7 SPI Master

The GPIO4 thru GPIO7 are configurable as a SPI master interface when GPIO_CONF1[SPI_EN] = 1. The SPI

master includes four I/Os:

• SCLK: SPI clock, generated by the device and is used for synchronization

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• MOSI: Master data output, driven by the device to output data to slave

• MISO: Master data input, detecting data from slave

• SS: slave select, driven by the device during SPI communication.

COMH

CLK

SDI

GPIO7

GPIO6

bq7961x

(ToS, S3)

SPI based

EEPROM

SDO

GPIO5

GPIO4

CS

COML

COMH

bq7961x

(S2)

CLK

SDI

GPIO7

GPIO6

SPI based

EEPROM

SDO

GPIO5

GPIO4

COML

CS

COMH

CLK

SDI

GPIO7

GPIO6

bq7961x

(S1)

SPI based

EEPROM

SDO

GPIO5

GPIO4

CS

COML

COMH

CLK

SDI

GPIO7

GPIO6

bq7961x

(Base, B0)

MCU

SPI based

EEPROM

TX

RX

TX

SDO

GPIO5

GPIO4

CS

COML

Host talks to the device SPI control registers to

perform read/write operation to an external SPI

based slave device

Device read/write to the external SPI based slave via

GPIO4...7 based on MCU‘s operation instruction

图9-39. SPI Master Stack Configuration

The SPI_CONF[CPOL] (clock polarity) and [CPHA] (clock phase) define the SPI clock format. The [CPOL] is

defined if the SPI clock is inverted or non-inverted. The [CPHA] is defined if the MISO and MOSI are sampled on

the leading (first) clock edge or on the trailing (second) clock edge, regardless of whether that clock edge is

rising or falling. The SPI_CONF[NUMBIT4:0] defines how many bits the transaction is (1-bit to 24-bit

transaction).

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CPOL = 0 CPHA = 0

CPOL = 0 CPHA = 1

Data Clocked

SCLK

SS

SCLK

SS

IDLE

MOSI

MISO

IDLE

MISO

IDLE

CPOL = 1 CPHA = 0

CPOL = 1 CPHA = 1

Data Clocked

SCLK

SS

SCLK

SS

MOSI

MISO

IDLE

MOSI

MISO

IDLE

Legend

Data on MISO and MOSI is sampled at this time

Data on MISO and MOSI is change at this time

图9-40. SPI Master CPOL and CPHA

t_HIGH:tLOW

f_SCLK

t_HIGH:tLOW

f_SCLK

t_HIGH:tLOW

f_SCLK

t_HIGH:tLOW

f_SCLK

t_SS,LOW

t_SS,HI

t_SS,LOW

t_SS,HI

SCLK

(CPOL=0)

SCLK

(CPOL=0)

SCLK

(CPOL=1)

SCLK

(CPOL=1)

SS

t_HD,MISO

t_SU,MISO

t_HD,MISO

MSB in

IDLE

DATA in

DATA out

CPHA=0

LSB in

MSB in

DATA in

DATA out

CPHA=1

LSB in

MISO

MOSI

MISO

MOSI

IDLE

MSB out

LSB out

MSB out

LSB out

t_VALID,MOSI

t_MOSI,DIS

t_VALID,MOSI

t_MOSI,DIS

图9-41. SPI Master Timing Diagram

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表9-21. Write to External SPI Slave

Step

Description

1

Configure the SPI clock polarity, clock phase, number of bit transactions:

a. Write to SPI_CONF register to configure SPI communication

2

3

Write the data (from 1 to 24 bits, specified in the SPI_CONF[NUMBIT4:0] setting):

a. Set up the data to send to SPI slave to the SPI_TX1 to SPI_TX3 registers

b. SPI_TX1 is the LSByte and SPI_TX3 is MSByte

Select the slave (assuming active low) and execute the SPI write action:

a. Send SPI_EXE register = 0x01 (that is, [SS_CTRL] = 0 and [SPI_GO] = 1)

4

5

Wait for the SPI communication to complete

Deselect the SS port (assuming active low, so deselecting means pull the SS pin high):

a. Send SPI_EXE register = 0x02 (that is, [SS_CTRL] = 1 and [SPI_GO] = 0)

表9-22. Read from External SPI Slave

Step

Description

1

Configure the SPI clock polarity, clock phase, number of bit transactions:

a. Write to SPI_CONF register to configure SPI communication

2

Select the slave and execute the SPI communication:

a. Send SPI_EXE register = 0x01 (that is, [SS_CTRL] = 0 and [SPI_GO] = 1)

3

4

Wait for the data transaction to complete

Read the data (from 1 to 24 bits, specified in the SPI_CONF[NUMBIT4:0] setting):

a. Read data from SPI slave from the SPI_RX1 to SPI_RX3 registers

b. SPI_TX1 is the LSByte and SPI_TX3 is MSByte

5

Deselect the SS port (assuming active low, so deselecting means pull the SS pin high):

a. Send SPI_EXE register = 0x02 (that is, [SS_CTRL] = 1 and [SPI_GO] = 0)

9.3.6.1.8 SPI Loopback

The SPI master has a loopback function that is enabled using the DIAG_COMM_CTRL[SPI_LOOPBACK] bit.

When enabled, the byte in the SPI_TX* registers are clocked directly to the MISO pin of the SPI master to verify

the SPI master functionality. This is performed internally, so no external connection is needed to run this test.

This verifies that the SPI function is working correctly. The SPI_CFG, SPI_TX*, and SPI_EXE registers are

written as a normal SPI transaction, but the external pins do not toggle during this mode. That is, the external

pins stay static in their last state and do not change state during the loopback operation.

The expected result of the test is that the byte in the SPI_TX* register is read into the SPI_RX* register. The SS

pin is latched to the setting in SPI_EXE[SS_CTRL] that existed when the LOOPBACK mode was enabled. The

CPHA and CPOL parameters must be set before entering LOOPBACK mode to ensure proper operation.

Changing the CPOL or CPHA parameters while in LOOPBACK mode may result in errant pulses on the SPI

outputs and is not recommended.

9.3.6.2 Fault Handling

9.3.6.2.1 Fault Status Hierarchy

The device monitors multiple types of faults such as:

• Battery cell monitoring through the hardware protector, like cell OV/UV, cell OT/UT, and so on

• System operation driven like device reset, communication timeout, thermal warning, and so on

• Command-based diagnostic check related like the various comparison through the main and AUX ADCs,

BIST run, and so on

• Automatic diagnostic check running in the background like the internal power supplies, OTP CRC, and so on

• Communication fault.

Each bit in the FAULT_SUMMARY register represents a group of faults which are stored in one or more lower

level fault registers. The FAULT_SUMMARY register represents the highest hierarchy level of fault status

detected by the device. Host system can periodically poll the FAULT_SUMMARY register to check the fault

status and only read the lower level fault registers if needed (for example, if FAULT_SUMMARY[FAULT_OVUV]

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= 1, host can read FAULT_OV1/2 and FAULT_UV1/2 registers to determine which cell channel triggered the

fault).

表 9-23 shows which lower level register corresponds to the FAULT_SUMMARY register bit. The description of

the register is covered in the 节9.5.

表9-23. Low-Level Fault Registers

FAULT_SUMMA

RY Bit Name

FAULT_PROT

FAULT_COMP_ADC

FAULT_OTP

FAULT_COMM

FAULT_OTUT

FAULT_OVUV

FAULT_SYS

FAULT_PWR

Lower level

register name

FAULT_PROT

1

FAULT_COMP_GPIO

FAULT_OTP ⁽¹⁾FAULT_ COMM1

FAULT_OT

FAULT_OV1

FAULT_SYS

FAULT_PWR1

(1)

FAULT_PROT

2

FAULT_COMP_VCCB1

FAULT_ COMM2

FAULT_UT

FAULT_OV2

FAULT_PWR2

FAULT_PWR3

(1)

FAULT_COMP_VCCB2

FAULT_COMP_VCOW1

FAULT_COMP_VCOW2

FAULT_COMP_CBOW1

FAULT_COMP_CBOW2

FAULT_COMP_CBFET1

FAULT_COMP_CBFET2

FAULT_COMP_MISC

FAULT_ COMM3

FAULT_UV1

FAULT_UV2

(1) Some of the bits in the FAULT_COMM1/2 and FAULT_OTP registers have a lower level of fault information than shown in the

DEBUG_COMM* and DEBUG_OTP registers.

9.3.6.2.1.1 Debug Registers

The DEBUG_COMM* and DEBUG_OTP registers are a form of fault status showing lower hierarchy level of fault

information for some of the bits in FAULT_COMM1 , FAULT_COMM2, and FAULT_OTP.

表9-24 shows the hierarchy relationship. See 节9.5 for the register description details.

表9-24. Debug Registers

Low-level Fault Register

Low-level Register Bit

Associated DEBUG Registers

DEBUG_UART_RC

[UART_RC] Fault related to received command frame from UART

FAULT_COMM1

[UART_RR] Fault related to received or transmitted response frame

[UART_TR] from UART

DEBUG_UART_RR_TR

[COMH_BIT] Fault related to error in a byte from COMH

DEBUG_COMH_BIT

DEBUG_COMH_RC

[COMH_RC] Fault related to received command frame from COMH

[COMH_RR] Fault related to received or transmitted response frame

[COMH_TR] from COMH

DEBUG_COMH_RR_TR

FAULT_COMM2

FAULT_OTP

[COML_BIT] Fault related to error in a byte from COML

DEBUG_COML_BIT

DEBUG_COML_RC

[COML_RC] Fault related to received command frame from COML

[COML_RR] Fault related to received or transmitted response frame

[COML_TR] from COML

DEBUG_COML_RR_TR

[SEC_DET] Single error correction in OTP

[DED_DET] Double error correction in OTP

DEBUG_OTP_SEC_BLK

DEBUG_OTP_DED_BLK

9.3.6.2.2 Fault Masking and Reset

9.3.6.2.2.1 Fault Masking

When a device detects a fault, the corresponding low-level register bit, including the one in the related bit in the

DEBUG_* registers is set. Based on the fault hierarchy relationship, the fault will be reflected in the

FAULT_SUMMARY register.

A group of faults can be masked, which the related low-level register flag will still be set, but the fault will not be

reflected to the corresponding FAULT_SUMMARY register. The faults can be masked through the FAULT_MSK1

and FAULT_MSK2 registers.

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For example, to mask the FAULT_SUMMARY[FAULT_OTUT] being set, host sets FAULT_MSK1[MSK_OT] = 1

and [MSK_UT] = 1.

When fault is masked, it will also prevent the device from asserting the NFAULT pin when the masked fault

occurs. See 节9.3.6.2.3 for details on NFAULT signal.

表9-25. Fault Masking

FAULT_SUMMARY Register Bit That

Masking Bit Name

Related Low-level Register(s) Affected

Will Be Masked

[MSK_PROT]

[MSK_UT]

FAULT_PROT*

FAULT_UT

[FAULT_PROT]

[FAULT_OTUT]

[FAULT_OVUV]

[MSK_OT]

FAULT_OT

[MSK_UV]

FAULT_UV*

FAULT_MSK1

[MSK_OV]

FAULT_OV*

[MSK_COMP]

[MSK_SYS]

FAULT_COMP_*

FAULT_SYS

[FAULT_COMP]

[FAULT_SYS]

[FAULT_PWR]

[MSK_PWR]

[MSK_OTP_CRC]

[MSK_OTP_DATA]

FAULT_PWR*

FAULT_OTP[CUST_CRC][FACT_CRC]

[FAULT_OTP]

All non-CRC bits in FAULT_OTP,

DEBUG_OTP_*

[MSK_COMM3_FCOMM]

[MSK_COMM3_FTONE]

[MSK_COMM3_HB]

[MSK_COMM2]

FAULT_COMM3[FCOMM_DET]

FAULT_COMM3[FTONE_DET]

FAULT_MSK2

[FAULT_COMM3]

FAULT_COMM3[HB_FAIL][HB_FAST]

FAULT_COMM2, DEBUG_COMH_*,

[FAULT_COMM2]

[FAULT_COMM1]

DEBUG_COML_*

[MSK_COMM1]

FAULT_COMM1, DEBUG_UART_*

9.3.6.2.2.2 Fault Reset

Once fault is detected, the fault status bit is latched until cleared using the reset bit. Similar to fault masking,

when the specific fault reset bit is set, the associated low-level fault registers, including the DEBUG_* registers

are cleared. The corresponding bit in the FAULT_SUMMARY register will clear if all its associated low-level

registers are cleared. If the fault condition persists and the reset bit is written, the fault status bit is not reset. The

fault indicator cannot be reset until the underlying fault condition is eliminated.

The fault is reset through the FAULT_RST1 and FAULT_RST2 registers; the fault reset bits are structured in the

same corresponding fault status registers as the fault masking bits.

9.3.6.2.3 Fault Signaling

Host can acquire the fault status with the following methods:

• Constantly polling the FAULT_SUMMARY status on each device in the daisy chain. If FAULT_SUMMARY is

non-zero, read the low-level fault status registers to obtain more information.

• Enable fault status to pass down the daisy chain to the base device. Enable base device’s NFAULT pin to

be asserted when the FAULT_SUMMARY is non-zero in any of the devices in the daisy chain. Host monitors

NFAULT. When NFAULT is triggered, host does a broadcast read on the FAULT_SUMMARY to determine

which device(s) is at fault.

When using the NFAULT pin in the base device to signal the host under a fault detection, the stack devices have

to transfer their fault status information to the base device. The information is transmitted through COMH/L

through the same communication cables. In ACTIVE mode, each device embeds the fault status to the

communication when a response frame is forwarded. In SLEEP mode, or using Heartbeat and Fault Tone in

SLEEP mode.

The NFAULT pin can be masked by configuring DEV_CONF[NFAULT_EN] = 0. When NFAULT is disabled, the

device will set the corresponding flag in FAULT_SUMMARY register but will not assert NFAULT.

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9.3.6.2.3.1 Fault Status Transmitting in ACTIVE Mode

In ACTIVE mode, stack devices can embed their fault status before retransmitting a response frame if

DEV_CONF[FCOMM_EN] = 1. When the [FCOMM_EN] = 1, the stack devices repurpose the SOF bit in the

response frame’s device address byte, register address bytes (both high and low address bytes) to a fault

status bit instead. See 图9-42. This will be referred to as fault status bits in the rest of this section.

INIT[7:0]

Dev ADR[7:0]

REG ADR[15:8]

REG ADR[7:0]

SYNC [1:0]

+1

SYNC = 2'b00

SOF = 0

(a) Response frame if [FCOMM_EN] = 0

SOF = 1

SOF = 0

INIT[7:0]

Dev ADR[7:0]

REG ADR[15:8]

REG ADR[7:0]

SYNC [1:0]

SYNC = 2'b00

SYNC [1:0]

SYNC = 2'b00

+1

SYNC = 2'b00

SOF = 1

Fault Status = 0: no fault

Fault Status = 1: fault

Fault Status = 0: no fault

Fault Status = 1: fault

Fault Status = 0: no fault

Fault Status = 1: fault

(b) Response frame if [FCOMM_EN] = 1

图9-42. Embed Fault Status in Communication Response Frame

To pass on the fault status of the stack devices, the host sends a broadcast read or sends a single device read

to the ToS device. Both types of reads will result in response frames passing through every device in the daisy

chain, giving each device an opportunity to OR their fault status to the fault status bits in the response frame.

An example of a response frame going through a daisy chain from a single device read command to the top

device is shown in 图9-43.

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[DIR_SEL] = 0

COMH

RX TX

(1) S3 is NOT at fault, returns its

response frame (fault status bit is

0b000) & transmits to S2

S3

COML

[DIR_SEL] = 0

COMH

S2

AT Fault

(2) S2 is at fault, so it —OR“ 0b111 to

the Fault Status bits of the response

frame and transmits to S1

AT Fault

S2

COML

[DIR_SEL] = 0

COMH

S1

COMH

S1

(3) S1 is not at fault, so it —OR“ 0b000 to the Fault

Status bits (resulting with 0b111) of the response frame

and transmits to B0

AT Fault

S1 will set FAULT_COMM3[FCOMM_DET] = 1 indicating

a device in the stack is at fault

(5) If FAULT_COMM3[FCOMM_DET] is not

masked, S1 and B0 will also in fault state after

transmitting the response frame

COML

[DIR_SEL] = 0

COMH

B0

COMH

B0

AT Fault

RX

TX

RX

MCU

TX

NFAULT

COML

INT

COML

(4) B0 detects the response frame has fault status bits set to

0b111, it assert NFAULT to host. It will also set

FAULT_COMM3[FCOMM_DET] = 1

图9-43. Transfer Fault Status in ACTIVE Mode (Respond to a Single Device Read)

When a device has no fault, it will OR the fault status bits with 0b000; otherwise, it will OR the fault status bits

with 0b111. Hence, if a fault exists in any device in the daisy chain, the fault status bits will be 0b111. For the

base device to assert the NFAULT pin, it requires at least two bits of the fault status bits to be 1.

Additionally, when a device detects a response frame with at least two of the fault status bits being 1, the device

will also set the FAULT_COMM3[FCOMM_DET] = 1. If this fault is not masked, the device will be in fault state as

well. Next time a response frame is transmitted, this device will OR the fault status bits with 0b111.

Host performs a broadcast read to detect which device in the daisy chain is at fault and what type of fault.

9.3.6.2.3.2 Fault Status Transmitting in SLEEP Mode

In SLEEP mode, the following fault detections are still active:

• Customer and Factory OTP shadow registers CRC check

• Device thermal warning

• Power supplies OV, UV, and oscillation detection

• If OVUV protectors are enabled, cell OV and UV detection.

• If OTUT protectors are enabled, thermistors OT and UT detection.

Because communication is not available in SLEEP mode, the device provides an option to transmit the fault

status through Heartbeat (device in no fault state) and Fault (device in fault state) Tones. These tones are

transmitted in the same direction as a communication command frame, which is based on the

CONTROL1[DIR_SEL] setting. For the tone signal to return back to the base device (so NFAULT can be

triggered if needed), a Ring architecture must be used to support transmitting fault status in SLEEP mode.

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[DIR_SEL] = 0

[DIR_SEL] = 1

S3

(ToS)

S3

[DIR_SEL] = 0

[DIR_SEL] = 1

S2

[DIR_SEL] = 1

S1

(ToS)

S1

NFAULT is asserted if B0

receives Fault Tone

[DIR_SEL] = 1

B0

(base)

B0

(base)

MCU

NFAULT

I/O

NFAULT

I/O

NFAULT is asserted if B0

receives Fault Tone

(b) Traveling direction with [DIR_SEL] = 1

(a) Traveling direction with [DIR_SEL] = 0

图9-44. Heartbeat or Fault Tone Traveling Direction

Both the Heartbeat and Fault Tones are a type of tone similar to the communication tone. One main difference is

a communication tone only transmits with a single burst of couplets, but Heartbeat and Fault Tones are sent with

a burst of couplets periodically. See 节9.3.6.2.3.3 for details.

9.3.6.2.3.3 Heartbeat and Fault Tone

The tones are enabled by setting DEV_CONF[HB_EN] = 1 and DEV_CONF[FTONE_EN] = 1 to enable the

Heartbeat and Fault Tone transmitters, respectively. The Heartbeat and Fault Tone receivers are always on in

SLEEP mode regardless of the [HB_EN] and [FTONE_EN] settings. To avoid fault detection (asserting NFAULT

or FAULT_SUMMARY register) by Heartbeat or Fault Tone fault, mask the fault by [MSK_COMM3_HB] = 1 or

[MSK_COMM3_FTONE] = 1.

The Heartbeat and Fault Tone are formed with couplets with “–“ polarity. They are differentiated by the

number of couplets. Unlike communication tones, Heartbeat and Fault Tone are transmitted periodically. The

period between tones is referring as Burst period. The number of couplets transmitted is always greater than the

number of couplets needed for detection.

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Heartbeat, Fault Tone Couplets (all —-— pulses)

CVDD

COM*P

COM*N

CVDD/2

CVSS

t_{FLTONE_HI}

f_COMTONE

COM*P œ COMP*N

t_{FLTTONE_LO}

Heartbeat or Fault Tone Detection

Burst period

Couplets detection by receiving device

COM*P,COM*N

Heartbeat or Fault Tone

Tone detection

(internal signal)

图9-45. Heartbeat and Fault Tone

9.3.6.3 Nonvolatile Memory

There are memory locations that are programmable in nonvolatile memory (NVM) using OTP (One Time

Programmable). The memory space is divided in two groups, factory space and customer space. The factory

space stores the device configurations that are essential for normal operation. This space is not accessible by

the host. The customer space contains the device default setting that host system can customize for their

application configuration. This space is readable and programmable by the host.

When a device reset occurs, factory and customer OTP values are reloaded to their shadow registers. Error

check and correction (ECC), single error correction (SEC) and double error detection (DED), are performed

during the factory and customer space OTP load. The corresponding FAULT_OTP[SEC_DET] or

FAULT_OTP[DED_DET] will be set if an error is detected.

Any load errors of the factory OTP space signal a fault using the FAULT_OTP[FACTLDERR]. Any load errors of

the customer OTP space signal a fault using the FAULT_OTP[CUSTLDERR]. Additionally, the OTP space

(factory and customer) are protected from data integrity problems using CRC. The corresponding

FAULT_OTP[FACT_CRC] and [CUST_CRC] bits will be set if a CRC error is detected.

If any overvoltage error conditions exist in the OTP pages space (factory and customer) during programming, the

OTP_FAULT[GBLOVERR] bit is set. Information received from the device with this error must not be considered

reliable.

9.3.6.3.1 OTP Page Status

There are two unused pages of OTP memory available for the customer to program. Each page status is held in

the OTP_CUST1_STAT and OTP_CUST2_STAT registers. The registers provide information on the current

status of the page such as:

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• Load status (if loaded, loaded with error, loaded but failed)

• Programmed successfully or available to be programmed

• Programmed status

When a reset occurs, the device evaluates the OTP page status and chooses the latest and valid OTP page to

load. Page 2 has priority over Page 1. If both pages have not been written, the factory OTP default are loaded.

节 9.5.1 shows all customer programmable OTP parameters. The register summary also shows the default

values when Customer OTP Page 1 and Page 2 are not programmed.

• A valid page is one where the OTP_CUST*_STAT[PROGOK] = 1.

• When the page is selected for loading, the OTP_CUST*_STAT1[LOADED] = 1.

• If a single error occurs in the loading of the page, the page is loaded after the single error is corrected and the

OTP_CUST*_STAT1[LOADWRN] = 1.

– Additionally, the DEBUG_OTP_SEC_BLK register is updated with the location of the error corrected block.

• If a double error occurs, the loading of that block is terminated and the hardware defaults of that block are

loaded (as indicated in 节9.5.1).

– The overall page loading process is not terminated for a DED, only the affected block is terminated.

– When a DED occurs, the OTP_CUST*_STAT1[LOADERR] = 1. Additionally, the DEBUG_OTP_DED_BLK

register is updated with the block where the double error occurred.

9.3.6.3.2 OTP Programming

节9.5.1 shows all parameters that can be programmed to the customer OTP page. There are two pages of OTP

memory available for customer to use.

Before programming the OTP, host ensures:

• All OTP shadow registers have the correct settings

• A customer OTP page is valid to be programmed. A valid page is one with OTP_CUST*_STAT1[TRY] = 0 and

OTP_CUST*_STAT1[FMTERR] = 0.

表9-26. Program the OTP

Step

Procedure

1

Unlock the OTP programming:

a. Write the following data to OTP_PROG_UNLOCK1A to OTP_PROG_UNLOCK1D registers.

•

OTP_PROG_UNLOCK1A <- data 0x02

OTP_PROG_UNLOCK1B <- data 0xB7

OTP_PROG_UNLOCK1C <- data 0x78

OTP_PROG_UNLOCK1D <- data 0xBC

b. Do another write with the following data to OTP_PROG_UNLOCK2A to OTP_PROG_UNLOCK2D registers.

•

OTP_PROG_UNLOCK2A <- data 0x7E

OTP_PROG_UNLOCK2B <- data 0x12

OTP_PROG_UNLOCK2C <- data 0x08

OTP_PROG_UNLOCK2D <- data 0x6F

Each block of registers must be written in order (that is, A, B, C, then D) with no other writes or reads between. The best

practice is to use the same Write command to update. Any attempt to update the registers out of sequence, or if another

register is written or read between writes, the entire sequence must be redone.

2

Check to confirm the OTP unlock procedure is successful:

a. Read to confirm OTP_PROG_STAT[UNLOCK] = 1

Issuing a Read command after step 1 is ok, but issuing the [PROG_GO] must be the next write command after the unlock

procedures.

3

4

Select the proper OTP page and start the OTP programming:

a. To program page1, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x01, or

b. To program page2, set OTP_PROG_CTRL[PAGESEL][PROG_GO] = 0x03

Wait t_PROG= 100ms for the OTP programming to complete. During this time no data communication is allowed.

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表9-26. Program the OTP (continued)

Step

Procedure

5

Check to ensure there is no error during OTP programming. The following bits are expected to be 1 after a successful

OTP programming:

a. OTP_PROG_STAT[DONE] = 1, OTP programming is done. No other bit will be set in this register.

b. If page 1 is programmed, OTP_CUST1_STAT[PROGOK], [TRY], [OVOK], and [UVOK] bits are 1. Other bits are 0.

c. If page 2 is programmed, OTP_CUST2_STAT[LOADED], [PROGOK], [TRY], [OVOK], and [UVOK] bits are 1. Other bits

are 0.

6

Issue a digital reset to reload the registers with the updated OTP values:

a. CONTROL1[SOFT_RESET] = 1

During programming, if a programming voltage OV or UV event occurs, the OTP_CUST*_STAT[UVOK] or

OTP_CUST_STAT2[OVOK] bit is 0 to indicate the programming voltage under- or overvoltage condition is

detected during the programing attempts. In addition, the [UVERR], [OVERR], [SUVERR], and [SOVERR] bits in

the OTP_PROG_STAT register indicate if there is programming voltage error during programming and stability

test.

备注

• During the programming procedure, device performs a programming voltage stability test before

actually programming the OTP. If a programming voltage fails the stability test, the device will not

set the OTP_CUST*_STAT[TRY] bit, giving the customer another attempt to program the page

again.

• If the host incorrectly selects a page for programming, the OTP_PROG_STAT[PROGERR] bit is

set. This indicates that the selected page was not available to be programmed. Select the correct

page and retry the programming.

• Device will not start OTP programming above 55°C temperature.

• OTP programming time (from [PROG_GO] = 1 to [DONE] =1) for LDOIN capacitor of 0.1μF is

100ms.

9.3.6.4 Diagnostic Control/Status

The device complies with applicable component level requirements for ASIL-D on voltage measurement,

temperature measurement and communication. The following sub-sections describe the diagnostic control and

fault status that can be used as part of the safety mechanisms.

The Safety Manual for BQ7961x-Q1 and the BQ7961x-Q1 FMEDA documents are available separately from

Texas Instruments. Contact TI Sales Associate or Applications Engineer for further information.

9.3.6.4.1 Power Supplies Check

9.3.6.4.1.1 Power Supply Diagnostic Check

The internal power supply circuits have overvoltage, undervoltage, oscillation detection, and/or current limit

checks. All these detections are continuously running in the background when the device is in ACTIVE or SLEEP

mode. If a failure is detected, the corresponding flags in the FAULT_PWR* registers will be set or in certain

failure modes, the device will reset. 表 9-27 summarizes the diagnostics that apply for each power supply and

the corresponding action when failure is detected.

表9-27. Power Supply Diagnostic Checks

Supply/

Ground Pin

OV Check

UV Check

OSC Check

Current Limit

Pin Open

LDOIN

AVDD

If this fails, set

If this fails, disable

If fails, set

Limit current to EC

FAULT_PWR1[AVDD_ DVDD and trigger a

FAULT_PWR1[AVDD_ table current limit

OSC] specification

OV]

digital reset.

After soft reset, device

sets [AVDDUV_DRST]

to indicate a reset is

caused by AVDD UV.

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表9-27. Power Supply Diagnostic Checks (continued)

Supply/

Ground Pin

OV Check

UV Check

OSC Check

Current Limit

Pin Open

DVDD

CVDD

TSREF

If this fails, set

FAULT_PWR1[DVDD_ digital reset

OV]

If this fails, trigger a

Limit current to EC

table current limit

specification

If this fails, set

FAULT_PWR1[CVDD_ FAULT_PWR1[CVDD_

OV]

If this fails, set

Limit current to EC

table current limit

specification

UV]

If this fails, set

If fails, set

Limit current to EC

FAULT_PWR2[TSREF_ FAULT_PWR2[TSREF_ FAULT_PWR2[TSREF_ table current limit

OV] and FAULT_OT

and FAULT_UT

UV] and FAULT_OT

and FAULT_UT

OSC] and FAULT_OT

and FAULT_UT

specification

registers to all 1s.

NEG5V

REFHP/REFHM

DVSS

If this fails, set

FAULT_PWR2[NEG5V_

UV]

If REFHP fails, set

FAULT_PWR2[REFH_

OSC]

If REFHM opens, set

the FAULT_PWR1

[REFHM_OPEN]

If this opens, set the

FAULT_PWR1[DVSS_

OPEN]

CVSS

If this opens, set the

FAULT_PWR1[CVSS_

OPEN]

备注

Due to the detection logic implemented, when AVDD OV or UV is detected, the AVDD OSC fault can

also be triggered. Similarly, when TSREF OV or UV, the TSREF OSC fault can also be triggered.

9.3.6.4.1.2 Power Supply BIST

The device implements a power supply BIST (Built-In Self-Test) function to test the primary power supply failure

diagnostic paths that cover the following detections:

• FAULT_PWR1[AVDD_OV], [AVDD_OSC], [DVDD_OV], [CVDD_OV], [CVDD_UV], [REFHM_OPEN],

[DVSS_OPEN], and [CVSS_OPEN]

• FAULT_PWR2[TSREF_OV], [TSREF_UV], [TSREF_OSC], [NEG5V_UV], [REFHM_OSC],and

[PWRBIST_FAIL]

The power supply BIST is essentially a check on the checker and it is a command base function initiated by host.

The power supply BIST, once started, will force a fault on failure detection path on each supply. Take AVDD OV

diagnostic path as an example, when the BIST engine tests the AVDD OV path, the following occur:

1. The BIST engine forces a fail to the AVDD OV comparator

2. The BIST engine then checks to ensure the signal to trigger FAULT register is asserted, and the signal to

trigger NFAULT is also asserted

3. The BIST engine resets the FAULT register and NFAULT signal (that is, clears the FAULT_PWR1/2/3

registers and deasserts NFAULT)

4. The BIST engine repeats step 1 to step 3 on the next power supply diagnostic path check (for example,

AVDD OSC) until all intended diagnostic paths covered by BIST are tested.

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备注

• During the BIST run, the NFAULT pin will be toggled on and off. Host ignores the NFAULT pin

status or can disable the NFAULT pin output by setting DEV_CONF[NFAULT_EN] = 0.

• Among all internal power supplies, TSREF is one that can be enabled or disabled by host. To

ensure TSREF diagnostic paths are tested during BIST run, host enables TSREF before starting

the power supply BIST. Otherwise, the BIST engine will ignore the TSREF diagnostic paths test

result during the BIST run.

• Because other nonpower supply-related faults can also trigger NFAULT, it is recommended to

mask all nonpower supply-related faults through FAULT_MSK1/2 registers before the power supply

BIST run.

• Host also ensures there are no power supply faults before starting the power supply BIST run.

Start power supply BIST by sending DIAG_PWR_CTRL[PWR_BIST_GO] = 1. The BIST run will not abort even if

a failure is detected during the run. At the end of the BIST run, the result is indicated by the

FAULT_PWR2[PWRBIST_FAIL] flag.

The power supply BIST forces a failure and ensures the diagnostic path triggers the fault accordingly. A failure

on the BIST run indicates a diagnostic path is unable to trigger in a fault condition. To further examine which path

is unable to indicate a failure, host can set the DIAG_PWR_CTRL[BIST_NO_RST] = 1. This bit disables the

reset step during the BIST run. Re-start power supply BIST with this option enabled. At the end of the BIST run,

examine the FAULT_PWR1 and FAULT_PWR2 registers. Any register flag that remains 0 indicates it is unable to

flag a failure.

AVDD OV diagnostic path

CVDD OV

DVDD OV

AVDD OV

AVDD OV diagnostic

path

AVDD output

AVDD

FAULT_PWR

registers

Reset

OV comparator

Force a reference voltage

that will cause a fail

MUX

To

NFAULT

OR

GATE

REF

Control to select

reference voltage

Reset

GND

图9-46. Power Supply BIST

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9.3.6.4.2 Thermal Shutdown and Warning Check

9.3.6.4.2.1 Thermal Shutdown

Thermal shutdown occurs when the thermal shutdown sensor senses an overtemperature condition of the

device. The sensor operates without interaction and is separated from the ADC measured die sensor. The

thermal shutdown function has a register-status indicator flag (FAULT_SYS[TSHUT]) that is saved during the

shutdown event and can be read after the device is awaken back up. When a TSHUT fault occurs, the part

immediately enters the SHUTDOWN mode. Any pending transactions on UART or daisy chain are discarded.

There is no fault signaling performed when a thermal shutdown event occurs as the device immediately shuts

down.

To awaken the device, host ensures the ambient temperature is below T_{SHUT_FALL}and sends a WAKE ping to

the base device. Host will not attempt to wake the device if the ambient temperature is still above T_{SHUT_FALL}

.

Upon waking up, the FAULT_SYS[TSHUT] bit is set. See 节 9.4.1.1 for more details. If the system faults are

unmasked, FAULT_MSK1[MSK_SYS] = 0, the thermal shutdown will be reflected as a fault and will be indicated

in the FAULT_SUMMARY register and the assertion of the NFAULT pin.

9.3.6.4.2.2 Thermal Warning

To warn the host of an impending thermal overload the device includes an overtemperature warning that signals

a fault when the die temperature approaches thermal shutdown. The device detects the die temperature through

the TWARN sensor against the thermal warning threshold. There are four threshold options configured by the

PWR_TRANSIT_CONF[TWARN_THR1:0] setting.

When the system fault is unmasked, and the temperature warning fault occurs, the FAULT_SYS[TWARN] = 1.

Host can take action to avoid a thermal shutdown.

9.3.6.4.3 Oscillators Watchdog

The oscillators are monitored by watchdog circuits. There are two oscillators in the device, the HFO and the

LFO. If these oscillators are not functioning, the device does not operate. If the HFO or LFO does not transition

within the expected time, the watchdog circuits causes a digital reset.

When this unexpected reset occurs, it is recommended that the host sends a SHUTDOWN ping/tone to the

problem device and then send a WAKE ping to reset the daisy chain. If the oscillators are truly damaged, the

device will not restart and must be replaced.

In addition to the watchdog, the LFO frequency is monitored to ensure it stays within acceptable limits. If the LFO

frequency falls outside of the expected range, the FAULT_SYS_FAULT[LFO] bit is set.

9.3.6.4.4 OTP Error Check

9.3.6.4.4.1 OTP CRC Test and Faults

CRC Test:

The factory registers and customer OTP shadow registers are covered by a CRC check that constantly runs in

the background. The CUST_CRC_RSLT_HI and CUST_CRC_RSLT_LO registers hold the current device's

computed CRC value. This value is compared against the customer programmed value in the CRC registers,

CUST_CRC_HI and CUST_CRC_LO. When updating any customer OTP shadow register covered in the CRC,

the host must update a new CRC value to CUST_CRC_HI and CUST_CRC_LO registers. The CRC calculation

is performed in the same manner (including the bit stream ordering) and with the same polynomial as described

in 节 9.3.6.1.1.2.1.6. The CRC check and comparison for factory and customer spaces is performed periodically

and the DEV_STAT[CUST CRC_DONE] and [FACT_CRC_DONE] bits are set after the check is complete. If the

bit is already set, it remains set until cleared with a read.

CRC Faults:

When CUST_CRC_HI/LO and CUST_CRC_RSLT_HI/LO do not match, the FAULT_OTP[CUST_CRC] flag is set

until the condition is corrected. Continuous monitoring of the factory NVM space occurs in a similar fashion,

concurrently with the monitoring of the customer space. When a factory register change is detected, the

FAULT_OTP[FACT_CRC] flag is set. When this fault occurs, the host should reset the fault flag to see if the fault

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persists. If the fault persists, the host must perform a reset of the part. If reset does not correct the issue, the

device is corrupted and must not be used.

9.3.6.4.4.2 OTP Margin Read

The device provides OTP margin read test modes, with which host can set up to reload the OTP with margin 1 or

margin 0. To start the margin read test, host selects the desired test mode through

DIAG_OTP_CTRL[MARGIN_MODE2:0] and sets DIAG_OTP_CTRL[MARGIN_GO] = 1. The device will reload

the OTP per the [MARGIN_MODE2:0] setting. Any OTP related error will be flagged to the FAULT_OTP register.

9.3.6.4.4.3 Error Check and Correct (ECC) OTP

ECC:

Register values for selected registers (0x0000 to 0x002F) are permanently stored in OTP. All registers also exist

as volatile storage locations at the same addresses, referred to as shadow registers. The volatile registers are

for reading, writing, and device control. For a list of registers included in the OTP, see 节9.5.1.

During wakeup, the device first loads all shadow registers with hardware default values listed in 节 9.5.1. Then

the device loads the registers conditionally with OTP contents from the results of the Error Check and Correct

(ECC) evaluation of the OTP. The OTP is loaded to shadow registers in 64-bit blocks; each block has its own

Error Check and Correct (ECC) value stored. The ECC detects a single-bit (Single-Error-Correction) or double-

bit (Double-Error-Detection) changes in OTP stored data. The ECC is calculated for each block, individually.

Single-bit errors are corrected, double-bit errors are only detected, not corrected. A block with good ECC is

loaded. A block with a single-bit error is corrected, and the FAULT_OTP[SEC_DET] bit is set to flag the

corrected error event. Additionally, the DEBUG_OTP_SEC_BLK register is updated with the location of the error

corrected block. This enables the host to keep track of potentially damaged memory. The block is loaded to

shadow registers after the single-bit error correction. Because the evaluation is on a block-by-block basis, it is

possible for multiple blocks to have a single-correctable error and still be loaded correctly. Multiple-bit errors can

exist with full correction, as long as they are limited to a single error per block.

A block with a bad ECC comparison (two-bit errors in one block) is not loaded and the FAULT_OTP[DED_DET]

bit is set to flag the failed bit-error event. Additionally, the DEBUG_OTP_DED_BLK register is updated with the

block where the double error occurred. The hardware default value remains in the register. This allows some

blocks to be loaded correctly (no fail or single-bit corrected value) and some blocks not to load. When the

FAULT_OTP[SEC_DET] or FAULT_OTP[DED_DET] bit is set and the condition is not cleared by a device reset,

the device is corrupted and must not be used.

The ECC engine uses the industry standard 72,64 SEC DEC ECC implementation. The OTP is protected by a

(72, 64) Hamming code, providing single error correction, double error detection (SECDED). For each 64 bits of

data stored in OTP, an additional 8 bits of parity information are stored. The parity bits are designated p0, p1, p2,

p4, p8, p16, p32, and p64. Bit p0 covers the entire encoded 72-bit ECC block. The remaining seven parity bits

are assigned according to the following rule:

• Parity bit p1 covers odd bit positions, that is, bit positions which have the least significant bit of the bit position

equal to 1 (1, 3, 5, and so on), including the p1 bit itself (bit 1).

• Parity bit p2 covers bit positions which have the second least significant bit of the bit position equal to 1 (2, 3,

6, 7, 10, 11, and so on), including the p2 bit itself (bit 2).

• The pattern continues for p4, p8, p16, p32, and p64. 表9-28 specifies the complete encoding.

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表9-28. (72, 64) Parity Encoding

Bit Position

Encoded Bits

Parity Bit p0

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

d63 d62 d61 d60 d59 d58 d57 p64 d56 d55 d54 d53 d52 d51 d50 d49 d48 d47

x

Coverage

p1

p2

x

p4

p8

x

p16

x

p32

p64

x

Bit Position

Encoded Bits

Parity Bit p0

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

d46 d45 d44 d43 d42 d41 d40 d39 d38 d37 d36 d35 d34 d33 d32 d31 d30 d29

x

Coverage

p1

p2

x

p4

p8

x

p16

x

p32

x

p64

Bit Position

Encoded Bits

Parity Bit p0

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

d28 d27 d26 p32 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12

x

Coverage

p1

p2

x

p4

p8

x

p16

x

p32

x

p64

Bit Position

Encoded Bits

Parity Bit p0

17

16

15

14

d9

x

13

d8

x

12

d7

x

11

d6

x

10

d5

x

9

d4

x

8

p8

x

7

d36

x

6

d2

x

5

d1

x

4

p4

x

3

d0

x

2

p2

x

1

p1

x

0

p0

x

d11 p16 d10

x

Coverage

p1

x

p2

p4

x

p8

x

p16

p32

p64

x

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表9-29. Encoder and Decoder Data IN and OUT Positioning

ENCODER

DATA IN

Encoded Bits

d0 to d7

DATA OUT

Bit Positions

OTP_ECC_DATAIN 1

OTP_ECC_DATAIN 2

OTP_ECC_DATAIN 3

OTP_ECC_DATAIN 4

OTP_ECC_DATAIN 5

OTP_ECC_DATAIN 6

OTP_ECC_DATAIN 7

OTP_ECC_DATAIN 8

OTP_ECC_DATAOUT 1

OTP_ECC_ DATAOUT 2

OTP_ECC_ DATAOUT 3

OTP_ECC_ DATAOUT 4

OTP_ECC_ DATAOUT 5

OTP_ECC_ DATAOUT 6

OTP_ECC_ DATAOUT 7

OTP_ECC_ DATAOUT 8

OTP_ECC_ DATAOUT 9

0 to 7

d8 to d15

8 to 15

d16 to d23

d24 to d31

d32 to d39

d40 to d47

d48 to d55

d56 to d63

16 to 23

24 to 31

32 to 39

40 to 47

48 to 55

56 to 63

64 to 71

DECODER

DATA IN

Bit Positions

0 to 7

DATA IN

Encoded Bits

d0 to d7

OTP_ECC_DATAIN 1

OTP_ECC_DATAIN 2

OTP_ECC_DATAIN 3

OTP_ECC_DATAIN 4

OTP_ECC_DATAIN 5

OTP_ECC_DATAIN 6

OTP_ECC_DATAIN 7

OTP_ECC_DATAIN 8

OTP_ECC_DATAIN 9

OTP_ECC_DATAOUT 1

OTP_ECC_ DATAOUT 2

OTP_ECC_ DATAOUT 3

OTP_ECC_ DATAOUT 4

OTP_ECC_ DATAOUT 5

OTP_ECC_ DATAOUT 6

OTP_ECC_ DATAOUT 7

OTP_ECC_ DATAOUT 8

8 to 15

d8 to d15

16 to 23

24 to 31

32 to 39

40 to 47

48 to 55

56 to 63

64 to 71

d16 to d23

d24 to d31

d32 to d39

d40 to d47

d48 to d55

d56 to d63

ECC Diagnostic Test: The device provides a diagnostic tool to test the ECC function. There are two modes that

are available to run the diagnostic. The first, auto mode (OTP_ECC_TEST[MANUAL_AUTO] = 0), uses internal

data to run the tests. In auto mode, the OTP_ECC_TEST[DED_SEC] bit selects the type of test that is to be

performed and the OTP_ECC_TEST[ENC_DEC] bit determines if the encoder or decoder function is to be

tested. The result of the ECC test is provided in the OTP_ECC_DATAOUT* registers within 1μs delay. The test

steps and expected results from each test are shown below.

Automatic Decoding steps:

1. Set ECC Test to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0

2. Set decoder setting OTP_ECC_TEST[ENC_DEC] = 0

3. Set decoder to single or double encoding setting with OTP_ECC_TEST[DED_SEC] (1 for DED or 0 for SEC)

4. Clear all SEC/DED faults by FAULT_RST2[RST_OTP_DATA] = 1

5. Enable ECC test OTP_ECC_TEST[ENABLE] = 1

6. Read FAULT_OTP[SEC_DET] flag for SEC or FAULT_OTP[DED_DET] flag for DED

7. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT8 to verify the decoder test results as in 表9-30

8. Disable ECC test OTP_ECC_TEST[ENABLE] = 0

Automatic Encoding steps:

1. Set ECC TEST to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0

2. Set the encoder setting using OTP_ECC_TEST[ENC_DEC] = 1

3. Enable the ECC test with OTP_ECC_TEST[ENABLE] = 1

4. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT9 to verify the encoder test results as in 表9-30

5. Disable ECC test OTP_ECC_TEST[ENABLE] = 0

表9-30. Decoder and Encoder Test Verification

[DED_SEC]

0 (SEC test)

[ENC_DEC]

0 (Decoder test)

1 (Encoder test)

[SEC_DET]

[DED_DET]

OTP_DATAOUT*

1

0

0x18C3 FF8A 68A9 8069

N/A

0xCD 3968 C140 2EA5 ED6D

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表9-30. Decoder and Encoder Test Verification (continued)

[DED_SEC]

1 (DED test)

[ENC_DEC]

0 (Decoder test)

1 (Encoder test)

[SEC_DET]

[DED_DET]

OTP_DATAOUT*

0x0000 0000 0000 0000

0xCD 3968 C140 2EA5 ED6D

0

1

N/A

9.3.6.4.5 Integrated Hardware Protector Check

9.3.6.4.5.1 Parity Check

When the OVUV and OTUT protectors are enabled, the register settings related to the OVUV and OTUT

configurations are latched to protector blocks. The device will check periodically in the background to ensure the

latched configurations remain the same throughout the protector operation.

The parity check covers the following latched setting. If a parity fault in the OVUV protector is detected, the

device will set the FAULT_PROT1[VPARITY_FAIL] = 1. If a parity fault in the OTUT protector is detected, the

device will set the FAULT_PROT1[TPARITY_FAIL] = 1.

表9-31. Protector Parity Check Settings

OVUV Protector

OV threshold, UV threshold

OVUV_MODE setting

NUM_CELL setting

OTUT Protector

OT threshold, UT threshold

OTUT_MODE setting

Note

Ensure threshold settings remains the same during the operation

Ensure the protector doesn’t switch to a different operation mode

GPIO_CONF1 to GPIO_CONF4 Ensure the active channel (either cell channels for OVUV or GPIO

settings channel for OTUT) remains the same during operation

9.3.6.4.5.2 OVUV and OTUT DAC Check

The OV, UV, OT, and UT DAC values are multiplexed to the AUX ADC from which the host can read out the

values as part of the diagnostic check on the protector threshold settings.

To measure the protector’s DAC value, it is recommended to lock the OVUV or OTUT protectors to a single

channel through OVUV_CTRL[OVUV_LOCK3:0] for OV and UV DAC measurement; and through

OTUT_CTRL[OTUT_LOCK2:0] for OT and UT DAC measurement, and restart the OVUV protectors or OTUT

protector to run in the single channel run mode. Host ensures the locked cell channel is not under OV or UV fault

or the locked GPIO channel is not under OT or UT fault. Otherwise, the DAC measurement will not be reflecting

the triggering threshold value. Note that the OV and UV DAC value is (0.8 x the threshold setting).

9.3.6.4.5.3 OVUV Protector BIST

The device implemented an OVUV BIST (Built-In-Self-Test) function to test the primary OVUV protector path.

Host can start the BIST run by setting [OVUV_MODE1:0] = 0b10 and [OVUV_GO] = 1. The BIST run covers:

1. OV and UV comparators thresholds:

a. A higher and lower than the set threshold are checked to ensure the comparator is triggered correctly.

b. If failure is detected, the corresponding FAULT_PROT2[OVCOMP_FAIL] or [UVCOMP_FAIL] bit will be

set.

2. The path from the OVUV MUX to UV fault status bit and NFAULT pin:

a. For each VC channel, a switch is open so that input to the OVUV MUX is open and will lead to a UV

detection to the channel under test

b. The BIST engine then checks the logic to assert corresponding FAULT_UV register bit and the NFAULT

is set properly.

c. The BIST engine resets the corresponding FAULT_UV bit and deasserts the NFAULT, then switches to

test the next channel and repeats the process until all active channels are tested.

d. If failure is detected, the corresponding [VPATH_FAIL] bit is set.

3. OV fault bit and NFAULT path

a. The BIST engine forces 1 to the FAULT_OV* register, one bit at time, to ensure each FAULT_OV*

register bit can be set and the NFAULT can be asserted, accordingly.

b. If failure is detected, the corresponding [VPATH_FAIL] bit will be set.

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If NFAULT is enabled, host observes NFAULT toggling during the BIST run. Upon completion of the BIST run,

the OVUV comparators will be turned off. Host starts the regular OVUV round robin mode by sending

[OVUV_GO] = 1 with [OVUV_MODE1:0] = 0b01 (round robin mode).

备注

• If a [OVUV_GO] = 1 is sent during the OVUV BIST run, device will execute the new GO command

based on the [OVUV_MODE1:0] setting.

• Before starting the OVUV Protector BIST, host masks out all the non-OVUV related faults, and

ensures there are no OV and UV faults on any cell channels (recommended all cell voltages to be

at least 100 mV apart from the OV or UV threshold during the BIST run). Otherwise, the BIST

result is not invalid.

• After BIST starts, if pre-existing fault is detected before starting step 2, the BIST engine will be

aborted and the FAULT_PROT2[BIST_ABORT] = 1.

• A no reset option, DIAG_PROT_CTRL[PROT_BIST_NO_RST] = 1, is available to command the

BIST engine not to reset the fault status and NFAULT pin after testing each channel. If a BIST run

fails, host can select this option and re-run BIST to detect which cell channel path is unable reflect

a fault condition in the fault registers.

9.3.6.4.5.4 OTUT Protector BIST

The device implemented an OTUT BIST function to test the primary OTUT protector path. Host can start the

BIST run by setting [OTUT_MODE1:0] = 0b10 and [OTUT_GO] = 1. The BIST run covers:

1. OT and UT comparator thresholds

a. A higher and lower than the set threshold are checked to ensure the comparator is triggering correctly.

b. If failure is detected, the corresponding FAULT_PROT2[OTCOMP_FAIL] or [UTCOMP_FAIL] bit will be

set.

2. The path from GPIO MUX to UT fault bit and NFAULT path

a. For each GPIO channel, the GPIO is internally pulled up so the input to the OTUT MUX is high and will

lead to a UT detection to the channel under test.

b. The BIST cycle then checks the logic to assert the corresponding FAULT_UT register bit and the

NFAULT is set properly.

c. The BIST engine resets the corresponding FAULT_UT bit and deasserts the NFAULT, then switches to

test the next channel.

d. If failure is detected, the corresponding [TPATH_FAIL] bit will be set.

3. OV fault bit and NFAULT path

a. The BIST engine forces 1 to the FAULT_OT register, one bit at time, to ensure each FAULT_OT register

bit can be set and the NFAULT can be asserted, accordingly.

b. If failure is detected, the corresponding [TPATH_FAIL] bit will be set.

If NFAULT is enabled, host observes NFAULT toggling during the BIST run. Upon completion of the BIST run,

the OTUT comparators will be turned off. Host starts the regular OTUT round robin mode by sending

[OTUT_GO] = 1 with [OTUT_MODE1:0] = 0b01 (round robin mode).

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备注

• If a [OTUT_GO] = 1 is sent during the OTUT BIST run, device will execute the new GO command

based on the [OVUV_MODE1:0] setting.

• Before starting the OTUT Protector BIST, host masks out all non-OTUT related faults, and ensures

there are no OT and UT faults on any GPIO during the BIST run). Otherwise, the BIST result is not

invalid.

• After BIST starts, if pre-existing fault is detected before starting step 2, the BIST engine will be

aborted and the FAULT_PROT2[BIST_ABORT] = 1.

• A no reset option, DIAG_PROT_CTRL[PROT_BIST_NO_RST] = 1, is available to command the

BIST engine not to reset the fault status and NFAULT pin after testing each channel. If a BIST run

fails, host can select this option and re-run BIST to detect which GPIO channel path is unable

reflect a fault condition in the fault registers.

9.3.6.4.6 Diagnostic Through ADC Comparison

9.3.6.4.6.1 Cell Voltage Measurement Check

Cell voltage measurement path comparison:

The cell voltage measurement check is performed by comparing the prefiltered measurement result from Main

ADC versus measurement result from AUX ADC. To read the compared value measured by Main ADC and AUX

ADC, MCU has to set up this diagnostic check to lock on a single channel using [AUX_CELL_SEL] setting and

the start this diagnostic check. In this configuration, the compared values from Main ADC and AUX ADC are

reported to DIAG_MAIN_HI/LO registers and DIAG_AUX_HI/LO registers respectively.

Both Main and AUX ADC has the same front end filters. This diagnostic time is mostly spend on waiting for the

AAF on the AUX ADC path to settle. The [AUX_SETTLE] setting allows the MCU to make trade-off between

diagnostic time and noise filter level. Additionally, when AUX ADC starts, by default, AUXCELL slot always align

to the Main ADC Cell1 slot. The [AUX_CELL_ALIGN] setting allows MCU to change this alignment to Main ADC

Cell8 slot, resulting with less sampling time delta between Main and AUX ADC on the higher channels.

Main ADC Path

Latest VCELL

Unfiltered value

Filters

(BCI &

AAF),

LS

SAR

ADC

De-

MUX

Digital

LPF

To VCELL

registers

MUX

To FAULT_COMP_VCCB

register

Comp

CB Filters

+

AUXCELL value

BCI &

AAF filters

SAR

ADC

De-

MUX

Comparison threshold set by

DIAG_COMP_CTRL1[VCCB_THR4:0]

To AUXCELL register

If single channel lock is

enabled

AUX ADC Path

图9-47. Cell Voltage Measurement Diagnostic

Before starting the cell voltage measurement comparison, host ensures:

• The desired AUXCELL channels to be tested are configured in the ADC_CTRL2[AUX_CELL_SEL4:0] setting

and AUX ADC is enabled and in continuous mode.

• Allow AUX ADC to run through all AUXCELL channels for the device to compensate for common mode error

before starting this diagnostic check.

• Main ADC must be enabled and is in continuous mode.

• Select the (VCELL –AUXCELL) comparison threshold through DIAG_COMP_CTRL1[VCCB_THR4:0]

setting.

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• Select the desired settling time for the AUX CELL channel through ADC_CONF1[AUX_SETTLE1:0].

To start the cell voltage measurement comparison:

1. Set DIAG_COMP_CTRL3[COMP_ADC_SEL2:0] = cell voltage measurement check (that is, 0b001) and set

[COMP_ADC_GO] = 1.

2. For each channel enabled by [AUX_CELL_SEL4:0], the device will compare abs[(VCELL –AUXCELL)] <

[VCCB_THR4:0].

3. Wait for the comparison to be accomplished, roughly [(number of channel) * (AUXCELL settling time + one

round robin cycle time)].

4. The cell voltage measurement comparison is completed when ADC_STAT2[DRDY_VCCB] = 1.

Host checks the FAULT_COMP_VCCB1 and FAULT_COMP_VCCB2 registers for the comparison result.

ADC comparison abort conditions:

The device will not start the cell voltage measurement comparison under the invalid conditions listed below.

When the comparison is aborted, the FAULT_COMP_MISC[COMP_ADC_ABORT] = 1, [DRDY_AUX_CEL] = 1,

[DRDY_VCCB] = 1, and FAULT_COMP_VCCB1/2 registers = 0xFF. If [AUX_CELL_SEL4:0] is set to locked at a

single channel, the AUX_CELL_HI/LO registers will be reset to default value 0x8000 if the comparison run is

aborted.

Invalid conditions or settings which will prevent the start of the cell voltage measurement comparison:

• Invalid [AUX_CELL_SEL] setting: results in no AUX ADC measurement on the selected channel. The

AUX_CELL_HI/LO registers are kept in default value.

• Channel higher than the NUM_CELL configuration is selected.

• Invalid BBVC_POSN setting:

– Adjacent channels are enabled in the BBVC_POSN1/2 registers.

– BBVC_POSN2[CELL1] is enabled.

– More than two channels are selected in BBVC_POSN1/2.

– [AUX_CELL_SEL] is locked to any of the selected channels in BBVC_POSN1/2.

• Main or AUX ADCs are off or not set in continuous mode.

Post-ADC digital LPF check:

The digital LPF is checked continuous whenever the Main ADC is running. A duplicate diagnostic LPF is

implemented to check against each LPF for each VC channel and the BBP/N channel. The check is performed

with one LPF at a time.

Example, to test LPF1 for cell channel 1, the input (that is, ADC measurement result from cell 1) is fed to the

LPF1 and the diagnostic LPF for a period of time. The output of the LPF1 and the diagnostic LPF are compared

against each other. Several outputs from LPF1 and diagnostic LPF will be compared to ensure the operation of

the LFP1 before moving to check the next LFP. If any of the LPFs fail the diagnostic check,

FAULT_COMP_MISC[LPF_FAIL] = 1.

When the LPF for each active cell channels is tested once, ADC_STAT2[DRDY_LPF] = 1. This diagnostic check

of the LPFs will continuously run in the background as long as the Main ADC is running.

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Main ADC

Conversion

VCell 1

LPF BB

VCell 16

Busbar

LPF 16

LPF BB

MUX

Pass/Fail

BIST

Compare

Indicates with

[LPF_FAIL] bit

DIAG

LFP

MUX

Inject Fault to check

DIAG LFP by setting

[LPF_FAULT_INJ] = 1

Main ADC

Conversion

VCell 1

LPF 1

VCell 16

Current

LPF 16

LPF CS

MUX

Pass/Fail

BIST

Compare

Indicates with

[LPF_FAIL] bit

DIAG

LFP

MUX

Inject Fault to check

DIAG LFP by setting

[LPF_FAULT_INJ] = 1

图9-48. Post-ADC LPF Diagnostic (Blue Path as Example of Checking LPF1)

Furthermore, the device also implements a check to verify the functionality of the diagnostic LPF itself. By setting

DIAG_COMP_CTRL4[LPF_FAULT_INJ] = 1 and restarting the Main ADC, the device will inject a fault into the

diagnostic LPF, forcing a failure during the LPF diagnostic check which then sets the [LPF_FAIL] = 1. When the

test is completed, simply set the [LPF_FAULT_INJ] = 0.

9.3.6.4.6.2 Temperature Measurement Check

Similar to the cell voltage measurement check, the device checks the thermistor temperature measurement by

comparing the Main ADC measurement to the AUX ADC measurement. To read the compared value measured

by Main ADC and AUX ADC, MCU has lock on a single channel using [AUX_GPIO_SEL] setting and the start

this diagnostic check. In this configuration, the compared values from Main ADC and AUX ADC are reported to

DIAG_MAIN_HI/LO registers and DIAG_AUX_HI/LO registers respectively.

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Main ADC Path

GPIO Measurement

GPIO1

GPIO

MUX

SAR

ADC

De-

MUX

To GPIO

Measurement

registers

GPIO8

To FAULT_COMP_GPIO

register

Comp

GPIO Measurement

GPIO

MUX

SAR

ADC

De-

MUX

Comparison threshold set by

DIAG_COMP_CTRL2[GPIO_THR2:0]

To AUX_GPIO

Registers if a single

GPIO is locked

AUX ADC Path

图9-49. Thermistor Temperature (GPIO) Measurement Diagnostic

Before starting the temperature measurement comparison, host ensures:

• Main ADC must be enabled and is in continuous mode.

• The desired GPIO channels to be tested are configured in the ADC_CTRL3[AUX_GPIO_SEL3:0] setting and

AUX ADC is enabled and in continuous mode.

• Select the comparison threshold through DIAG_COMP_CTRL2[GPIO_THR2:0] setting.

To start the cell voltage measurement comparison:

1. Set DIAG_COMP_CTRL3[COMP_ADC_SEL2:0] = GPIO measurement check (that is, 0b101) and set

[COMP_ADC_GO] = 1.

2. For each channel enabled by [AUX_GPIO_SEL4:0], the device will compare abs[(GPIO from Main –GPIO

from AUX)] < [GPIO_THR2:0].

3. Wait for the comparison to be accomplished which can take up to 64 ADC round robin times.

4. The GPIO measurement comparison is completed when ADC_STAT2[DRDY_GPIO] = 1.

Host checks the FAULT_COMP_GPIO register for the comparison result.

ADC comparison abort conditions:

The device will not start the temperature measurement comparison under the invalid conditions listed below.

When the comparison is aborted, the FAULT_COMP_MISC[COMP_ADC_ABORT] = 1, [DRDY_GPIO] = 1, and

FAULT_COMP_GPIO = 0xFF. If [AUX_GPIO_SEL3:0] is set to locked at a single channel, the AUX_GPIO_HI/LO

registers will be reset to default value 0x8000 if the comparison run is aborted.

Invalid conditions or settings which will prevent the start of the temperature measurement comparison:

• Invalid [AUX_GPIO_SEL] setting which the selected GPIO isn’t configured for ADC measurement. The

AUX_GPIO_HI/LO registers are kept in default value. This also applies to the case if [AUX_GPIO_SEL] is

selected for all GPIOs but none of the GPIOs are configured for ADC measurement.

• Main or AUX ADCs are off or not set in continuous mode.

9.3.6.4.6.3 Cell Balancing FETs Check

The cell balancing FET check is performed by turning on the balancing FET and comparing the voltage across

the FET (through the AUX ADC path) versus the cell voltage (through the Main ADC path). To read the

AUXCELL measurement used for the check, MCU has to set up this diagnostic check to lock on a single channel

using [AUX_CELL_SEL] setting and the start this diagnostic check. The AUXCELL compared value will be

reported to DIAG_AUX_HI/LO registers.

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Device

VCELL, cell voltage

measured by Main ADC from

VC pin

R_VC

V_Cn

R_CB

CB_n

To FAULT_COMP_CBFET*

registers

comp

+

Comparison threshold is fixed to

AUXCELL < ½ of VCELL

Q_CBn

R_VC

VC_n-1

CB_n-1

AUXCELL, cell voltage measured by

AUX ADC from CB pin

R_CB

图9-50. Cell Balancing FET Diagnostic

Before starting the cell balancing FET comparison, host ensures:

• Main ADC is running in continuous mode.

• Configured in the ADC_CTRL2[AUX_CELL_SEL4:0] to select the AUXCELL channels which the CB FETs

are tested.

• Select the desired settling time for the AUX CELL channel through ADC_CONF1[AUX_SETTLE1:0].

• Pause CB if balancing is running.

• Configured which CBFET to be tested through DIAG_CBFET_CTRL1 and DIAG_CBFET_CTRL2 registers.

– The rules of maximum of eight CBFETs to be on and turn on no more than two consecutive CBFETs still

apply.

– Recommended to test in odd and even manner.

To start the CBFET comparison:

1. Start AUX ADC in continuous mode.

2. Turn on the selected CBFET by setting DIAG_COMP_CTRL3[CBFET_CTRL_GO] = 1 and wait for

appropriate dv/dt time.

3. Set DIAG_COMP_CTRL3[COMP_ADC_SEL2:0] = CBFET check (that is, 0b100) and set [COMP_ADC_GO]

= 1.

4. The device turns on the CBFET configured in the above step and compares the AUXCELL measurement

(through CB channel) < half of the VCELL measurement (through VC channel). Only the CBFETs that are

enabled are checked.

5. The CBFET comparison is completed when ADC_STAT2[DRDY_CBFET] = 1.

6. Repeat this procedure for other set of CBFET test. To turn off the CBFET enabled for this test, MCU clear

the DIAG_CBFET1 and DIAG_CBFET2 registers then set the [CBFET_CTRL_GO] = 1. Otherwise, exiting

from the CB pause state by sending [CB_PAUSE] = 0 will resume the regular balancing which turns off the

CBFETs enabled for this test and resume on the CBFETs that are set for balancing.

Host checks the FAULT_COMP_CBFET1 and FAULT_COMP_CBFET2 registers for the comparison result.

Repeat the steps to compare the remaining CBFETs.

ADC comparison abort conditions:

The device will not start the CBFET comparison under the invalid conditions listed below. When the comparison

is aborted, the FAULT_COMP_MISC[COMP_ADC_ABORT] = 1, [DRDY_AUX_CEL] = 1, [DRDY_CBFET] = 1,

and FAULT_COMP_CBFET1/2 = 0xFF. If [AUX_CELL_SEL4:0] is set to locked at a single channel, the

AUX_CELL_HI/LO registers will be reset to default value 0x8000 if the comparison run is aborted.

Invalid conditions or settings which will prevent the start of the cell voltage measurement comparison:

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• Invalid [AUX_CELL_SEL] setting which results in no AUX ADC measurement on the selected channel. The

AUX_CELL_HI/LO registers are kept in default value.

• Channel higher than the NUM_CELL configuration is selected.

• Invalid BBVC_POSN setting:

– Adjacent channels are enabled in the BBVC_POSN1/2 registers.

– BBVC_POSN2[CELL1] is enabled.

– More than two channels are selected in BBVC_POSN1/2.

– [AUX_CELL_SEL] is locked to any of the selected channels in BBVC_POSN1/2.

• Main or AUX ADCs are off or not set in continuous mode.

• CB is running and it is not in pause mode.

• More than eight CBFETs are enabled, or more than two consecutive CBFETs are enabled in

DIAG_CBFET_CTRL1/2 registers.

9.3.6.4.6.4 VC and CB Open Wire Check

The device can detect an open wire connection on the VC and CB pins. A current sink is connected to each VC

and CB pin, except VC0 and CB0 pins which are connected with a current source.

When the current sink (or current source) is enabled and if there is an open wire connection, the external

differential capacitor will be depleted and the cell voltage measurement will drop to an abnormal level over time.

Similar detection concept applies to the VC0 and CB0 pins with a current source. If there is an open wire

connection, the VC0 or CB0 will be pulled up by the current source, resulting in a reduced cell voltage

measurement over time.

When the diagnostic comparison is enabled, the device will compare the cell voltage measurement from Main

ADC (for VC pins open wire detection) against a host-programmed threshold; or comparing the AUX CELL

measurement from the AUX ADC (for CB pins open wire detection) against a host-programmed threshold.

If MCU lock to a single CB channel though [AUX_CELL_SEL] before starting the CB open wire check. The

device will report the AUXCELL measurement used for the check comparison. The value is reported in

DIAG_AUX_HI/LO registers. Since there is no single channel lock mechanism in Main ADC, VC channel

measurement used for VC open wire will not be reported in DIAG_MAIN_HI/LO registers.

Device

R_VC

VC_n

OW current

sink

Cell to pcb wire

VCELL, cell voltage

measured by Main ADC

from VC pin

+

To FAULT_COMP_VCOW*

registers

Comp

C_VC

VC_n-1

R_VC

Comparison threshold set by

DIAG_COMP_CTRL2[OW_THR3:0]

OW current

sink

图9-51. Open Wire Detection

Before starting the open wire comparison, host ensures:

• For VC open wire detection, Main ADC is running in continuous mode.

• For CB open wire detection, AUX ADC is running in continuous mode

– Configured in the ADC_CTRL2[AUX_CELL_SEL4:0] to select the AUXCELL channels

– Select the desired settling time for the AUX CELL channel through ADC_CONF1[AUX_SETTLE1:0].

96

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• Configure the open wire detection threshold through DIAG_COMP_CTRL2[OW_THR3:0].

To start the open wire comparison:

1. Turn on the VC pins (or CB pins) current sink or source through DIAG_COMP_CTRL3[OW_SNK1:0].

2. Wait for dV/dt time of the external capacitor to deplete to the detection threshold if there is an open wire

fault.

3. For VC open wire detection, select DIAG_COMP_CTRL3[COMP_ADC_SEL2:0] = OW VC check (that is,

0b010) and set [COMP_ADC_GO] = 1. Or for CB open wire detection, [COMP_ADC_SEL2:0] = OW CB

check (that is, 0b011).

4. The device compares all active VCELL measurement (for VC open wire) or AUX CELL measurement (for CB

open wire) against the [OW_THR3:0] threshold setting.

5. When the comparison is completed, ADC_STAT2[DRDY_VCOW] = 1 for VC open wire (or [DRDY_CBOW] =

1 for CB open wire).

6. Host then turns off all current sinks and sources through DIAG_COMP_CTRL3[OW_SNK1:0].

Host checks the FAULT_COMP_VCOW1/2 or FAULT_COMP_CBOW1/2 registers for the comparison result.

9.3.7 Bus Bar Support

The device supports bus bar measurement in two types of connections:

• Bus bar connected to a dedicated bus bar channel through BBP and BBN pins

• Bus bar connected to a VC channel

A total of three bus bars can be connected to a single device, one through BBP/N pins and two through VC

channels. 表 9-32 shows the difference between the two connection methods. Details are described in the later

subsections.

表9-32. Bus Bar Connection Methods

Supporting Feature/

Bus Bar Connected Across BBP/BBN Pins

Bus Bar Connected Individually Across VC Pins

Limitation

Number of bus bar can be

connected per device

1

2

Connection channel

Can be connected to any channel but the bottom

one

Can be connected to any channel but the bottom

one

Bus bar measurement

Yes, result is output to BUSBAR_HI/LO registers

Yes, result is output to VCELLx_HI/LO registers,

where x is the VC channel the bus bar is connected

to

Integrated filters to bus bar

measurement

Yes, same front end filters as the regular cell

channels and post ADC digital LPF. BBP/N channel channels and post ADC digital LPF. Use the same

Yes, same front end filters as the regular cell

is x5 gain with ±1-V input range. Dedicated digital

LPF setting separated from the LPF setting used for

cell voltage measurements.

cell voltage LPF setting for bus bar measurement.

Host requires to adjust cell

measurement adjustment

Yes, a cell + bus bar are sharing a single VC

channel using this method. Host needs to separate channels and measurements are reported

No, cell and bus bar are connected to their own VC

out the bus bar measurement to obtain the actual

cell measurement on the shared channel.

separately

Cell balancing limitation

No CB limitation, but host turns on adjacent CBFETs No CB limitation but require to float the upper CB pin

when balancing a cell above the bus bar connected on the bus bar connected channel

channel

The device supports bus bar measurement in a connection when a bus bar is connected to a VC channel. A total

of two bus bars can be connected to a single device through the VC channels. 表 9-33 shows the details as

described in the later subsections.

表9-33. Bus Bar Connection Methods

Supporting Feature/ Limitation

Number of bus bar can be connected per device

Connection channel

Bus Bar Connected Individually Across VC Pins

2

Can be connected to any channel but the bottom one

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表9-33. Bus Bar Connection Methods (continued)

Supporting Feature/ Limitation

Bus Bar Connected Individually Across VC Pins

Bus bar measurement

Yes, result is output to VCELLx_HI/LO registers, where x is the VC channel the bus

bar is connected to

Integrated filters to bus bar measurement

Yes, same front end filters as the regular cell channels and post ADC digital LPF. Use

the same cell voltage LPF setting for bus bar measurement.

Host requires to adjust cell measurement

adjustment

No, cell and bus bar are connected to their own VC channels and measurements are

reported separately

Cell balancing limitation

No CB limitation but require to float the upper CB pin on the bus bar connected

channel

9.3.7.1 Bus Bar on BBP/BBN Pins

The device provides an dedicated bus bar channel through BBP/BBN pins for bus bar connection and

measurement. It is a floating channel allowing bus bar to be connected to any cell except the bottom cell of a

module. Using the bus bar channel maximizes the use of cell channels in the device across different module

sizes.

9.3.7.1.1 Typical Connection

With bus bar connected to BBP/BBN pins, it is intended to allow a single cell channel (VC channel) to be shared

with a cell + a bus bar (see 图 9-52 (a) connection). Usually, such connection introduced additional IR error to

the cell measurement to the system. The dedicated bus bar channel through BBP/BBN pins supported in the

device allows the host to measure the bus bar voltage to obtain the actual cell measurement.

图 9-52 (a) connection applies to bus bar connecting to any middle VC channel. That is, in a single device, there

is a cell connected above and below the BBP/BBN channel. To support hotplug on the bus bar channel, the

device only requires a 400-Ω filter resistor each on the BBP/N pins and a 0.47-µF/16-V differential capacitor

across the BBP/N pins.

If the bus bar connected to BBP/N is placed at the top of a module (see 图9-52 (b) connection), such connection

is the exception in the BBP/N case that a cell channel is not being shared. In this connection, actual cell

measurements are made through the VC channels and host does not require additional calculations.

图 9-52 (b) connection applies to bus bar connected to top of the module, where in a single device, no cell is

connected above the bus bar. To support hotplug on the bus bar channel, besides the 400-Ω filter resistor each

on BBP/N pins and a 0.47-µF/16-V differential capacitor across BBP/N pins, and additional 0.47-µF/16-V

differential capacitor is needed to connect from BBN to the top CB pins. This additional capacitor forms a

complete capacitor ladder from all cells in the module to the bus bar, allowing high spike voltage during hotplug

to distributor across the capacitor ladder.

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Pcb connector

+

Device

R_VC

VC0

C_VC

AVSS

Device

30 Ω

BAT

10 nF

Pcb connector

Device

R_VC

VC16

CB16

VC0

R_CB

+

C_VC

AVSS

C_CB

C_VC

R_VC

VC15

CB15

400 Ω

Device

R_CB

BBP

+

0.47 µF

C_CB

busbar

C_VC

R_VC

BBN

BAT

VC14

CB14

10Ω

bus bar connected BBP/N

above the top of a module.

R_CB

A cell + bus bar —sharing“ a single

VC channel

+

22 nF

In such connection, the VC

channel is not being —shared“

0.47 µF

400 Ω

R_VC

BBP

BBN

VC16

CB16

+

0.47 µF

A bus bar channel within, allowing host

to obtain the actual cell measurement by

subtracting the bus bar measuremement

R_CB

C_VC

busbar

C_CB

C_VC

R_VC

VC15

CB15

VC13

CB13

+

R_CB

+

(a) BBP/N connection with bus bar connected in any middle VC channel

(b) BBP/N connection with bus bar connected above the top of a module

图9-52. Bus Bar Connected Across BBP and BBN Pins

9.3.7.1.2 Bus Bar Measurement

The differential measurement across (BBP–BBN) is measured by the Main ADC and AUX ADC. See 节

9.3.2.1.1 and 节9.3.2.2.1 for details. Use the BBP_LOC register to indicate which VC channel is shared with the

BBP/N connection. This information enables the device to have better common mode correction for the final

ADC measurement. Host will be aware that additional IR error is introduced to the shared VC channel. If OVUV

protector is enabled, this shared channel may trigger earlier OV or UV detection due to the additional IR increase

(during charge) or decrease (during discharge) to the shared channel measurement.

9.3.7.1.3 Cell Balancing Handling

Because the bus bar is shared with a cell to a cell channel, there is no special handling on the cell balancing

control. Host will be aware that additional IR error is introduced to the VCB_DONE detection (through VC

channel) on the shared channel.

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Device

R_VC

V_Cn

R_CB

CB_n

C_CB

C_VC

I_CB

+

Q_CBn

R_VC

VC_n-1

CB_n-1

R_CB

+

CB Control

Q_CBn-1

图9-53. Cell Balancing with Bus Bar (Through BBP/N) Sharing a Cell Channel

9.3.7.1.4 Cell Voltage Diagnostic Control

The device still supports VC channel versus CB channel by looking at the sum of (cell + bus bar measurement)

comparison check on the shared channel. See 节 9.3.6.4.6.1. Additionally, bus bar measurement can be

checked by comparing bus bar channel measurement from Main ADC and AUX ADC.

If ADC_CTRL1[LPF_BB_EN]=0

Main ADC Path

Filters

SAR

ADC

De-

MUX

(BCI &

AAF),

LS

To BUSBAR_HI/LO

registers

Digital

LPF

MUX

Host to check the measurements

CB Filters

BusBar

Bus bar channel from

AUX ADC

SAR

ADC

De-

MUX

To AUXCELL register if [AUX_CELL_SEL4:0]

= 0x01 (busbar channel)

16:1

MUX

BCI &

AAF filters

MUX

Aux ADC Path

图9-54. Bus Bar Through BBP/N Measurement Check

The BBP/N pins have built-in current sink for open wire detection. The current sink is turned on when

DIAG_COMP_CTRL3[OW_SNK1:0] = 0b11. When there is a current flow through the bus bar, the (BBP–BBN)

measurement is non-zero. If there is an open wire on the BBP or BBN pin, the current sink changes the (BBP–

BBN) measurement to an abnormal value.

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R_VC

V_Cn

+

R_VC

BBP

Busbar to pcb

wire

OW current

sink

Busbar measured by

Main ADC across BBP/

BBN pins

C_VC

BusBar

R_VC

BBN

OW current

sink

R_VC

VC_n-1

Cell to pcb wire

+

图9-55. Current Sink for BBP/N Open Wire Detection

9.3.7.2 Bus Bar on Individual VC Channel

Besides connecting bus bar through BBP/N, the device also supports bus bar connection to an individual VC

channel. All VC channels, except the bottom channel (VC1-VC0), support –2V to 5V measurement.

The device supports bus bar connection to an individual VC channel. All VC channels, except the bottom

channel (VC1-VC0), support –2V to 5V measurement.

When bus bar is connected to an individual VC channel, host indicates the bus bar position in the

BBVC_POSN1 and BBVC_POSN2 registers. The following configuration is not supported for bus bar connection

through individual VC channel. Configuring BBVC_POSN1 register with such configuration can cause error in

balancing, OVUV detection and cell voltage measurement comparison check.

• Bottom channel does not support bus bar connection. That is, BBVC_POSN1[CELL1] must be 0.

• Maximum of two bus bars can be connected through this connection. That is, only two bits are set to 1 in the

BBVC_POSN1 registers.

• Bus bar cannot be connected to the adjacent channels.

9.3.7.2.1 Typical Connection

With bus bar connected to a VC channel individually, the upper CB pin on that channel is left floating to avoid

forward biasing the internal CBFET (see 图 9-56 (a) connection). This connection applies to bus bar connecting

to any middle VC channel individually. That is, in a single device, there is a cell connected above and below the

VC channel with bus bar connected. To ensure hotplug performance, the CB channel where the bus bar is

connected will still have the differential capacitor even if the upper CB pin is floating. This capacitor forms a

complete capacitor ladder from all cells and the bus bar connected to the device, allowing high-voltage spike

during hotplug to distribute across the capacitor ladder.

If bus bar is connected to above the top of a module to an individual VC channel (see 图 9-56 (b) connection),

the upper CB pin on that channel is left floating but the CB differential capacitor will still be connected.

Additionally, an additional RC filter is connected from the top CB pin to the BAT pin. This additional RC filter

(using the same RC values as the other RC filter on the CB pins) is to ensure a complete capacitor ladder is

formed for the device to distribute the high voltage spike with the same RC constant as the reset of the CB pins

during hotplug event.

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Pcb connector

30 Ω

+

BAT

Device

10 nF

Device

R_VC

VC0

C_VC

R_VC

AVSS

VC16

CB16

+

C_VC

30 Ω

BAT

Device

C_CB

10 nF

R_VC

VC15

CB15

C_CB

R_CB

R_VC

+

VC16

CB16

C_VC

R_CB

R_VC

busbar

VC14

CB14

C_VC

C_CB

R_CB

C_CB

R_VC

VC15

CB15

R_CB

busbar

C_CB

C_VC

+

R_VC

C_CB

C_VC

VC13

CB13

R_VC

VC14

CB14

R_CB

+

(a) Bus bar connected any middle individual VC channel

(b) Bus bar connected individual VC channel above the top of a module

图9-56. Bus Bar Connected to Individual VC Channel

9.3.7.2.2 Bus Bar Measurement

Bus bar measurement is performed through Main ADC measurement as one of the VC channels. The result is

reported to VCELLx_HI/LO register, where x is the channel connected with the bus bar. Digital LPF is enabled

and applied as the rest of the VC channel measurement configuration.

The VC channel indicated for bus bar connection (through BBVC_POSN1/2 registers) will be skipped for

VCB_DONE check during cell balancing, OV and UV detection when OVUV protectors are enabled, and will

have special handling during cell voltage measurement comparison check.

9.3.7.2.3 Cell Balancing Handling

Because the upper CB pin is open on the channel where bus bar is connected, to balance the cell connected

above bus bar, host turns on the adjacent CBFET and configures with the same timer setting.

Host configures BBVC_POSN1/2 register to indicate the bus bar connection. This information is used to avoid

the channel connected with bus bar to trigger a VCB_DONE detection and turn off its CBFET, which disconnects

the balancing path for the cell above the bus bar.

The balancing of the cell above the bus bar is still terminated based on the timer and cell voltage threshold,

which its CBFET will be turned off when one of the stop conditions is met. The balancing path is disconnected

even if the CBFET on the bus bar connected channel remains on.

备注

The CBFET on the bus bar connected channel will be on until the timer expired. This may lead to a

delayed flagging of the [CB_DONE] = 1 even if the actual cell balancing is completed.

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Device

R_VC

V_Cn

R_CB

CB_n

C_CB

VC_n

C_VC

I_CB

+

Configure with same CB

Timer setting

Q_CBn

R_VC

VC_n-1

CB_n-1

C_CB

CB Control

Q_CBn-1

R_CB

CB_n-2

VC_n-2

C_VC

+

R_VC

VC_n-2

图9-57. Cell Balancing with Bus Bar Connected to Individual VC Channel

9.3.7.2.4 Cell Voltage Diagnostic Control

The cell voltage comparison check is still performed by checking the Main ADC measurement versus the AUX

ADC measurement. Because the upper CB pin of the CB channel, where a bus bar is connected, is open, the

device handles the comparison check by comparing a sum of (cell + bus bar) from Main ADC versus sum of (cell

+ bus bar) from AUX ADC instead.

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Device

R_VC

VC_n

CB_n

R_CB

I_CB

+

C_CB

C_VC

VC_n

R_VC

Sum

VC_n-1

CB_n-1

C_CB

BusBar

R_CB

CB_n-2

C_VC

R_VC

+

VC_n-2

Comp

图9-58. Cell Measurement Check with Bus Bar Connected to Individual VC Channel

9.4 Device Functional Modes

The device has three power modes plus an POR state.

• POR: This is not a power mode. This is a condition in which the voltage at the BAT pin is less than VBAT min,

and all circuits including the AVAO_REF block in the device are powered off.

• SHUTDOWN: This is the lowest power mode. AVDD, DVDD and CVDD supplies are off. Only a gross

regulation at LDOIN pin is maintained. CVDD pin is will have a similar voltage as the LDOIN pin through

internal circuit in order to support WAKE detection.

• SLEEP: This is the low power operation mode. Only limited functions are available.

• ACTIVE: This is the full power operation mode. All functions are supported under this state.

The various functions supported under different power modes are summarized in 表 9-34 and the power state

diagram is shown in 图9-59.

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表9-34. Active Functions Summary

Functional Block

SHUTDOWN

SLEEP

ACTIVE

POR

Main ADC

This is not a power state. All circuits

are off. A sufficient voltage on VBAT

will POR the device and put it to

SHUTDOWN mode

√

AUX ADC

(1)

OV/UV protector

OT/UT protector

Cell Balancing

OTCB Detection

√

(1)

√

(1)

√

(1)

√

Module Balancing (via control through

MB_TIMER_CTRL)

UART

√

Comm Vertical Communication

Fault Status and NFAULT

Communication

√

Comm timeout

√

SLEEP timeout

√

Thermal Shutdown Detection

SPI Master

√

OTP programming

Always-on block to detect POR of the

device

√

(1) To enable cell balancing, OV/UV or OT/UT protector(s) in SLEEP mode, host must enable the function(s) in ACTIVE mode first, then

put the device to SLEEP.

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V_BAT< Min V_BAT

POR

1. Set CONTROL1[GOTO_SLEEP] = 1, OR

2. Long comm timeout occurs w/

COMM_TIMEOUT[CTL_ACT] = 0, OR

3. When cell and/or module balancing is done and

[BAL_ACT1:0] = 01

SLEEP MODE

Receive

SLEEPtoACTIVE

signal

Device reset

Receive WAKE

signal

ACTIVE MODE

1. Receive SHUTDOWN

signal, OR

2. Thermal shutdown

occurs, OR

3. SLEEP timeout

Receive WAKE signal, OR

Set CONTROL1[SOFT_RESET] = 1

Device reset

Receive WAKE

signal

Device reset

SHUTDOWN MODE

1. Set CONTROL1[GOTO_SHTUTDOWN] = 1, OR

2. Long comm timeout occurs w/

COMM_TIMEOUT[CTL_ACT] = 1, OR

3. Receive SHUTDOWN signal, OR

4. Thermal shutdown occurs

5. When cell and/or module balancing is done and

[BAL_ACT1:0] = 10

图9-59. Power State Diagram

9.4.1 Power Modes

9.4.1.1 SHUTDOWN Mode

This is the lowest power mode. In SHUTDOWN mode, most of the functions are off. The device remains idle to

simply monitor the WAKE ping/tone (see 节 9.4.3 for details) to wake up from this state. Only a gross regulation

on LDOIN and CVDD pins are maintain for WAKE ping/tone detection.

9.4.1.1.1 Exit SHUTDOWN Mode

Communication is not supported in SHUTDOWN mode, host must send a WAKE ping or WAKE tone to enter

ACTIVE mode. Once device transitions from SHUTDOWN mode to ACTIVE mode, the following table indicates

the expected fault bits being set under such transition has occurred.

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表9-35. Expected Fault Bit After Device Wake From SHUTDOWN

Device Position In

The Daisy Chain

Expected Fault Bits After Waking Up From SHUTDOWN

FAULT_SYS[DRST] = 1

Digital reset by the wake ping

FAULT_COMM3[FCOMM_DET]

= 1

[DRST] = 1 from the upper device

Base device

FAULT_COMM1[COMMCLR_D

ET] = 1

UART engine is reset

FAULT_SYS[DRST] = 1

Digital reset by the wake tone

[DRST] = 1 from the upper device

Digital reset by the wake tone

Stack device (except

top of stack)

FAULT_COMM3[FCOMM_DET]

= 1

Top of stack device

FAULT_SYS[DRST] = 1

POR

(Transition)

SHUTDOWN Mode

Transition

ACTIVE Mode

Min V_BAT

BAT

AVAO

LDOIN

CVDD

Min V_CVDDUV

Min V_AVDDUV

AVDD

DVDD

Comm

available

t_{SU(WAKE_SHUT)}

Comm

t_RST

Comm not available

time

图9-60. SHUTDOWN to ACTIVE Mode Transition

9.4.1.1.2 Enter SHUTDOWN Mode

During normal operation, host puts the device in SHUTDOWN mode through communication by sending

CONTROL1[GOTO_SHUTDOWN] = 1. In a daisy chain configuration, using broadcast write to send this

command will put all devices in the daisy chain in SHUTDOWN mode.

The device can also enter SHUTDOWN mode by one of the following conditions:

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• Communication timeout: automatically transitions from ACTIVE mode to SHUTDOWN mode if there is no

valid communication for the configured time. Host can enable this option through the

COMM_TIMEOUT_CONF register.

• SLEEP mode timeout: automatically transitions from SLEEP mode to SHUTDOWN mode if device is in

SLEEP mode for the configured time. Host can enable this option through

PWR_TRANSIT_CONF[SLP_TIME2:0].

• Upon balancing completion: automatically enter SHUTDOWN mode when all balancing of the devices is

completed. See 节9.3.3 for details. This option can result with devices in different power modes for a period

of time in a daisy chain configuration.

• Thermal shutdown: shuts down the device when the internal die temperature is greater than T_SHUT

• SHUTDOWN or HW_RESET ping/tone: These pings/tones are used as a recovery attempt on a loss

communication situation. A SHUTDOWN ping/tone puts the device into SHUTDOWN mode without using

communication, forcing most of the circuits to be off. A more aggressive recovery attempt uses HW_RESET

ping/tone which turns off all circuits except a bandgap and restarts the device in SHUTDOWN mode.

9.4.1.2 SLEEP Mode

This is the low power operation mode. In SLEEP mode, all internal power supplies are still on, but functions are

limited to cell balancing, OVUV and OTUT protectors, Heartbeat/Fault Tone/NFAULT transmission and detection.

9.4.1.2.1 Exit SLEEP Mode

Because host cannot communicate to the device, to exit SLEEP mode, host must send either a WAKE ping/tone

or SLEEPtoACTIVE ping/tone to transition to ACTIVE mode. A WAKE wakes up and resets the device, which

host will need to reconfigure the device setting; a SLEEPtoACTIVE only wakes up the device.

9.4.1.2.2 Enter SLEEP Mode

The device can enter SLEEP mode from ACTIVE mode only. During normal operation, host puts the device to

SLEEP mode through communication by sending CONTROL1[GOTO_SLEEP] = 1. In a daisy chain

configuration, using broadcast write to send this command will put all devices into SLEEP mode.

The device can also enter SLEEP mode in the following condition:

• Communication timeout: automatically transitions from ACTIVE mode to SLEEP mode if there is no valid

communication for the configured time. Host can enable this option through the COMM_TIMEOUT_CONF

register.

SLEEP

Mode

Transition

ACTIVE Mode

SLEEP

Mode

Transition

ACTIVE Mode

CVDD

AVDD

CVDD

AVDD

DVDD

Comm

DVDD

Comm

available

Comm

available

Comm not

available

Comm not

available

t_{SU(WAKE_SLP)}

t_RST

t_SU(SLP2ACT)

t

e

t

e

VE

to

e

I

T

to

e

s

time

n

e

n

e

d

s

d

e

r

c

i

e

r

n

C

c

i

n

e

to

/

e

/

v

A

e

v

e

g

s

e

g

s

e

c

i

n

c

i

n

d

i

e

d

t

e

i

v

t

p

v

e

n

p

e

x

D

E

to

e

EEPto

to

e

D

t

r

K

n

t

r

SL

A

VE

I

d

W

T

Sta

T

C

A

e

Sta

C

d

v

i

e

A

e

v

i

c

e

R

c

e

EEPto

SL

EEPto

SL

R

(a) Waking up with WAKE ping/tone

(b) Waking up with SLEEPtoACTIVE ping/tone

图9-61. SLEEP to ACTIVE Mode Transition

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9.4.1.3 ACTIVE Mode

This is the operation mode with full functionality support. Host can communicate to the device with full control on

various features as well as performance diagnostic in this mode.

9.4.1.3.1 Exit ACTIVE Mode

From ACTIVE mode, device can enter SLEEP mode or SHUTDOWN mode through command, ping/tone, timer,

or specific event. See 节9.4.1.1 and 节9.4.1.2 for details.

9.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode

Device can transition to ACTIVE mode from SHUTDOWN mode only through a WAKE ping/tone. Once in

ACTIVE mode, host clears some of the reset-related faults which are expected faults (see 节 9.4.1.1 for details)

indicating a POR on certain blocks due to the transition from SHUTDOWN mode to ACTIVE mode. Registers are

reset to default; the OTP shadow registers are reloaded with the OTP programmed values.

9.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode

From SLEEP mode, either a WAKE or SLEEPtoACTIVE ping/tone can put the device in ACTIVE mode. A WAKE

ping/tone will generate a digital reset to the device. Because the LDO supplies remain on during SLEEP mode,

only the FAULT_SYS[DRST] = 1 is set, indicating a digital reset has occurred. Certain expected faults related to

being reset are set. See SHUTDOWN mode for detail. Registers are reset to default, the OTP shadow registers

are reloaded with the OTP programmed values.

If a SLEEPtoACTIVE ping/tone is used to wake up the device from SLEEP mode to ACTIVE mode, device will

simply enter ACTIVE mode without digital resetting but the UART engine will be reset. Hence, in the base

device, the FAULT_COMM1[COMMCLR_DET] = 1 and host clears it after entering ACTIVE mode.

9.4.2 Device Reset

There are several conditions which the device will go through: a digital reset, putting the registers to their default

settings and reloading the OTP.

• A WAKE ping/tone is sent to transition from SHUTDOWN mode or SLEEP mode to ACTIVE mode.

• A WAKE ping/tone is received in ACTIVE mode.

• The CONTROL1[SOFT_RESET] = 1 command is sent in ACTIVE mode.

• A HW_RESET ping/tone is sent under any power mode. This generates a POR-like event to the device.

Upon the detection of a HW_RESET ping/tone, the device will turn off all internal blocks except a bandgap for

t_HWRSTduration. Afterward, the device will restart in SHUTDOWN mode.

• Internal power supply faults. See 节9.3.6.4 for details.

– AVDD UV, DVDD UV is detected.

• A HFO or LFP watchdog fault will reset the digital.

Apart from the full reset cases, the following conditions will only reset the UART engine. These conditions mainly

affect the base device because UART is used to talk to the host MCU. In the base device, the

FAULT_COMM1[COMMCLR_DET] = 1 will be set. These conditions do not affect the stack devices because

UART is inactive in those devices.

• A SLEEPtoACTIVE ping is sent to transition from SLEEP mode to ACTIVE mode.

• The following conditions not only clear the UART engine and set the [COMMCLR_DET] = 1, they also set

FAULT_COMM1[STOP_DET] = 1 as an indication that an unexpected UART STOP is detected.

– A SLEEPtoACTIVE ping is sent in ACTIVE mode.

– A COMM CLEAR signal is sent. This is a dedicated signal to clear the UART engine and instruct the

engine to look for a new start of communication frame. See 节9.3.6.1.1.1 for more details.

9.4.3 Ping and Tone

In the noncommunicable conditions such as in SHUTDOWN or SLEEP mode, or in the loss of communication

situations when host would like to instruct for a reset or power down as a communication recovery attempt, a

Ping or Tone is used as a form of communication to the device for a specific action.

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表9-36. Supported Ping/Tone in Different Power Modes

Ping/Tone Detection

SHUTDOWN ping

Detected Pin(s)

SHUTDOWN

SLEEP

ACTIVE

√

RX

√

SLEEPtoACTIVE ping

WAKE ping

RX

√

RX

√

HW_RESET ping

SHUTDOWN tone

SLEEPtoACTIVE tone

WAKE tone

RX

√

COMH/L

√

HW_RESET tone

Fault tone

√

Only fault tone detection is available

√

HEARTBEAT

√

9.4.3.1 Ping

A ping is a specific high-low-high signal to the RX pin of the device. Ping is used on the base device as only the

base device is connected to the host which the UART RX is accessible. The device detects different low times of

the ping signal to differentiate the different ping signals.

The communication pings are referring to the WAKE ping, SLEEPtoACTIVE ping, SHUTDOWN ping, and

HW_RESET ping. These pings instruct the device to a specific power mode when normal communication is not

available. By definition, a COMM CLEAR signal on the RX pin is a form of a ping. Because a COMM_CLR is to

clear the UART engine, this signal is covered in 节9.3.6.1.1.1.

t_{HLD_HWRST}

t_{HLD_SD}

t_{HLD_WAKE}

t_UART(StA)

High

Host shall release the RX line

after applying the HW_RESET

ping

RX

HW_RESET

SHUTDOWN

WAKE

SLEEPtoACTIVE

Ping duration

Return —high“ for next

operation

图9-62. Communication Pings

9.4.3.2 Tone

A tone is a fixed number of couplets (pulses) with a specified polarity (all “+” or all “–”) sent through the

differential vertical interface COMH and COML ports. Tone is used on stack devices as only the COMH/L ports

are accessible. The number of couplets for transmission is always greater than the number of couplets needed

for detection.

There are four communication tones corresponding to the four communication pings. They are WAKE tone,

SLEEPtoACTIVE tone, SHUTDOWN tone, and HW_RESET tone. In addition to the communication tones, there

are two extra tones related to device fault status: Heartbeat tone and Fault tone. These two fault status tones are

only available in SLEEP mode. See 节9.3.6.2.3.3 for details.

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Wake and SLEEP-to-ACTIVE Couplets (all —+“ pulses)

WAKE TONE DETECTION

CVDD

n_WAKEDETPulses

COM*P

COM*N

COM*P,COM*N

n_WAKE—+“ Pulses

CVDD/2

WAKEUP_DET

(internal signal)

CVSS

t_{COMTONE_HI}

SLEEP TO ACTIVE TONE DETECTION

t_COMMTONE

n_SLPtoACTDETPulses

COM*P œ COMP*N

COMXP, COMXN

SLP2ACT_DET

n_SLPtoACT—+“ Pulses

t_{COMTONE_LO}

A pulse

SHUTDOWN and HW_RESET Couplets (all —-— pulses)

SHUTDOWN TONE DETECTION

CVDD

n_SHDNDETPulses

COMXP, COMXN

HWRST_DET

n_SHDN—-“ Pulses

COM*P

COM*N

CVDD/2

CVSS

HW_RESET TONE DETECTION

t_{TONE_HI}

n_HWRSTDETPulses

f_COMTONE

COMXP, COMXN

HWRST_DET

n_HWRST—-“ Pulses

COM*P œ COMP*N

t_{TONE_LO}

图9-63. Communication Tones

9.4.3.3 Ping and Tone Propagation

Propagates:

The WAKE and SLEEPtoACTIVE pings/tones are part of the normal operation to wake up the device; hence,

these two pings/tones can propagate to the next device in a daisy chain configuration. That is, when a device

receives a WAKE ping/tone, it generates a WAKE tone and forwards it to the next device. Similar action applies

to SLEEPtoACTIVE ping/tone.

The direction of the tone forwarding follows the communication direction, which is set by the

CONTROL1[DIR_SEL] bit. See 节 9.3.6.1 for more details. The detection of the tone is supported from the

COMH and COML ports on stack devices regardless of the [DIR_SEL] setting. This does not apply to base

device because base device detects pings instead.

During normal operation, host can simply send a WAKE or SLEEPtoACTIVE ping to the base device and the

corresponding tone will be generated to the rest of the stack devices. During system development, if there is a

need to send WAKE or SLEEPtoACTIVE to only some of the devices in the daisy chain, host can use the

CONTROL1[SEND_WAKE] or CONTROL1[SEND_SLPTOACT] bit. Device that receives this command will send

the corresponding tone to the next device in the daisy chain. Because the WAKE and SLEEPtoACTIVE tones

propagate, the rest of the daisy chain connected above also receives the corresponding tone.

Does Not Propagate:

The SHUTDOWN and HW_RESET pings/tones are mostly used as a communication recovery attempt. Hence

these pings/tones do not propagate. That is, when a device receives a SHUTDOWN ping/tone, it starts the

shutdown process but the device does not generate another SHUTDOWN tone to the next device. Similar action

applies to HW_RESET ping/tone.

For a base device, as RX pin is connected to the host, SHUTDOWN or HW_RESET ping can be used on the

base device. For stack devices, it is required at least one stack device is connected to the problem device is

communicable. Host has to talk to the neighboring device and sets the CONTROL1[SEND_SHUTDOWN] = 1 or

CONTROL2[SEND_HW_RESET] = 1 to instruct the neighboring device to issue the corresponding tone to the

problem device. The detection of the tone is supported from the COMH and COML ports on stack devices

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regardless of the [DIR_SEL] setting. This does not apply to a base device because a base device detects pings

instead.

表9-37. Ping and Tone Propagation Summary

Ping/Tone

Propagable

Non-Propagable

WAKE

Receiving device will generate a WAKE tone to the

next device

SLEEPtoACTIVE

Receiving device will generate a SLEEPtoACTIVE

tone to the next device

SHUTDOWN

HW_RESET

Receiving device will initialize the shutdown process

Receiving device will initialize the HW reset process

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9.5 Register Maps

This section has three register map summary tables with registers listed per the order of the register address:

• The NVM (OTP) shadow registers. These read/write-able shadow registers are reset with OTP values

programmed in the customer OTP space. To program the custom OTP space, host writes the desired values

to these OTP shadow registers and follows the programming procedure. These registers are included in the

OTP CRC check. If customer OTP space is not programmed. The shadow registers are loaded with factory

configuration default value. If the OTP (either factory configuration default or value programmed in customer

OTP space) is failing to load after a device reset, the shadow registers will be loaded with the hardware reset

default value instead. The hardware reset default value and the factory configuration default values are the

same for the majority of the OTP shadow registers. Only the DIR0_ADDR_OTP, DIR1_ADD_OTP,

PWR_TRANSIT_CONF, CUST_CRC_HI/LO registers have a reset value versus factory default, and are

specified in 节9.5.1 and their register field descriptions.

• The Read/Write registers. These are registers that the host can read/write to during runtime. A device reset

will put these registers back to their reset value.

• The Read registers. These are registers that the host only has read access. A device reset will put these

registers back to their reset value.

The register summary tables use the following key:

• Addr = Register address

• Hex = Hexidecimal value

• NVM = Non-volatile memory (OTP) shadow registers

• RSVD = Reserved. Reserved register addresses or bits are not implemented in the device. Any write to these

bits is ignored. Reads to these bits always return 0.

• OTP_SPARE: These are spare OTP and shadow register bits that are implemented in the device. These

spare bits are included as part of the CRC calculation. These bits are read/write as normal, but do not

perform any function or influence any device behaviors.

• OTP_RSVDn = OTP and shadowed registers that are implemented but are reserved for device internal

usage, where n refers to the register address. MCU must keep these registers in their default value

• HW Reset default is the value loaded when digital resets (POR like event) whereas Factory Configuration

Default is the default value loaded into the OTP cell if customer doesn't program it themselves. Customer

cannot read the HW Reset value.

节 9.5.4 describes the definition of each bit in the registers. The registers in this section are grouped per

functional blocks.

9.5.1 OTP Shadow Register Summary

Register

Name

Addr RW

Hex Type

Reset

Value

Data

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DIR0_ADDR

_OTP

0

1

2

NVM HW Reset

Default =

0x00

SPARE[1:0]

ADDRESS[5:0]

Factory

Configurati

on Default

= 0x01

DIR1_ADDR

_OTP

NVM HW Reset

Default =

0x00

SPARE[1:0]

ADDRESS[5:0]

Factory

Configurati

on Default

= 0x01

DEV_CONF

NVM

0x54

RSVD

NO_ADJ MULTI

FCOMM

_EN

TWO_

STOP

_EN

NFAULT

_EN

FTONE

_EN

HB_EN

_CB

DROP

_EN

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Bit0

Register

Name

Addr RW

Hex Type

Reset

Value

Data

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

ACTIVE_CE

LL

3

NVM HW Reset

Default =

0x00

SPARE[3:0]

NUM_CELL[3:0]

Factory

Configurati

on Default

= 0x0A

OTP_SPARE

15

4

5

NVM

0x00

0x3F

0x00

0xE0

0x00

SPARE[7:0]

BBVC_POS

N1

CELL16

CELL8

CELL15 CELL14 CELL13

CELL12

CELL4

CELL11

CELL3

CELL10

CELL2

CELL9

CELL1

BBVC_POS

N2

6

CELL7

CELL6

CELL5

ADC_CONF

1

7

AUX_SETTLE[1:0]

SPARE[1:0]

LPF_BB[2:0]

LPF_VCELL[2:0]

ADC_CONF

2

8

ADC_DLY[5:0]

OV_THR[5:0]

UV_THR[5:0]

OV_THRES

H

9

SPARE

UV_THRES

H

A

B

C

D

E

F

OTUT_THR

ESH

UT_THR[2:0]

OT_THR[4:0]

UV_DISABL

E1

CELL16

CELL8

CELL15 CELL14 CELL13

CELL12

CELL4

CELL11

CELL3

CELL10

CELL9

CELL1

UV_DISABL

E2

CELL7

SPI_EN

SPARE

CELL6

CELL5

CELL2

GPIO_CONF

1

FAULT_

IN_EN

GPIO2[2:0]

GPIO4[2:0]

GPIO6[2:0]

GPIO8[2:0]

GPIO1[2:0]

GPIO3[2:0]

GPIO5[2:0]

GPIO7[2:0]

GPIO_CONF

2

SPARE

GPIO_CONF 10

3

SPARE[1:0]

GPIO_CONF 11

4

OTP_SPARE 12

14

SPARE[7:0]

OTP_SPARE 13

13

SPARE[7:0]

OTP_SPARE 14

12

OTP_SPARE 15

11

FAULT_MSK

1

16

MSK_ PROT MSK_UT MSK_OT MSK_UV MSK_OV

MSK_

COMP

MSK_

SYS

MSK_ PWR

FAULT_MSK

2

17

SPARE[1]

MSK_

OTP_

CRC

MSK_

OTP_

DATA

MSK_

COMM3

_HB

MSK_

COMM2

MSK_

COMM1

COMM3 COMM3

_FCOMM _FTONE

PWR_TRAN

SIT_CONF

18

NVM HW Reset

Default =

0x18

SPARE[2:0]

TWARN_THR[1:0]

SLP_TIME[2:0]

Factory

Configurati

on Default

= 0x10

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Register

Name

Addr RW

Hex Type

Reset

Value

Data

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

COMM_TIM

EOUT_CON

F

19

NVM

0x00

SPARE

CTS_TIME[2:0]

CTL_ ACT

CTL_TIME[2:0]

TX_HOLD_

OFF

1A

1B

NVM

0x00

DLY[7:0]

GAINL[7:0]

OFFSET[6:0]

GAINL[7:0]

OFFSET[6:0]

MAIN_ADC_

CAL1

MAIN_ADC_ 1C

CAL2

GAINH

AUX_ADC_

CAL1

1D

1E

1F

20

AUX_ADC_

CAL2

OTP_RSVD

1F

INTERNAL USE. DO NOT WRITE TO THIS ADDRESS

OTP_RSVD

20

21

22

23

24

25

26

27

28

NVM

0x00

DATA[7:0]

DELAY[5:0]

CUST_MISC

1 through

CUST_MISC

8

STACK_RES 29

PONSE

SPARE[1:0]

SPARE[2:0]

BBP_LOC

2A

2B

NVM

0x00

LOC[4:0]

OTP_RSVD

2B

INTERNAL USE. DO NOT WRITE TO THIS ADDRESS

OTP_SPARE 2C

10

NVM

0x00

SPARE[7:0]

OTP_SPARE 2D

9

OTP_SPARE 2E

8

OTP_SPARE 2F

7

OTP_SPARE 30

6

OTP_SPARE 31

5

OTP_SPARE 32

4

OTP_SPARE 33

3

OTP_SPARE 34

2

OTP_SPARE 35

1

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Bit0

Register

Name

Addr RW

Hex Type

Reset

Value

Data

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

CUST_CRC

_HI

36

37

NVM HW Reset

Default =

0x57

CRC[7:0]

Factory

Configurati

on Default

= 0x31

CUST_CRC

_LO

NVM HW Reset

Default =

0x89

CRC[7:0]

Factory

Configurati

on Default

= 0xF3

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9.5.2 Read/Write Register Summary

Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

OTP_PROG_UNL

OCK1A through

OTP_PROG_UNL

OCK1D

300

301

302

303

306

307

308

RW

0x00

CODE[7:0]

DIR0_ADDR

DIR1_ADDR

COMM_CTRL

RSVD

ADDRESS[5:0]

RSVD

STACK_

DEV

TOP_

STACK

CONTROL1

CONTROL2

309

30A

RW

0x00 DIR_SEL

0x00

SEND_

SHUT

DOWN

SEND_

WAKE

SEND_

SLPTO

ACT

GOTO_

SHUT

DOWN

GOTO_

SLEEP

SOFT_

RESET

ADDR_

WR

RSVD

SEND_

HW_

TSREF

_EN

RESET

OTP_PROG_CTR 30B

L

RW

0x00

RSVD

PAGE

SEL

PROG

_GO

ADC_CTRL1

30D

0x00

RSVD

LPF_BB

_EN

LPF_

VCELL_

EN

MAIN_GO

MAIN_MODE[1:0]

ADC_CTRL2

30E

RW

RSVD

AUX_CEL

L_ALIGN

AUX_CELL_SEL[4:0]

ADC_CTRL3

30F

310

318

319

31A

31B

31C

31D

31E

31F

320

321

322

323

324

325

326

327

RW

0x00

0x3F

AUX_GPIO_SEL[3:0]

INTERNAL USE. DO NOT WRITE TO THIS ADDRESS

RSVD

AUX_GO

AUX_MODE[1:0]

REG_INT_RSVD

CB_CELL16_CTR

L through

CB_CELL1_CTRL

TIME[4:0]

RSVD

VMB_DONE_THR 328

ESH

RSVD

MB_THR[5:0]

MB_TIMER_CTRL 329

RW

0x00

RSVD

TIME[4:0]

CB_THR[5:0]

VCB_DONE_THR

ESH

32A

RSVD

OTCB_THRESH

32B

RW

0x0F

RSVD

COOLOFF[2:0]

OTCB_THR[3:0]

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Bit1 Bit0

Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

OVUV_CTRL

32C

RW

0x00

VCB

DONE

_THR

_LOCK

OVUV_LOCK[3:0]

OVUV

_GO

OVUV_MODE[1:0]

OTUT_CTRL

32D

RW

0x00

RSVD

OTCB_

THR_

LOCK

OTUT_LOCK[2:0]

OTUT

_GO

OTUT_MODE[1:0]

DUTY[2:0]

BAL_CTRL1

BAL_CTRL2

32E

32F

RW

0x00

RSVD

FLTSTOP OTCB_

_EN EN

RSVD

CB_

PAUSE

BAL_ACT[1:0]

BAL_GO

AUTO_

BAL

BAL_CTRL3

FAULT_RST1

FAULT_RST2

330

331

332

RW

0x00

RSVD

BAL_TIME_SEL[3:0]

BAL_TIM

E_GO

RST_

PROT

RST_UT RST_OT RST_UV RST_OV

RST_

COMP

RST_SYS

RST_

PWR

RSVD

RST_OTP RST_OTP RST_ RST_

RST_

_CRC

RSVD

_DATA

COMM3_ COMM3_ COMM3_ COMM2

COMM1

FCOMM

FTONE

HB

DIAG_OTP_CTRL 335

RW

0x00

FLIP_

FACT_

CRC

MARGIN_MODE[2:0]

MARGIN

_GO

DIAG_COMM_CT

RL

336

RSVD

SPI_

LOOP

BACK

FLIP_TR

_CRC

DIAG_PWR_CTRL 337

RW

RSVD

BIST_

NO_RST BIST_GO

PWR_

DIAG_CBFET_CT

RL1

338

339

33A

33B

33C

33D

0x00 CBFET16 CBFET15 CBFET14 CBFET13 CBFET12 CBFET11 CBFET10 CBFET9

DIAG_CBFET_CT

RL2

0x00

CBFET8 CBFET7 CBFET6 CBFET5 CBFET4 CBFET3 CBFET2 CBFET1

DIAG_COMP_CT

RL1

VCCB_THR[4:0]

GPIO_THR[2:0]

BB_THR[2:0]

OW_THR[3:0]

COMP_ADC_SEL[2:0]

COMP_

DIAG_COMP_CT

RL2

RSVD

DIAG_COMP_CT

RL3

CBFET_C

TRL_GO

OW_SNK[1:0]

RSVD

COMP_

ADC_GO

DIAG_COMP_CT

RL4

LPF_

FAULT

_INJ

FAULT

_INJ

DIAG_PROT_CTR 33E

L

RW

0x00

RSVD

PROT_

BIST_

NO_RST

OTP_ECC_DATAI

N1 through

OTP_ECC_DATAI

N9

343

344

345

346

347

348

349

34A

34B

34C

RW

0x00

DATA[7:0]

OTP_ECC_TEST

SPI_CONF

RSVD

CPOL CPHA

DED_

SEC

MANUAL

_AUTO

ENC_

DEC

ENABLE

34D

RW

0x00

RSVD

NUMBIT[4:0]

118

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Register Name

Data

Addr RW Reset

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SPI_TX3,

SPI_TX2, and

SPI_TX1

34E

34F

350

351

352

353

354

355

700

RW

0x00

0x02

0x00

DATA[7:0]

SPI_EXE

RSVD

SS_CTRL SPI_GO

OTP_PROG_UNL

OCK2A through

OTP_PROG_UNL

OCK2D

CODE[7:0]

DEBUG_CTRL_U

NLOCK

DEBUG_COMM_

CTRL1

701

702

RW

0x04

0x0F

RSVD

UART_

BAUD

UART_

MIRROR

_EN

UART_

TX_EN

USER_

UART_

EN

USER_

DAISY

_EN

DEBUG_COMM_

CTRL2

RSVD

COML_

TX_EN

COML_

RX_EN

COMH_

TX_EN

COMH_

RX_EN

9.5.3 Read-Only Register Summary

Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PARTID

500

E00

501

502

503

504

505

506

507

508

509

R

0x00

0x31

REV[7:0]

DEV_REVID

DEV_REVID[7:0]

ID[7:0]

DIE_ID1 through

DIE_ID9

ID[7:0]

CUST_CRC_RSLT 50C

_HI

CRC[7:0]

CUST_CRC_RSLT 50D

_LO

R

0xF3

CRC[7:0]

OTP_ECC_DATA

OUT1 through

OTP_ECC_DATA

OUT9

510

511

512

513

514

515

516

517

518

519

R

0x00

DATA[7:0]

OTP_PROG_STA

T

0x00 UNLOCK OTERR

UVERR

OVERR SUVERR SOVERR

PROG

ERR

DONE

TRY

OTP_CUST1_STA 51A

T

R

0x00 LOADED

LOAD

WRN

LOAD

ERR

FMTERR PROGOK UVOK

OVOK

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Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

OTP_CUST2_STA 51B

T

R

0x00 LOADED

LOAD

WRN

LOAD

ERR

FMTERR PROGOK

UVOK

OVOK

TRY

SPI_RX3,

SPI_RX2, and

SPI_RX1

520

521

522

526

R

0x00

DATA[7:0]

DIAG_STAT

ADC_STAT1

ADC_STAT2

RSVD

DRDY_

OTUT

DRDY_

OVUV

DRDY_

BIST_

OTUT

DRDY_

BIST_

OVUV

DRDY_

BIST_

PWR

527

528

R

0x00

RSVD

DRDY_

AUX_

GPIO

DRDY_

AUX_

CELL

DRDY_

AUX_

MISC

DRDY_

MAIN_

ADC

0x00

RSVD

GPIO8

DRDY_

LPF

DRDY_

GPIO

DRDY_

VCOW

DRDY_

CBOW

DRDY_

CBFET

DRDY_

VCCB

GPIO_STAT

BAL_STAT

52A

52B

R

GPIO7

OT_

GPIO6

CB_

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

0x00 INVALID_

MB_RUN CB_RUN

ABORT

FLT

MB_

DONE

CB_

DONE

CBCONF PAUSE_ INPAUSE

DET

DEV_STAT

52C

52D

530

R

0x00

RSVD

FACT_

CRC_

DONE

CUST_

CRC_

DONE

OTUT_

RUN

OVUV_

RUN

RSVD

AUX_

RUN

MAIN_

RUN

FAULT_SUMMAR

Y

FAULT_

PROT

FAULT_

COMP_

ADC

FAULT_

OTP

FAULT_

COMM

FAULT_

OTUT

FAULT_

OVUV

FAULT_

SYS

FAULT_

PWR

FAULT_COMM1

RSVD

UART_TR UART_

RR

UART_

RC

COMM

CLR_

DET

STOP_

DET

FAULT_COMM2

FAULT_COMM3

FAULT_OTP

531

532

535

R

0x00

COML_

TR

COML_

RR

COML_

RC

COML_

BIT

COMH_

TR

COMH_

RR

COMH_

RC

COMH_

BIT

RSVD

FCOMM

_DET

FTONE

_DET

HB_FAIL HB_FAST

RSVD

LFO

DED_

DET

SEC_DET CUST_

CRC

FACT_

CRC

CUSTLD FACTLD

ERR

GBLOV

ERR

FAULT_SYS

536

53A

R

0x00

RSVD

GPIO

DRST

CTL

CTS

TSHUT

TWARN

FAULT_PROT1

RSVD

TPARITY VPARITY

_FAIL _FAIL

FAULT_PROT2

FAULT_OV1

53B

53C

R

0x00

RSVD

BIST_

ABORT

TPATH

_FAIL

VPATH

_FAIL

UTCOMP OTCOMP OVCOMP UVCOMP

_FAIL

OV16_

DET

OV15_

DET

OV14_

DET

OV13_

DET

OV12_

DET

OV11_

DET

OV10_ OV9_DET

DET

FAULT_OV2

FAULT_UV1

53D

53E

R

0x00 OV8_DET OV7_DET OV6_DET OV5_DET OV4_DET OV3_DET OV2_DET OV1_DET

0x00

UV16_

DET

UV15_

DET

UV14_

DET

UV13_

DET

UV12_

DET

UV11_

DET

UV10_

DET

UV9_DET

FAULT_UV2

FAULT_OT

FAULT_UT

53F

540

541

543

R

0x00 UV8_DET UV7_DET UV6_DET UV5_DET UV4_DET UV3_DET UV2_DET UV1_DET

0x00 OT8_DET OT7_DET OT6_DET OT5_DET OT4_DET OT3_DET OT2_DET OT1_DET

0x00 UT8_DET UT7_DET UT6_DET UT5_DET UT4_DET UT3_DET UT2_DET UT1_DET

FAULT_COMP_G

PIO

0x00

GPIO8_

FAIL

GPIO7_

FAIL

GPIO6_

FAIL

GPIO5_

FAIL

GPIO4_

FAIL

GPIO3_

FAIL

GPIO2_

FAIL

GPIO1_

FAIL

FAULT_COMP_V

CCB1

545

546

548

R

0x00 CELL16_ CELL15_ CELL14_ CELL13_ CELL12_ CELL11_ CELL10_ CELL9_

FAIL

FAULT_COMP_V

CCB2

0x00

CELL8_

FAIL

CELL7_

FAIL

CELL6_

FAIL

CELL5_

FAIL

CELL4_

FAIL

CELL3_

FAIL

CELL2_

FAIL

CELL1_

FAIL

FAULT_COMP_V

COW1

0x00 VCOW16 VCOW15 VCOW14 VCOW13 VCOW12 VCOW11 VCOW10 VCOW9

_FAIL _FAIL _FAIL _FAIL _FAIL _FAIL _FAIL _FAIL

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Register Name

Data

Addr RW Reset

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

FAULT_COMP_V

COW2

549

R

0x00

VCOW8

_FAIL

VCOW7

_FAIL

VCOW6

_FAIL

VCOW5

_FAIL

VCOW4

_FAIL

VCOW3

_FAIL

VCOW2

_FAIL

VCOW1

_FAIL

FAULT_COMP_VB 54B

OW1

0x00 CBOW16 CBOW15 CBOW14 CBOW13 CBOW12 CBOW11 CBOW10 CBOW9

_FAIL

FAULT_COMP_VB 54C

OW2

0x00

CBOW8

_FAIL

CBOW7

_FAIL

CBOW6

_FAIL

CBOW5

_FAIL

CBOW4

_FAIL

CBOW3

_FAIL

CBOW2

_FAIL

CBOW1

_FAIL

FAULT_COMP_C

BFET1

54E

0x00 CBFET16 CBFET15 CBFET14 CBFET13 CBFET12 CBFET11 CBFET10 CBFET9

_FAIL _FAIL _FAIL _FAIL _FAIL _FAIL _FAIL _FAIL

FAULT_COMP_C

BFET2

54F

0x00

CBFET8 CBFET7 CBFET6 CBFET5 CBFET4 CBFET3 CBFET2 CBFET1

_FAIL

FAULT_COMP_MI 550

SC

0x00

RSVD

COMP_ LPF_FAIL

ADC_

ABORT

FAULT_PWR1

FAULT_PWR2

FAULT_PWR3

CB_COMPLETE1

CB_COMPLETE2

BAL_TIME

552

553

554

556

557

558

R

0x00

RSVD

0x00

CVSS_

OPEN

DVSS_

OPEN

REFHM_

OPEN

CVDD_

UV

CVDD_

OV

DVDD_

OV

AVDD_

OSC

AVDD_

OV

RSVD

PWRBIST

_FAIL

RSVD

REFH_

OSC

NEG5V_ TSREF_ TSREF_ TSREF_

UV

OSC

UV

OV

RSVD

AVDDUV

_DRST

CELL16

_DONE

CELL15

_DONE

CELL14

_DONE

CELL13

_DONE

CELL12

_DONE

CELL11

_DONE

CELL10

_DONE

CELL9

_DONE

CELL8

_DONE

CELL7

_DONE

CELL6

_DONE

CELL5

_DONE

CELL4

_DONE

CELL3

_DONE

CELL2

_DONE

CELL1

_DONE

0x00 TIME_UNI

T

TIME[6:0]

VCELL16_HI/LO

568

569

56A

56B

56C

56D

56E

56F

570

571

572

573

574

575

576

577

578

579

57A

57B

57C

57D

57E

57F

R

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

RESULT[7:0]

VCELL15_HI/LO

VCELL14_HI/LO

VCELL13_HI/LO

VCELL12_HI/LO

VCELL11_HI/LO

VCELL10_HI/LO

VCELL9_HI/LO

VCELL8_HI/LO

VCELL7_HI/LO

VCELL6_HI/LO

VCELL5_HI/LO

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Bit1 Bit0

Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

VCELL4_HI/LO

VCELL3_HI/LO

VCELL2_HI/LO

VCELL1_HI/LO

BUSBAR_HI/LO

TSREF_HI/LO

GPIO1_HI/LO

GPIO2_HI/LO

GPIO3_HI/LO

GPIO4_HI/LO

GPIO5_HI/LO

GPIO6_HI/LO

GPIO7_HI/LO

GPIO8_HI/LO

580

581

582

583

584

585

586

587

588

589

58C

58D

58E

58F

590

591

592

593

594

595

596

597

598

599

59A

59B

59C

59D

R

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

RESULT[7:0]

DIETEMP1_HI/LO 5AE

5AF

DIETEMP2_HI/LO 5B0

5B1

AUX_CELL_HI/LO 5B2

5B3

AUX_GPIO_HI/LO 5B4

5B5

AUX_BAT_HI/LO

5B6

5B7

AUX_REFL_HI/LO 5B8

5B9

AUX_VBG2_HI/LO 5BA

5BB

AUX_AVAO_REF_ 5BE

HI/LO

5BF

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Register Name

Data

Addr RW Reset

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AUX_AVDD_REF_ 5C0

R

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

0x80

0x00

RESULT[7:0]

HI/LO

5C1

RESULT[7:0]

AUX_OV_DAC_HI 5C2

/LO

5C3

AUX_UV_DAC_HI/ 5C4

LO

5C5

AUX_OT_OTCB_

DAC_HI/LO

5C6

5C7

AUX_UT_DAC_HI/ 5C8

LO

5C9

AUX_VCBDONE_ 5CA

DAC_HI/LO

5CB

AUX_VCM_HI/LO

5CC

5CD

5D0

5D1

5D2

5D3

REFOVDAC_HI/L

O

DIAG_MAIN_HI/L

O

DIAG_AUX_HI/LO 5D4

5D5

DEBUG_COMM_S 780

TAT

0x33

for

base

0x3F

for

RSVD

HW_

UART_

DRV

HW_

DAISY_

DRV

COML_

TX_ON

COML_

RX_ON

COMH_

TX_ON

COMH_

RX_ON

stack

DEBUG_UART_R

C

781

782

783

R

0x00

RC_IERR

RC_

RC_SOF

RC_

BYTE_

ERR

RC_

UNEXP

RC_CRC

RR_CRC

TXDIS

DEBUG_UART_R

R_TR

0x00

RSVD

TR_SOF TR_WAIT RR_SOF

RR_

BYTE_

ERR

T

R

0x00

PERR

BERR_

TAG

SYNC2

SYNC1

BIT

DEBUG_COMH_R 784

C

RSVD

RC_IERR

TR_WAIT

RC_

RC_SOF

RC_

BYTE_

ERR

RC_

RC_CRC

TXDIS

UNEXP

DEBUG_COMH_R 785

R_TR

R

0x00

RR_

RR_SOF

RR_

BYTE_

ERR

RR_

RR_CRC

TXDIS

UNEXP

DEBUG_COML_BI 786

T

R

0x00

RSVD

PERR

BERR_

TAG

SYNC2

SYNC1

BIT

DEBUG_COML_R 787

C

RSVD

RC_IERR

TR_WAIT

RC_

TXDIS

RC_SOF

RC_

BYTE_

ERR

RC_

UNEXP

RC_CRC

DEBUG_COML_R 788

R_TR

R

0x00

RR_

TXDIS

RR_SOF

RR_

BYTE_

ERR

RR_

UNEXP

RR_CRC

DEBUG_UART_DI 789

SCARD

R

0x00

COUNT[7:0]

DEBUG_COMH_D 78A

ISCARD

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Bit1 Bit0

Data

Addr RW Reset

Register Name

Hex Type Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

DEBUG_COML_D 78B

ISCARD

R

0x00

COUNT[7:0]

DEBUG_UART_V

ALID_HI/LO

78C

78D

R

0x00

COUNT[7:0]

BLOCK[7:0]

DEBUG_COMH_V 78E

ALID_HI/LO

78F

DEBUG_COML_V 790

ALID_HI/LO

791

DEBUG_OTP_SE

C_BLK

7A0

7A1

DEBUG_OTP_DE

D_BLK

R

0x00

BLOCK[7:0]

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9.5.4 Register Field Descriptions

9.5.4.1 Device Addressing Setup

9.5.4.1.1 DIR0_ADDR_OTP

Address

NVM

0x0000

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE[1:0]

ADDRESS[5:0]

0

SPARE[1:0] = Spare

ADDRESS[5:0] = This register shows the default device address used when [DIR_SEL] = 0 and programmed in the OTP. Writing to

this register won’t change the device address actively in use.

This register is used for the system to program the device address to OTP, which will be loaded to the

DIR0_ADDR register at POR. For programming, follow the OTP programming procedure.

9.5.4.1.2 DIR1_ADDR_OTP

Address

NVM

0x0001

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE[1:0]

ADDRESS[5:0]

0

SPARE[1:0] = Spare

ADDRESS[5:0] = This register shows the default device address used when [DIR_SEL] = 1 and programmed in the OTP. Writing to

this register won’t change the device address actively in use.

This register is used for the system to program the device address to OTP, which will be loaded to the

DIR1_ADDR register at POR. For programming, follow the OTP programming procedure.

9.5.4.1.3 CUST_MISC1 through CUST_MISC8

Address 0x0021 to

0x0028

NVM

Name

Reset

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DATA[7:0]

0

DATA[7:0] = Customer scratch pad

9.5.4.1.4 DIR0_ADDR

Address

RW

0x0306

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

ADDRESS[5:0]

0

RSVD = Reserved

ADDRESS[5:0] = Always shows the current device address used by the device when [DIR_SEL] = 0. At POR, this register is

loaded from the device address value in the OTP (same OTP device address loaded to DIR0_ADDR_OTP

register). Host can re-address the device by writing a different device address to this register, and the device will

take on the new address immediately.

Note: CONTROL1[ADDR_WR] = 1 is required to write to this register. See 节9.5.4.3.11 for details.

9.5.4.1.5 DIR1_ADDR

Address

RW

0x0307

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

ADDRESS[5:0]

0

RSVD = Reserved

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ADDRESS[5:0] = Always shows the current device address used by the device when [DIR_SEL] = 1. At POR, this register is loaded

from the device address value in the OTP (same OTP device address loaded to DIR1_ADDR_OTP register). Host

can re-address the device by writing a different device address to this register, and the device will take on the new

address immediately.

Note: CONTROL1[ADDR_WR] = 1 is required to write to this register. See 节9.5.4.3.11 for details.

9.5.4.2 Device ID and Scratch Pad

9.5.4.2.1 PARTID

Address

0x0500

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

PARTID[7:0]

0

PARTID[7:0] Device Identification:

= 0x21 = BQ79616

0x01 = BQ79614

0x02 = BQ79612

0x03 = BQ75614

0x04 = BQ79656

0x05 = BQ79654

0x06 = BQ79652

0x0A = BQ756506

All other codes = Reserved

9.5.4.2.2 DEV_REVID

Address

Read Only

Reset

0xE00

Bit7

0

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0

A value of 0x00 indicates that the device is in normal operating mode. If a fault activates the Factory Testmode Detection,

the value will be non-zero. Refer Safety Manual for details on SM426: Fact Testmode Detection.

9.5.4.2.3 DIE_ID1 through DIE_ID9

Address

0x0501

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

ID[7:0]

0

ID[7:0] = Device Revision

0x10 = Revision A0

0x11 = Revision A1

0x20 = Revision B0

0x21 = Revision B1

0x22 = Revision B2

All other codes = Reserved

Address 0x0502 to

0x0509

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

ID[7:0]

0

ID[7:0] = Die ID for TI factory use

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9.5.4.3 General Configuration and Control

9.5.4.3.1 DEV_CONF

Address

NVM

0x0002

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

NO_ADJ_CB MULTIDROP FCOMM_EN

_EN

TWO_STOP

_EN

NFAULT_EN

FTONE_EN

HB_EN

Reset

0

1

0

1

0

1

0

RSVD = Reserved

NO_ADJ_CB = Indicates the device will not allow an adjacent CB FET to be turned on in manual CB control. If MCU has enabled

an adjacent CB FET, device will not start CB even if host sends [BAL_GO] = 1.

0 = Device will allow two adjacent CB FETs to be enabled.

1 = Device will not allow adjacent CB FET to be enabled.

MULTIDROP_EN = Defines if the device is used in a multidrop or daisy chain configuration. The TX and RX for COML and COMH will

be enabled or disabled based on the configuration.

0 = Daisy chain of base device

1 = Multidrop

FCOMM_EN = Enables the fault state detection through communication in ACTIVE mode.

0 = Disable

1 = Enable

TWO_STOP_EN = Enables two stop bits for the UART in case of severe oscillator error in the host and device.

0 = One STOP bit

1 = Two STOP bits

NFAULT_EN = Enables the NFAULT function.

0 = NFAULT always pulled up

1 = NFAULT pulled low to indicate an unmasked fault is detected.

Note: This bit setting does not affect the FAULT_SUMMARY register.

FTONE_EN = Enables FAULT TONE transmitter when device is in SLEEP mode.

0 = Disable

1 = Enable

HB_EN = Enables HEARTBEAT transmitter when device is in SLEEP mode.

0 = Disable

1 = Enable

9.5.4.3.2 ACTIVE_CELL

Address

NVM

0x0003

Bit 7

Bit 6

Bit 5

SPARE[3:0]

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

NUM_CELL[3:0]

0

1

0

1

0

Factory

OTP

Reset

SPARE[3:0] = Spare

NUM_CELL[3:0] = Configures the number of cells in series.

0x0 = 6S

0x1 = 7S

0x2 = 8S

:

0xA = 16S

Unused code defaults to CHIP_TYPE[MAX_CH1:0] setting (in factory trim).If the NUM_CELL setting has more

channels than the device offers, it would be capped to higest number of channel the device offers.

9.5.4.3.3 BBVC_POSN1

Address

NVM

0x0005

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CELL16

CELL15

CELL14

CELL13

CELL12

CELL11

CELL10

CELL9

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Reset

0

CELL9 to CELL16 = This register specifies which channel is connected with a bus bar. The cell voltage measurement diagnostic

comparison will handle those channel differently

0 = No special handling

1 = Special handling of the enabled channel(s). See 节9.3.7 for details.

9.5.4.3.4 BBVC_POSN2

Address

NVM

0x0006

Bit 7

CELL8

0

Bit 6

CELL7

0

Bit 5

CELL6

0

Bit 4

CELL5

0

Bit 3

CELL4

0

Bit 2

CELL3

0

Bit 1

CELL2

0

Bit 0

CELL1

0

Name

Reset

CELL1 to CELL8 = Among the active cells specified by the ACTIVE_CELL register, this register indicates which active channel is

excluded from the OV, UV and VCB_DONE monitoring. This register information is also used for cell voltage

measurement diagnostic comparison.

0 = No special handling of the functions mentioned above.

1 = Special handling of the functions mentioned above. See 节9.3.7 for details.

9.5.4.3.5 PWR_TRANSIT_CONF

Address

NVM

0x0018

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE[2:0]

TWARN_THR[1:0]

SLP_TIME[2:0]

0

1

0

Factory

Configura

tion

default

SPARE[2:0] = Spare

TWARN_THR[1:0] = Sets the TWARN threshold.

00 = 85°C

01 = 95°C

10 = 105°C (default)

11 = 115°C

SLP_TIME[2:0] = A timeout in SLEEP mode. This timer starts counting when device enters SLEEP mode. When the timer expires,

the device enters SHUTDOWN mode. The timer resets if device wakes up to ACTIVE mode.

000 = No timeout. Device remains in SLEEP mode (default at reset)

001 = 5 s

010 = 10 s

011 = 1 min

100 = 10 min

101 = 30 min

110 = 1 hour

111 = 2 hour

9.5.4.3.6 COMM_TIMEOUT_CONF

Address

NVM

0x0019

Bit 7

SPARE

0

Bit 6

Bit 5

Bit 4

Bit 3

CTL_ACT

0

Bit 2

Bit 1

Bit 0

Name

Reset

CTS_TIME[2:0]

0

CTL_TIME[2:0]

0

SPARE = Spare

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CTS_TIME[2:0] = Sets the short communication timeout. When this timer expires, the device sets the FAULT_SYS[CTL] bit. This

can be used as an alert to the system to prevent a long communication timeout.

000 = Disables short communication timeout (default at reset)

001 = 100 ms

010 = 2 s

011 = 10 s

100 = 1 min

101 = 10 min

110 = 30 min

111 = 1 hr

CTL_ACT = Configures the device action when long communication timeout timer expires.

0 = Sets FAULT_SYS[CTL] and sends device to SLEEP mode (default at reset)

1 = Sends the device to SHUTDOWN. FAULT_SYS[CTL] bit will not be set.

CTL_TIME[2:0] = Sets the long communication timeout. When this timer expires, the device takes the action configured by the

[CTL_ACT] bit.

000 = Disables long communication timeout (default at reset)

001 = 100 ms

010 = 2 s

011 = 10 s

100 = 1 min

101 = 10 min

110 = 30 min

111 = 1 hr

9.5.4.3.7 TX_HOLD_OFF

Address

NVM

0x001A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

DLY[7:0]

0

DLY[7:0] = Sets the number of bit periods from 0 to 255 to delay after receiving the STOP bit of a command frame and

before transmitting the 1st bit of response frame.

9.5.4.3.8 STACK_RESPONSE

Address

NVM

0x0029

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE[1:0]

DELAY[5:0]

0

DELAY[5:0] Add additional byte delay gap in daisy chain data response frame

= 0x00 = 0-µs

0x01 to 0x3F = 0.25-µs to 15.75-µs in 0.25us step

9.5.4.3.9 BBP_LOC

Address

NVM

0x002A

Bit 7

Bit 6

SPARE[3:0]

0

Bit 5

Bit 4

Bit 3

Bit 2

LOC[4:0]

0

Bit 1

Bit 0

Name

Reset

0

LOC[4:0] = Indicate the BBP pin location and show which VC channel the BB channel is sharing with. This information is

used for correcting the common mode error during BB channel ADC measurement

0x00 = BBP/N not in used

0x01 = BBP to negative side of Cell2, BBN to VC1

0x02 = BBP to negative side of Cell3, BBN to VC2

0x03 = BBP to negative side of Cell4, BBN to VC3

:

0x0F = BBP to negative side of Cell16, BBN to VC15

0x10= BBP to VC16, BBN to positive side of Cell16

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9.5.4.3.10 COMM_CTRL

Address

RW

0x0308

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

STACK_DEV TOP_STACK

0

RSVD = Reserved

STACK_DEV = Defines device as a base or stack device in daisy chain configuration.

0 = Base device

1 = Stack device

TOP_STACK = Defines device as highest addressed device in the stack.

0 = Not the ToS device

1 = Is the ToS device

9.5.4.3.11 CONTROL1

Address

RW

0x0309

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

DIR_SEL

SEND_

SHUTDOWN

SEND_WAKE

SEND_

SLPTOACT

GOTO_

SHUTDOWN

GOTO_

SLEEP

SOFT_RESET

ADDR_WR

Reset

0

DIR_SEL = Selects daisy chain communication direction.

0 = With two devices connected in daisy chain, command frame travels from COMH of the lower device to COML

of the next device.

1 = With two devices connected in daisy chain, command frame travels from COML of the lower device to COMH

of the next device.

SEND_SHUTDOWN = Sends SHUTDOWN tone to next device up the stack. The device receiving this bit set is unaffected. Bit is self-

cleared.

0 = Ready

1 = Send SHUTDOWN tone up the stack

SEND_WAKE = Sends WAKE tone to next device up the stack. Bit is self-cleared.

0 = Ready

1 = Send WAKE tone to next device up the stack.

SEND_SLPTOACT = Sends SLEEPtoACTIVE tone up the stack. Bit is self-cleared.

0 = Ready

1 = Send SLEEPtoACTIVE tone up the stack

GOTO_SHUTDOWN = Transitions device to SHUTDOWN mode. Bit is self-cleared.

0 = Ready

1 = Enter SHUTDOWN mode

GOTO_SLEEP = Transitions device to SLEEP mode. Bit is self-cleared.

0 = Ready

1 = Enter SLEEP mode

SOFT_RESET = Resets the digital to OTP default. Bit is self-cleared. Setting this bit will cause the device to generate WAKE tone

to the upper stack devices.

0 = Ready

1 = Reset device

ADDR_WR = Enables device to start auto-addressing. When this bit is set, device will not forward the first transition it receives,

allowing the device address to be written to a single device. See 节9.3.6.1.3.2 for details.

0 = Not performing auto-address. Device forwards communication transaction as normal.

1 = Device is being auto-addressed; the first communication transaction it receives will not be forwarded.

Host should not write multiple bits at the same to CONTROL1 register. The following shows the priority behavior

if multiple bits are written at the same write command to CONTROL1

• Power States:

– [SOFT_RESET] : Priority 1

– [GOTO_SHUTDOWN]: Priority 2

– [GOTO_SLEEP]: Priority 3

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• SEND tone:

– [SEND_WAKE]: Priority 1

– [SEND_SLPTOACT]: Priority 2

– [SEND_SD_HW_RST]: Priority 3

• Between the Power State bits and SEND tone bits:

– Power Stat bits: Priority 1

– SEND tone bits: Priority 2

9.5.4.3.12 CONTROL2

Address

RW

0x030A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

SEND_HW_

RESET

TSREF_EN

Reset

0

RSVD = Reserved

SEND_HW_RESET = Sends HW_RESET tone up the stack. Bit is cleared on read.

0 = Ready

1 = Send HW_RESET tone to next stack device up

TSREF_EN = Enables TSREF LDO output. Used to bias NTC thermistor.

0 = Disabled

1 = Enabled

9.5.4.3.13 CUST_CRC_HI

Address

NVM

0x0036

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CRC[7:0]

0

1

0

1

0

1

0

1

0

1

Factory

Configura

tion

Reset

CRC[7:0] = High-byte of the host-calculated CRC for customer OTP space.

9.5.4.3.14 CUST_CRC_LO

Address

NVM

0x0037

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CRC[7:0]

1

0

1

0

1

0

1

0

1

Factory

Configura

tion

Reset

CRC[7:0] = Low-byte of the host-calculated CRC for customer OTP space.

9.5.4.3.15 CUST_CRC_RSLT_HI

Address

0x050C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CRC[7:0]

0

1

0

1

CRC[7:0] = High-byte of the device-calculated CRC for customer OTP space.

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9.5.4.3.16 CUST_CRC_RSLT_LO

Address

0x050D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CRC[7:0]

1

0

1

CRC[7:0] = Low-byte of the device-calculated CRC for customer OTP space.

9.5.4.4 Operation Status

9.5.4.4.1 DIAG_STAT

Address

0x0526

Bit 7

Read

Only

Bit 6

RSVD

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

DRDY_OTUT DRDY_OVUV DRDY_BIST

_OTUT

DRDY_BIST

_OVUV

DRDY_BIST

_PWR

Reset

0

RSVD = Reserved

DRDY_OTUT = Indicates the OTUT round robin has run at least once. This bit is cleared when [OTUT_GO] = 1 with

[OTUT_MODE1:0] = 01 (start the OTUT round robin run) and set when at least 1 cycle of round robin is

completed.

0 = OTUT has not started or first round robin has not completed yet.

1 = At least 1 cycle of round robin has completed.

DRDY_OVUV = Indicates the OVUV round robin has at least run once. This bit is cleared when [OVUV_GO] = 1 with

[OVUV_MODE1:0] = 01 (start the OVUV round robin run) and set when at least 1 cycle of round robin is

completed.

0 = OVUV has not started or first round robin has not completed yet.

1 = At least 1 cycle of round robin has completed.

DRDY_BIST_OTUT = Indicates the status of the OTUT protector diagnostic. This bit is cleared when [OTUT_GO] = 1 with

[OTUT_MODE1:0] = 10 (start the BIST run) and set when the BIST cycle is completed.

0 = Not started or still running.

1 = BIST cycle completed.

DRDY_BIST_OVUV = Indicates the status of the OVUV protector diagnostic. This bit is cleared when [OVUV_GO] = 1 with

[OVUV_MODE1:0] = 10 (start the BIST run) and set when the BIST cycle is completed.

0 = Not started or still running.

1 = BIST cycle completed.

DRDY_BIST_PWR = Indicates the status of the power supplies diagnostic. This bit is cleared when [PWR_BIST_GO] = 1 (start the

BIST run) and set when the BIST cycle is completed.

0 = Not started or still running.

1 = BIST cycle completed.

9.5.4.4.2 ADC_STAT1

Address

0x0527

Bit 7

Read

Only

Bit 6

RSVD

0

Bit 5

Bit 4

RSVD

0

Bit 3

Bit 2

Bit 1

Bit 0

Name

DRDY_AUX

_GPIO

DRDY_AUX

_CELL

DRDY_AUX

_MISC

DRDY_MAIN

_ADC

Reset

0

RSVD = Reserved

DRDY_AUX_GPIO = AUX ADC has completed at least a single measurement on all active GPIO channels configured for ADC

measurement. This bit is cleared when [AUX_GO] is changed from 0 to 1.

0 = Not ready

1 = All GPIO inputs have completed at least a single measurement by the AUX ADC

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DRDY_AUX_CELL = Device has completed at least a single measurement on all AUXCELL channel(s) set by [AUX_CELL_SEL4:0].

This bit is cleared when [AUX_GO] is changed from 0 to 1.

0 = Not ready

1 = All [AUX_CELL_SEL4:0] configured channels have completed at least a single measurement

DRDY_AUX_MISC = Device has completed at least a single measurement on all AUX ADC MISC input channels (that is, completed a

single round robin run). This bit is cleared when [AUX_GO] is changed from 0 to 1.

0 = Not ready

1 = All AUX ADC MISC inputs have completed at least a single measurement

DRDY_MAIN_ADC = Device has completed at least a single measurement on all Main ADC input channels, including all GPIOs (that is,

completed a single round robin run). This bit is cleared when [MAIN_GO] is changed from 0 to 1.

0 = Not ready

1 = All Main ADC inputs have completed at least a single measurement

9.5.4.4.3 ADC_STAT2

Address

0x0528

Bit 7

Read

Only

Bit 6

Bit 5

DRDY_LPF

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DRDY_VCCB

0

Name

RSVD

DRDY_GPIO DRDY_VCOW DRDY_CBOW

DRDY_

CBFET

Reset

0

RSVD = Reserved

DRDY_LPF = Device has finished at least 1 round of LPF checks on all active cell channels. The comparison continues in the

background as long as the Main ADC is running. This bit is cleared when [MAIN_GO] = 1.

This data ready bit is also used when a fault is injected to test the DIAG_LPF engine using the [LPF_FLT_INJ] bit.

When [LPF_FLT_INJ] = 1, this bit is cleared to 0 and the device will restart the VC and BB and BB channel LPF

checks from the beginning using the fault inject [DIAG_LPF]. Once all channel LPFs are checked, the

[DRDY_LPF] = 1.

0 = Not ready

1 = Diagnostic comparison finished

DRDY_GPIO = Device has finished the GPIO Main and AUX ADC diagnostic comparisons on all active channels and the

comparisons are stopped. This bit is cleared when [COMP_ADC_GO] = 1.

0 = Not ready

1 = Diagnostic comparison finished

DRDY_VCOW = Device has finished VC OW diagnostic comparison on all active channels and the comparison is stopped. This bit

is cleared when [COMP_ADC_GO] = 1.

0 = Not ready

1 = Diagnostic comparison finished

DRDY_CBOW = Device has finished CB OW diagnostic comparison on all active channels and the comparison is stopped. This bit

is cleared when [COMP_ADC_GO] = 1.

0 = Not ready

1 = Diagnostic comparison finished

DRDY_CBFET = Device has finished CB FET diagnostic comparison on all active channels and the comparison is stopped. This bit

is cleared when [COMP_ADC_GO] = 1.

0 = Not ready

1 = Diagnostic comparison finished

DRDY_VCCB = Device has finished VCELL vs. AUXCELL diagnostic comparison on all active channels. This bit is cleared when

[COMP_ADC_GO] = 1.

0 = Not ready

1 = Diagnostic comparison finished

9.5.4.4.4 GPIO_STAT

Address

Read Only

Name

0x052A

Bit 7

GPIO8

0

Bit 6

GPIO7

0

Bit 5

GPIO6

0

Bit 4

GPIO5

0

Bit 3

GPIO4

0

Bit 2

GPIO3

0

Bit 1

GPIO2

0

Bit 0

GPIO1

0

Reset

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GPIO1 through GPIO8 = When GPIO is configured as digital input or output, this register shows the GPIO status.

0 = Low

1 = High

9.5.4.4.5 BAL_STAT

Address

0x052B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

INVALID_

CBCONF

OT_PAUSE CB_INPAUSE

_DET

MB_RUN

CB_RUN

ABORTFLT

MB_DONE

CB_DONE

Reset

0

R

INVALID_CBCONF = Indicates CB is unable to start (after [BAL_GO] = 1) due to improper CB control settings. Incorrect settings

include:

•

More than eight cells are enabled for CB.

More than two adjacent cells are enabled for CB if DEVICE_CONF[NO_ADJ_CB] = 0.

Any adjacent cells are enabled for CB if DEVICE_CONF[NO_ADJ_CB] = 1.

This bit is updated every time [BAL_GO] = 1.

0 = Valid CB setting

1 = Invalid CB setting

OT_PAUSE_DET = Indicates the OTCB is detected if [OTCB_EN] = 1. The bit is also set if CB TWARN is detected, which will also

pause CB. Valid only after [BAL_GO] = 1

0 = No OTCB or CB TWARN is detected

1 = Any NTC thermistor measurement is greater than OTCB_THR[3:0] setting, or die (CBFET) temperature is

greater than CB TWARN

CB_INPAUSE = Indicates the cell balancing pause status.

0 = CB is running or not started

1 = Paused (can be caused by OTCB detection, or host sets [CB_PAUSE] = 1)

MB_RUN = Indicates module balancing, controlled by the device, is running. Only valid if MB_TIMER_CTRL is not 0x00 and

after [BAL_GO] = 1. Does not indicate the cell balancing status.

0 = Completed or not started

1 = Module balancing, controlled by the device, is running

CB_RUN = Indicates cell balancing is running. Only valid after [BAL_GO] = 1. Does not indicate the module balancing status.

This bit remains as 1 even if CB is in pause state.

0 = Completed or not started

1 = At least 1 cell is in active cell balancing

ABORTFLT = Indicates cell balancing is aborted due to detection of unmasked fault. Cleared when BAL_CTRL1[BAL_GO] = 1.

CB abort does not trigger if CB is in pause ([CB_INPAUSE] =1) even if an unmasked fault is detected. The abort

at fault function will resume if CB is no longer in pause state.

0 = Not aborted or cell balancing not running

1 = Aborted

MB_DONE = Indicates module balancing is completed. Cleared when BAL_CTRL1[BAL_GO] = 1.

0 = Module balancing is still running or has not started

1 = Module balancing completed

CB_DONE = Indicates all cell balancing is completed. Cleared when BAL_CTRL1[BAL_GO] = 1.

0 = Cell balancing is still running or has not started

1 = All cell balancing is completed

9.5.4.4.6 DEV_STAT

Address

0x052C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

OTUT_RUN

0

Bit 3

OVUV_RUN

0

Bit 2

RSVD

0

Bit 1

AUX_RUN

0

Bit 0

MAIN_RUN

0

Name

RSVD

0

FACT_CRC

_DONE

CUST_CRC

_DONE

Reset

0

RSVD = Reserved

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FACT_CRC_DONE = Indicates the status of the factory CRC state machine. This bit is set when the factory CRC is calculated and

verified internally at least once. A read from this register will clear this bit.

0 = Not complete

1 = Complete (cleared on read)

CUST_CRC_DONE = Indicates the status of the customer CRC state machine. This bit is set when the CRC is calculated and compared

to the CUST_CRC* registers at least once. A read from this register will clear this bit.

0 = Not complete

1 = Complete (cleared on read)

OTUT_RUN = Shows the status of the OTUT protector comparators. This bit is set when OTUT BIST starts. When BIST is

completed or aborted, the device will turn off the OT and UT comparators automatically, and then this bit will be

cleared).

0 = off (that is, OTUT is not started or when [OTUT_GO] = 1 and [OTUT_MODE1:0] = 0)

1 = on (that is, when [OTUT_GO] = 1 and [OTUT_MODE1:0] is non-zero)

OVUV_RUN = Shows the status of the OVUV protector comparators. This bit is set when OVUV BIST starts. When BIST is

completed or aborted, the device will turn off the OV and UV comparators automatically, and then this bit will be

cleared).

0 = off (that is, OVUV is not started or when [OVUV_GO] = 1 and [OVUV_MODE1:0] = 0)

1 = on (that is, when [OVUV_GO] = 1 and [OVUV_MODE1:0] is non-zero)

AUX_RUN = Shows the status of the AUX ADC.

0 = off

1 = on

MAIN_RUN = Shows the status of the Main ADC.

0 = off

1 = on

9.5.4.5 ADC Configuration and Control

9.5.4.5.1 ADC_CONF1

Address

NVM

0x0007

Bit 7

Bit 6

Bit 5

Bit 4

LPF_BB[2:0]

0

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

AUX_SETTLE[1:0]

LPF_VCELL[2:0]

0

AUX_SETTLE[1:0] = The AUXCELL configures the AUX CELL settling time. Each AUXCELL has to wait for the anti-aliasing filter (AAF)

settling time in order to consider as a valid measurement. These bits provide the option to use different AAF or

bypass an AAF to trade for a fast measurement.

00 = 4.3 ms

01 = 2.3 ms

10 = 1.3 ms

11 = Reserved

LPF_BB[2:0] = Configures the post main SAR ADC low-pass filter cut-off frequency for BBP/N measurement. Same options as

the LPF_VCELL[2:0].

LPF_VCELL[2:0] = Configures the post ADC low-pass filter cut-off frequency for VCELL measurement.

0x0 = 6.5 Hz (154 ms average)

0x1 = 13 Hz (77 ms average)

0x2 = 26 Hz (38 ms average)

0x3 = 53 Hz (19 ms average)

0x4 = 111 Hz (9 ms average)

0x5 = 240 Hz (4 ms average)

0x6 = 600 Hz (1.6 ms average)

0x7 = 240 Hz

9.5.4.5.2 ADC_CONF2

Address

NVM

0x0008

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE[1:0]

ADC_DLY[5:0]

0

SPARE[1:0] = Spare

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ADC_DLY[5:0] = If [MAIN_GO] bit is written to 1, bit Main ADC is delayed for this setting time before being enabled to start the

conversion. This setting synchronizes the start of Main ADC throughout the daisy-chained stack.

The option ranges from 0 µs (no delay) to 200 µs in 5-µs steps.

Undefined code = 0 µs (no delay)

9.5.4.5.3 MAIN_ADC_CAL1

Address

NVM

0x001B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

GAINL[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

GAINL[7:0] = Main ADC 25°C gain calibration result (lower 8-bit). If customer performs gain calibration during production flow,

the gain result can be programmed to OTP and will be sent to this gain register at device reset. The device

automatically applies this data during ADC correction step.

Range from -0.78125% to 0.7782% in 0.0031% steps.

9.5.4.5.4 MAIN_ADC_CAL2

Address

NVM

0x001C

Bit 7

GAINH

0

Bit 6

OFFSET[6:0]

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

0

GAINH Main ADC 25°C gain calibration result (MS bit). If customer performs gain calibration during production flow, the

gain result can be programmed to OTP and will be sent to this gain register at device reset. The device

automatically applies this data during ADC correction step.

Range from -0.78125% to 0.7782% in 0.0031% steps.

OFFSET[6:0] = Main ADC 25°C offset calibration result. If customer performs offset calibration during production flow, the offset

result can be programmed to OTP and will be sent to this offset register at device reset. The device automatically

applies this data during ADC correction step.

Range from -12.20703-mV to 12.01630-mV in 0.19073-mV steps

9.5.4.5.5 AUX_ADC_CAL1

Address

NVM

0x001D

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

GAINL[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

GAINL[7:0] = AUX ADC 25°C gain calibration result (lower 8-bit). If customer performs gain calibration during production flow,

the gain result can be programmed to OTP and will be sent to this gain register at device reset. The device

automatically applies this data during ADC correction step.

Range from -0.78125% to 0.7782% in 0.0031% steps.

9.5.4.5.6 AUX_ADC_CAL2

Address

NVM

0x001E

Bit 7

GAINH

0

Bit 6

OFFSET[6:0]

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

0

GAINH AUX ADC 25°C gain calibration result (MS bit). If customer performs gain calibration during production flow, the

gain result can be programmed to OTP and will be sent to this gain register at device reset. The device

automatically applies this data during ADC correction step.

Range from -0.78125% to 0.7782% in 0.0031% steps.

OFFSET[6:0] = AUX ADC 25°C offset calibration result. If customer performs offset calibration during production flow, the offset

result can be programmed to OTP and will be sent to this offset register at device reset. The device automatically

applies this data during ADC correction step.

Range from -12.20703-mV to 12.01630-mV in 0.19073-mV steps

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9.5.4.5.7 ADC_CTRL1

Address

RW

0x030D

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

LPF_BB_EN

LPF_VCELL

_EN

MAIN_GO

MAIN_MODE[1:0]

Reset

0

RSVD = Reserved

LPF_BB_EN = Enables digital low-pass filter post-ADC conversion. LPF applies to BBP/N measurements only. The cut-off

frequency is configured by ADC_CONFIG1[LPF_BB[2:0].

LPF_VCELL_EN = Enables digital low-pass filter post-ADC conversion. LPF applies to VCELL measurements only. The cut-off

frequency is configured by ADC_CONFIG1[LPF_VCELL[2:0].

MAIN_GO = Starts main ADC conversion. When this bit is written to 1, all Main ADC inputs are sampled. Once the Main ADC

is started, any change to the Main ADC control setting has no effect until this bit is written to 1 again. This bit is

cleared to 0 in read.

0 = Ready. Writing 0 has no effect

1 = Start Main ADC

MAIN_MODE[1:0] = Sets the Main ADC run mode. In continuous run, if user would like to stop ADC, user must read all the ADC

conversion results, then stop it. ADC results are not valid before ADC is reenabled next time.

00 = Main ADC not running

01 = Single run. Run the main ADC round robin 8 times and then stop

10 = Continuous run. Continuous running the Main ADC round robin until host sends command to stop

11 = Reserved

9.5.4.5.8 ADC_CTRL2

Address

RW

0x030E

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

AUX_CELL_A

LIGN

AUX_CELL_SEL[4:0]

Reset

0

RSVD = Reserved

AUX_CELL_ALIGN = Align the AUX ADC AUXCELL measurement to Main ADC CELL1 or CELL8

0 = Dynamic Alignment

1 = Align to Main ADC CELL8

AUX_CELL_SEL[4:0] = Selects which AUXCELL channel(s) will be multiplexed through the AUX ADC.

0x00 = Run all active cell channels set by ACTIVE_CELL_CONF register

0x01 = Lock to AUX Busbar (BBP-BBN)

0x02 = Lock to AUXCELL1

0x03 = Lock to AUXCELL2

0x04 = Lock to AUXCELL3

:

0x11 = Lock to AUXCELL16

0x12 to 0x1F = RSVD

NOTE: If inactive channel or RSVD code is selected, device will not perform AUX ADC conversion on the

AUXCELL slot and the AUX_CELL_HI/LO registers will be kept in reset value.

9.5.4.5.9 ADC_CTRL3

Address

RW

0x030F

Bit 7

RSVD

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

AUX_GO

0

Bit 1

Bit 0

Name

Reset

AUX_GPIO_SEL[3:0]

AUX_MODE[1:0]

0

RSVD = Reserved

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AUX_GPIO_SEL[3:0] = Selects which GPIO channel(s) will be multiplexed through the AUX ADC to use for temperature measurement

diagnostic. If this selection is not set to 0x00, the AUX ADC will lock onto a single GPIO channel and the

measurement result is output to the AUX_GPIO_HI/LO registers.

0x00 = AUX ADC cycles through all GPIO channel(s) that are configured as ADC only or ADC and OTUT.

0x01 = Lock to GPIO1

0x02 = Lock to GPIO2

:

0x08 = Lock to GPIO8

All other codes are RSVD.

NOTE: If GPIO is not configured for ADC measurement or RSVD codes are selected, device will not perform AUX

ADC conversion on the GPIO slot and the AUX_GPIO_HI/LO registers will be kept in reset value.

AUX_GO = Starts AUX ADC conversion. When this bit is written to 1, all AUX ADC inputs are sampled. Once the AUX ADC is

started, any change to the AUX ADC control setting has no effect until this bit is written to 1 again. This bit is

cleared to 0 in read.

0 = Ready. Writing 0 has no effect.

1 = Start AUX ADC

AUX_MODE[1:0] = Sets the Main ADC run mode. In continuous run, if user would like to stop ADC, user must read all the ADC

conversion results, then stop it. ADC results are not valid before ADC is reenabled next time.

00 = AUX ADC not running

01 = Single run. Run the AUX ADC round robin once and then stop.

10 = Continuous run. Continually run the AUX ADC round robin until host sends command to stop.

11 = 8-round-robin run to measure all eight GPIOs once.

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9.5.4.6 ADC Measurement Results

9.5.4.6.1 VCELL16_HI/LO

VCELL16_HI

Address 0x0568

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell16 voltage in 2s complement. When host reads this

register, the device locks the Cell16 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL16_LO

Address

0x0569

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell16 voltage in 2s complement.

9.5.4.6.2 VCELL15_HI/LO

VCELL15_HI

Address 0x056A

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell15 voltage in 2s complement. When host reads this

register, the device locks the Cell15 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL15_LO

Address

0x056B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell15 voltage in 2s complement.

9.5.4.6.3 VCELL14_HI/LO

VCELL14_HI

Address 0x056C

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

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RESULT[7:0] = The ADC measurement result of the high-byte of the Cell14 voltage in 2s complement. When host reads this

register, the device locks the Cell14 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL14_LO

Address

0x056D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell14 voltage in 2s complement.

9.5.4.6.4 VCELL13_HI/LO

VCELL13_HI

Address 0x056E

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell13 voltage in 2s complement. When host reads this

register, the device locks the Cell13 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL13_LO

Address

0x056F

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell13 voltage in 2s complement.

9.5.4.6.5 VCELL12_HI/LO

VCELL12_HI

Address 0x0570

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell12 voltage in 2s complement. When host reads this

register, the device locks the Cell12 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL12_LO

Address

0x0571

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

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RESULT[7:0] = The ADC measurement result of the low-byte of the Cell12 voltage in 2s complement.

9.5.4.6.6 VCELL11_HI/LO

VCELL11_HI

Address 0x0572

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell11 voltage in 2s complement. When host reads this

register, the device locks the Cell11 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL11_LO

Address

0x0573

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell11 voltage in 2s complement.

9.5.4.6.7 VCELL10_HI/LO

VCELL10_HI

Address 0x0574

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell10 voltage in 2s complement. When host reads this

register, the device locks the Cell10 voltage low-byte from updating until the high-byte and low-byte registers are

read.

VCELL10_LO

Address

0x0575

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell10 voltage in 2s complement.

9.5.4.6.8 VCELL9_HI/LO

VCELL9_HI

Address 0x0576

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

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RESULT[7:0] = The ADC measurement result of the high-byte of the Cell9 voltage in 2s complement. When host reads this register,

the device locks the Cell9 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL9_LO

Address

0x0577

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell9 voltage in 2s complement.

9.5.4.6.9 VCELL8_HI/LO

VCELL8_HI

Address 0x0578

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell8 voltage in 2s complement. When host reads this register,

the device locks the Cell8 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL8_LO

Address

0x0579

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell8 voltage in 2s complement.

9.5.4.6.10 VCELL7_HI/LO

VCELL7_HI

Address 0x057A

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell7 voltage in 2s complement. When host reads this register,

the device locks the Cell7 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL7_LO

Address

0x057B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell7 voltage in 2s complement.

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9.5.4.6.11 VCELL6_HI/LO

VCELL6_HI

Address 0x057C

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell6 voltage in 2s complement. When host reads this register,

the device locks the Cell6 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL6_LO

Address

0x057D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell6 voltage in 2s complement.

9.5.4.6.12 VCELL5_HI/LO

VCELL5_HI

Address 0x057E

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell5 voltage in 2s complement. When host reads this register,

the device locks the Cell5 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL5_LO

Address

Read Only

Name

0x057F

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell5 voltage in 2s complement.

9.5.4.6.13 VCELL4_HI/LO

VCELL4_HI

Address 0x0580

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell4 voltage in 2s complement. When host reads this register,

the device locks the Cell4 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL4_LO

Address

0x0581

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Bit 0

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell4 voltage in 2s complement.

9.5.4.6.14 VCELL3_HI/LO

VCELL3_HI

Address 0x0582

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell3 voltage in 2s complement. When host reads this register,

the device locks the Cell3 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL3_LO

Address

0x0583

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell3 voltage in 2s complement.

9.5.4.6.15 VCELL2_HI/LO

VCELL2_HI

Address 0x0584

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell2 voltage in 2s complement. When host reads this register,

the device locks the Cell2 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL2_LO

Address

0x0585

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell2 voltage in 2s complement.

9.5.4.6.16 VCELL1_HI/LO

VCELL1_HI

Address 0x0586

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

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Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the Cell1 voltage in 2s complement. When host reads this register,

the device locks the Cell1 voltage low-byte from updating until the high-byte and low-byte registers are read.

VCELL1_LO

Address

0x0587

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the Cell1 Voltage in 2s complement.

9.5.4.6.17 BUSBAR_HI/LO

BUSBAR_HI

Address

0x0588

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] =

The ADC measurement result of the high-byte of the differential bus bar pins (BBP –BBN) in 2s complement.

When host reads this register, the device locks the low-byte from updating until the high-byte and low-byte

registers are read.

BUSBAR_LO

Address

0x0589

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] =

The ADC measurement result of the low-byte of the differential bus bar pins (BBP –BBN) in 2s complement.

9.5.4.6.18 TSREF_HI/LO

TSREF_HI

Address

0x058C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The TSREF high-byte result from Main ADC. When host reads this register, the device locks the TSREF low-byte

from updating until the high-byte and low-byte registers are read.

TSREF_LO

Address

0x058D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The TSREF low-byte result from Main ADC

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9.5.4.6.19 GPIO1_HI/LO

GPIO1_HI

Address

0x058E

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO1. When host reads this register, the device locks the GPIO1

low-byte from updating until the high-byte and low-byte registers are read.

GPIO1_LO

Address

0x058F

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO1.

9.5.4.6.20 GPIO2_HI/LO

GPIO2_HI

Address

0x0590

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RESULT[7:0]

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO2. When host reads this register, the device locks the GPIO2

low-byte from updating until the high-byte and low-byte registers are read.

GPIO2_LO

Address

0x0591

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO2.

9.5.4.6.21 GPIO3_HI/LO

GPIO3_HI

Address

0x0592

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RESULT[7:0]

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO3. When host reads this register, the device locks the GPIO3

low-byte from updating until the high-byte and low-byte registers are read.

GPIO3_LO

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Address

0x0593

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO3.

9.5.4.6.22 GPIO4_HI/LO

GPIO4_HI

Address

0x0594

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RESULT[7:0]

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO4. When host reads this register, the device locks the GPIO4

low-byte from updating until the high-byte and low-byte registers are read.

GPIO4_LO

Address

0x0595

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO4.

9.5.4.6.23 GPIO5_HI/LO

GPIO5_HI

Address

Read Only

Name

0x0596

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RESULT[7:0]

Reset

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO5. When host reads this register, the device locks the GPIO5

low-byte from updating until the high-byte and low-byte registers are read.

GPIO5_LO

Address

0x0597

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO5.

9.5.4.6.24 GPIO6_HI/LO

GPIO6_HI

Address

0x0598

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RESULT[7:0]

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Reset

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO6. When host reads this register, the device locks the GPIO6

low-byte from updating until the high-byte and low-byte registers are read.

GPIO6_LO

Address

0x0599

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO6.

9.5.4.6.25 GPIO7_HI/LO

GPIO7_HI

Address

0x059A

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RESULT[7:0]

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO7. When host reads this register, the device locks the GPIO7

low-byte from updating until the high-byte and low-byte registers are read.

GPIO7_LO

Address

0x059B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO7.

9.5.4.6.26 GPIO8_HI/LO

GPIO8_HI

Address

0x059C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RESULT[7:0]

1

0

RESULT[7:0] = The ADC measurement high-byte result of the GPIO8. When host reads this register, the device locks the GPIO8

low-byte from updating until the high-byte and low-byte registers are read.

GPIO8_LO

Address

0x059D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement low-byte result of the GPIO8.

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9.5.4.6.27 DIETEMP1_HI/LO

DIETEMP1_HI

Address

0x05AE

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The DieTemp1 high-byte result from Main ADC. When host reads this register, the device locks the DIETEMP1

low-byte from updating until the high-byte and low-byte registers are read.

DIETEMP1_LO

Address

0x05AF

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The DieTemp1 low-byte (temperature used for ADC correction) result from Main ADC.

9.5.4.6.28 DIETEMP2_HI/LO

DIETEMP2_HI

Address

0x05B0

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The DieTemp2 high-byte result from AUX ADC. When host reads this register, the device locks the DIETEMP2

low-byte from updating until the high-byte and low-byte registers are read.

DIETEMP2_LO

Address

0x05B1

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The DieTemp2 low-byte (temperature used for ADC correction) result from AUX ADC

9.5.4.6.29 AUX_CELL_HI/LO

AUX_CELL_HI

Address

0x05B2

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The ADC measurement result of the high-byte of the AUXCELL voltage in 2s complement. These

AUX_CELL_HI/LO registers will only report AUXCELL voltage measurement if host configures

[AUX_CELL_SEL4:0] to lock to a single AUXCELL channel.

When host reads this register, the device locks the AUXCELL voltage low-byte from updating until the high-byte

and low-byte registers are read.

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AUX_CELL_LO

Address

0x05B3

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The ADC measurement result of the low-byte of the AUX cell voltage in 2s complement. These

AUX_CELL_HI/LO registers will only report AUXCELL voltage measurement if host configures

[AUX_CELL_SEL4:0] to lock to a single AUXCELL channel.

9.5.4.6.30 AUX_GPIO_HI/LO

AUX_GPIO_HI

Address

0x05B4

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The AUX ADC measurement high-byte result of the GPIO that is locked by the [AUXGPIO_SEL3:0] bits. When

host reads this register, the device locks the AUX_GPIO low-byte from updating until the high-byte and low-byte

registers are read.

AUX_GPIO_LO

Address

0x05B5

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The AUX ADC measurement low-byte result of the GPIO that is locked by the [AUXGPIO_SEL3:0] bits.

9.5.4.6.31 AUX_BAT_HI/LO

AUX_BAT_HI

Address

Read Only

Name

0x05B6

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the BAT pin measurement from AUX ADC. When host reads this register, the device locks

the AUX_BAT low-byte from updating until the high-byte and low-byte registers are read.

AUX_BAT_LO

Address

0x05B7

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The low-byte result of the BAT pin measurement from AUX ADC.

9.5.4.6.32 AUX_REFL_HI/LO

AUX_REFL_HI

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Address

0x05B8

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The high-byte result of the internal reference, REFL, measurement from AUX ADC. When host reads this register,

the device locks the AUX_REL low-byte from updating until the high-byte and low-byte registers are read.

AUX_REFL_LO

Address

0x05B9

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The low-byte result of the internal reference, REFL, measurement from AUX ADC.

9.5.4.6.33 AUX_VBG2_HI/LO

AUX_VBG2_HI

Address

0x05BA

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The high-byte result of the internal reference, VBG2, measurement from AUX ADC. When host reads this register,

the device locks the AUX_VBG2 low-byte from updating until the high-byte and low-byte registers are read.

AUX_VBG2_LO

Address

Read Only

Name

0x05BB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the internal reference, VBG2, measurement from AUX ADC.

9.5.4.6.34 AUX_AVAO_REF_HI/LO

AUX_AVAO_REF_HI

Address

0x05BE

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The high-byte result of the AVAO_REF measurement from AUX ADC. When host reads this register, the device

locks the AUX_AVAO_REF low-byte from updating until the high-byte and low-byte registers are read.

AUX_AVAO_REF_LO

Address

0x05BF

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

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Reset

0

RESULT[7:0] = The low-byte result of the AVAO_REF measurement from AUX ADC.

9.5.4.6.35 AUX_AVDD_REF_HI/LO

AUX_AVDD_REF_HI

Address

0x05C0

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

1

0

RESULT[7:0] = The high-byte result of the AVDD_REF measurement from AUX ADC. When host reads this register, the device

locks the AUX_AVDD_REF low-byte from updating until the high-byte and low-byte registers are read.

AUX_AVDD_REF_LO

Address

0x05C1

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

RESULT[7:0] = The low-byte result of the AVDD_REF measurement from AUX ADC.

9.5.4.6.36 AUX_OV_DAC_HI/LO

AUX_OV_DAC_HI

Address

Read Only

Name

0x05C2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the OV comparator DAC measurement, which is (0.8 x OV threshold), from AUX ADC.

When host reads this register, the device locks the AUX_OV_DAC low-byte from updating until the high-byte and

low-byte registers are read.

AUX_OV_DAC_LO

Address

Read Only

Name

0x05C3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the OV comparator DAC measurement, which is (0.8 x OV threshold), from AUX ADC.

9.5.4.6.37 AUX_UV_DAC_HI/LO

AUX_UV_DAC_HI

Address

Read Only

Name

0x05C4

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the UV comparator DAC measurement, which is (0.8 x UV threshold), from AUX ADC.

When host reads this register, the device locks the AUX_UV_DAC low-byte from updating until the high-byte and

low-byte registers are read.

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AUX_UV_DAC_LO

Address

Read Only

Name

0x05C5

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the UV comparator DAC measurement, which is (0.8 x UV threshold), from AUX ADC.

9.5.4.6.38 AUX_OT_OTCB_DAC_HI/LO

AUX_OT_OTCB_DAC_HI

Address

Read Only

Name

0x05C6

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the OT comparator (either OT or OTCB threshold based on [OTCB_THR_LOCK] setting)

DAC measurement from AUX ADC. When host reads this register, the device locks the AUX_OT_OTCB_DAC

low-byte from updating until the high-byte and low-byte registers are read.

AUX_OT_OTCB_DAC_LO

Address

Read Only

Name

0x05C7

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the OT comparator (either OT or OTCB threshold based on [OTCB_THR_LOCK] setting)

DAC measurement from AUX ADC.

9.5.4.6.39 AUX_UT_DAC_HI/LO

AUX_UT_DAC_HI

Address

Read Only

Name

0x05C8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the UT comparator DAC measurement from AUX ADC. When host reads this register, the

device locks the AUX_UT_DAC low-byte from updating until the high-byte and low-byte registers are read.

AUX_UT_DAC_LO

Address

Read Only

Name

0x05C9

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the UT comparator DAC measurement from AUX ADC.

9.5.4.6.40 AUX_VCBDONE_DAC_HI/LO

AUX_VCBDONE_DAC_HI

Address

Read Only

Name

0x05CA

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

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Reset

1

0

RESULT[7:0] = The high-byte result of the UV comparator (VCBDONE Threshold) DAC measurement from AUX ADC. When

host reads this register, the device locks the AUX_VCBDONE_DAC low-byte from updating until the high-byte

and low-byte registers are read.

AUX_VCBDONE_DAC_LO

Address

Read Only

Name

0x05CB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the UV comparator (VCBDONE Threshold) DAC measurement from AUX ADC.

9.5.4.6.41 AUX_VCM_HI/LO

AUX_VCM_HI

Address

Name

0x05CC

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the VCM (common mode voltage on Main ADC) measurement from AUX ADC. When host

reads this register, the device locks the AUX_VCM low-byte from updating until the high-byte and low-byte

registers are read.

AUX_VCM_LO

Address

Read Only

Name

0x05CD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the VCM (common mode voltage on Main ADC) measurement from AUX ADC.

9.5.4.6.42 REFOVDAC_HI/LO

REFOVDAC_HI

Address 0x05D0

Read Only

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of the recorded OVDAC reference voltage trimmed at factory.

REFOVDAC_LO

Address

Read Only

Name

0x05D1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of the recorded OVDAC reference voltage trimmed at factory.

9.5.4.6.43 DIAG_MAIN_HI/LO

DIAG_MAIN_HI

Address 0x05D2

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Read Only

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of reported Main ADC comparison value used in the diagnostic ADC comparison. Valid if the

diagnostic ADC comparison is run when a single channel is locked

DIAG_MAIN_LO

Address

Read Only

Name

0x05D3

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of reported Main ADC comparison value used in the diagnostic ADC comparison. Valid if the

diagnostic ADC comparison is run when a single channel is locked

9.5.4.6.44 DIAG_AUX_HI/LO

DIAG_AUX_HI

Address 0x05D4

Read Only

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

1

0

RESULT[7:0] = The high-byte result of reported AUX ADC comparison value used in the diagnostic ADC comparison. Valid if the

diagnostic ADC comparison is run when a single channel is locked

DIAG_AUX_LO

Address

Read Only

Name

0x05D5

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

RESULT[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

RESULT[7:0] = The low-byte result of reported AUX ADC comparison value used in the diagnostic ADC comparison. Valid if the

diagnostic ADC comparison is run when a single channel is locked

9.5.4.7 Balancing Configuration, Control and Status

9.5.4.7.1 CB_CELL16_CTRL through CB_CELL1_CTRL

Address 0x0318 to

0x0327

RW

Bit 7

Bit 6

RSVD

0

Bit 5

Bit 4

Bit 3

Bit 2

TIME[4:0]

0

Bit 1

Bit 0

Name

Reset

0

RSVD = Reserved

TIME[4:0] = Sets the timer for cell* balancing. The selection is sampled whenever [BAL_GO] = 1 is set by the host MCU.

0x00 = 0 s = stop balancing

0x01 = 10 s

0x02 = 30 s

0x03 = 60 s

0x04 = 300 s

0x05 to 0x10 = range from 10 min to 120 min in 10-min steps

0x11 to 0x1F = range from 150 min to 540 min in 30-min steps and 600 min

9.5.4.7.2 VMB_DONE_THRESH

Address

0x0328

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Bit 0

RW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Reset

RSVD

MB_THR[5:0]

0

1

RSVD = Reserved

MB_THR[5:0] = If MB_TIMER_CTRL is not 0x00 and BAT voltage is less than this threshold, the module balancing through

GPIO3 stops. The selection is sampled whenever [AUX_GO] = 1 is set by the host MCU.

Note: To use this option, MCU enables the AUX ADC first before sending [BAL_GO] = 1. A new threshold setting

will take effect if MCU resends [AUX_GO] = 1. It is not necessary to resend [BAL_GO] = 1 as balancing is already

running.

Range from 18 V to 65 V with 1-V steps. Unused codes default to 65 V.

9.5.4.7.3 MB_TIMER_CTRL

Address

RW

0x0329

Bit 7

Bit 6

RSVD

0

Bit 5

Bit 4

Bit 3

Bit 2

TIME[4:0]

0

Bit 1

Bit 0

Name

Reset

0

RSVD = Reserved

TIME[4:0] = Sets the timer for module balancing. The selection is sampled whenever [BAL_GO] = 1 is set by the host MCU.

0x00 = 0 s = stop balancing

0x01 = 10 s

0x02 = 30 s

0x03 = 60 s

0x04 = 300 s

0x05 to 0x10 = range from 10 min to 120 min in 10-min steps

0x11 to 0x1F = range from 150 min to 540 min in 30-min steps and 600 min

9.5.4.7.4 VCB_DONE_THRESH

Address

RW

0x032A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

CB_THR[5:0]

0

RSVD = Reserved

CB_THR[5:0] = If a cell voltage is less than this threshold, the cell balancing on that cell stops. This threshold setting applies to all

cells. The selection is sampled whenever [OVUV_GO] = 1 is set by the host MCU.

Note: To use the VCB_DONE detection feature, host sets this threshold, then issues [OVUV_GO] = 1 before

starting CB (that is, sending [BAL_GO] = 1).

To change the VCB_DONE threshold detection, set a new threshold then re-issue [OVUV_GO] = 1 for the new

threshold to take effect. It is not necessary to re-issue [BAL_GO] = 1 to restart balancing in this case.

Range from 2.45-V to 4-V with 25-mV steps, where

0x00 = Disables voltage based on CB_DONE comparison

0x01 = threshold of 2.45-V

0x3F = threshold of 4-V

9.5.4.7.5 OTCB_THRESH

Address

RW

0x032B

Bit 7

RSVD

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

COOLOFF[2:0]

0

OTCB_THR[3:0]

0

1

RSVD = Reserved

COOLOFF[2:0] = Sets the COOLOFF hysteresis (resume temperature = OTCB_THR - COOLOFF hysteresis) to resume CB when

BAL_CTRL1[OTCB_EN] = 1 and OTCB is detected. The MCU configures the corresponding GPIO(s) to the ADC

and OTUT option.

Range from 4% to 14% in steps of 2% sourced from TSREF regulator voltage..

Unused code is set to 14%.

Default Reset setting 4%.

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OTCB_THR[3:0] = Sets the OTCB threshold when BAL_CTRL1[OTCB_EN] = 1. The MCU configures the corresponding GPIO(s) to

the ADC and OTUT option.

Range from 10% to 24% in steps of 2% sourced from TSREF regulator voltage..

Unused code is set to 24%.

Default Reset setting 24%.

9.5.4.7.6 BAL_CTRL1

Address

RW

0x032E

Bit 7

Bit 6

Bit 5

RSVD

0

Bit 4

Bit 3

Bit 2

Bit 1

DUTY[2:0]

0

Bit 0

Name

Reset

0

RSVD = Reserved

DUTY[2:0] = Selection is sampled whenever [BAL_GO] = 1 is set by the host MCU.

0x0 = 5 s

0x1 = 10 s

0x2 = 30 s

0x3 = 60 s

0x4 = 5 min

0x5 = 10 min

0x6 = 20 min

0x7 = 30 min

9.5.4.7.7 BAL_CTRL2

Address

RW

0x032F

Bit 7

RSVD

0

Bit 6

Bit 5

Bit 4

OTCB_EN

0

Bit 3

Bit 2

Bit 1

BAL_GO

0

Bit 0

AUTO_BAL

0

Name

Reset

CB_PAUSE FLTSTOP_EN

BAL_ACT[1:0]

0

RSVD = Reserved

CB_PAUSE = Pauses cell balancing on all cells to allow diagnostics to run.

0 = Normal cell balancing operation

1 = Pause all cell balancing

FLTSTOP_EN = Stops cell or module balancing if unmasked fault occurs. The selection is sampled whenever [BAL_GO] = 1 is set

by the host MCU.

0 = Balancing is continuous regardless of fault condition (excluding thermal shutdown)

1 = All CB balancing stops when any unmasked fault occurs

OTCB_EN = Enables the OTCB detection during cell balancing. The selection is sampled whenever [BAL_GO] = 1 is set by

the host MCU.

0 = Disable OTCB detection

1 = Enable OTCB detection

BAL_ACT[1:0] = Controls the device action when the MB and CB are completed. These bits are samples whenever [BAL_GO] = 1

is set by the host MCU. The action is valid.

00 = No action

01 = Enters SLEEP

10 = Enters SHUTDOWN

11 = Reserved

BAL_GO = Starts cell or module balancing. When written to 1, all balancing configuration registers are sampled. Any change

to the configuration registers has no effect until this bit is written to 1 again. The bit is self-clearing.

0 = Ready

1 = Start balancing

AUTO_BAL = Selects between auto or manual cell balance control. The selection is sampled whenever [BAL_GO] = 1 is set by

the host MCU.

0 = Manual cell balancing

1 = Auto cell balancing

9.5.4.7.8 BAL_CTRL3

Address

0x0330

Bit 7

RW

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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Name

Reset

RSVD

BAL_TIME_SEL[3:0]

BAL_TIME_G

O

0

RSVD = Reserved

BAL_TIME_GO Instruct the device to report the selected CB channel (set by [BAL_TIME_SEL3:0]) remaining balancing time to

BAL_TIME register. This bit is self clearing.

BAL_TIME_SEL[3:0] = Select a single CB channel to report its remaining balancing time

0x0 = CB Channel 1

0x1 = CB Channel 2

:

0xF = CB Channel 16

9.5.4.7.9 CB_COMPLETE1

Address

0x0556

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CELL16_

DONE

CELL15_

DONE

CELL14_

DONE

CELL13_

DONE

CELL12_

DONE

CELL11_

DONE

CELL10_

DONE

CELL9_ DONE

0

Reset

0

CELL9_DONE to Cell balance completion for cell9 to cell16. This register is cleared when MCU sets [BAL_GO] = 1.

CELL16_DONE = 0 = Balancing on the particular cell is still running or has not started

1 = Balancing completed on the particular cell

9.5.4.7.10 CB_COMPLETE2

Address

Read Only

Name

0x0557

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CELL8_DO CELL7_DONE CELL6_DONE CELL5_DONE CELL4_DONE CELL3_DONE CELL2_DONE CELL1_DONE

NE

Reset

0

CELL1_DONE to Cell balance completion for cell1 to cell8. This register is cleared when MCU sets [BAL_GO] = 1.

CELL8_DONE = 0 = Balancing on the particular cell is still running or has not started

1 = Balancing completed on the particular cell

9.5.4.7.11 BAL_TIME

Address

Read Only

Name

0x0558

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

TIME[6:0]

0

Bit 2

Bit 1

Bit 0

TIME_UNIT

0

Reset

0

TIME_UNIT = Indicates the unit reported by[TIME6:0]

0 = sec

1 = min

TIME[6:0] = Report the selected CB channel remaining balancing time

If [TIME_UNIT] = 0. Time report in sec with 5sec step

If [TIME_UNIT] = 1. Time report in min with 5min step

9.5.4.8 Protector Configuration and Control

9.5.4.8.1 OV_THRESH

Address

NVM

0x0009

Bit 7

SPARE

0

Bit 6

SPARE

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OV_THR[5:0]

1

SPARE = Spare

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OV_THR[5:0] = Sets the overvoltage threshold for the OV comparator. Changes on these bits require host to send another

[OVUV_GO] = 1 command.

All settings are at 25-mV steps.

0x02 to 0x0E: range from 2700 mV to 3000 mV

0x12 to 0x1E: range from 3500 mV to 3800 mV

0x22 to 0x2E: range from 4175 mV to 4475 mV

All other settings will default to 2700 mV.

9.5.4.8.2 UV_THRESH

Address

NVM

0x000A

Bit 7

Bit 6

SPARE

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

SPARE

0

UV_THR[5:0]

0

SPARE = Spare

UV_THR[5:0] = Sets the undervoltage threshold for the UV comparator. Changes on these bits require host to send another

[OVUV_GO] = 1 command.

All settings are at 50-mV steps.

0x00 to 0x26: range from 1200 mV to 3100 mV

All other settings will default to 3100 mV.

9.5.4.8.3 UV_DISABLE1

Address

NVM

0x000C

Bit 7

Bit 6

CELL15

0

Bit 5

CELL14

0

Bit 4

CELL13

0

Bit 3

CELL12

0

Bit 2

CELL11

0

Bit 1

CELL10

0

Bit 0

CELL9

0

Name

Reset

CELL16

0

CELL9 to Indicate which channels shall be excluded from UV and VCB_DONE detection

CELL16 = 0 = UV and VCB_DONE monitoring apply to the channel

1 = UV and VCB_DONE monitoring are excluded from the channel

9.5.4.8.4 UV_DISABLE2

Address

NVM

0x000D

Bit 7

CELL8

0

Bit 6

CELL7

0

Bit 5

CELL6

0

Bit 4

CELL5

0

Bit 3

CELL4

0

Bit 2

CELL3

0

Bit 1

CELL2

0

Bit 0

CELL1

0

Name

Reset

CELL8 to Indicate which channels shall be excluded from UV and VCB_DONE detection

CELL1 = 0 = UV and VCB_DONE monitoring apply to the channel

1 = UV and VCB_DOME monitoring are excluded from the channel

9.5.4.8.5 OTUT_THRESH

Address

NVM

0x000B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

OT_THR[4:0]

0

Bit 1

Bit 0

Name

Reset

UT_THR[2:0]

1

0

UT_THR[2:0] = Sets the UT threshold for the UT comparator. Changes on these bits require host to send another [OTUT_GO] =

1 command. The MCU configures the corresponding GPIO(s) to ADC and OTUT input.

Range from 66% to 80% in steps of 2% sourced from TSREF regulator voltage.

Default Reset setting 80%.

OT_THR[4:0] = Sets the OT threshold for the OT comparator. Changes on these bits require host to send another [OTUT_GO] =

1 command. The MCU configures the corresponding GPIO(s) to ADC and OTUT input.

Range from 10% to 39% in steps of 1% sourced from TSREF regulator voltage.

Unused code defaults to 39%.

Default Reset setting 39%.

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9.5.4.8.6 OVUV_CTRL

Address

RW

0x032C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

VCBDONE_

THR_LOCK

OVUV_LOCK[3:0]

OVUV_GO

OVUV_MODE[1:0]

Reset

0

VCBDONE_THR_LOCK = As the UV comparator is switching between UV threshold and VCBDONE threshold to measure the UV DAC or

the VCBDONE DAC result for diagnostics, the UV comparator has to lock onto only one threshold before

starting the AUX ADC measurement. This bit selects which threshold is locked to the UV comparator.

The bit is sampled when OVUV_MODE[1:0] is 0b11 which is locked to a single channel mode.

0 = UV threshold is selected

1 = VCBDONE threshold is selected

OVUV_LOCK[3:0] = Configures a particular single channel as the OV and UV comparators input when [OVUV_MOD1:0] = 0b11.

Changes on these bits require host to send another [OVUV_GO] = 1 command.

0x0 = Lock to Cell1

0x1 = Lock to Cell2

0x2 = Lock to Cell3

:

0xF = Lock to Cell16

OVUV_GO = Starts the OV and UV comparators. When written to 1, all OVUV configuration settings are sampled. This bit is

self-clearing.

0 = Ready

1 = Start OV and UV comparators

OVUV_MODE[1:0] = Sets the OV and UV comparators operation mode when [OVUV_GO] = 1. Changes on these bits require host to

send another [OVUV_GO] = 1 command.

00 = Do not run OV and UV comparators

01 = Run the OV and UV round robin with all active cells

10 = Run the OV and UV BIST cycle.

11 = Lock OV and UV comparators to a single channel configured by [OVUV_LOCK3:0]

Note: Active cells are defined by the ACTIVE_CELL[NUM_CELL3:0] register.

9.5.4.8.7 OTUT_CTRL

Address

RW

0x032D

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

OTCB_THR_

LOCK

OTUT_LOCK[2:0]

OTUT_GO

OTUT_MODE[1:0]

Reset

0

RSVD = Reserved

OTCB_THR_LOCK = As the OT comparator is switching between OT threshold and OTCB threshold to measure the OT or OTCB DAC

threshold result for diagnostics, the OT comparator has to lock onto only one threshold before starting the AUX

ADC measurement. This bit selects which threshold is locked to the OT comparator. The bit is sampled when

OTUT_MODE[1:0] = 0b11 which is locked to a single channel mode.

0 = OT threshold is selected

1 = OTCB threshold is selected

OTUT_LOCK[2:0] = Configures a particular single channel as the OT and UT comparators input when [OTUT_MOD1:0] = 0b11.

Changes on these bits require host to send another [OTUT_GO] = 1 command.

0x0 = Lock to GPIO1A

0x1 = Lock to GPIO2A

:

0x7 = Lock to GPIO8A

OTUT_GO = Starts the OT and UT comparators. When written to 1, all OTUT configuration settings are sampled. This bit is

self-clearing.

0 = Ready

1 = Start OT and UT comparators

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OTUT_MODE[1:0] = Sets the OT and UT comparators operation mode when [OTUT_GO] = 1. Changes on these bits require host to

send another [OTUT_GO] = 1 command.

00 = Do not run OT and UT comparators

01 = Run the OT and UT round robin with all active cells

10 = Run the OT and UT BIST cycle.

11 = Lock OT and UT comparators to a single channel configured by [OTUT_LOCK3:0]

9.5.4.9 GPIO Configuration

9.5.4.9.1 GPIO_CONF1

Address

NVM

0x000E

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FAULT_IN_

EN

SPI_EN

GPIO2[2:0]

GPIO1[2:0]

Reset

0

FAULT_IN_EN = Enables GPIO8 as an active-low input to trigger the NFAULT pin when the input signal is low.

0 = No fault input function. GPIO8 is configured based on [GPIO8_CONF2:0] setting.

1 = GPIO8 is set as active-low input to trigger NFAULT pin, [GPIO8_CONF2:0] setting is ignored.

SPI_EN = Enables SPI master on GPIO4, GPIO5 and GPIO6, GPIO7.

0 = SPI master disabled.

1 = SPI master enabled. Overwrite the [GPIO4_CONF2:0], [GPIO5_CONF2:0], [GPIO6_CONF2:0], and

[GPIO7_CONF2:0] settings.

GPIO2[2:0] = Configures GPIO2.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

GPIO1[2:0] = Configures GPIO1.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

9.5.4.9.2 GPIO_CONF2

Address

NVM

0x000F

Bit 7

SPARE

0

Bit 6

RSVD

0

Bit 5

Bit 4

GPIO4[2:0]

0

Bit 3

Bit 2

Bit 1

GPIO3[2:0]

0

Bit 0

Name

Reset

0

SPARE = Spare

GPIO4[2:0] = Configures GPIO4. If [SPI_EN] = 1, these configuration bits are ignored and the pin is used as SS for SPI master.

See 节9.3.6.1.7 for details.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

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GPIO3[2:0] = Configures GPIO3. If MB_TIMER_CTRL is not 0x00, this configuration is ignored and the pin is configured for

module balancing.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

9.5.4.9.3 GPIO_CONF3

Address

NVM

0x0010

Bit 7

Bit 6

Bit 5

Bit 4

GPIO6[2:0]

0

Bit 3

Bit 2

Bit 1

GPIO5[2:0]

0

Bit 0

Name

Reset

SPARE[1:0]

0

SPARE[1:0] = Spare

GPIO6[2:0] = Configures GPIO6. If [SPI_EN] = 1, these configuration bits are ignored and the pin is used as MOSI for SPI

master. See 节9.3.6.1.7 for details.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

GPIO5[2:0] = Configures GPIO5. If [SPI_EN] = 1, these configuration bits are ignored and the pin is used as MISO for SPI

master. See 节9.3.6.1.7 for details.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

9.5.4.9.4 GPIO_CONF4

Address

NVM

0x0011

Bit 7

Bit 6

Bit 5

Bit 4

GPIO8[2:0]

0

Bit 3

Bit 2

Bit 1

GPIO7[2:0]

0

Bit 0

Name

Reset

SPARE[1:0]

0

SPARE[1:0] = Spare

GPIO8[2:0] = Configures GPIO8. If [FAULT_IN_EN] = 1, these configuration bits are ignored and the pin is used as an input

such that an active low will trigger NFAULT.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

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GPIO7[2:0] = Configures GPIO7. If [SPI_EN] = 1, these configuration bits are ignored and the pin is used as SCLK for SPI

master. See 节9.3.6.1.7 for details.

000 = As disabled, high-Z

001 = As ADC and OTUT inputs

010 = As ADC only input

011 = As digital input

100 = As output high

101 = As output low

110 = As ADC input and weak pull-up enabled

111 = As ADC input and weak pull-down enabled

9.5.4.10 SPI Master

9.5.4.10.1 SPI_CONF

Address

RW

0x034D

Bit 7

RSVD

0

Bit 6

CPOL

0

Bit 5

CPHA

0

Bit 4

Bit 3

Bit 2

NUMBIT[4:0]

0

Bit 1

Bit 0

Name

Reset

0

RSVD = Reserved

CPOL = Sets the SCLK polarity.

0 = Idles low and clocks high

1 = Idles high and clocks low

CPHA = Sets the edge of SCLK where data is sampled on MISO.

0 = Leading clock transition

1 = Trailing clock transition

NUMBIT[4:0] = SPI transaction length. Set the number of SPI bits to read/write.

00000 = 24-bit

00001 = 1-bit

00010 = 2-bit

:

10111 = 23-bit

All others = 23-bit

9.5.4.10.2 SPI_EXE

Address

RW

0x0351

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

SS_CTRL

1

Bit 0

SPI_GO

0

Name

Reset

RSVD

0

RSVD = Reserved

SS_CTRL = Programs the state of SS.

0 = Output low

1 = Output high

SPI_GO = Executes the SPI transaction. This bit is self-clearing.

0 = Idle

1 = Execute the SPI

9.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1

Address 0x034E to

0x0350

RW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

DATA[7:0]

0

DATA[7:0] = Data to be used to write to SPI slave device. The bits are programmed by using SPI_CONF[NUMBIT4:0] and are

clocked out of MOSI starting from the LSB SPI_TX1 -> LSB SPI_TX2 -> LSB SPI_TX3.

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9.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1

Address 0x0520 to

0x522

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

DATA[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

R

DATA[7:0] = Data returned from a read during SPI transaction. Updated, starting with LSB SPI_RX1 -> LSB SPI_RX2 -> LSB

SPI_RX3, with the number of bits set by SPI_CONF[NUMBIT4:0] clocked in from MISO.

9.5.4.11 Diagnostic Control

9.5.4.11.1 DIAG_OTP_CTRL

Address

RW

0x0335

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

FLIP_FACT_

CRC

MARGIN_MODE[2:0]

MARGIN_GO

Reset

0

RSVD = Reserved

FLIP_FACT_CRC = An enable bit to flip the factory CRC value. This is for factory CRC diagnostic.

0 = Normal operation. No modification of the factory CRC

1 = Flip the CRC value. This causes a factory CRC fault, FAULT_OTP[FACT_CRC].

MARGIN_MODE[2:0] = Configures OTP Margin read mode:

0b000 = Normal Read

0b001 = Reserved

0b010 = Margin 1 Read

0b011 to 0b111 = Reserved

MARGIN_GO = Starts OTP Margin test set by the [MARGIN_MOD] bit. This bit self-clears and always reads 0.

0 = Ready

1 = Start the test

9.5.4.11.2 DIAG_COMM_CTRL

Address

RW

0x0336

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

SPI_

LOOPBACK

FLIP_TR_

CRC

Reset

0

RSVD = Reserved

SPI_LOOPBACK =

Enables SPI loopback function to verify SPI functionality. See the 节9.3.6.1.7 for more details.

0 = Disable

1 = Enable

FLIP_TR_CRC = Sends a purposely incorrect communication (during transmitting response) CRC by inverting all of the calculated

CRC bits.

0 = Send CRC as calculated

1 = Send inverted CRC

9.5.4.11.3 DIAG_PWR_CTRL

Address

RW

0x0337

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

BIST_NO_

RST

PWR_BIST_

GO

Reset

0

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RSVD = Reserved

BIST_NO_RST = Use for further diagnostic if the power supply BIST detects a failure. When this bit is set to 1, and then BIST cycle

is run using [PWR_BIST_GO], the device will not clear the FAULT_PWR1 and FAULT_PWR2 register, and does

not deassert the NFAULT signal at the end of BIST cycle.

0 = Cycle through BIST on the LDO comparators. The FAULT_PWR* registers are reset to 0 and NFAULT is

deasserted at the end of each LDO BIST run.

1 = Cycle through BIST on the LDO comparators. The FAULT_PWR* registers are not reset to 0, and NFAULT

remains asserted at the end of each LDO BIST run.

PWR_BIST_GO = When written to 1, the power supply BIST diagnostic will start. Any change in [BIST_NO_RST] has no effect until

this bit is written to 1 again. The bit self-clears.

0 = Ready

1 = Start power supply BIST diagnostic.

9.5.4.11.4 DIAG_CBFET_CTRL1

Address

RW

0x0338

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CBFET16 to CBFET9

0

CBFET16 to CBFET9 = Enables CBFET for CBFET diagnostic. This register is only sampled when [COMP_ADC_SEL2:0] = 0b100.

0 = CBFET off

1 = CBFET on

9.5.4.11.5 DIAG_CBFET_CTRL2

Address

RW

0x0339

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

CBFET8 to CBFET1

0

CBFET8 to CBFET1 = Enables CBFET for CBFET diagnostic. This register is only sampled when [COMP_ADC_SEL2:0] = 0b100.

0 = CBFET off

1 = CBFET on

9.5.4.11.6 DIAG_COMP_CTRL1

Address

RW

0x033A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

VCCB_THR[4:0]

0

VCCB_THR[4:0] = Configures the VCELL vs. AUXCELL delta. The VCELL vs. AUXCELL check is considered pass if the measured

delta is less than this threshold. This threshold applies to the bus bar comparison from Main to AUX ADC as well.

Range from 6 to 99mV in 3mV step

BB_THR[2:0] = RSVD = Additional delta value added to the VCCB_THR setting, used during VCELL vs. AUXCELL comparison when

comparing a cell connected above a bus bar (with the bus bar connected to a VC channel individually).

Range is from 5 mV to 40 mV in 5-mV steps. Reserved

9.5.4.11.7 DIAG_COMP_CTRL2

Address

RW

0x033B

Bit 7

RSVD

0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

GPIO_THR[2:0]

0

OW_THR[3:0]

0

RSVD = Reserved

GPIO_THR[2:0] = Configures the GPIO comparison delta threshold between Main and AUX ADC measurements.

Range is from 4-mV to 32-mV in 4-mV steps

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OW_THR[3:0] = Configures the OW detection threshold for diagnostic comparison. This threshold applies to the CB OW and VC

OW diagnostics.

Range is from 500 mV to 5 V in 300-mV steps.

9.5.4.11.8 DIAG_COMP_CTRL3

Address

RW

0x033C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

CBFET_CTRL

_GO

OW_SNK[1:0]

COMP_ADC_SEL[2:0]

COMP_ADC

_GO

Reset

0

RSVD = Reserved

CBFET_CTRL_GO = When this GO bit = 1, device turns on the CBFET configured and turns off whichever CBFET is clear in

DIAG_CBFET_CTRL1/2 regisetrs. This GO action is executed only if CB is not running or it’s in pause,

otherwise, CBFETs are controlled by regular CB control.

If CBFET are turned on by this GO bit, once CB is started or resume, the CBFET controls returns to the regular

CB control (and not by this GO bit action)

OW_SNK[1:0] = Turns on current sink on VC pins, CB pins, or BBP/N pins. Changes to these bits take effect immediately. Host

MCU is responsible to turn on the correct sink current before performing open wire (OW) test and to turn off the

sink current after OW test is completed.

00 = All VC, BBP/N, CB pins current sink is off.

01 = Turn on current sink on all VC pins

10 = Turn on current sink on all CB pins

11 = Turn on current sink on BBP/N pins

COMP_ADC_SEL[2:0] = Enables the device diagnostic comparison through the ADC measurements. Host enables the corresponding

ADCs in continuous mode before enabling this diagnostic. These bits are sampled when [COMP_ADC_GO] = 1.

000 = No ADC comparison is performed

001 = Cell voltage measurement check.

Device compares the cell channels specified by [AUX_CELL_SEL4:0] against the following criteria:

VCELL (from Main ADC) vs. AUXCELL (from AUX ADC) delta is less than [VCCB_THR4:0].

The [DRDY_VCCB] = 1 when this comparison is completed.

010 = Open wire (OW) check on VC pins.

MCU enables the current sink on all VC pins through the [OW_SNK1:0] before enabling this comparison. Device

compares corresponding VC pins specified by ACTIVE_CELL register against the following criteria: VCELL (from

Main ADC) is less than DIAG_COMP_CTRL2 [OW_THR3:0].

The [DRDY_VC_OW] = 1 when the comparison is completed.

011 = Open wire (OW) check on CB pins

MCU enables the current sink on all VC pins through the [OW_SNK1:0] before enabling this comparison. Device

compares corresponding CB pins specified by [AUX_CELL_SEL4:0] against the following criteria: AUXCELL

(from AUX ADC) is less than DIAG_COMP_CTRL2 [OW_THR3:0]. The [DRDY_CBOW] = 1 when the

comparison is completed.

100 = CBFET check.

MCU preconfigures the following before starting this check:

•

Pause cell balancing if balancing is enabled.

Enable the CBFET configured by DIAG_CBFET_CTRL1/2 registers.

Configure the [EXTD_CBFET] to decide if all CBFET returns to pause state (that is, turn off all CBFET) or

remains their status as specified by DIAG_CBFET_CTRL1/2 registers.

When this test starts, device will turn on CBFET specified by DIAG_CBFET_CTRL1/2 registers and then

compares the channel specified by [AUX_CELL_SEL4:0] with the following criteria:

AUXCELL (from AUX ADC) < 1/3 of VCELL (from Main ADC). [DRDY_CBFET] = 1 when the comparison is

completed.

101 = GPIO measurement check (applies to GPIO configured as ADC and OTUT inputs or ADC only input).

Device compares main GPIO measurement vs. AUX GPIO measurements delta is less than [GPIO_THR2:0]. The

[DRDY_GPIO] = 1 when the comparison is completed.

Other codes: No ADC comparison is performed

COMP_ADC_GO = Device starts diagnostic test specified by [COMP_ADC_SEL2:0] setting. When this bit is written to 1, the selected

[COMP_ADC_SEL2:0] is sampled. Change of [COMP_ADC_SEL2:0] setting has no effect unless this GO bit is

written to 1 again.

This bit is cleared to 0 in read.

0 = Ready. Writing 0 has no effect

1 = Star diagnostic selected by [COMP_ADC_SEL2:0]

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9.5.4.11.9 DIAG_COMP_CTRL4

Address

RW

0x033D

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

COMP_

FAULT_INJ

LPF_FAULT

_INJ

Reset

0

RSVD = Reserved

COMP_FAULT_INJ = Injects fault to the ADC comparison logic. If any ADC comparison diagnostic is run with this bit set, the

comparison result is expected to fail.

0 = Disable

1 = Enable

LPF_FAULT_INJ = Injects fault condition to the diagnostic LPF during LPF diagnostic. The FAULT_COMP_MISC[LPF_FAIL] is

expected to be set.

0 = Disable

1 = Enable

9.5.4.11.10 DIAG_PROT_CTRL

Address

RW

0x033E

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

PROT_BIST

_NO_RST

Reset

0

RSVD = Reserved

PROT_BIST_NO_RST = Use for further diagnostic if the protector BIST detects a failure. When this bit is set to 1, the device will not clear

the FAULT_OV1/2, FAULT_UV1/2, FAULT_OT, and FAULT_UT registers. The NFAULT signal will be latched

once it is asserted.

Note: Host ensures there is no fault before starting the BIST run with this bit set to 0.

0 = During BIST run, when the device asserts a fault to check the protector comparators and MUX and asserts

the correct OV, UV, OT, and UT fault bits the NFAULT pin. When this bit is 0, the device clears the fault and

deasserts NFAULT before switching to the next channel.

1 = During BIST run, the fault created during the test will not be cleared before switching to next cell or GPIO

channel. The NFAULT pin is latched once it is asserted.

9.5.4.12 Fault Configuration and Reset

9.5.4.12.1 FAULT_MSK1

Address

NVM

0x0016

Bit 7

Bit 6

MSK_UT

0

Bit 5

MSK_OT

0

Bit 4

MSK_UV

0

Bit 3

MSK_OV

0

Bit 2

MSK_COMP

0

Bit 1

MSK_SYS

0

Bit 0

MSK_PWR

0

Name

Reset

MSK_PROT

0

MSK_PROT = Masks the FAULT_PROT* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_PROT* is set to 1.

1 = No NFAULT action regardless of FAULT_PROT* bit status.

MSK_UT = Masks the FAULT_UT* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_UT* is set to 1.

1 = No NFAULT action regardless of FAULT_UT* bit status.

MSK_OT = Masks the FAULT_OT* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_OT* is set to 1.

1 = No NFAULT action regardless of FAULT_OT* bit status.

MSK_UV = Masks the FAULT_UV* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_UV* is set to 1.

1 = No NFAULT action regardless of FAULT_UV* bit status.

MSK_OV = Masks the FAULT_OV* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_OV* is set to 1.

1 = No NFAULT action regardless of FAULT_OV* bit status.

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MSK_COMP = Masks the FAULT_COMP_* registers to trigger NFAULT.

0 = Assert NFAULT if any bit from FAULT_COMP_* is set to 1.

1 = No NFAULT action regardless of FAULT_COM_* bit status.

MSK_SYS = To mask the NFAULT assertion from any FAULT_SYS register bit.

0 = Assert NFAULT if any bit from FAULT_SYS is set to 1.

1 = No NFAULT action regardless of FAULT_SYS bit status.

MSK_PWR = To mask the NFAULT assertion from any FAULT_PWR1 to FAULT_PWR3 register bit.

0 = Assert NFAULT if any bit from FAULT_PWR1 to FAULT_PWR3 is set to 1.

1 = No NFAULT action regardless of FAULT_PWR1 to FAULT_PWR3 bit status.

9.5.4.12.2 FAULT_MSK2

Address

NVM

0x0017

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

SPARE[1]

MSK_OTP_

CRC

MSK_OTP_ MSK_COMM3 MSK_COMM3 MSK_COMM3 MSK_COMM2 MSK_COMM1

DATA

0

_FCOMM

0

_FTONE

0

_HB

0

Reset

0

SPARE[1] = Spare

MSK_OTP_CRC = Masks the FAULT_OTP register ([CUST_CRC] and [FACT_CRC] only) on NFAULT triggering.

0 = Assert NFAULT if any bit described above is set to 1.

1 = No NFAULT action regardless of the status of the bits described above.

MSK_OTP_DATA = Masks the FAULT_OTP register (all bits except [CUST_CRC] and [FACT_CRC]) on NFAULT triggering.

0 = Assert NFAULT if any bit described above is set to 1.

1 = No NFAULT action regardless of the status of the bits described above.

MSK_COMM3_FCOMM Masks FAULT_COMM3[FCOMM_DET] fault on NFAULT triggering.

= 0 = Assert NFAULT if FAULT_COMM3[FCOMM_DET] is set to 1.

1 = No NFAULT action regardless of FAULT_COMM3[FCOMM_DET] status.

MSK_COMM3_FTONE Masks FAULT_COMM3[FTONE_DET] fault on NFAULT triggering.

= 0 = Assert NFAULT if FAULT_COMM3[FTONE_DET] is set to 1.

1 = No NFAULT action regardless of FAULT_COMM3[FTONE_DET] status.

MSK_COMM3_HB = Masks FAULT_COMM3[HB_FAST] or [HB_FAIL] faults on NFAULT triggering.

0 = Assert NFAULT if FAULT_COMM3[HB_FAST] or [HB_FAIL] is set to 1.

1 = No NFAULT action regardless of FAULT_COMM3[HB_FAST] or [HB_FAIL] status.

MSK_COMM2 = Masks FAULT_COMM2 register on NFAULT triggering.

0 = Assert NFAULT if any bit from FAULT_COMM2 register is set to 1.

1 = No NFAULT action regardless of FAULT_COMM2 register bit status.

MSK_COMM1 = Masks FAULT_COMM1 register on NFAULT triggering.

0 = Assert NFAULT if any bit from FAULT_COMM1 register is set to 1.

1 = No NFAULT action regardless of FAULT_COMM1 register bit status.

9.5.4.12.3 FAULT_RST1

Address

RW

0x0331

Bit 7

Bit 6

RST_UT

0

Bit 5

RST_OT

0

Bit 4

RST_UV

0

Bit 3

RST_OV

0

Bit 2

RST_COMP

0

Bit 1

RST_SYS

0

Bit 0

RST_PWR

0

Name

Reset

RST_PROT

0

RST_PROT = Resets the FAULT_PROT1 and FAULT_PROT2 registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

RST_UT = Resets all FAULT_UT registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

RST_OT = Resets all FAULT_OT registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

RST_UV = Resets all FAULT_UV* registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

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RST_OV = Resets all FAULT_OV* registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

RST_COMP = Resets all FAULT_COMP_* registers to 0x00.

0 = No reset

1 = Reset registers to 0x00

RST_SYS = To reset the FAULT_SYS register to 0x00. This bit self-clears to 0 after writing to 1.

0 = Do not reset

1 = Reset to 0x00

RST_PWR = To reset the FAULT_PWR1 to FAULT_PWR3 registers to 0x00. This bit self-clears to 0 after writing to 1.

0 = Do not reset

1 = Reset to 0x00

9.5.4.12.4 FAULT_RST2

Address

RW

0x0332

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

RST_OTP

_CRC

RST_OTP_

DATA

RST_COMM3 RST_COMM3 RST_COMM3 RST_COMM2 RST_COMM1

_FCOMM

0

_FTONE

0

_HB

0

Reset

0

RSVD = Reserved

RST_OTP_CRC = Resets the FAULT_OTP register ([CUST_CRC] and [FACT_CRC] only).

0 = No reset

1 = Reset the register to 0x00

RST_OTP_DATA = Resets the FAULT_OTP register ([SEC_DETECT] and [DED_DETECT] only).

0 = No reset

1 = Reset the register to 0x00

RST_COMM3_FCOMM Resets FAULT_COMM3[FCOMM_DET].

= 0 = No reset

1 = Reset the related bit to 0

RST_COMM3_FTONE Resets FAULT_COMM3[FTONE_DET].

= 0 = No reset

1 = Reset the related bit to 0

RST_COMM3_HB = Resets FAULT_COMM3[HB_FAST] and [HB_FAIL] bits.

0 = No reset

1 = Reset the related bits to 0

RST_COMM2 = Resets FAULT_COMM2, DEBUG_COML*, and DEBUG_COMM_COMH* registers.

0 = No reset

1 = Reset registers to 0x00

RST_COMM1 = Resets FAULT_COMM1 and DEBUG_COMM_UART* registers.

0 = No reset

1 = Reset registers to 0x00

9.5.4.13 Fault Status

9.5.4.13.1 FAULT_SUMMARY

This register is the soft version of the NFAULT.

Address

0x052D

Bit 7

Read

Only

Bit 6

Bit 5

FAULT_OTP

0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FAULT_PWR

0

Name

FAULT_PRO

T

FAULT_

COMP_ADC

FAULT_

COMM

FAULT_OTUT FAULT_OVUV FAULT_SYS

Reset

0

FAULT_PROT = This bit is set if [MSK_PROT] = 0 and any of the FAULT_PROT1 or FAULT_PROT2 register bits is set.

0 = No protector (OVUV, OTUT comparators) fault.

1 = Protector fault is detected

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FAULT_COMP_ADC = This bit is set if [MSK_COMP] = 0 and any of the following registers is set:

•

FAULT_COMP_VCCB1/2

FAULT_COMP_VCOW1/2

FAULT_COMP_CBOW1/2

FAULT_COMP_CBFET1/2

FAULT_COMP_GPIO

FAULT_COMP_MISC

0 = No ADC comparison fault (that is, none of the FAULT_COMP_* registers are set).

1 = ADC comparison fault is detected.

FAULT_OTP = This bit is set if [MSK_OTP] = 0 and any of the FAULT_OTP register bits is set.

0 = No OTP-related fault detected or OTP faults are masked.

1 = OTP-related fault is detected.

FAULT_COMM = This bit is set if any of the following is true:

•

[MSK_COMM1] = 0 and any of the FAULT_COMM1 register bits is set.

[MSK_COMM2] = 0 and any of the FAULT_COMM2 register bits is set.

[MSK_COMM3_HB] = 0 and the FAULT_COMM3[HB_FAST] bit or [HB_FAIL] bit is set.

[MSK_COMM3_FTONE] = 0 and the FAULT_COMM3[FTONE_DET] is set.

[MSK_COMM3_FCOMM] = 0 and if FAULT_COMM3[FCOMM_DET] is set.

0 = No UART, VIF, or FTONE fault is detected, or UART, VIF, and FTONE faults are masked.

1 = UART, VIF, or UT fault is detected.

FAULT_OTUT = This bit is set if any of the following is true:

[MSK_OT] = 0 and any of the FAULT_OT1 or FAULT_OT2 bits is set.

[MSK_UT] = 0 and any of the FAULT_UT1 or FAULT_UT2 bits is set.

•

0 = No OT or UT fault is detected, or OT and UT faults are masked.

1 = OT or UT fault is detected

FAULT_OVUV = This bit is set if any of the following is true:

[MSK_OV] = 0 and any of the FAULT_OV1 or FAULT_OV2 bits is set.

[MSK_UV] = 0 and any of the FAULT_UV1 or FAULT_UV2 bits is set.

•

0 = No OV or UV fault is detected, or OV and UV faults are masked.

1 = OV or UV fault is detected.

FAULT_SYS = This bit is set if [MSK_SYS] = 0 and any of the FAULT_SYS register bits is set.

0 = No system related fault detected or system faults are masked.

1 = System related fault is detected.

FAULT_PWR = This bit is set if [MSK_PWR] = 0 and any of the FAULT_PWR1 to FAULT_PWR3 register bits is set.

0 = No power rail related fault is detected or power rail faults are masked.

1 = Power rail related fault is detected.

9.5.4.13.2 FAULT_COMM1

Address

Read Only

Name

0x0530

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSVD

UART_TR

UART_RR

UART_RC

COMMCLR

_DET

STOP_DET

Reset

0

RSVD = Reserved

UART_TR = Indicates a UART FAULT is detected when transmitting a response frame. Further details of the fault information

are available in the DEBUG_UART_RR_TR register.

0 = No fault

1 = Fault

UART_RR = Indicates a UART FAULT is detected when receiving a response frame. Further details of the fault information are

available in the DEBUG_UART_RR_TR register.

0 = No fault

1 = Fault

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UART_RC = Indicates a UART FAULT is detected during receiving a command frame. Further details of the fault information

are available in the DEBUG_UART_RC register.

0 = No fault

1 = Fault

COMMCLR_DET = A UART communication clear signal is detected. A detection of SLEEPtoACTIVE ping in ACTIVE or SLEEP mode

or detection of WAKE pin in ACTIVE mode will also set this bit.

0 = No UART Clear

1 = UART Clear detected

STOP_DET = Indicates an unexpected STOP condition is received. A detection of SLEEPtoACTIVE signal in ACTIVE mode will

also set this bit.

0 = No fault

1 = Fault

9.5.4.13.3 FAULT_COMM2

Address

0x0531

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

COML_TR

0

COML_RR

0

COML_RC

0

COML_BIT

0

COMH_TR

0

COMH_RR

0

COMH_RC

0

COMH_BIT

0

COML_TR = Indicates a COML byte level fault is detected when transmitting a response frame. Further details of the fault

information are available in the DEBUG_COML_RR_TR register.

0 = No fault

1 = Fault

COML_RR = Indicates a COML byte level fault is detected when receiving a response frame. Further details of the fault

information are available in the DEBUG_COML_RR_TR register.

0 = No fault

1 = Fault

COML_RC = Indicates a COML byte level fault is detected when receiving a command frame. Further details of the fault

information are available in the DEBUG_COML_RC register.

0 = No fault

1 = Fault

COML_BIT = Indicates a COML bit level fault is detected which would cause at least one byte level fault. Further details of the

fault information are available in the DEBUG_COML_BIT register.

0 = No fault

1 = Fault

COMH_TR = Indicates a COMH byte level fault is detected when transmitting a response frame. Further details of the fault

information are available in the DEBUG_COMH_RR_TR register.

0 = No fault

1 = Fault

COMH_RR = Indicates a COMH byte level fault is detected when receiving a response frame. Further details of the fault

information are available in the DEBUG_COMH_RR_TR register.

0 = No fault

1 = Fault

COMH_RC = Indicates a COMH byte level fault is detected when receiving a command frame. Further details of the fault

information are available in the DEBUG_COMH_RC register.

0 = No fault

1 = Fault

COMH_BIT = Indicates a COMH bit level fault is detected which would cause at least one byte level fault. Further details of the

fault information are available in the DEBUG_COMH_BIT register.

0 = No fault

1 = Fault

9.5.4.13.4 FAULT_COMM3

Address

0x0532

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

FCOMM_DET FTONE_DET

HB_FAIL

0

HB_FAST

0

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RSVD = Reserved

FCOMM_DET = Received communication transaction with the Fault Status bits set by any of the upper stack device(s).

0 = Fault Status are clear, indicating no fault is detected from any of the upper stack device(s).

1 = Fault Status are set from the receiving communication transaction.

FTONE_DET = Indicates a FAULT TONE is received. Detection is monitoring the COML side if [DIR_SEL] = 0 and vice versa.

0 = No FAULT TONE detected

1 = FAULT TONE detected

HB_FAIL = Indicates HEARTBEAT is not received within an expected time. Detection is monitoring the COML side if

[DIR_SEL] = 0 and vice versa.

0 = No fault

1 = Fault

HB_FAST = Indicates HEARTBEAT is received too frequently. Detection is monitoring the COML side if [DIR_SEL] = 0 and

vice versa. This bit may also be set when [FTONE_DET] = 1 depends on how soon the FAULT TONE is detected

from the previous HEATBEAT

0 = No fault

1 = Fault

9.5.4.13.5 FAULT_OTP

Address

0x0535

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

RSVD

0

DED_DET

0

SEC_DET

0

CUST_CRC

0

FACT_CRC

0

CUSTLDERR FACTLDERR

GBLOVERR

0

RSVD = Reserved

DED_DET = Indicates a DED error has occurred during the OTP load. (Unknown during encoding)

0 = No fault

1 = Fault

SEC_DET = Indicates a SEC error has occurred during the OTP load. (Unknown during encoding)

0 = No fault

1 = Fault

CUST_CRC = Indicates a CRC error has occurred in the customer register space.

0 = No fault

1 = Fault

FACT_CRC = Indicates a CRC error has occurred in the factory register space.

0 = No fault

1 = Fault

CUSTLDERR = Indicates errors during the customer space OTP load process. Read OTP_CUST1_STAT and

OTP_CUST2_STAT registers for the specific error condition. This error bit is set if one of the following is true:

•

No Customer OTP page is programmed.

The highest Customer OTP page has a [FMTERR].

The highest Customer OTP page has [TRY] = 1 and is not [PROGOK].

LOADERR happened on the selected Customer OTP page.

Information received from the device with this error must not be considered reliable.

Writing [RST_OTP_DATA] = 1 does not reset this bit. To recheck this error, a device reset or HW_RESET is

needed.

0 = No fault

1 = Fault

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FACTLDERR = Indicates errors during the factory space OTP load process. This error bit is set if one of the following is true:

•

No factory OTP page is programmed.

The highest factory OTP page has a [FMTERR].

The highest factory OTP page has [TRY] = 1 and is not [PROGOK].

LOADERR happened on the selected factory OTP page.

Information received from the device with this error must not be considered reliable.

Writing [RST_OTP_DATA] = 1 does not reset this bit. To recheck this error, a device reset or HW_RESET is

needed.

0 = No fault

1 = Fault

GBLOVERR = Indicates that on overvoltage error is detected on one of the OTP pages. Read OTP_CUST1_STAT and

OTP_CUST2_STAT registers to determine the specific page(s). Information received from the device with this

error must not be considered reliable.

Writing [RST_OTP_DATA] = 1 does not reset this bit. To clear this bit, a device reset or HW_RESET is needed.

Repeat the programming procedure on a different page (if available) will force the device to re-evaluate the

condition.

0 = No fault

1 = Fault

9.5.4.13.6 FAULT_SYS

Address

0x0536

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

LFO

0

RSVD

0

GPIO

0

DRST

0

CTL

0

CTS

0

TSHUT

0

TWARN

0

LFO = Indicated LFO frequency is outside an expected range

0 = No fault detected

1 = Fault detected

RSVD = Reserved

GPIO = Indicates GPIO8 detects a FAULT input when GPIO_CONF1[FAULT_IN_EN] = 1.

0 = No fault detected

1 = FAULT input detected

DRST = Indicates a digital reset has occurred.

0 = No digital reset

1 = Digital reset has occurred

CTL = Indicates a long communication timeout occurred. Device action is configured by [CTL_ACT]. This bit is not

observable if the action is set to device shutdown.

0 = No fault

1 = Long communication timeout occurs. Observable if long timeout action is set to SLEEP.

CTS = Indicates a short communication timeout occurred. No action from the device. This can be served as an alert to

system before reaching long communication timeout.

0 = No fault

1 = Short communication timeout occurs

TSHUT = Indicates the previous shutdown was a thermal shutdown, in which the die temperature (die temp 2) is higher than

the thermal shutdown threshold.

0 = Die temperature is less than thermal shutdown threshold

1 = The previous shutdown was a thermal shutdown

TWARN = Indicates the die temperature (die temp 2) is higher than the TWARN_THR[1:0] setting. No action is taken by the

device at the moment yet. This serves as a warning signal that the die temperature is approaching thermal

shutdown.

0 = Die temperature is less than TWARN_THR[1:0]

1 = Die temperature is greater than TWARN_THR[1:0]

9.5.4.13.7 FAULT_PROT1

Address

0x053A

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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Name

RSVD

TPARITY_

FAIL

VPARITY_

FAIL

Reset

0

RSVD = Reserved

TPARITY_FAIL = Indicates a parity fault is detected on any of the following OTUT related configurations:

•

OT or UT threshold setting

[OTUT_MODE1:0] setting

GPIO_CONF1...4 settings

0 = No fault

1 = Fault

VPARITY_FAIL = Indicates a parity fault is detected on any of the following OVUV related configurations:

•

OV or UV threshold setting

[OVUV_MODE1:0] setting

[NUM_CELL3:0] setting

0 = No fault

1 = Fault

9.5.4.13.8 FAULT_PROT2

Address

0x053B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

0

BIST_ABORT TPATH_FAIL VPATH_FAIL

UTCOMP_

FAIL

OTCOMP_

FAIL

OVCOMP_

FAIL

UVCOMP_

FAIL

Reset

0

RSVD = Reserved

BIST_ABORT = Indicates either OVUV or OTUT BIST run is aborted.

0 = BIST runs to completion

1 = BIST abort

TPATH_FAIL = Indicates a fault is detected along the OTUT signal path during BIST test.

0 = No fault

1 = Fault

VPATH_FAIL = Indicates a fault is detected along the OVUV signal path during BIST test.

0 = No fault

1 = Fault

UTCOMP_FAIL = Indicates the UT comparator fails during BIST test.

0 = No fault

1 = Fault

OTCOMP_FAIL = Indicates the OT comparator fails during BIST test.

0 = No fault

1 = Fault

OVCOMP_FAIL = Indicates the OV comparator fails during BIST test.

0 = No fault

1 = Fault

UVCOMP_FAIL = Indicates the UV comparator fails during BIST test.

0 = No fault

1 = Fault

9.5.4.13.9 FAULT_OV1

Address

0x053C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OV16_DET

0

OV15_DET

0

OV14_DET

0

OV13_DET

0

OV12_DET

0

OV11_DET

0

OV10_DET

0

OV9_DET

0

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OV9_DET to OV16_DET OV fault status for Cell9 to Cell16, results are from the OV comparator detection.

=

9.5.4.13.10 FAULT_OV2

Address

0x053D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OV8_DET

0

OV7_DET

0

OV6_DET

0

OV5_DET

0

OV4_DET

0

OV3_DET

0

OV2_DET

0

OV1_DET

0

OV1_DET to OV8_DET = OV fault status for Cell1 to Cell8, results are from the OV comparator detection.

9.5.4.13.11 FAULT_UV1

Address

0x053E

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

UV16_DET

0

UV15_DET

0

UV14_DET

0

UV13_DET

0

UV12_DET

0

UV11_DET

0

UV10_DET

0

UV9_DET

0

UV9_DET to UV16_DET UV fault status for Cell9 to Cell16, results are from the UV comparator detection.

=

9.5.4.13.12 FAULT_UV2

Address

0x053F

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

UV8_DET

0

UV7_DET

0

UV6_DET

0

UV5_DET

0

UV4_DET

0

UV3_DET

0

UV2_DET

0

UV1_DET

0

UV1_DET to UV8_DET = UV fault status for Cell1 to Cell8, results are from the UV comparator detection.

9.5.4.13.13 FAULT_OT

Address

0x0540

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

OT8_DET

0

OT7_DET

0

OT6_DET

0

OT5_DET

0

OT4_DET

0

OT3_DET

0

OT2_DET

0

OT1_DET

0

OT1_DET to OT8_DET = OT fault status for GPIO1 to GPIO8, results are from the OT comparator detection.

9.5.4.13.14 FAULT_UT

Address

0x0541

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Reset

UT8_DET

0

UT7_DET

0

UT6_DET

0

UT5_DET

0

UT4_DET

0

UT3_DET

0

UT2_DET

0

UT1_DET

0

UT1_DET to UT8_DET = UT fault status for GPIO1 to GPIO8, results are from the UT comparator detection.

9.5.4.13.15 FAULT_COMP_GPIO

Address

0x0543

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

GPIO8_FAIL GPIO7_FAIL

GPIO6_FAIL

GPIO5_FAIL

GPIO4_FAIL

GPIO3_FAIL

GPIO2_FAIL

GPIO1_FAIL

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Reset

0

GPIO1_FAIL to Indicates ADC vs. AUX ADC GPIO measurement diagnostic results for GPIO1 to GPIO8.

GPIO8_FAIL = 0 = Diagnostic pass

1 = Diagnostic fail. GPIO from Main ADC vs. AUX ADC measurement is greater than [GPIO_THR2:0]

9.5.4.13.16 FAULT_COMP_VCCB1

Address

0x0545

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CELL16_FAI CELL15_FAIL CELL14_FAIL CELL13_FAIL CELL12_FAIL CELL11_FAIL CELL10_FAIL CELL9_FAIL

L

Reset

0

CELL9_FAIL to Indicates voltage diagnostic results for cell9 to cell16.

CELL16_FAIL = 0 = Diagnostic pass

1 = Diagnostic fail. VCELL vs. AUXCELL measurement is greater than [VCCB_THR4:0]

9.5.4.13.17 FAULT_COMP_VCCB2

Address

Read Only

Name

0x0546

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CELL8_FAI CELL7_FAIL

L

CELL6_FAIL

CELL5_FAIL

CELL4_FAIL

CELL3_FAIL

CELL2_FAIL

CELL1_FAIL

Reset

0

CELL1_FAIL to Indicates voltage diagnostic results for cell1 to cell8.

CELL8_FAIL = 0 = Diagnostic pass

1 = Diagnostic fail. VCELL vs. AUXCELL measurement is greater than [VCCB_THR4:0]

9.5.4.13.18 FAULT_COMP_VCOW1

Address

0x0548

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VCOW9_FAIL

0

Name

VCOW16

_FAIL

VCOW15

_FAIL

VCOW14

_FAIL

VCOW13

_FAIL

VCOW12

_FAIL

VCOW11

_FAIL

VCOW10

_FAIL

Reset

0

VCOW9_FAIL to Indicates VC OW diagnostic results for cell9 to cell 16.

VCOW16_FAIL = 0 = Diagnostic pass

1 = Diagnostic fail. VCELL measurement is less than [OW_THR3:0]

9.5.4.13.19 FAULT_COMP_VCOW2

Address

0x0549

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

VCOW8_FA VCOW7_FAIL VCOW6_FAIL VCOW5_FAIL VCOW4_FAIL VCOW3_FAIL VCOW2_FAIL VCOW1_FAIL

IL

Reset

0

VCOW1_FAIL to Indicates VC OW diagnostic results for cell1 to cell 8.

VCOW8_FAIL = 0 = Diagnostic pass

1 = Diagnostic fail. VCELL measurement is less than [OW_THR3:0]

9.5.4.13.20 FAULT_COMP_CBOW1

Address

0x054B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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Name

Reset

CBOW16_

CBOW15_

FAIL

CBOW14_

FAIL

CBOW13_

FAIL

CBOW12_

FAIL

CBOW11_

FAIL

CBOW10_

FAIL

CBOW9_FAIL

0

FAIL

0

CBOW9_FAIL to Results of the CB OW diagnostic for CB FET9 to CB FET16.

CBOW16_FAIL = 0 = Pass

1 = Fail

9.5.4.13.21 FAULT_COMP_CBOW2

Address

Read Only

Name

0x054C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CBOW8_FA CBOW7_FAIL CBOW6_FAIL CBOW5_FAIL CBOW4_FAIL CBOW3_FAIL CBOW2_FAIL CBOW1_FAIL

IL

Reset

0

CBOW1_FAIL to Results of the CB OW diagnostic for CB FET1 to CB FET8.

CBOW8_FAIL = 0 = Pass

1 = Fail

9.5.4.13.22 FAULT_COMP_CBFET1

Address

0x054E

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CBFET9_FAIL

0

Name

CBFET16_

FAIL

CBFET15_

FAIL

CBFET14_

FAIL

CBFET13_

FAIL

CBFET12_

FAIL

CBFET11_

FAIL

CBFET10_

FAIL

Reset

0

CBFET9_FAIL to Results of the CB FET diagnostic for CB FET9 to CB FET16.

CBFET16_FAIL = 0 = Pass

1 = Fail

9.5.4.13.23 FAULT_COMP_CBFET2

Address

0x054F

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CBFET8_FA CBFET7_FAIL CBFET6_FAIL CBFET5_FAIL CBFET4_FAIL CBFET3_FAIL CBFET2_FAIL CBFET1_FAIL

IL

Reset

0

CBFET1_FAIL to Results of the CB FET diagnostic for CB FET1 to CB FET8.

CBFET8_FAIL = 0 = Pass

1 = Fail

9.5.4.13.24 FAULT_COMP_MISC

Address

0x0550

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LPF_FAIL

0

Name

RSVD

COMP_ADC

_ABORT

Reset

0

RSVD = Reserved

COMP_ADC_ABORT = Indicates the most recent ADC comparison diagnostic is aborted due to improper setting. Valid only if one of the

ADC comparison diagnostics has started.

0 = ADC comparison diagnostic run to completion

1 = ADC comparison diagnostic is aborted

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LPF_FAIL = Indicates LPF diagnostic result.

0 = Pass

1 = Fail

9.5.4.13.25 FAULT_PWR1

Address

0x0552

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

CVDD_UV

0

Bit 3

CVDD_OV

0

Bit 2

DVDD_OV

0

Bit 1

AVDD_OSC

0

Bit 0

AVDD_OV

0

Name

CVSS_OPE DVSS_OPEN

N

REFHM_

OPEN

Reset

0

CVSS_OPEN = Indicates an open condition on CVSS pin.

0 = No fault

1 = Fault

DVSS_OPEN = Indicates an open condition on DVSS pin.

0 = No fault

1 = Fault

REFHM_OPEN = Indicates an open condition on REFHM pin.

0 = No fault

1 = Fault

CVDD_UV = Indicates an undervoltage fault on the CVDD LDO.

0 = No fault

1 = Fault

CVDD_OV = Indicates an overvoltage fault on the CVDD LDO.

0 = No fault

1 = Fault

DVDD_OV = Indicates an overvoltage fault on the DVDD LDO.

0 = No fault

1 = Fault

AVDD_OSC = Indicates AVDD is oscillating outside of acceptable limits.

0 = No fault

1 = Fault

This fault could trigger when transitioning from SLEEP to ACTIVE mode. So, if this fault is set, please ignore it

and reset the fault.

AVDD_OV = Indicates an overvoltage fault on the AVDD LDO.

0 = No fault

1 = Fault

9.5.4.13.26 FAULT_PWR2

Address

0x0553

Bit 7

Read

Only

Bit 6

Bit 5

RSVD

0

Bit 4

REFH_OSC

0

Bit 3

NEG5V_UV

0

Bit 2

TSREF_OSC

0

Bit 1

TSREF_UV

0

Bit 0

TSREF_OV

0

Name

RSVD

0

PWRBIST_

FAIL

Reset

0

RSVD = Reserved

PWRBIST_FAIL = Indicates a fail on the power supply BIST run.

0 = No fault

1 = Fault

REFH_OSC = Indicates REGH reference is oscillating outside of an acceptable limit.

0 = No fault

1 = Fault

NEG5V_UV = Indicates an undervoltage fault on the NEG5V charge pump.

0 = No fault

1 = Fault

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TSREF_OSC = Indicates TSREF is oscillating outside of an acceptable limit.

0 = No fault

1 = Fault

TSREF_UV = Indicates an undervoltage fault on the TSREF LDO.

0 = No fault

1 = Fault

TSREF_OV = Indicates an overvoltage fault on the TSREF LDO.

0 = No fault

1 = Fault

9.5.4.13.27 FAULT_PWR3

Address

0x0554

Bit 7

Read

Only

Bit 6

Bit 5

RSVD

0

Bit 4

Bit 3

Bit 2

RSVD

0

Bit 1

RSVD

0

Bit 0

Name

AVDDUV_

DRST

Reset

0

RSVD = Reserved

AVDDUV_DRST = Indicates a digital reset occurred due to AVDD UV detected. This also applies when device wakes up after a

SHUTDOWN or HW Reset event.

0 = No reset

1 = Digital reset occurred due to AVDD UV

9.5.4.14 Debug Control and Status

9.5.4.14.1 DEBUG_CTRL_UNLOCK

Address

RW

0x0700

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

CODE[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

CODE[7:0] = Write the unlock code (0xA5) to this register to activate the setting in the DEBUG_COMM_CTRL* register.

Any other value than the unlock code will deactivate any effect in the DEBUG_COMM_CTRL* setting and return

to the normal settings of the device.

9.5.4.14.2 DEBUG_COMM_CTRL1

Address

RW

0x0701

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

UART_BAUD

UART_

UART_TX_EN

USER_

MIRROR_EN

UART_EN

DAISY_EN

Reset

0

1

0

RSVD = Reserved

UART_BAUD = This bit changes the UART baud rate to 250kb/s. Useful on VIF debug. When system sets all daisy chain devices

to the 250kb/s baud rate, it slows down the response byte through the VIF to increase the robustness of the VIF

for debug purposes.

0 = Default 1Mb/s

1 = 250kb/s

UART_MIRROR_EN =

This bit enables the stack VIF communication to mirror to UART. To use this debug function, the stack device’s

UART TX has to be enabled first by setting [UARTTX_EN] = 1.

0 = Disable

1 = Enable

Note: This test mode only mirrors received response frames that are received on COMH/COML in a stack device.

It does not mirror received command frames or locally generated response frames that originate in the device.

UART_TX_EN = Stack device, by default, has the UART TX disabled. This bit enables the UART TX to allow read/write via UART

on the stack device.

0 = Disable

1 = Enable

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USER_UART_EN = This bit enables the debug UART control bits, [UART_TX_EN] and [UART_MIRROR_EN].

0 = The setting of the bits mentioned above has no effect.

1 = The device configures the UART per [UART_TX_EN] and [UART_MIRROR_EN] settings

USER_DAISY_EN = This bit enables the debug COML and COMH control bits in the DEBUG_COMM_CTRL2 register

0 = The setting of DEBUG_COMM_CTRL2 register has no effect.

1 = The device configures the COML and COMH per DEBUG_COMM_CTRL2 register setting.

9.5.4.14.3 DEBUG_COMM_CTRL2

Address

RW

0x0702

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

COML_TX

_EN

COML_RX

_EN

COMH_TX

_EN

COMH_RX

_EN

Reset

0

1

RSVD = Reserved

COML_TX_EN = Enables COML transmitter.

0 = Disable

1 = Enable

COML_RX_EN = Enables COML receiver.

0 = Disable

1 = Enable

COMH_TX_EN = Enables COMH transmitter.

0 = Disable

1 = Enable

COMH_RX_EN = Enables COMH receiver.

0 = Disable

1 = Enable

9.5.4.14.4 DEBUG_COMM_STAT

Address

0x0780

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

HW_UART

_DRV

HW_DAISY

_DRV

COML_TX

_ON

COML_RX

_ON

COMH_TX

_ON

COMH_RX

_ON

Reset

(Base)

0

1

0

1

Reset

1

(Stack)

RSVD = Reserved

HW_UART_DRV = Indicates the UART TX is controlled by the device itself or by MCU control. Applicable to the stack device in which

the UART TX is disabled by default once a device is configured as ‘STACK’.

0 = The DEBUG_COMM_CTRL1[USER_UART_EN] = 1. UART TX is under manual control through the

DEBUG_COMM_CTRL2 register.

1 = UART TX is controlled by the device

HW_DAISY_DRV = Indicates the COML and COMH are controlled by the device itself or by MCU control.

0 = The DEBUG_COMM_CTRL1[USER_DAISY_EN] = 1. COML and COMH are under manual control through

the DEBUG_COMM_CTRL2 register.

1 = COML and COMH are controlled by the device

COML_TX_ON = Shows the current COML transmitter status.

0 = off

1 = on

COML_RX_ON = Shows the current COML receiver status.

0 = off

1 = on

COMH_TX_ON = Shows the current COMH transmitter status.

0 = off

1 = on

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COMH_RX_ON = Shows the current COMH receiver status.

0 = off

1 = on

9.5.4.14.5 DEBUG_UART_RC

Address

0x0781

Bit 7

Read

Only

Bit 6

Bit 5

RC_IERR

0

Bit 4

RC_TXDIS

0

Bit 3

RC_SOF

0

Bit 2

Bit 1

RC_UNEXP

0

Bit 0

RC_CRC

0

Name

RSVD

RC_BYTE

_ERR

Reset

0

RSVD = Reserved

RC_IERR = Detects initialization byte error in the received command frame. This may be due to the frame initialization byte

has a stop error, incorrect frame type is set, or reserved command type bit is set. All bytes that follow are ignored

until a communication CLEAR is received.

When a communication frame is ignored, the device will not attempt to detect any communication error in the

ignored frame nor counting it as valid/discard in the frame counters.

0 = No error

1 = Error detected

RC_TXDIS = Detects if UART TX is disabled, but the host MCU has issued a command to read data from the device.

0 = No error

1 = Error detected

RC_SOF = Detects a start-of-frame (SOF) error. That is, an UART CLEAR is received on the UART before the current frame

is finished.

0 = No error

1 = Error detected

RC_BYTE_ERR = Detects any byte error, other than the error in the initialization byte, in the received command frame. All bytes that

follow are ignored until a communication CLEAR is received.

When a communication frame is ignored, the device will not attempt to detect any communication error in the

ignored frame nor counting it as valid/discard in the frame counters.

0 = No error

1 = Error detected

RC_UNEXP = In a stack device (that is, [STACK_DEV] = 1 and [MULTIDROP] = 0), it is not expected to receive a stack or

broadcast command through the UART interface. If so, this is detected as an error and this bit is set.

If device is configured with [MULTIDROP] = 1, this bit will not be set.

0 = No error

1 = Error detected

RC_CRC = Detects a CRC error in the received command frame from UART. The frame will be considered as discarded

frame.

0 = No error

1 = Error detected

9.5.4.14.6 DEBUG_UART_RR_TR

Address

0x0782

Bit 7

Read

Only

Bit 6

RSVD

0

Bit 5

Bit 4

TR_SOF

0

Bit 3

TR_WAIT

0

Bit 2

RR_SOF

0

Bit 1

Bit 0

RR_CRC

0

Name

RR_BYTE

_ERR

Reset

0

RSVD = Reserved

TR_SOF = Indicates that a UART CLEAR is received while the device is still transmitting data.

0 = No error

1 = Error detected

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TR_WAIT = The device is waiting for its turn to transfer a response out but the action is terminated because either:

•

The device receives a UART CLEAR signal.

The device receives a new command.

This bit is valid when broadcast or stack read command has been issued.

0 = No error

1 = Error detected

RR_SOF = Indicates a UART CLEAR is received while receiving the response frame. Response frames on the UART only

apply in multidrop mode.

0 = No error

1 = Error detected

RR_BYTE_ERR = Detects any byte error, other than the error in the initialization byte, in the received response frame. All bytes that

follow are ignored until a communication CLEAR is received.

When a communication frame is ignored, the device will not attempt to detect any communication error in the

ignored frame nor counting it as valid/discard in the frame counters.

0 = No error

1 = Error detected

RR_CRC = Detects are CRC error in the received response frame from UART. The frame will be considered as a discarded

frame.

0 = No error

1 = Error detected

9.5.4.14.7 DEBUG_COMH_BIT

Address

Read Only

Name

0x0783

Bit 7

Bit 6

RSVD

0

Bit 5

Bit 4

PERR

0

Bit 3

BERR_TAG

0

Bit 2

SYNC2

0

Bit 1

SYNC1

0

Bit 0

BIT

0

Reset

0

RSVD = Reserved

PERR = Detects abnormality of the incoming communication frame and hence, the device will forward the communication

frame with [BERR] bit set. Any error bit that is set in this register will also set the [PERR] bit. However, an

abnormality that isn’t classified in the register can also trigger the [PERR] bit (for example, detecting missing

data or wrong data order).

0 = No communication error detected, the forwarded communication frame does not have the [BERR] inserted.

1 = Detected abnormality of the received communication frame. [BERR] is asserted to the forwarded

communication.

BERR_TAG = Set when the received communication is tagged with [BERR] = 1.

0 = Received communication frame has no [BERR]

1 = Received communication frame has [BERR]

SYNC2 = The Preamble half-bit and the [SYNC1:0] bits are detected. Device is using the timing information extracted from

these bits but it is unable to detect valid data.

0 = No error

1 = Error detected

SYNC1 = Unable to detect the preamble half-bit or any of the [SYNC1:0] bits. It could be the bit is missing or the signal is

too distorted to be detectable.

0 = No error

1 = Error detected

BIT = The device has detected a data bit; however, the detection samples are not enough to assure a strong 1 or 0.

0 = No error

1 = Error detected

9.5.4.14.8 DEBUG_COMH_RC

Address

Read Only

Name

0x0784

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSVD

RC_IERR

RC_TXDIS

RC_SOF

RC_BYTE

_ERR

RC_UNEXP

RC_CRC

Reset

0

RSVD = Reserved

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RC_IERR = Detects initialization byte error in the received command frame. This may due to improper formatting of a byte

such as a frame initialization byte is expected, but start-of-frame (SOF) bit is not set, or an invalid frame type is

selected. Because bytes received on the COMH/COML are propagated up the stack, it is likely devices in the

upper stack will also detect this error.

All bytes that follow are ignored until a SOF bit is set is received.

When a communication frame is ignored, the device will not attempt to detect any communication error in the

ignored frame nor counting it as valid/discard in the frame counters.

0 = No error

1 = Error detected

RC_TXDIS = Valid when [DIR_SEL] = 1. Device detects the COMH TX is disabled but the device receives a command to read

data (that is, to transmit data out). The command frame will be counted as a discard frame.

0 = No error

1 = Error detected

RC_SOF = Valid when [DIR_SEL] = 1. Detects a start-of-frame (SOF) error on COMH. The SOF bit is set only in the

initialization frame but the SOF bit is set in the current frame that is not expected.

0 = No error

1 = Error detected

RC_BYTE_ERR = Valid when [DIR_SEL] = 1. Detected any byte error, other than the error in the initialization byte, in the received

command frame. This error can trigger one or more error bit set in the DEBUG_COMMH_BIT register.

0 = No error

1 = Error detected

RC_UNEXP = If [DIR_SEL] = 0, but device receives command frame from COMH which is an invalid condition and device will

set this error bit.

0 = No error

1 = Error detected

RC_CRC = Indicates a CRC error that resulted in one or more COMH command frames being discarded. Any other errors in

the frame are not indicated as the frame was discarded.

0 = No error

1 = Error detected

9.5.4.14.9 DEBUG_COMH_RR_TR

Address

Read Only

Name

0x0785

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSVD

TR_WAIT

RR_TXDIS

RR_SOF

RR_BYTE

_ERR

RR_UNEXP

RR_CRC

Reset

0

RSVD = Reserved

TR_WAIT = The device is waiting for its turn to transfer a response out but the action is terminated because the device

receives a new command.

This bit is valid when broadcast or stack read command has been issued.

0 = No error

1 = Error detected

RR_TXDIS = Valid when [DIR_SEL] = 0, device receives a response but fails to transmit to the next device because the COMH

TX is disabled. The frame is counted as a discarded frame.

0 = No error

1 = Error detected

RR_SOF = Valid when [DIR_SEL] = 0. Detects a start-of-frame (SOF) error on COMH. The SOF bit is set only in the

initialization frame but the SOF bit is set in the current frame that is not expected.

0 = No error

1 = Error detected

RR_BYTE_ERR = Valid when [DIR_SEL] = 0. Detects any byte error, other than the error in the initialization byte, in the received

response frame. This error can trigger one or more error bits set in the DEBUG_COMMH_BIT register.

0 = No error

1 = Error detected

RR_UNEXP = If [DIR_SEL] = 1, but device received response frame from COMH which is an invalid condition and device sets

this error bit.

0 = No error

1 = Error detected

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RR_CRC = Indicates a CRC error that resulted in one or more COMH response frames being discarded. Most other errors in

the frame are not indicated as the frame was discarded. If [RR_BYTE_ERR] is observed on the final byte of the

CRC, both CRC and BERR will be indicated.

0 = No error

1 = Error detected

9.5.4.14.10 DEBUG_COML_BIT

Address

Read Only

Name

0x0786

Bit 7

Bit 6

RSVD

0

Bit 5

Bit 4

PERR

0

Bit 3

BERR_TAG

0

Bit 2

SYNC2

0

Bit 1

SYNC1

0

Bit 0

BIT

0

Reset

0

RSVD = Reserved

PERR = Detect abnormality of the incoming communication frame and the outgoing communication frame will be set with

BERR. Any error bit that is set in this register will also set the [PERR] bit. However, abnormality that isn’t

classified in the register can also trigger the [PERR] bit (for example, detecting missing data or wrong data order.

0 = No communication error detected, the forwarded communication frame does not have the BERR inserted

1 = Detected abnormality of the received communication frame. BERR is asserted to the forwarded

communication.

BERR_TAG = Set when the received communication is tagged with BERR.

0 = Received communication frame has no BERR

1 = Received communication frame has BERR

SYNC2 = The Preamble half-bit and the [SYNC1:0] bits are detected. Device is using the timing information that is extracted

from these bits but it is unable to detect valid data.

0 = No error

1 = Error detected

SYNC1 = Unable to detect the preamble half-bit or any of the [SYNC1:0] bits. It could be the bit is missing or the signal is

too distorted to be detectable.

0 = No error

1 = Error detected

BIT = The device has detected a data bit. However, the detection samples are not enough to assure a strong 1 or 0.

0 = No error

1 = Error detected

9.5.4.14.11 DEBUG_COML_RC

Address

Read Only

Name

0x0787

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSVD

RC_IERR

RC_TXDIS

RC_SOF

RC_BYTE

_ERR

RC_UNEXP

RC_CRC

Reset

0

RSVD = Reserved

RC_IERR = Detected initialization byte error in the received command frame. This may due to improper formatting of a byte

such as a frame initialization byte is expected, but start-of-frame (SOF) bit is not set, or an invalid frame type is

selected. Because bytes received on the COMH/COML are propagated up the stack, it is likely devices in the

upper stack will also detect this error. All bytes that follow are ignored until a SOF bit is received.

When a communication frame is ignored, the device will not attempt to detect any communication error in the

ignored frame nor counting it as valid/discard in the frame counters.

0 = Error not detected

1 = Error detected

RC_TXDIS = Valid when [DIR_SEL] = 0. Device detects the COML TX is disabled but the device receives a command to read

data (that is, to transmit data out). The command frame will be counted as a discarded frame.

0 = No error

1 = Error detected

RC_SOF = Valid when [DIR_SEL] = 0. Detects a start-of-frame (SOF) error on COML. The SOF bit is set only in the

initialization frame but the SOF bit is set in the current frame that is not expected.

0 = No error

1 = Error detected

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RC_BYTE_ERR = Valid when [DIR_SEL] = 0. Detected any byte error, other than the error in the initialization byte, in the received

command frame. This error can trigger one or more error bits set in the DEBUG_COMML_BIT register.

0 = No error

1 = Error detected

RC_UNEXP = If [DIR_SEL] = 1, but device received command frame from COML which is an invalid condition and device will

set this error bit.

0 = No error

1 = Error detected

RC_CRC = Indicates a CRC error that resulted in one or more COML command frames being discarded. Any other errors in

the frame are not indicated as the frame was discarded.

0 = No error

1 = Error detected

9.5.4.14.12 DEBUG_COML_RR_TR

Address

0x0788

Bit 7

Read

Only

Bit 6

Bit 5

TR_WAIT

0

Bit 4

RR_TXDIS

0

Bit 3

RR_SOF

0

Bit 2

Bit 1

RR_UNEXP

0

Bit 0

RR_CRC

0

Name

RSVD

RR_BYTE

_ERR

Reset

0

RSVD = Reserved

TR_WAIT = The device is waiting for its turn to transfer a response out but the action is terminated because the device

receives a new command.

This bit is valid when broadcast or stack read command has been issued.

0 = No error

1 = Error detected

RR_TXDIS = Valid when [DIR_SEL] = 1, device receives a response but fails to transmit to the next device because the COML

TX is disabled. The frame is counted as a discarded frame.

0 = No error

1 = Error detected

RR_SOF = Valid when [DIR_SEL] = 1. Detects a start-of-frame (SOF) error on COML. The SOF bit is set only in the

initialization frame but the SOF bit is set in the current frame that is not expected.

0 = No error

1 = Error detected

RR_BYTE_ERR = Valid when [DIR_SEL] = 1. Detects any byte error, other than the error in the initialization byte, in the received

response frame. This error can trigger one or more error bits set in the DEBUG_COMML_BIT register.

0 = No error

1 = Error detected

RR_UNEXP = If [DIR_SEL] = 0, but device received a response frame from COML which is an invalid condition and device will

set this error bit.

0 = No error

1 = Error detected

RR_CRC = Indicates a CRC error that resulted in one or more COML response frames being discarded. Most other errors in

the frame are not indicated as the frame was discarded. If [RR_BYTE_ERR] is observed on the final byte of the

CRC, both CRC and BERR are indicated.

0 = No error

1 = Error detected

9.5.4.14.13 DEBUG_UART_DISCARD

Address

0x0789

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = UART frame counter to track the number of discard frames received or transmitted. The registers of the

DEBUG_UART_DISCARD and DEBUG_UART_VALID* are latched and the related counters are reset when this

register is read.

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9.5.4.14.14 DEBUG_COMH_DISCARD

Address

0x078A

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = COMH frame counter to track the number of discard frames received or transmitted. The registers of the

DEBUG_COMH_DISCARD and DEBUG_COMH_VALID* are latched and the related counters are reset when

this register is read.

9.5.4.14.15 DEBUG_COML_DISCARD

Address

0x078B

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = COML frame counter to track the number of discard frames received or transmitted. The registers of the

DEBUG_COML_DISCARD and DEBUG_COML_VALID* are latched and the related counters are reset when this

register is read.

9.5.4.14.16 DEBUG_UART_VALID_HI/LO

DEBUG_UART_VALID_HI

Address

0x078C

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = The high-byte of UART frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_UART_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_UART_DISCARD is read.

DEBUG_UART_VALID_LO

Address

0x078D

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = The low-byte of UART frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_UART_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_UART_DISCARD is read.

9.5.4.14.17 DEBUG_COMH_VALID_HI/LO

DEBUG_COMH_VALID_HI

Address

0x078E

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

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COUNT[7:0] = The high-byte of COMH frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_COMH_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_COMH_DISCARD is read.

DEBUG_COMH_VALID_LO

Address

0x078F

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = The low-byte of COMH frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_COMH_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_COMH_DISCARD is read.

9.5.4.14.18 DEBUG_COML_VALID_HI/LO

DEBUG_COML_VALID_HI

Address

0x0790

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = The high-byte of COML frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_COML_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_COML_DISCARD is read.

DEBUG_COML_VALID_LO

Address

0x0791

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

COUNT[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

COUNT[7:0] = The low-byte of COML frame counter to track the number of valid frames received or transmitted. Counter

saturates when both DEBUG_COML_VALID_HI/LO is 0xFF. This register is latched and the related counter is

reset when DEBUG_COML_DISCARD is read.

9.5.4.14.19 DEBUG_OTP_SEC_BLK

Address

0x07A0

Bit 7

Read

Only

Bit 6

Bit 5

Bit 4

Bit 3

BLOCK[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

BLOCK[7:0] = Holds last OTP block address where SEC occurred. Valid only when FAULT_OTP[SEC_DET] = 1.

9.5.4.14.20 DEBUG_OTP_DED_BLK

Address

Read Only

Name

0x07A1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

BLOCK[7:0]

Bit 2

Bit 1

Bit 0

Reset

0

BLOCK[7:0] = Holds last OTP block address where DED occurred. Valid only when FAULT_OTP[DED_DET] = 1.

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9.5.4.15 OTP Programming Control and Status

9.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D

Address 0x0300 to

0x0303

RW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

CODE[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

CODE[7:0] = The first 32-bit OTP programming unlock code is required as part of the OTP programming unlock sequence

before performing OTP programming. This 32-bit code is entered in the sequence from OTP_PROG_UNLOCK1A

to OTP_PROG_UNLOCK1D. These registers always read back 0.

9.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D

Address 0x0352 to

0x0355

RW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

CODE[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

CODE[7:0] = The second 32-bit OTP programming unlock code, required as part of the OTP programming unlock sequence

before performing OTP programming. This 32-bit code is entered in the sequence from OTP_PROG_UNLOCK2A

to OTP_PROG_UNLOCK2D. These registers always read back 0.

9.5.4.15.3 OTP_PROG_CTRL

Address

RW

0x030B

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

PAGESEL

0

Bit 0

PROG_GO

0

Name

Reset

RSVD

0

RSVD = Reserved

PAGESEL = Selects which customer OTP page to be programmed.

0 = page 1

1 = page 2

PROG_GO = Enables programming for the OTP page selected by OTP_PROG_CTRL[PAGESEL]. Requires

OTP_PROG_UNLOCK1* and OTP_PROG_UNLOCK2* registers are set to the correct codes.

0 = Ready

1 = Start OTP programming

9.5.4.15.4 OTP_ECC_TEST

Address

RW

0x034C

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

RSVD

DED_SEC

MANUAL_

AUTO

ENC_DEC

ENABLE

Reset

0

RSVD = Reserved

DED_SEC = Sets the decoder function (SEC or DED) to test. This bit is ignored during encoder testing.

0 = Test SEC functionality. Sets the FAULT_OTP[SEC_DETECT] flag and outputs test result to

OTP_ECC_DATAOUT* registers.

1 = Test DED functionality. Sets the FAULT_OTP[DED_DETECT] flag and outputs test result

OTP_ECC_DATAOUT*.

Note: If SEC or DEC fault is detected, host sets [RST_OTP_DATA] = 1 to reset the corresponding fault. Switch to

run SEC test does not clear DEC fault or vice versa.

MANUAL_AUTO = Sets the location of the data to use for the ECC test.

0 = Auto mode. Use the internal data for test.

1 = Manual mode. Uses data in ECC_DATAIN_n registers for test. Use for MPF test.

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ENC_DEC = Sets the encoder/decoder test to run when OTP_ECC_TEST[ENABLE] = 1.

0 = Run decoder test

1 = Run encoder test

ENABLE = Executes the OTP ECC test configured by [ENC_DEC] and [DED_SEC] bits.

0 = Normal operation, ECC test disabled

1 = Initiate test

9.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9

Address 0x0343 to

0x034B

RW

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

DATA[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

DATA[7:0] =

When ECC is enabled in manual mode, CUST_ECC_TEST[MANUAL_AUTO] = 1, OTP_ECC_DATAIN1…9

registers are used to test the ECC encoder/decoder.

If CUST_ECC_TEST[ENC_DEC] = 1, ECC_DATAIN8 through ECC_DATAIN1 are fed to the encoder.

If CUST_ECC_TEST[ENC_DEC] = 0, ECC_DATAIN9 through ECC_DATAIN1 are fed to the decoder. The

ECC_DATAOUT0…8 bytes must be read back to verify functionality.

9.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9

Address 0x0510 to

0x0518

Read

Only

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

DATA[7:0]

Bit 2

Bit 1

Bit 0

Name

Reset

0

DATA[7:0] = OTP_ECC_DATAOUT* bytes output the results of the ECC decoder and encoder tests.

If CUST_ECC_TEST[ENC_DEC] = 0, ECC_DATAOUT8 through ECC_DATAOUT1 are read to determine a

successful decoder test.

If CUST_ECC_TEST[ENC_DEC] = 1, ECC_DATAOUT9 through ECC_DATAOUT1 are read to determine a

successful encoder test. The correct result depends on the input to the test.

9.5.4.15.7 OTP_PROG_STAT

Address

Read Only

Name

0x0519

Bit 7

Bit 6

OTERR

0

Bit 5

UVERR

0

Bit 4

OVERR

0

Bit 3

SUVERR

0

Bit 2

SOVERR

0

Bit 1

PROGERR

0

Bit 0

DONE

0

UNLOCK

0

Reset

UNLOCK = Indicates the OTP programming function unlock status. After this bit is set (that is, OTP programming is enabled),

the host writes to the OTP_PROG_CTRL register to start the OTP programming. Writing to any other register

relocks the OTP programming function and clears this bit to 0. [PROG_GO] = 1 also clears this bit to 0.

0 = OTP programming locked

1 = OTP programming is unlocked

OTERR = Indicates the die temperature is greater than T_{OTP_PROG}and device does not start OTP programming.

0 = No fault

1 = Detected die temperature is greater than T_{OTP_PROG}. Abort OTP programming.

UVERR = Indicates an undervoltage error detected on the programming voltage during OTP programming. This bit is

cleared with [PROG_GO] = 1.

0 = No error

1 = UV error detected

OVERR = Indicates an overvoltage error detected on the programming voltage during OTP programming. This bit is cleared

with [PROG_GO] = 1. Information received from the device with this error must not be considered reliable.

0 = No error

1 = OV error detected

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SUVERR = A programming voltage stability test is performed before starting the actual OTP programming. This bit indicates

an undervoltage error is detected during the voltage stability test. This bit is cleared with [PROG_GO] = 1.

0 = No error

1 = UV error detected during OTP programming voltage stability test

SOVERR = A programming voltage stability test is performed before starting the actual OTP programming. This bit indicates

an overvoltage error is detected during the voltage stability test. This bit is cleared with [PROG_GO] = 1.

0 = No error

1 = OV error detected during OTP programming voltage stability test

PROGERR Indicates when an error is detected due to incorrect page setting caused by any of the following:

=

•

Trying to program but OTP programming [UNLOCK] = 0.

Trying to program a page that has [TRY] = 1.

Trying to program a page which has [FMTERR] = 1.

This bit is cleared with [PROG_GO] = 1.

0 = No error or programming not attempted

1 = Error detected

DONE = Indicates the status of the OTP programming for the selected page. This bit is cleared with [PROG_GO] = 1.

0 = Not completed or programming not attempted

1 = Complete.

9.5.4.15.8 OTP_CUST1_STAT

Address

Read Only

Name

0x051A

Bit 7

Bit 6

LOADWRN

0

Bit 5

LOADERR

0

Bit 4

FMTERR

0

Bit 3

PROGOK

0

Bit 2

UVOK

0

Bit 1

OVOK

0

Bit 0

TRY

0

LOADED

0

Reset

LOADED = Indicates OTP page 1 has been selected for loading into the related registers. See [LOADERR] and [LOADWRN]

for error and warning status.

0 = Not selected for loading

1 = Page 1 selected and loaded

LOADWRN Indicates OTP page 1 was loaded but with one or more SEC warnings.

= 0 = No warning, or no load attempted

1 = Warning

LOADERR = Indicates an error while attempting to load OTP page 1; that is, DED is detected while loading the selected page.

0 = No error, or no load was attempted.

1 = Error detected

FMTERR = Indicates a formatting error in OTP page 1; that is, when [UVOK] or [OVOK] is set, but [TRY] = 0. Do not program

if this bit is set.

0 = No error

1 = Error detected

PROGOK = Indicates the validity for loading for OTP page 1. A valid page indicates that successful programming occurred.

0 = Not valid

1 = Valid

UVOK = Indicates an OTP programming voltage undervoltage condition is detected during programming attempt for OTP

page 1. The OV condition may also trigger the UV as part of the shutdown process.

0 = UV condition detected. Also reads as 0 if no programming attempt is performed.

1 = No UV condition detected

OVOK = Indicates an OTP programming voltage overvoltage condition is detected during programming attempt for OTP

page 1. The OV condition will trigger the UV as part of the shutdown process. The device must be taken out of

service.

0 = OV condition detected. Also reads as 0 if no programming attempt is performed.

1 = No OV condition detected

TRY = Indicates a first programming attempt for OTP page 1.

0 = No first attempt made

1 = First attempt made

9.5.4.15.9 OTP_CUST2_STAT

Address

0x051B

Bit 7

Read Only

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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Name

Reset

LOADED

LOADWRN

0

LOADERR

0

FMTERR

0

PROGOK

0

UVOK

0

OVOK

0

TRY

0

LOADED = Indicates OTP page 2 has been selected for loading into the related registers. See [LOADERR] and [LOADWRN]

for error and warning status.

0 = Not selected for loading

1 = Page 2 selected and loaded

LOADWRN Indicates OTP page 2 was loaded but with one or more SEC warnings.

= 0 = No warning, or no load attempted

1 = Warning

LOADERR Indicates an error while attempting to load OTP page 2; that is, DED is detected while loading the selected page.

= 0 = No error, or no load was attempted.

1 = Error detected

FMTERR = Indicates a formatting error in OTP page 2; that is, when [UVOK] or [OVOK] is set, but [TRY] = 0. Do not program

if this bit is set.

0 = No error

1 = Error detected

PROGOK = Indicates the validity for loading for OTP page 2. A valid page indicates that successful programming occurred.

0 = Not valid

1 = Valid

UVOK = Indicates an OTP programming voltage undervoltage condition is detected during programming attempt for OTP

page 2. The OV condition may also trigger the UV as part of the shutdown process.

0 = UV condition detected. Also reads as 0 if no programming attempt is performed.

1 = No UV condition detected

OVOK = Indicates an OTP programming voltage overvoltage condition is detected during programming attempt for OTP

page 2. The OV condition will trigger the UV as part of the shutdown process. The device must be taken out of

service.

0 = OV condition detected. Also reads as 0 if no programming attempt is performed.

1 = No OV condition detected

TRY = Indicates a first programming attempt for OTP page 2.

0 = No first attempt made

1 = First attempt made

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10 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

The BQ7961x-Q1 device family provides high-accuracy, cell voltages and temperature measurements for 6-

series to 16-series battery modules.

10.2 Typical Applications

10.2.1 Base Device Application Circuit

The following application circuit (see 图10-1) is based on the BQ79616-Q1 device connecting to a 16S module.

To COML of the

North Device

Isolation

Circuit

COMHP

CVDD

N

COMHN

CVSS

N

1

DVDD

DVSS

N

10 kꢀ

TSREF

GPIO1

N

1

REFHP

REFHM

N

GPIO2

GPIO3

AVDD

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

NEG5V

AVSS

N

LDOIN

If communication device is used on the system side

If NO (system side) communication device is in use

NPNB

BAT

200

ꢀ

100

ꢀ

30

ꢀ

RX

TX

To CVDD

VCC2

VCC

10 nF

100 kꢀ

VCC1

100 kꢀ

PMIC

VCC

INA

TX

RX

100

ꢀ

NFAULT

AVSS

N

OUTA

OUTB

RX

TX

VC16

VC15

BAT

0.47 uF

OPTIONAL

INB

OUTC

INT

+

CELL 16

CELL 15

1

optional

RS

TX

RX

NFAULT

HV to LV

Isolation

(Transformer)

INC

GND

GND2

0.47 uF

TX

GND1

optional

MCU

SYS

100

ꢀ

COMLN

COMLP

COMHP NFAULT

COMHN

VC1

VC0

ISO774x

0.47 uF

1

MCU

BQ79600

Communication Device

(Base Device)

+

0.47 uF

CELL

1

To COMH of the

Top of Stack

10

ꢀ

CB16

CB15

CELL 16

CELL 15

COMLN

COMLP

0.47 uF

10

Isolation

circuit

10

ꢀ

CB1

CB0

CELL

1

OPTIONAL: Only necessary for ring

architecture applications

0.47 uF

CELL 1-

BBP

BBN

图10-1. Typical Base Device with Measurement Application Circuit

10.2.1.1 Design Requirements

表10-1 below shows the design parameters.

表10-1. Recommended Design Requirements

PARAMETER

VALUE

Module Voltage Range (Voltage at the BAT pin)

9V to 80V

6 to 16 cells (BQ79616-Q1), 6 to 14 cells (BQ79614-Q1), 6 to 12

cells (BQ79612-Q1)

Number of cells (single device)

Cell voltage range

0V to 5V

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10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Cell Sensing and Balancing Inputs

Related Pins

Components

Filter resistor

Value

Description

VC0 to VC16

Only differential RC filters are needed for VC channels. Besides serving for

input signal filtering, these components are required to support hot-plug events

during cell module insertion. Hence, it is highly recommended to use the

component values as suggested.

100 Ω

Filter capacitor

0.47 μF/16 V

or 1 μF/16 V

CB0 to CB16

Filter resistor

Depends on

The filter resistor on CB pins sets the maximum balancing current. See 节9.3.3

system’s

for details.

balancing current Only differential RC filters are needed for CB channels.

requirements

Besides serving for input signal filtering, these components are required to

support hot-plug events during cell module insertion. Hence, it is highly

recommended to use the component values as suggested.

Filter capacitor

0.47 μF/16 V

or 1 μF/16 V

Cell Connections

It is recommended to populate the battery cells from bottom channels (both VC and CB channels) and up,

leaving upper channels as unused channels if cell module size is smaller than the maximum channel size of the

BQ7961x-Q1 device. Unused channel(s) in BQ79616-Q1, BQ79614-Q1, and BQ79612-Q1 will be connected as

shown in 图 10-2. PCB Layout for open/NC pins should have minimum trace lengths and should not be

connected to a wire or cable.

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30 ꢀ

BAT

30 ꢀ

BAT

VC16 (or NC in 14S/12S device)

100 ꢀ

VC16

CB16

CB16 (or NC in 14S/12S device)

VC15 (or NC in 14S/12S device)

CB15 (or NC in 14S/12S device)

10 ꢀ

+

CELL16

CELL15

100 ꢀ

VC15

CB15

10 ꢀ

VCn+1

CBn+1

100 ꢀ

VC14

CB14

VCn

10 ꢀ

+

CELL n

CELL14

10 ꢀ

CBn

100 ꢀ

VCn

+

CELL n

(b) One PCB for all channels applications œ For BQ79616: Configured for 16 VC and CB

(a) Customized PCB for certain channels applications - Short unused pins to BAT Pin

30 ꢀ

BAT

100 ꢀ

VC16/NC

10 ꢀ

+

CB16/NC

CELL16

30 ꢀ

100 ꢀ

VC15/NC

BAT

10 ꢀ

+

CB15/NC

CELL15

CELL14

100 ꢀ

VC16

VC14/NC

CB14/NC

10 ꢀ

+

CB16

+

CELL16

100 ꢀ

VC15

VC13/NC

CB13/NC

10 ꢀ

+

CB15

CELL15

CELL13

CELL12

100 ꢀ

VC14

CB14

VC12

CB12

10 ꢀ

+

CELL14

100 ꢀ

VCn

+

CELL n

(d) One PCB for all channels applications œ For BQ79612: Configured for 12 VC and CB

If floating the unused VC and CB pins, capacitors in black corresponding to CB pins need

to be populated, but capacitors and resistors in grey corresponding to VC and CB pins

need to be unpopulated

(c) One PCB for all channels applications œ For BQ79616: Configured for 15 VC and CB

If floating the unused VC and CB pins, capacitors in black corresponding to CB pins need

to be populated, but capacitors and resistors in grey corresponding to VC and CB pins

need to be unpopulated

图10-2. Unused VC and CB Channels

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10.2.1.2.2 BAT and External NPN

Related Pins

BAT

Components

Filter resistor

Value

Description

Single-ended RC filter, recommended values must be used for

hot-plug performance.

30 Ω

Filter capacitor

10 nF/100 V

Can use lower voltage rating based

on module size

NPNB

NPN (Q1)

The external NPN is used to form a pre-regulation circuit to

provide a 6-V (typical) input to the LDOIN pin.

The voltage rating of the NPN can be optimized by the following

equation:

Collector–emitter breakdown

voltage 80 V to 100 V, but can use

lower rating based on module size

Power rating ≥1 W

NPN voltage rating = Max VModule –Min VLDOIN + Margin

Where:

Gain > 80 at the expected load

current

Max VModule = maximum module voltage with fully charged

cells

Current handling >100 mA

Min VLDOIN = the minimum spec of the VLDOIN parameter

Margin = system transient voltage + design margin per

application requirement

Resistor on

Various based on module voltage

The resistor has a couple purposes:

external NPN

collector (R_NPN

(a) For an RC filter for the NPN pre-regulation circuit

(b) Share the thermal dissipation with the NPN

)

Capacitor on

external NPN

collector

The capacitor forms the RC filter for the NPN pre-regulation

circuit

The capacitor rating is based on peak voltage spike seen on the

module. For smaller module size, <100-V rated capacitor can be

used. System designer selects the optimized voltage-rated

capacitor per their system tolerance and requirements.

0.22 μF/100 V

Can use lower voltage rating based

on module size

To reduce the power rating needed for the external NPN (Q1), system designer can put power resistors on the

NPN collector to create IR drop from the module voltage (VModule). 图 10-3 shows the current paths to power

the BQ7961x device.

Typical ISTARTUP current i.e. Inrush startup current when device enters from SHUTDOWN to ACTIVE is 20mA

for TI recommended components. This current is sum of IBAT + ILDOIN, and is dependent on PCB board

components and layout, so recommend user to characterize on their end.

Main current path to power the device

VModule

VCollector

0.22 µF

R_NPN

30 ꢀ

BAT

Small current path

to BAT to power an

Always-On circuit in

the device

Q1

NPNB

10 nF

100 ꢀ

LDOIN

VC16

+

0.1 µF

CELL 16

图10-3. Power Consumption Paths

To ensure there is sufficient headroom to maintain 6 V (typical) regulated voltage on LDOIN pin, system designer

ensures VCollector has ≥8 V at any time with the assumption of about 2-V drop across the NPN.

Hence, maximum allowable R_NPNvalue = ((Min VModule) –(VCollector)) / (Max peak current)

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Where:

Min VModule: based on module size and minimum cell voltage per application

VCollector: 8 V with the assumption of about 2-V drop across NPN

Max peak current: highest operation current, which is the active current with all functions turned on. Note that

different communication isolation components (for example, capacitor isolation versus transformer, or the type of

transformer) contribute different loading to the total power consumption.

Power the device separately from the to of the battery stack:

The device is designed to be powered by the battery stack. If there is a need to power the device from a

separately source such as in 图 10-4, the following relationship between the voltage on the BAT pin and the

highest VC pin voltage (with respected to ground): BAT voltage >= (0.5 * highest VC voltage) + 2

For example, if the device is connected to a 14S module with max cell voltage of 4.2V/cell, the highest VC pin is

VC14, and the highest VC14 voltage is (4.2V * 14) = 58.8V. If the BAT pin is powered separately, BAT voltage

must be >= 31.4V.

Similarly, if BBP/N channel is connected above the highest cell stack, the BBP pin will has the highest voltage

(with respected to ground) than the VC pins. In this scenario, VBAT >= [(VBBP-2.5) * 0.84] + 4.5.The

requirement applies when BAT is power separately and it is to ensure proper operation of the internal level

shifter. Fail to maintain the voltage relationship will increase the ADC measurement error on the VC and BB

channels.

R_NPN

30 ꢀ

Separate

Power

source

BAT

0.22 µF

Q1

NPNB

10 nF

Top of stack

module

100 ꢀ

LDOIN

VC14

+

0.1 µF

CELL 14

图10-4. Separate Power Source to BAT

10.2.1.2.3 Power Supplies, Reference Input

Related Pins

AVDD, TSREF

DVDD

Components

Bypass capacitor

Bypass Capacitor

Bypass capacitor

Value

Description

Bypass capacitor for the internal LDOs

1 μF/10 V

2.2 μF/10 V

4.7 µF/10 V

0.1 μF/10 V

Bypass capacitor for DVDD

CVDD

Bypass capacitor for CVDD

NEG5V

Bypass capacitor for the negative charge pump

10.2.1.2.4 GPIO For Thermistor Inputs

When using external thermistor, for ADC measurement only, there is no limitation of what type of thermistors

(NTC or PTC) or the bias resistor (R1) value or whether the thermistor is placed on high side or low side with

respected to the bias resistor.

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However, when using with the integrated OTUT comparators, the programmable OT and UT threshold ranges

are designed to work with a 103NTC (10 kΩ at 25°C) type of NTC thermistor, following the connection shown in

图10-5 with different options for the R1 and R2 resistors.

• Option 1: R₁= 10 kΩ, and no R₂

• Option 2: R₁= 10 kΩ, and R₂= 100 kΩ for better linearity at cold temperature

• Option 3: R₁= 3.6 kΩ, and R₂= 15 kΩ. This base option can be used for NTC used for the OTCB feature

assuming system designer allows the PCB temperature to be higher than the cell temperature during

balancing. Because the device does not differentiate which NTC is used on the cells versus the PCB, NTC

biasing with this option scales the NTC’s hot temperature curve differently, allowing the threshold set for OT

comparator to be triggered at a lower GPIO voltage. Thus, making the device to only trigger OTCB threshold

on this NTC.

The device does not require external RC for temperature measurement. However, it is common for system

designer to add an RC filter on the GPIO pin for the NTC circuit. System designer can select the RC values for

the application need. Example: R_GPIO= 1 kΩ, C_GPIO= 0.1 μF to 1 μF.

Unused GPIO must be grounded to AVSS with a 10-kΩresistor.

Device

TSREF

1 …F

R₁

R_GPIO

(OPTIONAL)

GPIO1

R₂

(OPTIONAL)

C_GPIO

(OPTIONAL)

图10-5. NTC Connection

10.2.1.2.5 Internal Balancing Current

When internal cell balancing is used, the max balancing current the device can support (before going into

thermal pause) can vary based on the ambient temperature.

10.2.1.2.6 UART, NFAULT

If device is used as a base device, the UART interface requires the TX and RX pins are pulled up through a 10-

kΩ to 100-kΩ resistor. Do not leave TX and RX unconnected. The TX must be pulled high to prevent triggering

an invalid communications frame during the idle state. When using a serial cable to connect to the host

controller, connect the TX pull-up on the host side and the RX pull-up to the CVDD on the device side.

If device is used as a stack device, the TX pin is disabled by default and is left floating. RX pin is shorted to

CVDD.

NFAULT pin for base device, if not used, must be left floating. Otherwise, pull it up with 100-kΩ to CVDD.

NFAULT pin on stack device is floating.

10.2.1.2.7 Daisy Chain Isolation

The device works with multiple daisy chain isolation types: capacitor isolation, capacitor-choke isolation, and

transformer isolation. For devices that are daisy-chained on the same PCB, capacitor isolation without ESD

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diode as shown in 图 10-6 is sufficient. Unused COMLP/H or COMHP/N pins must be connected with 1-kΩ

termination resistor.

10.2.1.2.7.1 Devices Connected on the Same PCB

表10-2. Isolation Components for Devices Connected on the Same PCB

Components

R_TERM

Value

1 kΩ

49 Ω

Description (Capacitor Isolation on the Same PCB)

Termination resistor

R_SERIES

Filter resistor and impedance matching resistor.

The connection between devices must be ~120 Ω (~50 Ω on each end of the signal connection of

the device plus 10-Ω internal resistance)

C_BYPASS

C_ISO

220 pF/50 V

2.2 nF

Bypass capacitor

Isolation capacitor

Voltage rating depends on application requirement. It is common to select 2x of module voltage

rating to provide standoff margin in the event of a fault in the system.

C_ISO

2.2 nF

R_SERIES

49 Ω

R_SERIES

49 Ω

COMLP

COMHP

C_BYPASS

220 pF

C_BYPASS

220 pF

R_TERM

1 kꢀ

R_TERM

1 kꢀ

C_ISO

2.2 nF

R_SERIES

49 Ω

R_SERIES

49 Ω

COMLN

COMHN

C_BYPASS

220 pF

C_BYPASS

220 pF

Components Required for Cap Coupled Daisy Chain on the same PCB

图10-6. Capacitor Isolation with Devices on the Same PCB

10.2.1.2.7.2 Devices Connected on Different PCBs

For devices that are daisy-chained to different PCBs through a pair of twisted cables, all three isolation types can

be used for daisy chain isolation, however it is not possible to use one type of isolation on one side of the daisy

chain (for example, transformer isolation on COMLP/N to the Battery Management Unit) while using a different

type of isolation for the other side of the daisy chain (for example, capacitor isolation on COMH/N to the Cell

Module Unit).

Option 1: Capacitor Isolation

表10-3. Components for Capacitor Isolation on Different PCBs

Components

R_TERM

Value

1 kΩ

49 Ω

Description (Capacitor Isolation Between PCBs)

Termination resistor

R_SERIES

Filter resistor and impedance matching resistor.

The connection between devices must be ~120 Ω (~50 Ω on each end of the signal connection of

the device plus 10-Ω internal resistance)

C_BYPASS

C_ISO

220 pF/50 V

2.2 nF

Bypass capacitor

Isolation capacitor

Voltage rating depends on application requirement. It is common to select 2x of module voltage

rating to provide standoff margin in the event of a fault in the system.

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表10-3. Components for Capacitor Isolation on Different PCBs (continued)

Components

Value

Description (Capacitor Isolation Between PCBs)

ESD diode

TVS diode

The ESD protector should provide protection to the communication interface pins during hot-plug

events and also for absorption of high-voltage transients during service disconnect or reconnect.

Select the ESD diodes to limit the maximum voltage on the COM* bus to below the maximum

rating. A voltage rating close to the maximum voltage to provide the highest possible common-

mode voltage range is recommended for best EMC performance. The capacitance must be low

compared to the coupling capacitance (if using capacitor coupling).

C_ISO

2.2 nF

C_ISO

2.2 nF

R_SERIES

49 Ω

R_SERIES

49 Ω

COMLP

COMHP

C_BYPASS

220 pF

ESD

R_TERM

1 kΩ

R_TERM

1 kΩ

R_SERIES

49 Ω

R_SERIES

49 Ω

COMLN

COMHN

Twisted pair cabling

between modules

C_BYPASS

220 pF

C_BYPASS

220 pF

C_ISO

2.2 nF

C_ISO

2.2 nF

Components Required for Cap Coupled Daisy Chain on different pcb

图10-7. Capacitor Isolation on Different PCB

图 10-7 shows the capacitor isolation circuit for devices connecting between PCBs. Similar to the capacitor

isolation on the same PCB case, the capacitor must be rated with a high enough voltage to provide standoff

margin in the event of a fault in the system that exposes the device to a local hazardous voltage. The voltage is

determined by the application requirement but it is common to select 2x of the module voltage.

The capacitance on the daisy chain bus has a direct effect on performance. All parasitic capacitances from the

support components and cabling must be taken into consideration when designing for communication

robustness to EMC. Capacitance from the cables, ESD diodes, bypass capacitance, and chokes form a

capacitive divider with the isolation capacitors that may affect performance. Additionally, the amount of

capacitance on the bus has a direct impact to the operating current during communication (the capacitor

charging or discharging).

Option 2: Capacitor Plus Common-Mode Choke Isolation

表10-4. Components for Capacitor Plus Common-Mode Choke Isolation

Components

R_TERM

Value

1 kΩ

49 Ω

Description (Capacitor Plus Choke Isolation Between PCBs)

Termination resistor

R_SERIES

Filter resistor and impedance matching resistor.

The connection between devices must be ~120 Ω (~50 Ω on each end of the signal connection of

the device plus 10-Ω internal resistance)

C_BYPASS

C_ISO

220 pF/50 V

2.2 nF

Bypass capacitor

Isolation capacitor

Voltage rating depends on application requirement. It is common to select 2x of module voltage

rating to provide a standoff margin in the event of a fault in the system.

Common-mode

choke

100 μH to 500 Common-mode choke (The inductance range 100 μH to 500 μH is a general guidance value, not

a guaranteed range as there are many parameters affecting the performance of common-mode

choke. When coming to specific recommended part, please refer to SLVAEP4 BQ79616-Q1 Daisy

Chain Communications Application Report. User shall perform the through test in their

environment.)

μH

ESD diode

(optional)

TVS diode

Optional ESD protection depends on pcb level ESD requirement (Adding this diode or not is subject

to the user’s system level ESD requirement)

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C_ISO

2.2 nF

C_ISO

2.2 nF

R_SERIES

49 Ω

R_SERIES

49 Ω

COMLP

COMHP

Common-mode

Choke

Common-mode

Choke

ESD (optional)

R_TERM

1 kΩ

R_TERM

1 kΩ

C_ISO

2.2 nF

R_SERIES

49 Ω

470 µH

R_SERIES

49 Ω

470 µH

COMLN

COMHN

Twisted pair cabling

between modules

C_BYPASS

220 pF

C_ISO

2.2 nF

C_BYPASS

220 pF

Components Required for cap-choke Daisy Chain with Cabling

图10-8. Capacitor Plus Choke Isolation

Longer cable lengths, or abnormally noisy applications may require the use of a common-mode choke filter.

Capacitor plus choke isolation has better noise immunity than capacitor only. For these applications, use an

automotive grade from 100 μH to 500 μH common-mode filter minimum for proper operation. To achieve the

best performance in noisy environments, use dual common-mode filters (470 μH). The recommended

impedance of the choke is at least 1 kΩfrom 1 MHz to 100 MHz and above 300 Ωfor higher frequencies.

Option 3: Transformer Isolation

表10-5. Components for Transformer Isolation

Components

R_TERM

Value

1 kΩ

49 Ω

Description (Capacitor Plus Choke Isolation Between PCBs)

Termination resistor

R_SERIES

Filter resistor and impedance matching resistor.

The connection between devices must be ~120 Ω (~50 Ω on each end of the signal connection

of the device plus 10-Ω internal resistance)

C_BYPASS

220 pF/50 V

Bypass capacitor

Transformer

Inductance: 150 μH The inductance range 150 μH to 1400 μH is a general guidance value, not a guaranteed range

as there are many parameters affecting the performance of transformer. When coming to

specific recommended part, please refer to SLVAEP4 BQ79616-Q1 Daisy Chain

Communications Application Report. User shall perform the through test in their environment.

to 1400 μH

ESD diode

(optional)

TVS diode

Optional ESD protection depends on pcb level ESD requirement (Adding this diode or not is

subject to the user’s system level ESD requirement)

Transmformer

Isolation

Transmformer

Isolation

R_SERIES

49 Ω

R_SERIES

49 Ω

COMHP

COMLP

ESD (optional)

C_BYPASS2

100 pF

R_TERM

1 kΩ

R_TERM

1 kΩ

R_SERIES

49 Ω

R_SERIES

49 Ω

COMHN

COMLN

C_BYPASS

220 pF

Twisted pair cabling

between modules

图10-9. Transformer Isolation

Transformer isolation is supported and can be implemented as above. For example, transformer isolation can be

used between the low-voltage and high-voltage boundary for galvanic isolation.

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10.2.1.3 Application Curve

图10-10. Response Frame for 8 Registers Read from Stack Devices

10.2.2 Daisy Device Application Circuit

The following application circuit (see 图10-11) is based on the BQ79616-Q1 device connecting to a 16S module.

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HV System

(Cell Module Control)

LV System

(Battery Management Unit)

OPTIONAL: Only necessary for ring architecture applications

Leave unconnected for

Top of Stack Device

COMHP

COMHN

Isolation

circuit

1

kꢀ

CVDD

CVSS

N

COMHP

COMHN

N

DVDD

DVSS

N

To COML of the Base

Device

REFHP

REFHM

N

AVDD

1

NEG5V

AVSS

10 kꢀ

N

TSREF

GPIO1

N

LDOIN

1

GPIO2

NPNB

BAT

200

ꢀ

100

ꢀ

30

ꢀ

RX

TX

To CVDD

10 nF

100

ꢀ

NFAULT

N

VC16

0.47 µF

+

CELL 16

0.47 uF

VC0

0.47 µF

CELL

1

Isolation

N

10

ꢀ

N

CB16

CELL 16

0.47 uF

COMLN

COMLP

ꢀ

CELL

1

CB0

0.47 uF

Stack-N Device

N

Isolation

circuit

CVDD

CVSS

N

COMHP

COMHN

N

DVDD

DVSS

N

REFHP

REFHM

N

1

10 kꢀ

N

TSREF

GPIO1

1

AVDD

NEG5V

AVSS

GPIO2

N

LDOIN

NPNB

BAT

CVDD

200

ꢀ

100

ꢀ

30

ꢀ

RX

TX

10 nF

NFAULT

AVSS

100

ꢀ

N

VC16

Bq79600

Communication Device

0.47 µF

PMIC

VCC

+

CELL 16

0.47 µF

BAT

1

100

HV to LV Isolation

(Transformer)

VC0

RX

TX

RX

0.47 µF

CELL

1

COMHP

COMHM

NFAULT

GND

N

10

ꢀ

N

To COMH of the

Top of Stack

CB16

MCU

CELL 16

0.47 µF

COMLN

COMLP

ꢀ

CELL

1

COMLN

COMLP

CB0

0.47 µF

Stack 1 Device

Isolation

circuit

N

OPTIONAL: Only necessary for ring architecture applications

图10-11. Daisy Device Application Circuit

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10.2.2.1 Design Requirements

See 节10.2.1.1 section for design requirements.

10.2.2.2 Detailed Design Procedure

See 节10.2.1.2 section for detailed design procedure.

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11 Power Supply Recommendations

The device is powered by BAT pin and the LDOIN pin, with which the LDOIN pin is regulated by the pregulation

circuit form with an external NPN. The device can be powered by a battery module as low as 9 V (without OTP

programming) on the BAT pin. However, system designer must scale the R_NPNresistor accordingly to ensure

there is sufficient headroom to have 6 V on the LDOIN pin after the IR drop across R_NPNand the external NPN.

Example, if BAT voltage is at 9 V, the R_NPNreduces to 10 Ω to allow sufficient voltage at the LDOIN pin.

Scale the value of RNPN according to the min

module voltage.

R_NPN

Lower the min module voltage in application,

smaller the RNPN value should be used

30 ꢀ

BAT

0.22 mF

10 nF

NPNB

Q1

100 ꢀ

VC16

LDOIN

+

0.1 µF

CELL 16

图11-1. Device Powering Path

Multiple cell modules can be connected to the same device through the bus bar support of the BQ7961x-Q1

family. The same power will be drawn from each of the cell modules.

Main current path to power the device

Small current path to BAT

for an Always-on circuit

R_NPN

30 ꢀ

BAT

0.22 …F

Q1

NPNB

10 nF

LDOIN

0.1 …F

图11-2. Device Can Be Powered by Multiple Cell Modules in Stack

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12 Layout

The layout for this device must be designed carefully. Any design outside these guidelines can affect the ADC

accuracy and EMI performance. Care must be taken in the layout of signals to and from the device to avoid

coupling noise onto sensitive inputs. The layout of ground and power connections, as well as communication

signals, should also be made carefully.

12.1 Layout Guidelines

12.1.1 Ground Planes

It is very important to establish a clean grounding scheme to ensure best performance of the device. There are

three ground pins (AVSS, DVSS, CVSS) for the device’s internal power supplies and one ground reference

(REFHM) for the precision reference. There are noisy grounds and quiet grounds that must be separated in the

layout initially and re-joined together in a lower PCB layer. The external components (for example, bypass

capacitors) must be tied to the proper grounding group if possible to keep the separation of noisy and quiet

grounds apart.

• AVSS ground:

– Bypass capacitor for these pins: BAT, VC0, CB0, and AVDD.

– Package power pad.

• DVSS ground:

– Bypass capacitor for DVDD.

– GPIO filter capacitor (if used). It can also connect to AVSS ground plane, if needed.

• CVSS ground:

– Bypass capacitor for GPIOs, CVDD, TSREF, NEG5V, LDOIN, COMHP/N, and COMLP/N.

• REFHM ground:

– Bypass capacitor for REFHP.

– If possible, separate out REFHM from AVSS on the signal connection layer and re-connect REFHM to

AVSS ground plane in the lower layer.

Even on a PCB layer that is mainly for signal routing, it is good practice to pour have a small island of ground

pour if possible to provide a low-impedance ground, rather than simply a via through the ground trace to an

lower ground plane.

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Create more solid ground planes as well as separating noisy and

quiet grounds for better performance

Main Ground Plane

DVSS

Connect all grounds together

CVSS

BAT

CVSS

CVDD

Layer1

Layer2

NEG5V

Layer3

AVSS

REFHP

REFHM

Small island of ground pour if possible

to via down to lower layers

REFHM

AVSS

Connect REFHM to AVSS

图12-1. Grounding Layout Consideration

If multiple devices are placed on the same PCB, each device must have its own ground plane with proper layout

clearance.

Ground Plane 2

bq796xx

Device 2

Proper clearance is

required. Depends on

the number of cells

connects to each

device, the 2 grounds

can be >50V apart

Ground Plane 1

bq796xx

Device 1

图12-2. Separate Ground Planes Per Device on the Same PCB

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12.1.2 Bypass Capacitors for Power Supplies and Reference

The bypass capacitors of the following pins must be placed as close to the device pins as possible to ensure

proper performance, especially for the REFHP capacitor.

• REFHP, BAT, LDOIN, AVDD, DVDD, CVDD, TSREF, and NEG5V

12.1.3 Cell Voltage Sensing

Cell voltage sensing traces (VC pins and CB pins) must be placed in parallel with impedance matching. The

balancing traces (CB pins) must be sized properly to carry the maximum balancing current and proper thermal

performance for the application.

It is recommended to use separate cables, connect tabs, and PCB traces for the BAT pin and top VC pin

connections. Same applies to AVSS and VC0 connections. This avoids the device current impact on the top and

bottom cell voltage measurements.

If the same cable and connector tab is used for BAT/top VC pins connection and AVSS/VC0 pins connection, the

PCB trace going to BAT/top VC pins and AVSS/VC0 pins must be separated at the connector tabs. Note the

device current will still go through the cell to the PCB cable, which may introduce IR errors across the cable

connection to the top and bottom cell measurements.

12.1.4 Daisy Chain Communication

It is important to have proper layout on the COMHP/N and COMLP/N circuits in order to have the best robust

daisy chain communication.

• Keep differential traces as short as possible and as straight as possible. Minimize turns and avoid any

looping on the traces.

• Keep the differential traces on the same layers. Run the trace in parallel with shielding and matching trace

impedance.

• Place the isolation components close to the connectors.

• When using capacitive isolation, place the high-voltage capacitor of the COMxP/N pair (where x = H or L)

close to each other along the parallel traces.

• Create a keep-out area (no other traces and no ground plane) around the daisy chain components in all PCB

layers.

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Main Ground Plane

R_TERM

1 kΩ

Layer1

Layer2

Keep-out area: no other

traces/ground plans

CVSS

Layer3

CVSS

CVDD

R_SERIES

49Ω

R_SERIES

49Ω

NEG5V

COMHP

C_ISO

2.2 nF

C_ISO

2.2 nF

R_SERIES

49Ω

R_SERIES

49Ω

COMHN

COMLN

COMLP

R_TERM

1 kΩ

Shield COMH/L traces

Daisy chain communication

circuits

Keep COMH/L trace straight and on the same layer

图12-3. Daisy Chain Layout Consideration

12.2 Layout Example

This section presents the BQ79616-Q1 Evaluation Module (EVM) design as a layout example.

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Separating grounds to keep the noisy

ground apart from quiet ground

DVDD

AVSS

CVDD

COML/COMH traces

Avoid turns on the traces,

matching impedance, ground

(CVDD) shielding between traces

Daisy chain circuit components: Keep-out

area with no other traces or ground plans

图12-4. Top Signal Layer

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图12-5. Second Layer with Solid, Separate Ground Planes

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图12-6. ThIrd Layer with Single Ground Plane

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13 Device and Documentation Support

13.1 Device Support

13.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

13.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

13.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

PAP 64

10 x 10, 0.5 mm pitch

HTQFP - 1.2 mm max height

QUAD FLATPACK

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226442/A

www.ti.com

PACKAGE OUTLINE

TM

PAP0064F

PowerPAD TQFP - 1.2 mm max height

SCALE 1.300

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

16

33

17

32

A

0.27

64X

60X 0.5

0.17

0.08

C A B

4X 7.5

C

SEATING PLANE

1.2 MAX

(0.127)

TYP

SEE DETAIL A

17

32

0.25

GAGE PLANE

(1)

8X (R0.091)

NOTE 4

33

16

0.15

0.05

0.08 C

0 -7

0.75

0.45

6.5

5.3

DETAIL A

65

A

17

TYPICAL

20X (R0.137)

NOTE 4

1

48

49

64

4226412/A 11/2020

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs.

4. Strap features may not be present.

5. Reference JEDEC registration MS-026.

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EXAMPLE BOARD LAYOUT

TM

PAP0064F

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(8)

NOTE 8

(6.5)

SYMM

SOLDER MASK

49

64

DEFINED PAD

64X (1.5)

(R0.05)

TYP

1

48

64X (0.3)

65

(11.4)

SYMM

(1.1 TYP)

60X (0.5)

33

16

(

0.2) TYP

VIA

METAL COVERED

32

17

SEE DETAILS

BY SOLDER MASK

(1.1 TYP)

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4226412/A 11/2020

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,

plugged or tented.

10. Size of metal pad may vary due to creepage requirement.

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EXAMPLE STENCIL DESIGN

TM

PAP0064F

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(6.5)

BASED ON

0.125 THICK STENCIL

SYMM

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

64

49

64X (1.5)

1

48

64X (0.3)

(R0.05) TYP

SYMM

65

(11.4)

60X (0.5)

33

16

METAL COVERED

BY SOLDER MASK

17

32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

7.27 X 7.27

6.5 X 6.5 (SHOWN)

5.93 X 5.93

0.125

0.15

0.175

5.49 X 5.49

4226412/A 11/2020

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

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型号：	BQ79612-Q1
厂家：	TEXAS INSTRUMENTS
描述：	符合 ASIL-D 标准的汽车类 12 节串联精密电池监控器、平衡器和集成保护器电池监控
文件：	总222页 (文件大小：6388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ79612-Q1 [TI]

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