BUF12800AIPWPR [TI]

12 通道伽马电压发生器 | PWP | 24 | -40 to 85;


型号：	BUF12800AIPWPR
厂家：	TEXAS INSTRUMENTS
描述：	12 通道伽马电压发生器 \| PWP \| 24 \| -40 to 85 光电二极管电压发生器
文件：	总27页 (文件大小：1194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BUF12800

SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

REFERENCE VOLTAGE GENERATOR

for LCD GAMMA CORRECTION

F_DEATURES

A_DPPLICATIONS

12-CHANNEL GAMMA CORRECTION

10-BIT RESOLUTION

TFT-LCD REFERENCE DRIVERS

REFERENCE VOLTAGE GENERATORS

INDUSTRIAL PROCESS CONTROL

DOUBLE-BUFFERED DAC REGISTERS

INTEGRATED REFERENCE BUFFERS

RAIL-TO-RAIL OUTPUT

DESCRIPTION

LOW SUPPLY CURRENT: 900µA/ch

SUPPLY VOLTAGE: 7V to 18V

DIGITAL SUPPLY: 2.3V to 5.5V

The BUF12800 is a programmable voltage reference

generator designed for dynamic gamma correction in

TFT-LCD panels. It provides 12 programmable outputs,

each with 10-bit resolution.

INDUSTRY-STANDARD TWO-WIRE INTERFACE

− High-Speed Mode: 3.4MHz

TI’s new, small geometry, state-of-the-art, analog CMOS

process allows the use of one digital-to-analog converter

(DAC) per channel while still maintaining a very small chip

size. This topology has the advantage of significantly

increased programming speed over existing program-

mable buffers.

HIGH ESD RATING:

− 4kV HBM, 1kV CDM, 200V MM

DEMO BOARD AND SOFTWARE AVAILABLE

REFH

1, 2

Programming of each output occurs through an industry-

standard, two-wire serial interface. Unlike existing

programmable buffers, the BUF12800 offers a high-

speed, two-wire interface mode that allows clock speeds

up to 3.4MHz. The BUF12800 features a double-buffered

DAC register structure that significantly simplifies imple-

mentation of dynamic gamma control. This further reduces

programming time, especially when many channels have

to be updated simultaneously.

BUF12800

Out A

Out B

Out C

Out D

Out E

Out F

Out G

Out H

Out I

Reference pins set the high and low voltages of the output

range. They are internally buffered, which simplifies

design. They may be connected to external resistors to

divide the output range for finer resolution of outputs.

The BUF12800 is available in a TSSOP-24 PowerPAD

package. It is specified from −40°C to +85°C.

BUF12800 RELATED PRODUCTS

Out J

Out K

Out L

FEATURES

PRODUCT

11-ChannelGamma Correction Buffer, Int V

BUF11702

BUF07703

BUF06703

BUF05703

BUFxx704

BUF20800

COM

6-Channel Gamma Correction Buffer, Int V

6-Channel Gamma Correction Buffer

4-Channel Gamma Correction Buffer, Int V

High-Supply Voltage Gamma Buffers

COM

SDA

SCL

Control IF

20-Channel Programmable Buffer, 10-Bit, V

COM

REFL

11, 12

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.

ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ

ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ

ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

(1)

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V

handledwith appropriate precautions. Failure to observe

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V

proper handling and installation procedures can cause damage.

Signal Input Terminals, SCL, SDA, AO, LD:

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to +6V

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

(2)

Output Short-Circuit

. . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . −40°C to +95°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

ESD Rating:

Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 4000V

Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . 1000V

Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

(1)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

(2)

Short-circuit to ground, one amplifier per package.

(1)

ORDERING INFORMATION

PRODUCT

PACKAGE-LEAD

PACKAGE DESIGNATOR

PACKAGE MARKING

BUF12800

TSSOP-24

PWP

BUF12800

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

PIN CONFIGURATION

Top View

TSSOP

V_S

24 Out L

Out K

Out J

Out I

REFH⁽²⁾

V_SD

SCL

SDA

20 Out H

19 Out G

PowerPAD

Lead−Frame

Die Pad

Exposed on

Underside

Out F

Out E

Out D

(1)

GND_D

REFL⁽²⁾10

15 Out C

(1)

GND_A

Out B

Out A

(1)

(2)

GND and GND are internally connected and must be at the same voltage potential.

Connecting a capacitor to this node is not recommended.

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, T = −40°C to +85°C.

At T = +25°C, V = 18V, V = 5V, V

= 17V, V

= 1V, R = 1.5kΩ connected to ground, and C = 200pF, unless otherwise noted.

REFH

REFL

BUF12800

MIN

TYP

MAX

PARAMETER

CONDITIONS

UNIT

ANALOG

Buffer Output Swing—High

Buffers A-F, Code = 1023, Sourcing 10mA, V

Buffers G-L, Code = 1023, Sourcing 10mA, V

= 17.8

17.7

16.3

17.8

16.98

1.0

REFH

Buffer Output Swing—Low

Buffers A-F, Code = 0, Sinking 10mA, V

Buffers G-L, Code = 0, Sinking 10mA, V

= 0.2

1.1

0.3

REFL

= 0.2

0.2

REFL

Buffer Output Reset and Power-Up Value

Buffer A

Buffer B

Buffer C

Buffer D

Buffer E

Buffer F

Code 3E0h (11 1110 0000)

Code 360h (11 0110 0000)

Code 320h (11 0010 0000)

Code 300h (11 0000 0000)

Code 2C0h (10 1100 0000)

Code 240h (10 0100 0000)

16.452

14.450

13.450

12.952

11.952

9.950

16.502

14.500

13.500

13.002

12.002

10.000

16.552

14.550

13.550

13.052

12.052

10.050

Buffer G

Buffer H

Buffer I

Buffer J

Buffer K

Buffer L

Code 1C0h (01 1100 0000)

Code 140h (01 0100 0000)

Code 100h (01 0000 0000)

Code 0E0h (00 1110 0000)

Code 0A0h (00 1010 0000)

Code 020h (00 0010 0000)

7.955

5.958

4.957

4.459

3.457

1.457

8.005

6.008

5.007

4.509

3.507

1.507

8.055

6.058

5.057

4.559

3.557

1.557

REFH Input Range

REFL Input Range

Integral Nonlinearity

Differential Nonlinearity

Gain Error

− 0.2

0.2

V − 4

INL

0.3

0.12

Bits

DNL

Bits

Program to Out Delay

Output Accuracy

vs Temperature

µs

and V

Held Constant

µV/°C

MΩ

mV/mA

REFH

REFL

Input Resistance at V

and V

INH

100

0.5

REFH

REFL

Load Regulation, 10mA, All Buffers

50mA, Buffers A-F

REG

= V /2, I = +5mA to −5mA Step

OUT

1.5

OUT

= V /2, I

= 50mA, I

= 50mA

mV/mA

OUT

SINKING

SOURCING

ANALOG POWER SUPPLY

Operating Voltage Range

Total Analog Supply Current

over Temperature

Outputs at Reset Values, No Load

DIGITAL

Logic 1 Input Voltage

Logic 0 Input Voltage

Logic 0 Output Voltage

Input Leakage

0.7(V )

0.3(V

)

= 3mA

0.15

0.01

0.4

SINK

µA

kHz

MHz

Clock Frequency

Standard/Fast Mode

High-Speed Mode

400

3.4

CLK

DIGITAL POWER SUPPLY

Operating Voltage Range

2.3

5.5

(1)

Digital Supply Current

Outputs at Reset Values, No-Load, Two-Wire Bus Inactive

µA

over Temperature

100

TEMPERATURE RANGE

Specified Range

−40

−65

+85

+95

°C

Operating Range

Storage Range

Junction Temperature < +125°C

+150

(2)

Thermal Resistance, TSSOP-24

Junction-to-Ambient

Junction-to-Case

30.13

0.92

°C/W

(1)

(2)

See the typical characteristic Digital Supply Current vs Two-Wire Bus Activity.

PowerPAD attached to PCB, 0lfm airflow, and 76mm x 76mm copper area.

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS

At T = +25°C, V = 18V, V = 5V, V

= 17V, V

= 1V, R = 1.5kΩ connected to ground, and C = 200pF, unless otherwise noted.

REFH

REFL

ANALOG SUPPLY CURRENT vs TEMPERATURE

V_S= 18V

DIGITAL SUPPLY CURRENT vs TEMPERATURE

V_S= 10V

V_SD= 5V

V_S= 10V

V_SD= 3.3V

−

100

Tem pe r at ur e ( C)

Temperature ( C)

Figure 1

Figure 2

FULL−SCALE OUTPUT SWING

OUTPUT VOLTAGE vs OUTPUT CURRENT

Channels A−F (sourcing), Code = 3FFh

V_REFL= 1V, V_REFH= 17.8V

REFH = 17V

REFL = 1V

R_LOADConnected to GND

→

Code 3FF 000

Channels G−L (sourcing),

Code = 3FFh, V_REFL= 0.2V,

V_REFH= 17V, R_LOADConnected to GND

Channels A−F (sinking), Code = 000h,

V_REFL= 1V, V_REFH= 17.8V,

Channels G−L (sinking),

Code = 000h, V_REFL= 0.2V,

→

Code 000 3FF

R_LOADConnected to 18V

V_REFH= 17V, R_LOADConnected to 18V

Time (1 s/div)

100

Output Current (mA)

Figure 3

Figure 4

DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE

INTEGRAL NONLINEARITY ERROR vs INPUT CODE

0.6

0.4

0.2

0.6

0.4

0.2

−

0.2

0.4

0.6

−

0.2

0.4

0.6

200

400

600

800

1000

200

400

600

800

1000

Input Code

Figure 5

Figure 6

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

Each buffer is capable of full-scale change in output

voltage in less than 4µs; see Figure 4, typical

characteristic Full-Scale Output Swing.

APPLICATIONS INFORMATION

The BUF12800 programmable voltage reference allows fast

and easy adjustment of 12 programmable reference outputs,

The BUF12800 uses an analog supply of 7V to 18V and a

digital supply of 2.3V to 5.5V. The digital supply must be

applied prior to or simultaneously with the analog supply

to avoid excessive current and power consumption;

damage to the device may occur if it is left connected only

to the analog supply for an extended time.

each with 10-bit resolution.

It allows very simple,

time-efficient adjustment of the gamma reference voltages.

The BUF12800 is programmed through a high-speed

standard two-wire interface. The BUF12800 features a

double-register structure for each DAC channel to simplify

the implementation of dynamic gamma control (see the

Dynamic Control section). This allows pre-loading of register

data and rapid updating of all channels simultaneously.

Figure 7 shows the BUF12800 in a typical configuration.

In this configuration, the BUF12800 device address is 74h.

The output of each DAC is immediately updated as soon

as data are received in the corresponding register (LD = 0).

For maximum dynamic range, set V_REFH= V_S− 0.2V and

Buffers A−F are able to swing to within 300mV of the

positive supply rail, and to within 1.1V of the negative

supply rail. Buffers G−L are able to swing to within 1.7V

of the positive supply rail, and to within 300mV of the

negative supply rail. (See the Electrical Characteristics

table for further information).

_REFL= V_S+ 0.2V.

BUF12800

(1)

V_S

Out L 24

Source

Driver

V_S

(1)

V_S

Out K 23

10µF

1µF

100nF

(1)

REFH

V_DS

Out J

3.3V

Out I 21

SCL

SDA

Out H

Timing

Controller

Out G 19

Out F 18

(1)

Out E

Out D

(2)

GND_D

REFL

V_S

Out C 15

(2)

GND_A

Out B

Out A

GND_A

(1)

(2)

RC combination optional.

GND and GND are internally connected and must be at the same voltage potential.

Figure 7. Typical Application Configuration

ꢠꢄ ꢡ ꢢ ꢣꢤ ꢥ ꢥ

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

acknowledge this byte; the communication protocol prohibits

acknowledgment of the Hs master code. On receiving a

master code, the BUF12800 will switch on its Hs mode filters,

and communicate at up to 3.4MHz. Additional high-speed

transfers may be initiated without resending the Hs mode

byte by generating a repeat START without a STOP. The

BUF12800 will switch out of Hs mode at the first occurrence

of a STOP condition.

TWO-WIRE BUS OVERVIEW

The BUF12800 communicates through an industry-stan-

dard, two-wire interface to receive data in slave mode. This

standard uses a two-wire, open-drain interface that supports

multiple devices on a single bus. Bus lines are driven to a

logic low level only. The device that initiates the

communication is called a master, and the devices controlled

by the master are slaves. The master generates the serial

clock on the clock signal line (SCL), controls the bus access,

and generates the START and STOP conditions.

GENERAL CALL RESET AND POWER-UP

The BUF12800 responds to a General Call Reset, which is

an address byte of 00h (0000 0000) followed by a data byte

of 06h (0000 0110). The BUF12800 acknowledges both

bytes. Upon receiving a General Call Reset, the BUF12800

performs a full internal reset, as though it had been powered

off and then on. It always acknowledges the General Call

address byte of 00h (0000 0000), but does not acknowledge

any General Call data bytes other than 06h (0000 0110).

To address a specific device, the master initiates a START

condition by pulling the data signal line (SDA) from a HIGH

to LOW logic level while SCL is HIGH. All slaves on the bus

shift in the slave address byte, with the last bit indicating

whether a read or write operation is intended. During the

ninth clock pulse, the slave being addressed responds to

the master by generating an Acknowledge and pulling

SDA LOW.

When the BUF12800 powers up, it automatically performs

a reset. As part of the reset, the BUF12800 is configured

based on the codes shown in Table 1.

Data transfer is then initiated and 8 bits of data are sent

followed by an Acknowledge Bit. During data transfer,

SDA must remain stable while SCL is HIGH. Any change

in SDA while SCL is HIGH will be interpreted as a START

or STOP condition.

Table 1. BUF12800 Reset Codes

RESET CODES

Once all data has been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH while SCL is HIGH.

BUFFER

(Hex)

(Decimal)

(Binary)

BUFFER A

BUFFER B

BUFFER C

BUFFER D

BUFFER E

BUFFER F

BUFFER G

BUFFER H

BUFFER I

BUFFER J

BUFFER K

BUFFER L

Code 3E0

Code 360

Code 320

Code 300

Code 2C0

Code 240

Code 1C0

Code 140

Code 100

Code 0E0

Code 0A0

Code 020

992

864

800

768

704

576

448

320

256

224

160

11 1110 0000

11 0110 0000

11 0010 0000

11 0000 0000

10 1100 0000

10 0100 0000

01 1100 0000

01 0100 0000

01 0000 0000

00 1110 0000

00 1010 0000

00 0010 0000

The BUF12800 can act only as a slave device; therefore,

it never drives SCL. SCL is an input only for the BUF12800.

ADDRESSING THE BUF12800

The address of the BUF12800 is 111010x, where x is the

state of the A0 pin. When the A0 pin is LOW, the device will

acknowledge on address 74h (1110100). If the A0 pin is

HIGH, the device will acknowledge on address 75h

(1110101).

Other valid addresses are possible through a simple mask

change. Contact your TI representative for information.

Buffer values are calculated using Equation 1:

DATA RATES

* V

REFL

1024

REFH

D^TheS^twta^on^-wda^irr^ed:^ba^ul^slo^ow^ps^era^ac^telo^scⁱkⁿf^oreⁿq^eu^oe^fn^tc^hy^reo^ef ^su^pp^et^eo^d1^m00^ok^dH^ez^s;^:

₊ƪ

_{decimal value of code}ƫ_) V

REFL

OUT

(1)

Fast: allows a clock frequency of up to 400kHz; and

High-speed mode (also called Hs mode): allows a

clock frequency of up to 3.4MHz.

Other reset values are available as

custom

modification—contact your TI representative for details.

OUTPUT VOLTAGE

The BUF12800 is fully compatible with all three modes. No

special action is required to use the device in Standard or

Fast modes, but High-speed mode must be activated. To

activate High-speed mode, send a special address byte of

00001xxx, with SCL = 400kHz, following the START

condition; xxx are bits unique to the Hs-capable master,

which can be any value. The BUF12800 will respond to the

High-speed mode command regardless of the value of these

last three bits. This byte is called the Hs master code. (Note

that this is different from normal address bytes—the low bit

does not indicate read/write status.) The BUF12800 will not

Buffer output values are determined by the reference

voltages (V_REFHand V_REFL) and the decimal value of the

binary input code used to program that buffer. The value is

calculated using Equation 1; see the Reset and Power-Up

section. The valid voltage ranges for the reference

voltages are:

4V v V_REFHv V_S* 0.2V and 0.2V v V_REFLv V_S* 4V

The BUF12800 outputs are capable of a full-scale voltage

output change in less than 4µs—no intermediate steps are

required.

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

bytes are for DAC_L. The DAC register is updated

after receiving the 24th byte. For each DAC, begin by

sending the most significant byte (bits D15−D8, of

which only bits D9 and D8 have meaning), followed by

the least significant byte (bits D7−D0).

READ/WRITE OPERATIONS

The BUF12800 is able to read from a single DAC or

multiple DACs, or write to the register of a single DAC, or

multiple DACs in a single communication transaction.

DAC addresses begin with 0000, which corresponds to

DAC_A, through 1011, which corresponds to DAC_L.

Write commands are performed by setting the read/write

bit LOW. Setting the read/write bit HIGH will perform a read

transaction.

5. Send a STOP condition on the bus.

The BUF12800 will acknowledge each byte. To terminate

communication, send a STOP or START condition on the

bus. Only DACs that have received both bytes will be

updated.

Writing

To write to a single DAC register:

Reading

1. Send a START condition on the bus.

To read the register of one DAC:

2. Send the device address and read/write bit = LOW.

The BUF12800 will acknowledge this byte.

1. Send a START condition on the bus.

2. Send the device address and read/write bit = LOW.

The BUF12800 will acknowledge this byte.

3. Send a DAC address byte. Bits D7−D4 have no

meaning; Bits D3−D0 are the DAC address. Only DAC

addresses 0000 to 1011 are valid and will be

acknowledged.

4. Send a START or STOP/START condition on the bus.

5. Send correct device address and read/write

bit = HIGH. The BUF12800 will acknowledge this

byte.

3. Send a DAC address byte. Bits D7−D4 are unused

and should be set to 0. Bits D3−D0 are the DAC

address. Only DAC addresses 0000 to 1011 are valid

and will be acknowledged.

4. Send two bytes of data for the specified DAC. Begin

by sending the most significant byte first (bits D15−D8,

of which only bits D9 and D8 are used), followed by the

least significant byte (bits D7−D0). The DAC register

is updated after receiving the second byte.

6. Receive two bytes of data. They are for the specified

DAC. The first received byte is the most significant

byte (bits D15−D8, of which only bits D9 and D8 have

meaning); the next is the least significant byte (bits

D7−D0).

5. Send a STOP condition on the bus.

The BUF12800 will acknowledge each data byte. If the

master terminates communication early by sending a

STOP or START condition on the bus, the specified

not the same as updating the DAC output voltage. See the

Output Latch section.

7. Acknowledge after receiving each byte.

8. Send a STOP condition on the bus.

Communication may be terminated by sending a

premature STOP or START condition on the bus, or by not

sending the acknowledge.

The process of updating multiple registers begins the

same as when updating a single register. However,

instead of sending a STOP condition after writing the

addressed register, the master will continue to send data

for the next register. The BUF12800 will automatically and

sequentially step through subsequent registers as addi-

tional data is sent. The process will continue until all de-

sired registers have been updated or a STOP condition is

sent.

To read multiple DAC registers:

1. Send a START condition on the bus.

2. Send the device address and read/write bit = LOW.

The BUF12800 will acknowledge this byte.

3. Send either the DAC_A address byte to start at the

first DAC or send the address byte for whichever DAC

will be the first in the sequence of DACs to be read.

The BUF12800 will begin with this DAC and step

through subsequent DACs in sequential order.

4. Send the device address and read/write bit = HIGH.

5. Receive bytes of data. The first two bytes are for the

specified DAC. The first received byte is the most

significant byte (bits D15−D8, of which only bits D9

and D8 have meaning). The next byte is the least

significant byte (bits D7−D0).

To write to multiple registers:

1. Send a START condition on the bus.

2. Send the device address and read/write bit = LOW.

The BUF12800 will acknowledge this byte.

3. Send either the DAC_A address byte to start at the

first DAC or send the address of whichever DAC will

be the first to be updated. The BUF12800 will begin

with this DAC and step through subsequent DACs in

sequential order.

4. Send the bytes of data. The first two bytes are for the

DAC addressed in step 3. Its register is automatically

updated after receiving the second byte. The next two

bytes are for the following DAC. The DAC register is

updated after receiving the fourth byte. The last two

6. Acknowledge after receiving each byte.

7. When all desired DACs have been read, send a STOP

or START condition on the bus.

Communication may be terminated by sending a

premature STOP or START condition on the bus, or by not

sending the acknowledge.

ꢠꢄ ꢡ ꢢ ꢣꢤ ꢥ ꢥ

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

TIMING DIAGRAMS

Figure 8. Write Single DAC Register

Figure 9. Read Single DAC Register

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

Figure 10. Write Multiple DAC Registers

Figure 11. Read Multiple DAC Registers

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

Table 2. BUF12800 Bus Address Options

OUTPUT LATCH

Because the BUF12800 features a double-buffered

same as updating the DAC output voltage. There are three

methods for latching transferred data from the storage

registers into the DACs to update the DAC output voltage.

BUF12800 ADDRESS

ADDRESS

A0 Pin is LOW

(device will acknowledge on address 74h)

111 0100

A0 Pin is HIGH

(device will acknowledge on address 75h)

111 0101

Method 1 requires externally setting the latch pin low,

LD = LOW, which will update each DAC output voltage

whenever its corresponding register is updated.

Table 3. Quick-Reference Table of DAC

Addresses

Method 2 externally sets LD = HIGH to allow all DAC

output voltages to retain their values during data transfer

and until LD = LOW, which will simultaneously update the

output voltages of all 12 DACs to the new register values.

DAC

ADDRESS

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

0000 1000

0000 1001

0000 1010

0000 1011

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

DAC I

Method 3 uses software control. LD is maintained HIGH,

and all 12 DACs are updated when the master writes a ‘1’

in bit 15 of any DAC register. The update will occur after

receiving the 16-bit data for the currently-written register.

Use methods 2 and 3 to transfer a future data set into the

first bank of registers in advance to prepare for a very fast

update of DAC output voltages.

The General Call Reset and the power-up reset will update

the DACs regardless of the state of the latch pin.

DAC J

DAC K

DAC L

Table 4. Quick-Reference Table of Commands

COMMAND

CODE

General Call Reset

Address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110).

00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master.

High-Speed Mode

This byte is called the Hs master code.

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

a picture is still being displayed. Because the data is only

stored into the first register bank, the DAC output values

remain unchanged—the display is unaffected. During the

vertical sync period, the DAC outputs (and therefore, the

gamma voltages) can be quickly updated either by using

an additional control line connected to the LD pin, or

through software—writing a ‘1’ in bit 15 of any DAC

input structure, see the Output Latch section.

DYNAMIC GAMMA CONTROL

Dynamic gamma control is a technique used to improve

the picture quality in LCD TV applications. The brightness

in each picture frame is analyzed and the gamma curves

are adjusted on a frame-by-frame basis. The gamma

curves are typically updated during the short vertical

blanking period in the video signal. Figure 12 shows a

block diagram using the BUF12800 for dynamic gamma

control.

Example: Update all 12 registers simultaneously via

software.

The BUF12800 is ideally suited for rapidly changing the

gamma curves due to its unique topology:

Step 1: Check if LD pin is placed in HIGH state.

•

double register input structure to the DAC

fast serial interface

Step 2: Write DAC Registers 1−12 with bit 15 always 0.

Step 3: Write any DAC register a second time with

identical data. Make sure that bit 15 is ‘1’. All DAC

channels will be updated simultaneously after receiving

the last bit of data.

simultaneous updating of all DACs by software.

See the Read/Write Operations to write to all

registers and Output Latch sections.

The double register input structure saves programming

time by allowing updated DAC values to be pre-stored into

the first register bank. Storage of this data can occur while

Histogram

SDA

Gamma

Adjustment

Algorithm

Digital

Picture

Data

BUF12800

Gamma References

SCL

Black

White

A through L

Timing Controller/ Controller

Source Driver

Figure 12. Dynamic Gamma Control

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

BUF12800 uses the most advanced high-voltage CMOS

process available today, which allows it to be competitive

with traditional gamma buffers.

REPLACEMENT OF TRADITIONAL GAMMA

BUFFER

Traditional gamma buffers rely on a resistor string (often

using expensive 0.1% resistors) to set the gamma

voltages. During development, the optimization of these

gamma voltages can be time consuming. Programming

these gamma voltages with the BUF12800 can

significantly reduce the time required for gamma voltage

optimization. The final gamma values can be written into

an external EEPROM to replace a traditional gamma

buffer solution. During power-up of the LCD panel, the

timing controller can read the EEPROM and load the

values into the BUF12800 to generate the desired gamma

voltages. Figure 13a shows the traditional resistor string;

Figure 13b shows the more efficient alternative method

using the BUF12800.

This technique offers significant advantages:

•

It shortens development time significantly.

It allows demonstration of various gamma curves

to LCD monitor makers by simply uploading a

different set of gamma values.

•

It allows simple adjustment of gamma curves

during production to accommodate changes in

the panel manufacturing process.

It decreases cost and space.

a) Traditional

b) BUF12800 Solution

BUFxx704

BUF12800

Timing

Controller

Out A

SDA

Out B

SCL

EEPROM

Out K

Out L

SDA

Control Interface

SCL

LCD Panel Electronics

Figure 13. Replacement of Traditional Gamma Buffer

ꢠ

ꢄ

ꢡ

ꢢ

ꢣ

ꢤ

ꢥ

www.ti.com

SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

PROGRAMMABLE V

REFH AND REFL INPUT RANGE

COM

Channels A−F of the BUF12800 can drive more than

100mA up to 2V to the supply rails (see Figure 4, typical

characteristic Output Voltage vs Output Current).

Therefore, any of these channels can be used to drive the

Best performance and output swing range of the

BUF12800 are achieved by applying REFH and REFL

voltages that are slightly below the power-supply

voltages. Most specifications have been tested at

REFH = V_S− 200mV and REFL = GND + 200mV. The

REFH internal buffer is designed to swing very closely to

V_Sand the REFL internal buffer to GND. However, there

is a finite limit on how close they can swing before

saturating. To avoid saturation of the internal REFH and

REFL buffers, the REFH voltage should not be greater

than V_S− 100mV and REFL voltage should not be lower

than GND + 100mV. The other consideration when trying

to maximize the output swing capability of the gamma

buffers is the limitation in the swing range of output buffers

(OUT A−L), which depends on the load current. A typical

load in the LCD application is 5−10mA. For example, if

OUT A is sourcing 10mA, the swing is typically limited to

about V_S− 200mV. The same applies to OUT L, which

typically limits at GND + 200mV when sinking 10mA. An

increase in output swing can only be achieved for much

lighter loads. For example, a 3mA load typically allows the

swing to be increased to approximately V_S− 100mV and

GND + 100mV.

_COMnode on the LCD panel. To store the gamma and the

V_COMvalues, an external EEPROM is required. During

power-up of the LCD panel, the timing controller can then

read the EEPROM and load the values into the BUF12800

to generate the desired gamma voltages as well as V_COM

voltages. Figure 14 shows channels A and B of the

BUF12800 being used for V_COMvoltages.

BUF12800

Out A

V_COM

Out B

Out C

Out D

Connecting REFH directly to V_Sand REFL directly to GND

does not damage the BUF12800. However, as discussed

above, the output stages of the REFH and REFL buffers

will saturate. This condition is not desirable and can result

in a small error in the measured output voltages of OUT

A−L. As described above, this method of connecting

REFH and REFL does not help to maximize the output

swing capability.

Gamma

References

Out K

Out L

SDA

Control Interface

SCL

Figure 14. BUF12800 Used for Programmable

COM

ꢠꢄ ꢡ ꢢ ꢣꢤ ꢥ ꢥ

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

INDEPENDENTLY PROGRAMMABLE RGB

GAMMA: BUF20800

TOTAL TI PANEL SOLUTION

In addition to the BUF12800 programmable voltage

reference, TI offers a complete set of ICs for the LCD

panel market, including gamma correction buffers,

source and gate drivers, timing controllers, various

power-supply solutions, and audio power solutions.

Figure 15 shows the total IC solution from TI.

Some very high resolution LCD screens require the

adjustment of the gamma voltages for each color

(Red—R, Green—G, Blue—B). The BUF20800 offers 20

programmable gamma channels. By using 6 channels for

each color, 18 channels would be used in total for adjusting

the gamma. In addition to those, 1 or 2 channels could be

used to program V_COM

Reference

V_COM

Gamma Correction

BUF12800

15 V

26 V

TPS65140

TPS65100

LCD

2.7 V−5 V

−

14 V

Supply

3.3 V

TPA3005D2

TPA3008D2

Audio

Speaker

Driver

Source Driver

Logic and

Timing

Controller

High−Resolution

TFT−LCS Panel

Figure 15. TI LCD Solution

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www.ti.com

SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

Figure 16 provides ideas on how the BUF12800 can be

used in an application. A microcontroller with a two-wire

serial interface controls the various DACs of the

BUF12800. The BUF12800 can be used for:

BUF12800 IN INDUSTRIAL APPLICATIONS

The wide supply range, high output current and very low

cost make the BUF12800 attractive for a range of medium

accuracy industrial applications such as programmable

power supplies, multi-channel data-acquisition systems,

data loggers, sensor excitation and linearization,

power-supply generation, and others. Each DAC channel

features 1LSB DNL and INL.

sensor excitation

programmable bias/reference voltages

variable power-supplies

high-current voltage output

4-20mA output

set-point generators for control loops.

Many systems require different levels of biasing and power

supply for various components as well as sensor

excitation, control-loop set-points, voltage outputs, current

outputs, and other functions. The BUF12800, with its 12

programmable DAC channels, provides great flexibility to

the whole system by allowing the designer to change all

these parameters via software.

NOTE: At power-up the output voltages of the BUF12800

DACs are pre-defined by the codes in Table 1. Therefore,

each DAC voltage will be set to a different level at

power-up or reset.

+18V

+5V

BUF12800

0.3V to 17V

Voltage

Output

+5V

High Current

Voltage Output

2V to 16V, 100mA

Sensor Excitation/Linearization

Control Loop

Set Point

4−20mA

+5V

Bias Voltage

Generator

4−20mA

Generator

+2.5V Bias

LED Driver

Offset

INA

Adjustment

Ref

+4V

+4.3V

Comparator

Threshold

Supply Voltage

Generator

Ref

+7.5V

Reference

for MDAC

SOA

SCL

MDAC

Figure 16. Industrial Application Ideas

ꢠꢄ ꢡ ꢢ ꢣꢤ ꢥ ꢥ

www.ti.com

SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

3. Additional vias may be placed anywhere along the

thermal plane outside of the thermal pad area. This

helps dissipate the heat generated by the

BUF12800 IC. These additional vias may be larger

than the 13-mil diameter vias directly under the

thermal pad. They can be larger because they are

not in the thermal pad area to be soldered; thus,

wicking is not a problem.

GENERAL PowerPAD DESIGN

CONSIDERATIONS

The BUF12800 is available in the thermally-enhanced

PowerPAD package. This package is constructed using

a downset leadframe upon which the die is mounted, as

shown in Figure 17(a) and (b). This arrangement

results in the lead frame being exposed as a thermal

pad on the underside of the package; see Figure 17(c).

Due to this thermal pad having direct thermal contact

with the die, excellent thermal performance is achieved

by providing a good thermal path away from the thermal

pad.

4. Connect all holes to the internal plane that is at the

same voltage potential as the GND pins.

5. When connecting these holes to the internal plane,

do not use the typical web or spoke via connection

methodology. Web connections have a high thermal

resistance connection that is useful for slowing the

heat transfer during soldering operations. This

makes the soldering of vias that have plane

connections easier. In this application, however, low

thermal resistance is desired for the most efficient

heat transfer. Therefore, the holes under the

BUF12800 PowerPAD package should make their

connection to the internal plane with a complete

connection around the entire circumference of the

plated-through hole.

The PowerPAD package allows for both assembly and

thermal management in one manufacturing operation.

During the surface-mount solder operation (when the

leads are being soldered), the thermal pad must be

soldered to a copper area underneath the package.

Through the use of thermal paths within this copper

area, heat can be conducted away from the package

into either a ground plane or other heat-dissipating

device. Soldering the PowerPAD to the PCB is

always required, even with applications that have

low power dissipation. This provides the necessary

thermal and mechanical connection between the lead

frame die pad and the PCB.

6. The top-side solder mask should leave the terminals

of the package and the thermal pad area with its

eight holes exposed. The bottom-side solder mask

should cover the holes of the thermal pad area. This

prevents solder from being pulled away from the

thermal pad area during the reflow process.

The PowerPAD must be connected to the device’s most

negative supply voltage, GND and GND .

1. Prepare the PCB with a top-side etch pattern. There

should be etching for the leads as well as etch for the

thermal pad.

7. Apply solder paste to the exposed thermal pad area

and all of the IC terminals.

2. Place recommended holes in the area of the thermal

pad. Ideal thermal land size and thermal via patterns

(2x4) can be seen in the technical brief, PowerPAD

Thermally-Enhanced Package (SLMA002), avail-

able for download at www.ti.com. These holes

should be 13 mils (0.330mm) in diameter. Keep

them small, so that solder wicking through the holes

is not a problem during reflow.

8. With these preparatory steps in place, the

BUF12800 IC is simply placed in position and run

through the solder reflow operation as any standard

surface-mount component. This preparation results

in a properly installed part.

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SBOS315D − DECEMBER 2004 − REVISED DECEMBER 2007

Exposed Thermal Pad

DIE

Side View (a)

DIE

End View (b)

Bottom View (c)

NOTE: The thermal pad is electrically isolated from all terminals in the package.

Figure 17. Views of Thermally-Enhanced DGN Package

For a given q , the maximum power dissipation is

shown in Figure 18, and is calculated by the following

formula:

T_MAX* T_A

q_JA

_{P +}ǒ Ǔ

Where:

P_D= maximum power dissipation (W)

T_MAX= absolute maximum junction temperature (125°C)

T_A= free-ambient air temperature (°C)

q_JA= q_JC+ q_CA

−

100

T_A, Free−Air Temperature ( C)

q_JC= thermal coefficient from junction to case (°C/W)

q_CA= thermal coefficient from case-to-ambient air (°C/W)

Figure 18. Maximum Power Dissipation vs Free-

Air Temperature (with PowerPAD soldered down)

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

BUF12800AIPWP

BUF12800AIPWPR

ACTIVE

HTSSOP

PWP

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

BUF12800

2000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BUF12800AIPWPR

HTSSOP PWP

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 24

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

BUF12800AIPWPR

2000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

BUF12800AIPWP

PWP

HTSSOP

530

10.2

3600

3.5

Pack Materials-Page 3

GENERIC PACKAGE VIEW

PWP 24

4.4 x 7.6, 0.65 mm pitch

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224742/B

www.ti.com

PACKAGE OUTLINE

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

0.1 C

AREA

22X 0.65

7.9

7.7

NOTE 3

7.15

0.30

24X

4.5

4.3

0.19

0.1

C A

(0.15) TYP

SEE DETAIL A

4X (0.2) MAX

NOTE 5

2X (0.95) MAX

NOTE 5

EXPOSED

THERMAL PAD

0.25

GAGE PLANE

5.16

4.12

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

2.40

1.65

4222709/A 02/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present and may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(2.4)

24X (1.5)

SYMM

SEE DETAILS

24X (0.45)

(R0.05)

TYP

(7.8)

NOTE 9

(1.1)

TYP

SYMM

(5.16)

22X (0.65)

(

0.2) TYP

VIA

(1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-24

4222709/A 02/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0024B

PowerPAD^TMTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(2.4)

BASED ON

0.125 THICK

STENCIL

24X (1.5)

(R0.05) TYP

24X (0.45)

(5.16)

SYMM

BASED ON

0.125 THICK

STENCIL

22X (0.65)

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.68 X 5.77

2.4 X 5.16 (SHOWN)

2.19 X 4.71

0.125

0.15

0.175

2.03 X 4.36

4222709/A 02/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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BUF12800AIPWPR [TI]

相关型号：

BUF12840

BUF12840AIRGER

BUF12840AIRGET

BUF12840_12

BUF12840_14

BUF16820

BUF16820AIDAPR

BUF16820AIDAPRG4

BUF16820AIDAPRG4

BUF16821

BUF16821

BUF16821-Q1