BUF802IRGTR [TI]
宽带宽、2.3nV/√Hz、高输入阻抗 JFET 缓冲器 | RGT | 16 | -40 to 85;
| 型号： | BUF802IRGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 宽带宽、2.3nV/√Hz、高输入阻抗 JFET 缓冲器 | RGT | 16 | -40 to 85 |
| 文件： | 总39页 (文件大小：2305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BUF802
ZHCSOA7C –JUNE 2021 –REVISED MARCH 2022
BUF802 宽带宽、2.3 nV/√Hz、高输入阻抗缓冲器
1 特性
3 说明
• 大信号带宽(1VPP)：3.1 GHz
• 压摆率：7000 V/μs
• 输入电压噪声：2.3nV/√Hz
• 1% 稳定时间：0.7ns
• 输入阻抗：50GΩ|| 2.4pF
• 能够驱动50Ω负载
• 可调静态电流，用于功率和性能权衡
• 具有快速过驱恢复功能的集成输入和输出钳位
• 电压电源：±4.5V 至±6.5V
BUF802 器件是一款具有 JFET 输入级的开环、单位增
益缓冲器，能够为数据采集系统 (DAQ) 前端提供低噪
声、高阻抗缓冲。BUF802 支持直流至 3.1 GHz 的带
宽，同时在整个频率范围内提供出色的失真和噪声性
能。
BUF802 可在需要更高精度性能的应用中与精密放大器
一同用于复合环路。BUF802 采用创新架构来简化高精
度、宽带宽复合环路的设计。
BUF802 具有可调静态电流引脚，让设计人员能够以带
宽和失真来换取较低的静态电流，因此适用于宽频率范
围。BUF802 具有集成的输入和输出钳位，能够保护器
件及其后续信号链免受过驱电压的影响。
2 应用
• 示波器前端
• 高频数据采集
• 高输入阻抗和高压摆率T&M 系统
• 示波器编码器和前端附加卡
• 有源探头
器件信息(1)
封装尺寸（标称值）
器件型号
BUF802
封装
VQFN (16)
3.00mm × 3.00mm
• 无损检验(NDT)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
.
.
.
.
0.8
Input
Output
.
0.6
0.4
0.2
0
.
.
.
-0.2
-0.4
-0.6
-0.8
+ 6V
IN
50 Ω
OUT
50 Ω
BUF802
- 6V
>1 G Impedance
Time (500 ps/div)
瞬态响应
阻抗变换电路：使用BUF802
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS998
BUF802
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ZHCSOA7C –JUNE 2021 –REVISED MARCH 2022
Table of Contents
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................28
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................31
12.1 Documentation Support.......................................... 31
12.2 接收文档更新通知................................................... 31
12.3 支持资源..................................................................31
12.4 Trademarks.............................................................31
12.5 Electrostatic Discharge Caution..............................31
12.6 术语表..................................................................... 31
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: Wide Bandwidth Mode.......6
6.6 Electrical Characteristics: Low Quiescent
Current Mode................................................................ 8
6.7 Typical Characteristics................................................9
7 Parameter Measurement Information .........................15
8 Detailed Description......................................................16
8.1 Overview...................................................................16
8.2 Functional Block Diagram.........................................16
Information.................................................................... 31
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (February 2022) to Revision C (March 2022)
Page
• Relaxed DC Gain specifications......................................................................................................................... 6
• Relaxed DC Gain specifications......................................................................................................................... 8
Changes from Revision A (December 2021) to Revision B (February 2022)
Page
• Updated the Application and Implementation section.......................................................................................25
Changes from Revision * (June 2021) to Revision A (December 2021)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
CLH
NC
CLL
NC
13
16
15
14
13
14
15
16
VS+
IN
1
2
3
12
11
10
VSO+
OUT
12
11
10
1
2
3
Clamp
Diode
Output
Stage
JFET
THERMAL PAD
VSO-
IN_Bias
I2
I1
4
9
9
4
IN_Aux
NC
6
7
8
5
5
8
7
6
8
VS-
VS-
Aux_Bias R_Bias
*Pin 5 and Pin 8 Internally Shorted
图5-1. RGT Package, 16-Pin VQFN
(Top View and Bottom View)
表5-1. Pin Functions
PIN
Operating
Mode(1) (2)
TYPE(4)
DESCRIPTION
NAME
Aux_Bias
CLH
NO.
6
P
I
CL
BF, CL
BF, CL
BF, CL
CL
Connect to VS- to enable control of OUT through the In_Aux.
Input pin for setting positive clamp voltage
Input pin for setting negative clamp voltage
Signal input
15
CLL
14
I
IN
2
I
In_Aux
In_Bias
NC
4
I
Auxiliary input for controlling OUT through an external amplifier.
JFET biasing pin
3
I
CL
16, 13, 9
Do not connect.
—
O
I
—
OUT
11
7
BF, CL
BF, CL
BF, CL
Signal output
R_Bias
VS+
Output stage bias current setting pin
Positive power supply connection for Input Stage.
1
P
Negative power supply connection for Input Stage. Pin 5 and Pin 8 are
internally shorted.
VS-
5, 8
P
BF, CL
(3)
VSO+
12
10
P
P
BF, CL
BF, CL
Positive power supply connection for Output Stage.
Negative power supply connection for Output Stage.
(3)
VSO-
The thermal pad is electrically isolated from the die and pins. Connect the
thermal pad to any potential.
Thermal Pad
—
—
(1) See 节8.4 for more information on Buffer Mode (BF) and Composite Loop Mode (CL) functional modes.
(2) Pins specified as CL should only be used when operating in Composite Loop Mode and left floating when operating in Buffer Mode.
(3) VSO and VS should be tied to the same potential since they are internally connected to each other through back-to-back diodes.
(4) I = input, O= output, P= power, NC = no connect.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
14
UNIT
VS = (VS+) –(VS–
)
Supply voltage(2)
V
VSO = (VSO+) –(VSO–
)
Maximum dVS/dT for supply turn-on and turn-off
Input
0.1
V/µs
V
IN
(VS+) to (VS–) –0.5
CLH
CLL
Positive Clamp
Mid-supply
VS+
Negative Clamp
VS–
Mid-supply
100
V
Input Clamp Diode
mA
°C
°C
TJ
Junction temperature
Storage temperature
150
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) VSO and VS should be tied to the same potential. VSO and VS are internally connected to each other through back to back diodes.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±4.5
9
NOM
±5
MAX
±6.5
13
UNIT
V
Dual Supply voltage
Single Supply voltage
Ambient temperature
(1)
VS = (VS+) –(VS–
)
10
V
TA
25
85
°C
–40
(1) BUF802 can be used with any possible combination of VS+ and VS– , provided the recommended operating condition is not exceeded
6.4 Thermal Information
BUF802
THERMAL METRIC(1)
RGT (VQFN)
UNIT
16 PINS
53
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
61
27
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.7
27
ΨJB
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BUF802
THERMAL METRIC(1)
RGT (VQFN)
16 PINS
13
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: Wide Bandwidth Mode
at TA = 25°C, VS = ±6V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0V (mid-supply), CLH and CLL tied to VS+ and VS–
respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ)
PARAMETER
Test Condition
MIN
TYP
MAX UNIT
AC PERFORMANCE
SSBW
LSBW
Small-Signal Bandwidth
Large-Signal Bandwidth
VOUT = 100 mVPP
VOUT = 1 VPP
3.1
3.1
VOUT = 2 VPP
1.6
GHz
Bandwidth for 0.1 dB flatness
Bandwidth for -1 dB flatness
Bandwidth for -2 dB flatness
Slew rate
0.6
1.8
VOUT = 1 VPP
2.4
RL = 50 Ω
SR
VOUT = 1.2-V step, VIN-SR = 13000 V/µs
VOUT = 1.2-V step (10% to 90%)
VOUT = 0.25-V step (10% to 90%)
7000
0.16
0.15
1.3
V/µs
ns
Rise and fall time
Settling time to 0.1%
Settling time to 1%
VOUT = 1.2-V step, VIN-SR = 13000 V/µs
ns
0.7
1/f corner
18
kHz
en
in
Voltage noise
Current noise
f = 100 MHz in BF Mode and CL Mode
2.3
nV/√Hz
pA/√Hz
f = 10 kHz
1.5
–68/–
VOUT = 2 VPP
f = 500 MHz
f = 1 GHz
58
–55/–
59
HD2/HD3 Harmonic distortion
dBc
–45/–
VOUT = 1 VPP
f = 2 GHz
49
–43/–
f = 2 GHz, RL = 50 Ω
41
DC PERFORMANCE
V
OUT –VIN
–600
–800
mV
VOS
Input offset voltage
Input offset voltage drift
Input bias current
TA = –40℃to 85℃
TA = –40℃to 85℃
–900
dVOS/dT
IB
±700
3
±1330
25
µV/℃
pA
220
TA = –40℃to 85℃
TA = –40℃to 85℃
VOUT = ± 0.5 V
44
140
IAB
Auxiliary Input bias current
µA
200
0.97
0.96
0.95
0.97
0.96
0.94
0.978
0.971
0.961
0.99
0.98
0.97
0.99
0.98
0.97
RL = 200 Ω
RL = 100 Ω
RL = 50 Ω
RL = 200 Ω
RL = 100 Ω
RL = 50 Ω
G
DC Gain
V/V
VOUT = ± 0.5 V ,TA = –40℃
to 85℃
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6.5 Electrical Characteristics: Wide Bandwidth Mode (continued)
at TA = 25°C, VS = ±6V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0V (mid-supply), CLH and CLL tied to VS+ and VS–
respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ)
PARAMETER
Test Condition
MIN
TYP
MAX UNIT
INPUT
ZIN
Input impedance
Input Clamp current rating
VCLH range(1)
f = 100 MHz
50 || 2.4
100
GΩ|| pF
Continous Current Rating
mA
0
VS+
V
VCLL range(1)
VS–
0
CLH Clamping Time
CLL Clamping Time
Time taken to clamp VOUT to VCLH during overdrive
Time taken to clamp VOUT to VCLL during overdrive
f = 500 MHz
0.2
0.2
4.5
2.1
1.2
nsec
VPP
Input Voltage Range
f = 1 GHz
f = 2 GHz
THD = –40 dBc
OUTPUT
VS+ –
1.9
TA = 25℃
VS–
+
3.4
Output Swing
V
VS+ –
2.0
TA = –40℃to 85℃
VS–
+
3.4
ZO
Output impedance
f = 100 MHz
1.2
Ω
AUXILIARY INPUT
0.18
0.26
0.23
V/V
V/V
GAUX VOUT to In_Aux Gain
TA = –40℃to 85℃
VS–
+
VS–
+
Default voltage at In_Aux
VS–+ 3
V
V
2.3
3.8
VS–
+
VS–
+
In_Aux Input Voltage Range
1.0
5.0
VOUT to In_Aux Bandwidth
RHF
800
100
MHz
Resistance between In_Bias to JFET source
kΩ
POWER SUPPLY
VS Operating voltage range
±4.5
±6.5
37
V
34
35.5
36
IQ
Quiescent current
mA
IOUT = 0 (R_bias = 17.8 kΩ) TA = –40℃to 85℃
CL Mode enabled
40
PSRR at 100 kHz on VS+
49
PSRR
Power-supply rejection ratio
dB
PSRR at 100 kHz on VS–
38
(1) The 0-V limits are for bipolar and balanced power supplies. For other supply configurations mid-supply will set the minimum limit for
VCLH and maximum limit for VCLL
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6.6 Electrical Characteristics: Low Quiescent Current Mode
at TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF. RS = 25 Ω, VOCM = 0 V (mid-supply), CLH and CLL tied to VS+ and VS–
respectively, Low Quiescent Current Mode unless otherwise specified (R_Bias = 35.7 kΩ)
PARAMETER
Test Condition
MIN
TYP
MAX UNIT
AC PERFORMANCE
SSBW
LSBW
Small-Signal Bandwidth
Large-Signal Bandwidth
VOUT = 100 mVPP
VOUT = 1 VPP
2.6
2
VOUT = 2 VPP
0.7
0.45
1.4
5500
0.3
0.16
1.4
0.8
10
GHz
Bandwidth for 0.1 dB flatness
Bandwidth for -1 dB flatness
Slew rate
VOUT = 1 VPP
SR
VOUT = 1.2-V step, VIN-SR = 13000 V/µs
VOUT = 1.2-V step (10% to 90%)
VOUT = 0.25-V step (10% to 90%)
V/µs
ns
Rise and fall time
Settling time to 0.1%
Settling time to 1%
VOUT = 1.2-V step, VIN-SR = 13000 V/µs
ns
1/f corner
kHz
en
in
Voltage noise
Current noise
f = 100 MHz
f = 10 kHz
2.2
1.5
nV/√Hz
pA/√Hz
–35/–
VOUT = 2 VPP
f = 500 MHz
f = 100 MHz
f = 500 MHz
32
–80/–
HD2/HD3 Harmonic distortion
dBc
77
VOUT = 1 VPP
–56/–
54
DC PERFORMANCE
0.96
0.95
0.96
0.95
0.975
0.963
0.99
RL = 200 Ω
RL = 100 Ω
RL = 200 Ω
RL = 100 Ω
VOUT = ± 0.5 V
0.98
V/V
0.99
G
DC Gain
VOUT = ± 0.5 V ,TA = –40℃
to 85℃
0.98
nsec
Ω
INPUT
CLH Clamping Time
CLL Clamping Time
Time taken to clamp VOUT to VCLH during overdrive
Time taken to clamp VOUT to VCLL during overdrive
0.3
0.7
OUTPUT
ZO
Output impedance
f = 100 MHz
1.2
POWER SUPPLY
VS
Operating voltage range
±4.5
±6.5
24
V
21
22
IQ
Quiescent current
mA
IOUT = 0 (R_bias = 35.7 kΩ)
TA = –40℃to 85℃
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6.7 Typical Characteristics
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
3
3
0
0
-3
-3
-6
-6
VOUT = 20 mVPP
VOUT = 100 mVPP
VOUT = 1 VPP
VOUT = 20 mVPP
VOUT = 100 mVPP
VOUT = 1 VPP
-9
-9
VOUT = 2 VPP
VOUT = 2 VPP
-12
-12
100M
1G
10G
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
Wide Bandwidth Mode
Low Quiescent Current Mode
图6-1. Frequency Response vs Output Voltage
图6-2. Frequency Response vs Output Voltage
0
3
VOUT = 20 mVPP
VOUT = 100 mVPP
VOUT = 1 VPP
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
-3
-6
-9
VS = 4.5 V
VS = 5 V
VS = 6 V
-12
100M
1M
10M
100M
Frequency (Hz)
1G
10G
1G
10G
Frequency (Hz)
Wide Bandwidth Mode
.
图6-3. Frequency Response vs Output Voltage,
图6-4. Frequency Response vs Supply Voltage
0.1 dB Flatness
3
0
3
0
-3
-3
-6
-6
RL = 100
RL = 200
-9
-9
R_Bias = 17.8 k
RL = 1 k
RL = 2 k
R_Bias = 35.7 k
R_Bias = 100 k
-12
100M
-12
100M
1G
10G
1G
10G
Frequency (Hz)
Frequency (Hz)
.
.
图6-5. Frequency Response vs Output Load
图6-6. Frequency Response vs R_Bias Resistance
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6.7 Typical Characteristics (continued)
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
6
3
0
3
-3
0
-6
-3
-6
-9
CL = 400 fF
CL = 1 pF
CL = 3 pF
CL = 3 pF, RISO = 22
CL = 1 pF, RISO = 39
-12
100M
-9
100M
1G
10G
1G
10G
Frequency (Hz)
Frequency (Hz)
.
.
图6-8. Frequency Response vs Cap Load with Recommended
图6-7. Frequency Response vs Capacitive Load
RISO
0.8
0.6
0.4
0.2
0
0.8
Input
Wide Bandwidth Mode
Low IQ Mode
0.6
0.4
0.2
0
-0.2
-0.2
-0.4
-0.6
-0.8
-0.4
Input
-0.6
-0.8
Wide Bandwidth Mode
Low IQ Mode
Time (200 ps/div)
Time (200 ps/div)
Rising edge, VOUT = 1.2 VPP
Falling edge, VOUT = 1.2 VPP
图6-9. Large-Signal Transient Response
图6-10. Large-Signal Transient Response
0.2
0.2
Input
Wide Bandwidth Mode
Low IQ Mode
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
Input
Wide Bandwidth Mode
Low IQ Mode
Time (200 ps/div)
Time (200 ps/div)
Rising edge, VOUT = 250 mVPP
Falling edge, VOUT = 250 mVPP
图6-12. Small-Signal Transient Response
图6-11. Small-Signal Transient Response
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6.7 Typical Characteristics (continued)
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
-20
-30
-40
-50
-60
-70
-80
-90
10
0
HD2, Wide Bandwidth Mode
HD3, Wide Bandwidth Mode
HD2, Low IQ Mode
HD2, Wide Bandwidth Mode
HD3, Wide Bandwidth Mode
HD2, Low IQ Mode
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
HD3, Low IQ Mode
HD3, Low IQ Mode
100M
1G
100M
1G
Frequency (Hz)
Frequency (Hz)
VOUT = 2 VPP
VOUT = 1 VPP
图6-14. Harmonic Distortion vs Frequency
图6-13. Harmonic Distortion vs Frequency
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-35
HD2, VOCM = −0.5 V
HD2, VOCM = +0.5 V
HD3, VOCM = −0.5 V
HD3, VOCM = +0.5 V
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
HD2, Wide Bandwidth Mode
HD3, Wide Bandwidth Mode
HD2, Low IQ Mode
HD3, Low IQ Mode
100M
1G
4.5 V
5 V
Supply (VS)
5.5 V
6 V
Frequency (Hz)
.
f = 500 MHz
图6-16. Harmonic Distortion vs Output Common Mode Voltage
图6-15. Harmonic Distortion vs Supply Voltage
-40
-40
HD2
HD3
HD2
HD3
-45
-50
-55
-60
-65
-70
-75
-80
-45
-50
-55
-60
-65
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
10
100
RL ()
1k
Output Voltage (VPP
)
f = 1 GHz
f = 1 GHz
图6-17. Harmonic Distortion vs Output Voltage
图6-18. Harmonic Distortion vs Output Load
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6.7 Typical Characteristics (continued)
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
-9
-12
-15
-18
-21
-24
-27
-30
1M
10M
100M
Frequency (Hz)
.
With RC pole of 2 kΩand 10 pF at IN_Aux pin
图6-20. Auxiliary Path Frequency Response
图6-19. Voltage and Current Noise Density vs Frequency
10k
35
Wide Bandwidth Mode
Low IQ Mode
30
25
20
15
10
5
1k
100
10
1
0
10M
100M
1G
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
.
.
图6-21. Input Impedance vs Frequency
图6-22. Output Impedance vs Frequency
250
200
150
100
50
0
-50
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
μ= 3.1 pA, σ= 1.03 pA
40 units
图6-23. Input Bias Current Distribution
图6-24. Input Bias Current vs Temperature
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6.7 Typical Characteristics (continued)
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
200
50
45
40
35
30
25
20
15
10
0
-200
-400
-600
-800
-1000
-5
-4
-3
-2
-1
0
1
2
3
4
5
-50
-25
0
25
50
75
100
Input Common Mode Voltage (V)
Ambient Temperature (°C)
.
Wide Bandwdith Mode and Low IQ Mode
图6-26. Quiescent Current vs Temperature
图6-25. Input Bias Current vs Input Common Mode Voltage
12000
10000
8000
6000
4000
2000
0
0.976
0.975
0.974
0.973
0.972
0.971
0.97
0.969
0.968
0.967
0.966
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
Gain (V/V)
Normalized to 25 °C values, 40 units
.
μ= 0.971 V/V, σ= 0.000485 V/V
图6-28. DC Gain vs Temperature
图6-27. DC Gain Histogram
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
630
620
610
600
590
580
570
560
550
-50
-25
0
25
50
75
100
Input Offset Voltage (mV)
Ambient Temperature (°C)
Normalized to 25 °C values, 40 units
图6-30. Offset Voltage vs Temperature
μ= 587.668 mV, σ= 8.80778 mV
图6-29. Offset Voltage Histogram
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6.7 Typical Characteristics (continued)
At TA = 25°C, VS = ±6 V, RL = 100 Ω|| 400 fF, RS = 25 Ω, VOCM = 0 V (mid-supply), VOUT = 1 VPP, CLH and CLL tied to VS+
and VS- respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ).
4
3
20k
15k
10k
5k
Input
Output, VCLH/VCLL = 2 V
2
1
0
-1
-2
-3
-4
0
-4
-3
-2
-1
0
1
2
3
4
Clamp Voltage Error (%)
Time (500 ps/div)
.
.
图6-32. Clamp Voltage Error Histogram
图6-31. Transient Clamp Response
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7 Parameter Measurement Information
图7-1 through 图7-3 show the various test setup configurations for the BUF802.
+6 V
+6 V
+ 6 V
+ 6 V
1 M
VS+
VS+
CLH
CLH
50
Cable
50
RISO
50
RS
OUT
VSO+
VSO–
VSO+
VSO–
IN
IN
OUT
400 fF
100 nF
R_Bias
VS–
R_Bias
VS–
50
50
CL
Hi-Z
CLL
100
CLL
400 fF
Variable
Voltage Source
–6 V
DC Parameters Measurment
–6 V
DMM
-6 V
Source
Spectrum Analyzer
-6 V
AC Parameters Measurment
图7-1. Main Path Electrical Characteristics Measurement
CLH
CLL
+6 V
+6 V
Main path
Aux path
VS+
VSO+
Variable voltage
source
VS+
CLH
DMM
Output
Driver
IN
IN
OUT
VSOœ
VSO+
OUT
In_Bias
VSOœ
In_Aux
In_Bias
R_Bias
100 ꢀ
VSœ
Hi-Z
CLL
In_Aux
VSœ
R_Bias
VSœ
Aux_Bias
œ6 V
œ6 V
图7-3. Auxiliary Path Electrical Characteristics
图7-2. Main Path and Auxiliary Path
Measurement
图 7-2 shows the two inputs for BUF802 (IN and In_Aux) which control the output. The IN pin controls the output
of BUF802 through the Main Path, whereas the In_Aux pin controls the output through the Auxiliary Path. Either
the Main Path or the Auxiliary Path, can be used to steer the output. The electrical characteristics of the Main
Path and the Auxiliary Path is specified in 节6.7.
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8 Detailed Description
8.1 Overview
The BUF802 device is a high input-impedance, open-loop buffer that can be used in signal acquisition front-end
applications. The BUF802 can be used as a standalone buffer, Buffer Mode (BF Mode), or in a composite loop
with a precision amplifier, Composite Loop Mode (CL Mode), to achieve DC precision and a wide, large-signal
bandwidth. The low output impedance and high output current drive strength enables the BUF802 to drive loads
as high as 50 Ω. The BUF802 comes with adjustable quiescent current to customize system level power and
performance trade-off.
8.2 Functional Block Diagram
Input Stage
Clamp Stage
CLL
Diamond Buffer / Output Stage
VSO+
VS+
CLH
JFET
IN
Ra
100 kꢀ
RHF
In_Bias
OUT
VBIAS
VCCS
In_Aux
I2
I1
VSOœ
Aux_Bias
VSœ
CLH
R_Bias
图8-1. Functional Block Diagram
图 8-1 shows an overview of the internal structure of the BUF802. The internal schematic of the BUF802 can be
divided into the following 3 parts:
• Input Stage, which consists of a low noise JFET and its biasing circuitry. The Input Stage can be configured
in two modes, BF Mode and CL Mode. Choosing one of the two modes affects the circuit operation of the
Input Stage. The Clamp and Output Stage operation are unaffected by the mode selection. 节8.4 describes
the two modes in greater detail.
• Clamp Stage, which provides the following functions:
1. Protects the input of the BUF802 against large input signal transients through diode clamps to VS- and
CLH respectively.
2. Ensures the output voltage of the BUF802 does not exceed the voltage at the CLH and CLL.
• Output Stage, which tracks the JFET source voltage and is optimized to drive a 50 Ω and 100 Ω load while
maintaining signal fidelity.
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8.3 Feature Description
8.3.1 Input and Output Over-Voltage Clamp
+6 V
1 kꢀ
1 …F
VZ = 2 V
Input clamp
circuit
Output clamp
circuit
CLH
D1
Q1
Q2
Output
JFET
OUT
pre-driver
+
clamp
IN
+
Clamp
diode
œ
D2
CLL
1 kꢀ
VZ = œ2 V
œ6 V
图8-2. Internal Input and Output Over-Voltage Clamp
The BUF802 device integrates an input and output clamp circuit. The input clamp protects the BUF802 from
large input transients and the output clamp protects the subsequent stages from being overdriven.
• Input Clamp Circuit:
– 图8-2 shows the input of the BUF802 tied to pins CLH and VS- through two internal clamp diodes, D1 and
D2. The diodes are rated for 100 mA of continuous current but can withstand much higher transient
currents. If the JFET input voltage exceeds the voltage at CLH or VS-, the diodes get forward biased,
clamping the JFET to CLH and VS-. A 1 μF capacitor connected in parallel to the zener diode, helps in
transient absorption travelling through the D1 diode.
– 图8-3 shows how the external clamping diodes can be used in cases where the 100 mA current rating of
D1 and D2 is insufficient. When using external clamping, disable the internal protection of the BUF802 by
connecting CLH and CLL to VS+ and VS-.
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+6 V
Input clamp
circuit
Output
clamp circuit
VS+
CLH
Q1
Q2
Output
D1
JFET
OUT
pre-driver
+
clamp
IN
+
Clamp
diode
œ
D2
CLL
VS-
œ6 V
图8-3. External Input Clamp Circuit
• Output Clamp Circuit:
– The output protection circuit prevents the stages following the BUF802 from being overdriven and also
ensures that the BUF802 recovers rapidly from a saturated state resulting from an input or output
overdrive condition. In a typical data-acquisition system, the BUF802 would be followed by a variable gain
amplifier (VGA). High-speed VGAs are typically designed on 5 V processes making it susceptible to
potential damage from the 12 V BUF802. The voltage applied to the CLH and CLL pins dictate the
maximum output swing of the BUF802.
– As shown in 图8-3, the internal clamps can be disabled by connecting CLH and CLL to VS+ and VS-
respectively. When the clamps are disabled, the maximum output swing is limited by the output swing
specification described in 节6.5. The response time and accuracy of the output clamp is shown in 节6.7.
– The output THD of the BUF802 degrades when VCLH and VCLL are set close to the expected VOUT peak
value. To prevent signal degradation, maintain at least a 1.5 V difference between the expected peak
output voltage and the clamp voltage applied at the CLH and CLL pins. 图8-4 shows the relation between
the absolute clamp voltage value and THD for a 1 VPP output.
-40
-45
-50
-55
-60
-65
-70
-75
4
3
THD, f = 500 MHz
THD, f = 1 GHz
Input
Output, VCLH/VCLL = 2 V
2
1
0
-1
-2
-3
-4
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Clamp Voltage (+VCLH / −VCLL
)
Time (500 ps/div)
图8-4. THD vs VCLH / VCLL for VOUT = 1 VPP
图8-5. Transient Clamp Response
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8.3.2 Adjustable Quiescent Current
The BUF802 includes an adjustable quiescent current feature to allow the system designer to trade-off the
current consumed versus the distortion performance obtained. As shown in 图 8-1, connect a resistor between
R_Bias and VS- to set the bias point operating current of the output stages. 图 8-6 shows the quiescent current
variation as a function of R_Bias value.
55
-10
-20
-30
-40
-50
-60
-70
-80
2100
1800
1500
1200
900
600
300
0
50
45
40
35
30
25
20
15
10
5
THD, f = 500 MHz
THD, f = 1 GHz
1dB flatness frequency range
10k
100k
R_Bias (W)
1M
D003
10k
30k
R_Bias ()
100k
.
图8-7. THD and Bandwidth vs R_Bias
图8-6. Quiescent Current vs R_Bias
图 8-7 shows that changing the resistor between R_Bias and VS- primarily affects the THD of the output signal.
节 6.5 and 节 6.6 specify the AC and DC parameters of the BUF802 at two different R_Bias values. The DC
parameters are independent of the quiescent current setting.
8.3.3 ESD Structure
图 8-8 shows the internal ESD structure of the BUF802. VSO and VS supply pins are internally shorted to each
other through back-to-back diodes. Refer to 节 10 for further information. The input ESD diodes D1 and D2 are
optimized to carry 100 mA of continuous current while the remaining ESD diodes are rated for 10 mA.
VSO+
VS+
CLH
JFET
D1
D2
IN
In_Bias
In_Aux
RHF
100 k
Supply
ESD
Supply
ESD
OUT
I2
I1
VS-
VSO-
R_Bias
Aux_Bias
图8-8. Internal ESD Structure
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8.4 Device Functional Modes
CLH
CLL
Main path
Aux path
VS+
VSO+
OUT
VSOœ
Output
Driver
IN
In_Bias
In_Aux
VSœ
R_Bias
VSœ
Aux_Bias
图8-9. Main Path and Auxiliary Path
The BUF802 has been designed to operate in two modes, Buffer Mode (BF Mode) and Composite Loop Mode
(CL Mode):
In BF Mode, the BUF802 uses the JFET, output driver and bipolar transistors in the Main Path to reproduce the
signal, applied on IN, at the output of the BUF802. 图 8-9 shows the Main Path and the Auxiliary Path of the
BUF802. The BUF802 can operate from DC to high-frequency and can therefore be used as a standalone buffer.
While being used in BF Mode, only the Main Path of the BUF802 is used.
In CL Mode, the BUF802 utilizes the Auxiliary signal path and the Main Path to control the output voltage. As the
name suggests in the Composite Loop Mode, the BUF802 is used in a composite loop with a precision amplifier
to achieve DC precision and a wide, large-signal bandwidth simultaneously. The composite loop splits the
applied signal to low-frequency and high-frequency components and passes them over to different circuits with
suitable transfer function. The low-frequency and high-frequency signal components then recombine inside the
BUF802 and are repoduced at the OUT pin.
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8.4.1 Buffer Mode (BF Mode)
VS+
VSO+
CLH
OUT
IN
I1
VSO-
VS-
R_Bias
图8-10. Internal Schematic –BF Mode
The wide large-signal bandwidth and fast slew rate of the BUF802 coupled with Hi-Z input are useful in a variety
of high-frequency signal chain applications. As shown in 图 8-10 the BUF802 uses the Main Path and operates
the JFET and transistors as source follower and emitter followers to reproduce signal applied on IN, at the output
of BUF802. The pins associated with only CL Mode (Pin No. 6, 4, and 3) are left floating while operating in BF
Mode.
+6V
1k
VZ = 2V
CLH
C1pF
+6V
OUT
Input
IN
BUF802
kꢀ
kꢀ
800
200
ꢀ
R1
1M
CLL
+
Precision
Amp
1k
VZ = -2V
-
- 6V
R2
R3
-6V
C2
Rx
Ry
图8-11. Composite Loop Using BF Mode
图 8-11 shows how the BUF802 can also be used in a composite loop while being operated in BF Mode. The
operation of BUF802 in 图 8-11 would still be called BF Mode since the signal is being transferred through the
Main Path only. The Auxiliary path and the pins associated with the Auxiliary path and CL Mode are kept
disabled. The low-frequency and high-frequency signal components are combined externally through the
discrete components R1 and C1 prior to being applied at the IN pin.
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8.4.2 Composite Loop Mode (CL Mode)
VS+
9
6
G ( Main Path )
330 pF
JFET
3
IN
Signal_In
0
Ra
-3
10M
100 k
Cross-Over
Frequency
Region
Diamond
Buffer
-6
In_Bias
RHF
VS+
-9
network
OUT
-12
-15
-18
-21
-24
-27
-30
GAUX ( Auxiliary Path )
In_Aux
+
Precision
Amp
Q1
-
Rb
I2
I1
High Frequency Region
Low Frequency Region
VS-
Aux_Bias
1
10 100 1k 10k 100k 1M 10M 100M 1G 10G
Frequency (Hz)
β
network
D004
图8-13. CL Mode Frequency Response
图8-12. Internal Schematic –CL Mode
The 330 pF input series capacitor shown in 图 8-12 splits the input signal into a low-frequency and high-
frequency component. These signals are applied to In_Aux and IN respectively. The IN pin controls the output of
BUF802 through the Main Path, whereas the In_Aux pin controls the output through the Auxiliary Path.
The transfer function of the composite loop in CL Mode can be split into the following 3 frequency regions:
1. Low Frequency Region: The gain of the composite loop in the low-frequency region is α/β(determined by
αand βnetwork). In the low-frequency region the 330 pF input capacitor presents a high-impedance in the
Main Path, causing the signal to flow through the precision amplifier and the In_Aux pin. This region spans
from DC to fLF. fLF is the pole resulting from the gain bandwidth of the precision amplifier, the Auxiliary Path
bandwidth, and parasitic capacitance of the components along the path.
2. High Frequency Region: In the high-frequency region, the precision amplifier and the Auxiliary Path run out
of bandwidth. The net gain of the composite loop in this region is determined solely by the Main Path gain of
the BUF802, which is denoted by G. This region spans from the pole created at fHF till the LSBW of the
BUF802. The fHF is the pole resulting from the 330 pF series capacitor and the 10 MΩresistor on the
In_Bias pin.
3. Cross-over Frequency Region: the Main Path and Auxiliary Path work in conjunction to determine the gain
in the crossover region. To maintain a flat frequency response in this region, the following conditions have to
be met:
a. α/β= G
b. High frequency response pole fHF<< Low frequency pole fLF
A detailed analysis of discrete component selection to achieve a flat frequency response is discussed further
in 节9.1.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The BUF802 offers a wide large-signal bandwidth, high-slew rate along with high-input impedance making it
ideal for data acquisition systems. In applications where DC precision is not needed or in cases where the input
is AC coupled, the BUF802 can be used as a standalone input buffer in BF Mode. In case the precision required
is higher than that offered by the BUF802, operate the BUF802 in CL Mode with a precision amplifier in a
composite loop.
9.2 Typical Application
9.2.1 Oscilloscope Front-End Amplifier Design
+ 6 V
1 k
VZ = 2 V
1
F
CLH
IN
30
Input
330 pF
To VGA
10 M
OUT
R_Bias
In_Bias
In_Aux
+6 V
R
2 800 k
1 200 k
Aux_Bias
17.8 k
CLL
+
2 k
R
OPA140
50
1 k
100 pF
–
–
V
–6 V
VZ = –2 V
6.8 nH
CF 56 pF
R
2 80 k
RPOT
图9-1. Oscilloscope Front-End Amplifier
9.2.1.1 Design Requirements
The following table shows the target specification for a 1-GHz oscilloscope front-end and precision amplifier.
Specification
Value
Input Impedance
1 MΩ/ 50 Ω
S Parameters (f = 1 GHz)
Offset Drift
S11 = –15 dB, S21 = –1.5 dB
1 µV/°C maximum
80 µVRMS
Noise at Highest Resolution (50 ΩInput)
9.2.1.2 Detailed Design Procedure
• Input Impedance: The JFET-input stage of the BUF802 offers giga ohm's of input impedance and therefore
enables the front-end to be terminated with a 1 MΩresistor without affecting performance. A 50 Ω
resistance can also be switched in offering matched termination for high-frequency signals. The BUF802
therefore enables the designer to use both 1 MΩand 50 Ωtermination in the same signal chain.
• Noise: The total noise of the front-end amplifier is the function of the voltage and current noise of the
BUF802, OPA140, and the resistors thermal noise. The dominant noise source, however, is contributed by
the voltage noise of the BUF802 due to its presence across the complete bandwidth. Thus, the total RMS
noise of the front-end amplifier shall be approximately equal to the voltage noise of BUF802 over 1 GHz.
The specified input referred voltage noise of the BUF802, as shown in 节6.5, is 2.3 nV/√Hz. The total input
referred RMS noise in a bandwidth of 1 GHz is given by the following equation:
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EnRMS = 2.3 nV/√Hz × √(1 GHz × 1.22) = 80 µVRMS
.
(1)
1.22 = Brickwall correction factor. Detailed calculations can be found on TI Precision Labs –Op Amps: Noise
–Spectral Density.
Total input refered spot noise as a function of frequency is shown in 图9-3. Assuming the oscilloscope has 8
divisions on the screen and a highest resolution of 1 mV, the full-scale reading is 8 mVPP or 2.82 mVRMS
Thus, the SNR of the front-end amplifier stage at the highest-resolution setting is:
.
20 × log (2.82 mVRMS / 80 µVRMS) = 31 dB.
(2)
• S11 Optimzation: The front-end amplifier circuit should have a perfect 50 Ωtermination to achieve the
required S11 parameter of -15 dB across the frequency. While it is possible to mount an exact 50 Ω
resistance at the input of the front-end composite loop circuit, the parasitic capacitance of the BUF802
appears in parallel to this 50 Ωresistance resulting in a net imperfect termination.
The parasitic input capacitance of BUF802 (IN pin) is 2.4 pF. At 1 GHz this parasitic capacitance reduces
down to an impedance of 66.3 Ω. Thus, the net input impedance as seen by the signal at the input is the
following:
66.3 Ω|| 50 Ω= 28.5 Ω
(3)
This results in an imperfect termination for the 50 Ωsource resulting in poor S11. The addition of a 30 Ω
resistance in series with the input trace and a 6.8 nH inductor in series with the onboard 50 Ωtermination
helps isolate the input parasitic capacitance as well as ensures the net input impedance is maintained at 50
Ω. The S11 response of this modified circuit is shown in 图9-4.
+ 6V
30
Input
OUT
BUF802
- 6V
50
2.4 pF
6.8 nH
图9-2. Net Input Impedance
• Uniform Gain Across Frequency: The front-end amplifier circuit is designed with BUF802 and OPA140
connected in a composite loop. The loop splits the input signal into low- and high-frequency components,
taking both components to the output through two different circuits (transfer functions) and recombining them
to reproduce a net output signal. The end goal is to achieve a smooth transition between the two circuits and
ensure a flat frequency response from DC till the frequency of interest.
CL Mode of BUF802 simplifies this design for achieving a flat frequency response from DC till the frequency
of interest (1 GHz in this case). To achieve a flat response, the following two conditions have to be met:
1. α/β= G
2. High frequency response pole fHF<< low frequency pole fLF
αis the input attenuation factor and βis the inverse of the non-inverting gain of the precision amplifier. G is
the DC gain of the Main Path of the BUF802. Since G can vary from device-to-device, trimming either αor
βis recommended to achieve a flat frequency response. In 图9-1, βmay be trimmed using the RPOT.
Since G is ≈1 V/V and αis 1/5 (200 kΩ/ (200 kΩ+ 800 kΩ)), RPOT should be trimmed so that β≈1/5.
For the βnetwork, it is recommended to use resistors which are an order of magnitude of resistance lower
than the resistors used in the αnetwork. Therefore βresistor values of 80 kΩand ≈20 kΩhave been
chosen.
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fHF is the pole resulting from the 330 pF series capacitor and the 10 MΩresistor on the In_Bias pin.
fHF = 1/(2 × pi × R × C) = 1/(2 × 3.14 × 10 MΩ× 330 pF) = 48 Hz
(4)
(5)
fLF is the pole resulting from the gain bandwidth of the precision amplifier (OPA140), the Auxiliary Path
bandwidth and other parasitic capacitance of the resistor network.
fLF = GBW × GAUX × β= 440 kHz
Where GBW is the gain bandwidth product of the precision amplifier (OPA140) = 11 MHz. GAUX is the gain
from In_Aux to OUT = 0.2 V/V. 1/βis the external non-inverting gain set for the precision amplifier = 5 V/V.
Based on the above value of fHF and fLF, the required condition of fHF<< fLF is met. CF, connected across the
precision amplifier, is required to compensate for the parasitic capacitance and to make the overall poles and
zeros cancel each other. The value of CF can be found by using the following equation:
CF = CINPA × ((G × Rα2 / Rβ2) –1)).
(6)
Where CINPA is the common mode input capacitance of the precision amplifier, OPA140 in this case.
Plugging in the value of these components arrives at CF = 56 pF. In the final system, based on the quality of
the flat band response needed, CF may or may not be trimmed along with RPOT in the final production flow.
9.2.1.3 Application Curves
1000
100
10
0
-5
-10
-15
-20
-25
-30
-35
-40
S11
S21
1
10M
100M
Frequency (Hz)
1G
10k
100k
1M
10M
100M
1G
Frequency (Hz)
图9-4. S11 and S21 Response
图9-3. Front-End Composite Loop Noise
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
100
1k
10k
Frequency (Hz)
100k
1M
图9-5. Frequency Response Flatness: Cross-Over Frequency Region
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9.2.2 Transforming a Wide-Bandwidth, 50 ΩInput Signal Chain to High-Input Impedance
+6 V
BUF802 EVM
TIDA-01022
VZ = 2V
1 k
+2.5 V
+2.5 V
2.2-GHz LOW PASS FILTER
LMH5401
25
LMH6401
1 μF
127
3.9nF
365
5.6 nF
Input
30 Ω
330 pF
4.99
CLH
IN
VIN+
0.01 uF
IN+
10
10
10
10
50 Ω
22.6
40
10 M
_
1 pF
1 pF
2.4 pF
2.4 pF
1.21 k
OUT
RBias
Aux_Bias
In_Bias
+
+6 V
ADC
In_Aux
CLL
800 k
IN-
_
ADC12DJ3200
1.21 k
+
+
2 k
40
22.6
VIN-
127
25
OPA140
200 k
3.9 nF
5.6 nF
50
4.99
1 k
100 pF
0.01 uF
+2.5 V
0.01 uF
-
25
365
VOCM
VOCM
-6 V
SCK, SDI
SDO, CSb
-6 V
VZ = -2V
2 K
6.8 nH
PD
-2.5 V
PD
-2.5 V
50
56pF
VCM
2 K
80 k
Rx
Offset Control
DAC
R
-2.5 V
图9-6. BUF802 + TIDA-01022: Signal Chain
9.2.2.1 Detailed Design Results
TIDA-01022 reference design primarily focuses on a multichannel high-speed analog front-end, which is typically
used in end equipment like a digital storage oscilloscope (DSO), wireless communication test equipment
(WCTE), and radars. A 50 Ωinput data acquisition (DAQ) signal chain like that of TIDA-01022 can be converted
into a high-input impedance DAQ system by inserting the BUF802 at the front.
TIDA-01022 orginally features the following:
• LMH5401 is a high-performance, differential amplifier with an usable bandwidth from DC to 2 GHz. It is used
as single to differential conversion amplifier in this signal chain. The device offers excellent linearity
performance at a fixed 12-dB gain.
• LMH6401 is a wideband digitally controlled variable gain, differential in and differential out, amplifier. The
noise and distortion performance are optimized to drive ultra-wideband ADCs. The device offers DC to 4.5-
GHz bandwidth with a gain range from –6 dB to 26 dB in 1-dB steps. The gain can be controlled using a
standard serial peripheral interface (SPI).
• The ADC12DJ5200RF device is a 12 bit, giga-sample, analog-to-digital converter (ADC) that can directly
sample input frequencies from DC to above 10 GHz. ADC12DJ5200RF can be configured as a dual-channel,
5.2 GSPS ADC or single-channel, 10.4 GSPS ADC.
The BUF802 along with offering high-input impedance and low-noise for the front-end amplifier, holds capability
of driving matched loads of 50 Ω, making it easy to retrofit with predesigned analog front-end signal chains. 图
9-7 to 图 9-9 shows the comparison of native performance of the TI design TIDA-01022 and performance
achieved post addition of BUF802 at the front-end. Adding BUF802 at the input of TIDA-01022 translates the
original 50 Ω input imepdance TI design to a high-input impedance DAQ signal chain. A simplified schematic of
BUF802 + TIDA-01022 is shown in 图9-6.
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9.2.2.2 Application Curves
3
60
56
52
48
44
40
BUF802 + TIDA-01022
TIDA-01022 only
BUF802 + TIDA-01022
TIDA-01022 only
0
-3
-6
-9
1M
10M
100M
Frequency (Hz)
1G
100k
1M
10M
100M
1G
Frequency (Hz)
图9-8. Total Harmonic Distortion (THD) vs
图9-7. Gain vs Frequency
Frequency
56
54
52
50
48
46
44
BUF802 + TIDA-01022
TIDA-01022 only
42
1M
10M
100M
Frequency (Hz)
1G
图9-9. Signal To Noise Ratio (SNR) vs Frequency
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10 Power Supply Recommendations
The BUF802 is intended to operate with supplies ranging from ±4.5 V to ±6.5 V. The BUF802 can operate on
either single-sided supplies or split supplies. When using split supplies, the supplies may be symmetrically
balanced around GND or asymmetric. For best AC performance, the input and output signal should be centered
around the mid-supply.
Minimize the distance between the power-supply pins and decoupling capacitors. The high frequency capacitors
(< 0.1 µF) should be placed close to the supply-pins on the same side of the PCB as the BUF802. Larger
capacitors (> 1 µF) can be placed further away from the device. 节 11 has additional details on decoupling
capacitor layout and routing.
The BUF802 has two sets of supply pins: VS+ and VS-; VSO+ and VSO-. The separation of the input and output
stage supply pins minimize spurious cross-talk and maximizes transient decoupling between the two stages. 图
8-1 shows how both sets of supply pins are internally connected through back-to-back diodes. It is therefore
imperative that the supply pins for the input and output stages are connected to the same potential. As shown in
节11, maintain separate and individual decoupling capacitors for all the supply pins.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with the BUF802 requires careful attention to board layout, parasitics, and
passive component selection. Consider the following:
• Peaking in the S21 transfer function: keeping the trace length minimum is of prime importance to ensure
no peaking occurs in the S21 transfer function of the BUF802. The trace inductance can form a resonant
circuit with the input capacitance of the BUF802, causing peaking in the S21 response. Add a small resistor
(R5 in 图11-1) in series with the DC blocking capacitor to dampen the LC resonance created by the trace
inductance and the input capacitance of the BUF802. Choose series capacitors (C7 in 图11-1) with low
equivalent series inductance (ESL) to minimize total inductance.
• Power-supply bypass capacitors: mount the power-supply bypass capacitors as close to the supply pins as
possible and on the same side of the PCB as the BUF802. As shown in 图11-1, choose low-inductance LICC
capacitors (C5, C6, C13, and C10) to minimize high frequency impedance between the BUF802 and the
bypass capacitors. Use multiple vias between the bypass capacitor and GND to reduce series inductance. As
shown in 图11-1, also use multiple vias to GND on the 50 Ω input termination resistor (R3). Connect the
bypass and termination vias to a solid GND plane.
• High precision signal path, consisting of the precision op amp along with discrete components, can be
adjusted and moved around to give precedence to the above two points. In the 图11-3, the precision
components were placed on the opposite side of the PCB as the BUF802.
• Thermal pad of the BUF802 is thermally conductive but electrically insulated to the die. This gives the circuit
designer flexibility in connecting the thermal pad to any voltage. Choose a power or GND plane with the
highest thermal mass for effective heat dissipation.
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11.2 Layout Example
VCC
VCC1
GND1
VEE1
Pin1
OPA
Pin12
Pin1
Pin12
CLH
CLL
C5
0.1uF
25V
C6
0.1uF
25V
C1
2.2µF
50V
C3
16V
0.22uF
C15
16V
0.22uF
C4
16V
0.22uF
D1
MMSZ4679T1G
2V
C17
16V
0.22uF
D2
MMSZ4679T1G
2V
C18
16V
0.22uF
TP1
TP2
C13
0.1uF
25V
C10
0.1uF
25V
C2
2.2µF
50V
C9
16V
0.22uF
C8
16V
0.22uF
C14
16V
0.22uF
5012
5012
GND
VEE
R14
0
R19
0
Pin8910
OPA
Pin5
Pin5
Pin8910
GND
GND
U1
VCC
R7
50
OUT
1
1
11
15
14
VCC
VOUT
VCH
VCL
VCC
12
2
VCC2
VIN
R1
J1
CLH
CLL
C7
R5
R6
50
1
IN
J2
1.00k
VEE
VEE
30.9
R2
100V
330pF
IN_Aux
IN_Bias
R_Bias
GND
4
VIN_AUX
VIN_BIAS
RBIAS
R3
50
R4
13.0k
1.00k
R8
VEE
3
GND
5
10.0M
VEE
VEE
GND
VEE
R11
7
8
R9
787k
10
6
17.8k
VEE2
VEE_B
R12
0
L1
6.8nH
VEE
Aux_Bias
GND
9
13
16
NC
NC
NC
OPA140AIDBVT
3
U2
CLL
CLH
17
PAD
R10
1
R20
200k
4
BUF802IRGT
2.00k
R13
200k
TP5
C12
50V
GND
C19
16V
100pF
VCC
5012
GND
0.22uF
GND
C11
GND
GND
25V
56pF
R21
R15
10.0k
78.7k
R17
R18
R16
1
32.4k
0
C16
100nF
50V
J3
GND
GND
GND
图11-1. Layout Example: Schematic for Layout Reference
Ord rable: Ch geMe in varia
ID N/A
Number AMPS131
SVN Rev: No in versio co tro
Rev:
xa Instrume ts
warra th this sign will me th sp cificatio s, will
lice sors warra th th sign is ro ctio worth
/o its lice sors
warra th ccuracy complete ss this sp cificatio
suita le fo yo licatio fit fo rticula
sh ld completely valid te test yo
informatio co tain th rein
rp se will rate in impleme tatio
sign impleme tatio to co firm th syste fu ctio lity fo yo
xa Instrume ts
/o its lice sors
/o its
licatio
xa Instrume ts
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图11-2. Layout Example: Top Layer
图11-3. Layout Example: Bottom Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless
test systems reference designs
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BUF802IRGTR
ACTIVE
VQFN
RGT
16
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BUF802
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF802IRGTR
VQFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGT 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
BUF802IRGTR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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