CAXC8T245QWRGYRQ1 [TI]
具有可配置电压转换和三态输出的汽车类 8 位双电源总线收发器 | RGY | 24 | -40 to 125;
| 型号： | CAXC8T245QWRGYRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可配置电压转换和三态输出的汽车类 8 位双电源总线收发器 | RGY | 24 | -40 to 125 总线收发器 |
| 文件： | 总41页 (文件大小：2799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
具有可配置电压转换和三态输出的SN74AXC8T245-Q1 汽车8 位双电源总线收
发器
SN74AXC8T245-Q1 器件旨在实现数据总线间的异步
通信。根据方向控制输入（DIR1 和 DIR2）的逻辑电
1 特性
• 符合面向汽车应用的AEC-Q100 标准
• 采用可湿侧面QFN (WRGY) 封装
• 通过认证且完全可配置的双电源轨设计可允许各个
端口在0.65V 至3.6V 的电源电压范围内运行
• 工作温度范围为–40°C 至+125°C
• 多向控制引脚，支持同步升降转换
平，此器件将数据从 A 总线传输至 B 总线，或者将数
据从 B 总线传输至 A 总线。输出使能 (OE) 输入可用
于禁用输出，从而有效隔离总线。
SN74AXC8T245-Q1 器件旨在使控制引脚（DIR 和
OE）以VCCA 为基准。
• 从1.8V 转换到3.3V 时，支持高达380Mbps 的转
换速率
• VCC 隔离功能可在断电情况下有效隔离两条总线
• 局部断电模式可在断电情况下限制回流电流
• 兼容SN74AVC8T245-Q1 电平转换器
• 闩锁性能超过100mA，符合JESD 78 II 类规范
该器件专用于使用 Ioff 的局部断电应用。当器件断电
时，Ioff 电路将会禁用输出。这会抑制电流反流到器件
中，从而防止损坏器件。
VCC 隔离功能可确保当任一 VCC 输入电源低于 100mV
时，所有电平转换器输出都将禁用并处于高阻抗状态。
为了确保电平转换器I/O 在上电或断电期间处于高阻抗
状态，应将 OE 通过上拉电阻器接到 VCCA；此电阻器
的最小值由驱动器的灌电流能力决定。
2 应用
• 信息娱乐系统音响主机
• ADAS 融合
• ADAS 前置摄像头
• HEV 电池管理系统
器件信息
器件型号(1)
封装尺寸（标称值）
封装
SN74AXC8T245PW-Q1
SN74AXC8T245RHL-Q1
TSSOP (24) 4.40mm × 7.80mm
3 说明
VQFN (24)
3.50mm × 5.50mm
3.50mm × 5.50mm
SN74AXC8T245WRGY-Q1 VQFN (24)
通过AEC-Q100 认证的SN74AXC8T245-Q1 器件是一
款 8 位同相总线收发器，可用于解决在最新电压节点
（0.7V、0.8V 和 0.9V）上运行的器件与在业界通用电
压节点（1.8V、2.5V 和 3.3V）上运行的器件之间的电
压电平不匹配问题。
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
3.3 V
1.5 V
Processor
VCCA DIR1 DIR2
VCCB
B1
Power Management
A1
A2
A3
A4
器件通过两条独立电源轨（VCCA 和 VCCB）运行，运
行电压可低至 0.65V。数据引脚 A1 至 A8 均用于跟踪
VCCA，可承受 0.65V-3.6V 的电源电压。数据引脚 B1
至 B8 均用于跟踪 VCCB，可承受 0.65V-3.6V 的电源电
压。
Control Block
B2
B3
B4
B5
B6
B7
B8
SN74AXC8T245-Q1
Data Block
Interrupts
Register Map
Sensor Block
A5
A6
A7
A8
GND
GND
典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES892
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
Table of Contents
7 Parameter Measurement Information..........................18
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 接收文档更新通知................................................... 26
12.3 支持资源..................................................................26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 0.7 V..................... 7
6.7 Switching Characteristics, VCCA = 0.8 V..................... 8
6.8 Switching Characteristics, VCCA = 0.9 V..................... 9
6.9 Switching Characteristics, VCCA = 1.2 V................... 10
6.10 Switching Characteristics, VCCA = 1.5 V................. 11
6.11 Switching Characteristics, VCCA = 1.8 V................. 12
6.12 Switching Characteristics, VCCA = 2.5 V................. 13
6.13 Switching Characteristics, VCCA = 3.3 V................. 14
6.14 Operating Characteristics: TA = 25°C..................... 15
6.15 Typical Characteristics............................................17
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (May 2021) to Revision C (October 2021)
Page
• 重新编排了器件信息表.......................................................................................................................................1
• 在特性中添加了可湿性侧面信息........................................................................................................................ 1
• Added wettable flank information in Feature Description ................................................................................ 21
Changes from Revision A (July 2019) to Revision B (May 2021)
Page
• 向器件信息表添加了SN74AXC8T245QRGYQ1 器件型号................................................................................1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added the RGY Package to the Pin Configuration and Functions section.........................................................3
• Added the RGY Package to the Thermal Information section............................................................................5
Changes from Revision * (November 2018) to Revision A (July 2019)
Page
• 将状态更改为量产数据........................................................................................................................................1
• Added Typical Characteristics graphs for Production Data release. ................................................................17
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5 Pin Configuration and Functions
VCCA
DIR1
A1
1
24
23
22
21
20
19
18
17
VCCB
VCCB
OE
B1
2
2
3
23
VCCB
DIR1
A1
3
22 OE
A2
4
4
21
A2
B1
5
20
A3
B2
A3
5
B2
6
19
A4
B3
A4
6
B3
PAD
7
18
A5
B4
A5
7
B4
8
17
A6
B5
A6
8
B5
9
16
A7
B6
A7
9
16
15
14
13
B6
10
11
15
A8
B7
A8
10
11
12
B7
14
DIR2
B8
DIR2
GND
B8
GND
PAD —may be grounded (recommended) or left floating.
.
图5-2. RHL and WRGY Package 24-Pin VQFN Top
图5-1. PW Package 24-Pin TSSOP Top View
View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
PW, RHL,
WRGY
NAME
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
DIR1
3
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Input/output A1. Referenced to VCCA
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Input/output A2. Referenced to VCCA
Input/output A3. Referenced to VCCA
Input/output A4. Referenced to VCCA
Input/output A5. Referenced to VCCA
Input/output A6. Referenced to VCCA
Input/output A7. Referenced to VCCA
Input/output A8. Referenced to VCCA
Input/output B1. Referenced to VCCB
Input/output B2. Referenced to VCCB
Input/output B3. Referenced to VCCB
Input/output B4. Referenced to VCCB
Input/output B5. Referenced to VCCB
Input/output B6. Referenced to VCCB
Input/output B7. Referenced to VCCB
Input/output B8. Referenced to VCCB
5
6
7
8
9
10
21
20
19
18
17
16
15
14
2
Direction-control signal 1. Referenced to VCCA. Refer to 表8-1.
Direction-control signal 2. Refer to 表8-1.
DIR2
GND
11
I
Referenced to VCCA. Tie to GND to maintain backward compatibility with SN74AVC8T245-
Q1 device.
12
13
Ground
Ground
—
—
Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high-
impedance mode. Referenced to VCCA. Refer to 表8-1.
OE
22
I
VCCA
1
A-port supply voltage. 0.65 V ≤VCCA ≤3.6 V
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V
—
—
—
23
24
VCCB
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX
4.2
4.2
4.2
4.2
4.2
4.2
4.2
UNIT
V
Supply voltage, VCCA
Supply voltage, VCCB
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
(2)
Input voltage, VI
V
V
Voltage applied to any output
in the high-impedance or power-off state, VO
(2)
B port
A port
VCCA + 0.2
VCCB + 0.2
(2) (3)
Voltage applied to any output in the high or low state, VO
V
B port
Input clamp current, IIK
VI < 0
mA
mA
mA
mA
°C
Output clamp current, IOK
VO < 0
–50
Continuous output current, IO
Continuous current through VCCA, VCCB, or GND
Junction Temperature, TJ
50
–50
100
150
150
–100
Storage temperature, Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节6.3.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
0.65
MAX
3.6
UNIT
V
VCCA
VCCB
Supply voltage
Supply voltage
0.65
3.6
V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCI × 0.70
VCCI × 0.70
VCCI × 0.65
1.6
Data inputs
2
VIH
High-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCA × 0.70
VCCA × 0.70
VCCA × 0.65
1.6
Control inputs
(DIR, OE)
Referenced to VCCA
2
VCCI × 0.30
VCCI × 0.30
VCCI × 0.35
0.7
Data inputs
0.8
VIL
Low-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCA × 0.30
VCCA × 0.30
VCCA × 0.35
0.7
Control inputs
(DIR, OE)
Referenced to VCCA
0.8
VI
Input voltage(3)
Output voltage
0
0
0
3.6
V
V
(2)
Active state
Tri-state
VCCO
VO
3.6
10
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
125
–40
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
6.4 Thermal Information
SN74AXC8T245-Q1
THERMAL METRIC(1)
PW (TSSOP)
24 PINS
92.0
RHL (VQFN) WRGY (VQFN)
UNIT
24 PINS
35.0
39.9
13.8
0.3
24 PINS
48.1
43.2
26.1
2.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
29.3
RθJB
ψJT
Junction-to-board thermal resistance
46.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.5
46.2
13.8
1.4
26.0
15.8
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)(1) (2)
–40°C to 85°C
–40°C to 125°C
MIN TYP(4) MAX
VCCO –0.1
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
MIN TYP(4) MAX
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
IOH = –100 µA
IOH = –50 µA
IOH = –200 µA
IOH = –500 µA
V
CCO –0.1
0.55
0.58
0.65
0.85
1.05
1.2
0.55
0.58
0.65
0.85
1.05
1.2
High-level
VOH output
VI = VIH
V
IOH = -3 mA
IOH = -6 mA
IOH = -8 mA
IOH = -9 mA
IOH = -12 mA
IOL = 100 µA
IOL = 50 µA
IOL = 200 µA
IOL = 500 µA
IOL = 3 mA
IOL = 6 mA
IOL = 8 mA
IOL = 9 mA
IOL = 12 mA
voltage
1.4 V
1.4 V
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
1.75
2.3
3 V
3 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.1
0.1
0.1
0.1
0.18
0.2
0.18
0.2
Low-level
VOL output
voltage
VI = VIL
0.25
0.35
0.45
0.55
0.7
0.25
0.35
0.45
0.55
0.7
V
1.4 V
1.4 V
1.65 V
2.3 V
1.65 V
2.3 V
3 V
3 V
Input leakage Control Inputs (DIR, OE):
II
0.65 V - 3.6 V
0 V
0.65 V - 3.6 V
0 V - 3.6 V
0 V
-0.5
-8
0.5
8
-1
-12
-12
1
12
12
µA
µA
current
VI = VCCA or GND
A Port:
VI or VO = 0 V - 3.6 V
Partial power
down current
Ioff
B Port:
0 V - 3.6 V
-8
8
VI or VO = 0 V - 3.6 V
A Port:
VO = VCCO or GND, VI = VCCI
or GND, OE = VIH
3.6 V
3.6 V
3.6 V
3.6 V
-8
-8
8
-12
-12
12
High-
IOZ
impedance
state output
current
µA
µA
(3)
B Port:
VO = VCCO or GND, VI = VCCI
or GND, OE = VIH
8
12
40
0.65 V - 3.6 V
0 V
0.65 V - 3.6 V
3.6 V
20
VCCA supply
current
ICCA
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
-2
-2
-12
-12
3.6 V
0 V
12
20
12
25
40
0.65 V - 3.6 V
0 V
0.65 V - 3.6 V
3.6 V
VCCB supply
current
ICCB
25 µA
3.6 V
0 V
ICCA Combined
supply
ICCB current
+
VI = VCCI or GND, IO = 0 mA
Control Inputs (DIR, OE):
0.65 V - 3.6 V
3.3 V
0.65 V - 3.6 V
3.3 V
30
60 µA
pF
Input
Ci
4.5
5.7
4.5
5.7
capacitance VI = 3.3 V or GND
Ports A and B:
OE = VCCA, VO = 1.65V DC +
1 MHz -16 dBm sine wave
Data I/O
Cio
3.3 V
3.3 V
pF
capacitance
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) All typical values are for TA = 25°C
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6.6 Switching Characteristics, VCCA = 0.7 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
MIN
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
MAX
UNIT
MAX
172
172
172
172
192
195
156
157
237
237
223
223
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
114
114
153
153
192
195
129
129
237
237
145
145
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
82
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
49
49
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
82
Propagation
delay
tpd
tdis
ten
ns
126
126
192
195
118
120
237
237
106
106
88
From input B
to output A
88
192
195
120
122
237
237
74
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
From input OE
to output B
74
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
MAX
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
46
MIN
MAX
49
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
61
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
142
142
81
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
46
49
61
Propagation
delay
tpd
tdis
ten
ns
83
82
81
From input B
to output A
83
82
81
81
192
195
69
192
195
66
192
195
67
192
195
150
150
237
237
552
552
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
70
67
67
237
237
68
237
237
69
237
237
84
From input OE
to output A
From input OE
to output B
68
69
84
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: SN74AXC8T245-Q1
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ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
6.7 Switching Characteristics, VCCA = 0.8 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
MIN
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
UNIT
MAX
153
153
114
114
101
103
141
142
102
102
202
202
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
95
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
62
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
32
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
95
62
32
Propagation
delay
tpd
tdis
ten
ns
95
78
52
From input B
to output A
95
78
52
101
103
114
115
102
102
124
124
101
103
104
106
102
102
86
101
103
106
109
102
102
52
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
From input OE
to output B
86
52
B-PORT SUPPLY VOLTAGE (VCCB
1.8 V ± 0.15 V 2.5 V ± 0.2 V
MAX
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
3.3 V ± 0.3 V
UNIT
MIN
MAX
26
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
25
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
35
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
25
25
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
26
25
35
Propagation
delay
tpd
tdis
ten
ns
42
41
40
40
From input B
to output A
42
41
40
40
101
103
55
101
103
51
101
103
49
101
103
51
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
57
53
50
52
102
102
44
102
102
43
102
102
45
102
102
58
From input OE
to output A
From input OE
to output B
44
43
45
58
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: SN74AXC8T245-Q1
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
6.8 Switching Characteristics, VCCA = 0.9 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
0.8 V ± 0.04 V 0.9 V ± 0.045 V
MAX
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
1.2 V ± 0.1 V
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
127
127
82
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
52
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
23
78
78
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
52
23
Propagation
delay
tpd
tdis
ten
ns
63
52
39
From input B
to output A
82
63
52
39
125
128
131
133
124
128
191
191
125
128
105
107
124
128
113
113
125
128
96
125
128
99
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
98
101
124
128
41
124
128
75
From input OE
to output A
From input OE
to output B
75
41
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
17
MIN
MAX
15
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
14
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
17
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
17
15
14
17
Propagation
delay
tpd
tdis
ten
ns
28
24
22
22
From input B
to output A
28
24
22
22
125
128
47
125
128
44
125
128
40
125
128
73
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
50
46
42
73
124
128
34
124
128
32
124
128
31
124
128
35
From input OE
to output A
From input OE
to output B
34
32
31
35
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: SN74AXC8T245-Q1
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
6.9 Switching Characteristics, VCCA = 1.2 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
MAX
88
MIN
0.5
0.5
0.5
0.5
0.5
0.5
MAX
52
MIN
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
0.5
0.5
0.5
0.5
0.5
0.5
MAX
15
39
39
23
23
87
91
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
88
52
15
Propagation
delay
tpd
ns
49
32
15
From input B
to output A
49
32
15
From input
OE
to output A
87
87
87
91
91
91
tdis Disable time
ns
ns
From input
OE
to output B
0.5
0.5
119
121
0.5
0.5
94
96
0.5
0.5
85
88
0.5
0.5
89
93
–40°C to 85°C
–40°C to 125°C
From input
OE
to output A
0.5
0.5
34
36
0.5
0.5
34
36
0.5
0.5
34
36
0.5
0.5
34
36
–40°C to 85°C
–40°C to 125°C
ten Enable time
From input
OE
to output B
0.5
0.5
168
168
0.5
0.5
98
98
0.5
0.5
61
61
0.5
0.5
29
30
–40°C to 85°C
–40°C to 125°C
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
MIN
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
UNIT
MAX
10
10
13
13
87
91
38
41
34
36
22
23
MIN
MAX
9
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
7
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
9
7
8
Propagation
delay
tpd
ns
11
11
87
91
35
38
34
36
19
20
8
7
From input B
to output A
8
7
87
91
31
33
34
36
17
18
87
91
29
31
34
36
17
18
From input OE
to output A
tdis
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
ten
From input OE
to output B
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: SN74AXC8T245-Q1
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
6.10 Switching Characteristics, VCCA = 1.5 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
UNIT
MIN
0.5
MAX
84
MIN
0.5
MAX
42
MIN
0.5
MAX
28
MIN
0.5
MAX
13
13
–40°C to 85°C
From input A
to output B
0.5
84
0.5
42
0.5
28
0.5
–40°C to
125°C
Propagation
delay
tpd
tdis
ten
ns
0.5
0.5
46
46
0.5
0.5
26
26
0.5
0.5
17
17
0.5
0.5
10
10
–40°C to 85°C
From input B
to output A
–40°C to
125°C
0.5
0.5
34
37
0.5
0.5
34
37
0.5
0.5
34
37
0.5
0.5
34
37
–40°C to 85°C
From input OE
to output A
–40°C to
125°C
Disable time
ns
0.5
0.5
115
117
0.5
0.5
89
91
0.5
0.5
80
83
0.5
0.5
85
89
–40°C to 85°C
From input OE
to output B
–40°C to
125°C
0.5
0.5
21
23
0.5
0.5
21
23
0.5
0.5
21
23
0.5
0.5
21
23
–40°C to 85°C
From input OE
to output A
–40°C to
125°C
Enable time
ns
0.5
0.5
159
159
0.5
0.5
90
90
0.5
0.5
55
55
0.5
0.5
24
25
–40°C to 85°C
From input OE
to output B
–40°C to
125°C
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
UNIT
MIN
MAX
9
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
7
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
6
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
9
7
6
6
Propagation
delay
tpd
tdis
ten
ns
9
7
6
5
From input B
to output A
9
8
6
5
34
37
35
38
21
23
17
18
34
37
31
34
21
23
15
15
34
37
28
31
21
23
12
13
34
37
25
27
21
23
11
12
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
From input OE
to output B
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: SN74AXC8T245-Q1
SN74AXC8T245-Q1
ZHCSII8C –NOVEMBER 2018 –REVISED OCTOBER 2021
www.ti.com.cn
6.11 Switching Characteristics, VCCA = 1.8 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
UNIT
MIN
MAX
82
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
41
41
25
25
37
40
87
89
17
19
88
88
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
24
24
15
15
37
40
78
81
17
19
54
54
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
11
11
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
82
Propagation
delay
tpd
tdis
ten
ns
49
From input B
to output A
49
9
37
37
40
83
87
17
19
23
23
From input OE
to output A
40
Disable time
Enable time
ns
ns
113
115
17
From input OE
to output B
From input OE
to output A
19
157
157
From input OE
to output B
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
MIN MAX
0.5
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
MAX
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
6
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
5
5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
7
6
Propagation
delay
tpd
tdis
ten
ns
7
6
5
4
From input B
to output A
7
7
5
4
37
40
33
36
17
19
15
16
37
40
30
33
17
19
13
14
37
40
27
29
17
19
10
11
37
40
57
60
17
19
9
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
From input OE
to output B
10
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6.12 Switching Characteristics, VCCA = 2.5 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
UNIT
MIN
MAX
81
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
40
40
25
25
25
28
85
87
11
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
22
22
14
14
25
28
76
78
11
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
81
8
Propagation
delay
tpd
tdis
ten
ns
61
7
From input B
to output A
61
7
25
25
28
81
84
11
12
21
21
From input OE
to output A
28
Disable time
Enable time
ns
ns
111
113
11
From input OE
to output B
From input OE
to output A
12
12
86
86
12
52
52
155
155
From input OE
to output B
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
6
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
4
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
4
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
6
5
5
4
Propagation
delay
tpd
tdis
ten
ns
6
5
4
4
From input B
to output A
6
5
5
4
25
28
31
34
11
12
14
14
25
28
28
31
11
12
11
12
25
28
25
28
11
12
9
25
28
23
25
11
12
7
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
From input OE
to output B
9
8
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6.13 Switching Characteristics, VCCA = 3.3 V
See 图7-1 and 图7-2 for test circuit and loading conditions. See 图7-3 and 图7-4 for measurement waveforms.
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
0.7 V ± 0.05 V
0.8 V ± 0.04 V 0.9 V ± 0.045 V
1.2 V ± 0.1 V
MAX
UNIT
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
81
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
40
40
35
35
22
24
84
86
9
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
22
22
17
17
22
24
75
78
9
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
7
8
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
81
Propagation
delay
tpd
tdis
ten
ns
142
142
22
From input B
to output A
22
24
80
83
9
From input OE
to output A
24
Disable time
Enable time
ns
ns
111
113
9
From input OE
to output B
From input OE
to output A
10
10
86
86
10
51
51
10
20
20
154
154
From input OE
to output B
B-PORT SUPPLY VOLTAGE (VCCB
)
PARAMETER
TEST CONDITIONS
1.5 V ± 0.1 V
1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
UNIT
MIN
MAX
5
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
4
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
4
MIN
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
From input A
to output B
5
4
4
4
Propagation
delay
tpd
tdis
ten
ns
5
5
4
4
From input B
to output A
6
5
4
4
22
24
30
33
9
22
24
27
30
9
22
24
25
27
9
22
24
23
25
9
From input OE
to output A
Disable time
Enable time
ns
ns
From input OE
to output B
From input OE
to output A
10
13
14
10
10
11
10
8
10
7
From input OE
to output B
8
7
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6.14 Operating Characteristics: TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA = VCCB = 0.7 V
MIN
TYP MAX
1.2
UNIT
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
1.8
1.8
Power dissipation
CL = 0, RL = Open
1.7
CpdA capacitance per transceiver
f = 1 MHz, tr = tf = 1 ns
(A to B: outputs enabled)
pF
1.7
1.7
2
2.5
1.1
1.8
1.8
Power dissipation
CL = 0, RL = Open
1.7
CpdA capacitance per transceiver
f = 1 MHz, tr = tf = 1 ns
pF
pF
pF
1.7
(A to B: outputs disabled)
1.7
2
2.1
9.3
11.8
11.8
12
Power dissipation
CL = 0, RL = Open
CpdA capacitance per transceiver
f = 1 MHz, tr = tf = 1 ns
(B to A: outputs enabled)
12.2
13
16.4
18.1
2.6
1.2
1.1
Power dissipation
CL = 0, RL = Open
1.2
CpdA capacitance per transceiver
f = 1 MHz, tr = tf = 1 ns
1.2
(B to A: outputs disabled)
1.3
1.6
3.9
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6.14 Operating Characteristics: TA = 25°C (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VCCA = VCCB = 0.7 V
9.3
11.7
11.8
11.9
12.2
12.9
16.3
18
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
VCCA = VCCB = 0.7 V
VCCA = VCCB = 0.8 V
VCCA = VCCB = 0.9 V
VCCA = VCCB = 1.2 V
VCCA = VCCB = 1.5 V
VCCA = VCCB = 1.8 V
VCCA = VCCB = 2.5 V
VCCA = VCCB = 3.3 V
Power dissipation
CpdB capacitance per transceiver
(A to B: outputs enabled)
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
pF
2.6
11.7
11.8
11.9
12.2
12.9
16.3
3.9
Power dissipation
CpdB capacitance per transceiver
(A to B: outputs disabled)
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
pF
pF
pF
1.2
1.8
1.8
Power dissipation
CpdB capacitance per transceiver
(B to A: outputs enabled)
1.7
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
1.7
1.7
2
2.5
1.1
1.8
1.8
Power dissipation
CpdB capacitance per transceiver
(B to A: outputs disabled)
1.7
CL = 0, RL = Open
f = 1 MHz, tr = tf = 1 ns
1.7
1.7
2
2.1
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6.15 Typical Characteristics
3.4
3.2
3
1.25
1.2
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
1.15
1.1
1.05
1
2.8
2.6
2.4
2.2
2
0.95
0.9
0.85
0.8
0.75
0.7
1.8
1.6
1.4
0.65
0.6
VCC = 0.7V
VCC = 1.2V
0.55
0
0.5
1
1.5
2
2.5
IOH (mA)
3
3.5
4
4.5
5
0
2
4
6
8
10
IOH (mA)
12
14
16
18
20
D001
D001
图6-2. Typical (TA=25°C) Output High Voltage (VOH
)
图6-1. Typical (TA=25°C) Output High Voltage (VOH
vs Source Current (IOH
)
vs Source Current (IOH
)
)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
220
200
180
160
140
120
100
80
60
40
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
VCC = 0.7V
VCC = 1.2V
20
0
-50
0
0
2
4
6
8
10
IOL (mA)
12
14
16
18
20
0
0.5
1
1.5
2
2.5
IOL (mA)
3
3.5
4
4.5
5
D001
D001
图6-3. Typical (TA=25°C) Output High Voltage (VOL) 图6-4. Typical (TA=25°C) Output High Voltage (VOL
)
vs Sink Current (IOL
)
vs Sink Current (IOL)
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7 Parameter Measurement Information
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f =1 MHz
• Z0 = 50 Ω
• dv / dt ≤1 ns/V
Measurement Point
2 X VCCO
Open
GND
S1
RL
Output Pin
Under Test
(1)
CL
RL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
VCCO
RL
CL
VTP
Parameter
S1
Open
1.1 V - 3.6 V
2 kꢀ 15 pF
N/A
N/A
tpd
Open
0.65 V - 0.95 V 20 kꢀ 15 pF
3 V - 3.6 V 2 kꢀ 15 pF
1.65 V - 2.7 V 2 kꢀ 15 pF
1.1 V - 1.6 V
0.65 V - 0.95 V 20 kꢀ 15 pF
3 V - 3.6 V 2 kꢀ 15 pF
1.65V - 2.7 V 2 kꢀ 15 pF
1.1 V - 1.6 V 2 kꢀ 15 pF
0.65 V - 0.95 V 20 kꢀ 15 pF
2 X VCCO
2 X VCCO
0.3 V
0.15 V
0.1 V
0.1 V
(1)
ten(1), tdis
2 kꢀ 15 pF 2 X VCCO
2 X VCCO
GND
0.3 V
GND
0.15 V
(2)
ten(2), tdis
GND
GND
0.1 V
0.1 V
A. Output waveform on the conditions that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
图7-2. Load Circuit Conditions
(1)
VCCI
VCCI / 2
VCCI / 2
An, Bn Input
GND
tpd
tpd
(2)
VOH
VCCO / 2
VCCO / 2
Bn, An Output
(2)
VOL
A. VCCI is the supply pin associated with the input port.
B. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
图7-3. Propagation Delay
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VCCA
OE
VCCA / 2
VCCA / 2
GND
tdis
ten
(3)
VCCO
Output(1)
VCCO / 2
VOL + VTP
(4)
VOL
(4)
VOH
VOH - VTP
Output(2)
VCCO / 2
GND
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
图7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74AXC8T245-Q1 device is an 8-bit, dual-supply non-inverting transceiver with bidirectional voltage level
translation. The I/O pins labeled with A and the control pins (DIR1, DIR2, and OE) are supported by VCCA, and
the I/O pins labeled with B are supported by VCCB. The A port and the B port are able to accept I/O voltages
ranging from 0.65 V to 3.6 V.
8.2 Functional Block Diagram
OE
VCCA
Control Block To Enable or
Disable Outputs (Note: Inputs
on each buffer are always
enabled)
DIR1
VCCB
DIR2
GND
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
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8.3 Feature Description
8.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V
Both supply pins are configured from 0.65 V to 3.6 V, which makes the device suitable for translating between
any of the low voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Multiple Direction Control Pins
Two control pins are used to configure the 8 data I/Os. I/O channels 1 through 4 are grouped together and I/O
channels 5 through 8 are banked together. The benefit of this is to permit simultaneous up-translation and down-
translation within one device. This eliminates the need for multiple devices, where each device can only provide
up-translation or down-translation sequentially. Simultaneous up and down translation is supported when both
VCCA and VCCB are at least 1.40 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
This feature is to limit the leakage current of an I/O pin being driven to a voltage as large as 3.6 V while having
its corresponding power supply rail powered down. This is represented by the Ioff parameter in the Electrical
Characteristics table.
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8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
图8-1. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with
automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area
for solder adhesion which assists in reliably creating a side fillet as shown in 图 8-1. Please see the mechanical
drawing for additional details.
8.4 Device Functional Modes
All control inputs are referenced to VCCA and must be driven to a valid Logic High or Logic Low (that is, not
floating) to assure proper device operation and to prevent excessive power consumption. 表8-1 summarizes the
possible modes of device operation based on the configuration of the control inputs.
表8-1. Function Table
CONTROL INPUTS(1)
Signal Direction
OE
H
L
DIR1
DIR2
Bits 1:4
Bits 5:8
Disabled (Hi-Z)
B to A
X
L
X
L
L
L
H
L
B to A
A to B
B to A
L
H
H
A to B
L
H
A to B
(1) Input circuits of the data I/Os are always active and must be driven to a valid logic level.
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The AEC-Q100 qualified SN74AXC8T245-Q1 device can be used in level-translation applications for interfacing
devices or systems operating at different voltage nodes. Figure 9-1 depicts an application in which the
SN74AXC8T245-Q1 device is up-translating a 0.7 V input to a 3.3 V output to interface between a system
controller and a peripheral device.
9.2 Typical Application
0.7 V
3.3 V
0.1 µF
0.1 µF
10
kΩ
10
kΩ
VCCA
VCCB
OE
DIR1
DIR2
GND
10
kΩ
Controller
SN74AXC8T245-Q1
Peripheral
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
图9-1. Typical Application Schematic
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9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
0.65 V to 3.6 V
0.65 V to 3.6 V
Input voltage range
Output voltage range
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXC8T245-Q1 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXC8T245-Q1 device is driving to determine the output
voltage range.
9.2.3 Application Curve
图9-2. Translation Up (0.7 V to 3.3 V) at 2.5 MHz
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. There are no additional requirements for power supply
sequencing.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Power Sequencing for AXC Family of Devices application report.
11 Layout
11.1 Layout Guidelines
To assure reliability of the device, follow common printed-circuit board layout guidelines.
• Use bypass capacitors on power supplies.
• Use short trace lengths to avoid excessive loading.
• Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
Bypass Capacitor
VCCA
Bypass
Capacitor
1
2
VCCA
DIR1
A1
24
23
22
21
20
19
18
17
16
15
14
13
VCCB
VCCB
OE
B1
From Source
From Source
From Source
From Source
From Source
From Source
From Source
From Source
3
To Destination
4
A2
To Destination
To Destination
5
A3
B2
6
A4
B3
SN74AXC8T245-Q1
(PW Package)
To Destination
To Destination
7
A5
B4
8
A6
B5
To Destination
To Destination
9
A7
B6
10
11
12
A8
B7
To Destination
DIR2
GND
B8
GND
图11-1. SN74AXC8T245-Q1 Device Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, SN74AXC8245-Q1 Evaluation Module user's guide
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Power Sequencing for AXC Family of Devices application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CAXC8T245QRHLRQ1
CAXC8T245QWRGYRQ1
SN74AXC8T245QPWRQ1
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
RHL
RGY
PW
24
24
24
1000 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AX8T245Q
NIPDAU
NIPDAU
AX8T245Q
AX8T245Q
TSSOP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AXC8T245-Q1 :
Catalog : SN74AXC8T245
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CAXC8T245QRHLRQ1
VQFN
RHL
RGY
PW
24
24
24
1000
3000
2000
330.0
330.0
330.0
12.4
12.4
16.4
3.8
3.8
5.8
5.8
8.3
1.2
1.2
1.6
8.0
8.0
8.0
12.0
12.0
16.0
Q1
Q1
Q1
CAXC8T245QWRGYRQ1 VQFN
SN74AXC8T245QPWRQ1 TSSOP
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CAXC8T245QRHLRQ1
CAXC8T245QWRGYRQ1
SN74AXC8T245QPWRQ1
VQFN
VQFN
RHL
RGY
PW
24
24
24
1000
3000
2000
367.0
367.0
356.0
367.0
367.0
356.0
35.0
35.0
35.0
TSSOP
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGY 24
5.5 x 3.5 mm, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4203539-5/J
PACKAGE OUTLINE
VQFN - 1 mm max height
RGY0024E
PLASTIC QUAD FLATPACK-NO LEAD
A
3.6
3.4
B
0.1 MIN
PIN 1 INDEX AREA
5.6
5.4
(0.13)
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.1±0.1
2X 1.5
(0.2) TYP
12
13
18X 0.5
11
14
(0.16)
A
A
SYMM
25
2X
4.1±0.1
4.5
EXPOSED
THERMAL PAD
23
2
0.3
24X
0.2
24
1
PIN 1 ID
(OPTIONAL)
SYMM
24X
0.1
C A B
0.05
C
0.5
0.3
4225182/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGY0024E
PLASTIC QUAD FLATPACK-NO LEAD
(3.3)
(2.1)
2X (1.5)
24X (0.6)
24X (0.25)
1
24
2
23
18X (0.5)
(Ø0.2) VIA
TYP
SYMM
2X
25
(4.1)
(5.3)
(4.5)
(0.68)
(1.12)
11
14
(R0.05) TYP
13
12
(0.8)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225182/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGY0024E
PLASTIC QUAD FLATPACK-NO LEAD
(3.3)
2X (1.5)
24X (0.6)
24X (0.25)
1
24
2
23
25
18X (0.5)
METAL
TYP
SYMM
2X
(5.3)
(4.5)
(1.36)
6X (1.16)
(R0.05) TYP
11
14
13
12
6X (0.94)
(0.57)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
76% PRINTED COVERAGE BY AREA
SCALE: 15X
4225182/A 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
A
3.6
3.4
B
PIN 1 INDEX AREA
5.6
5.4
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.05±0.1
2X 1.5
SYMM
0.5
0.3
24X
(0.1) TYP
13
12
18X 0.5
11
14
21
SYMM
2X
4.05±0.1
4.5
23
2
0.30
24X
0.18
0.1
0.05
24
1
PIN 1 ID
(OPTIONAL)
C A B
C
4X (0.2)
2X (0.55)
4225250/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
1
24
24X (0.6)
24X (0.24)
2X (0.4)
23
2
18X (0.5)
2X (1.105)
6X (0.67)
(4.05)
25
SYMM
4.6
4.4
(5.3)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
(Ø 0.2) VIA
TYP
(R0.05) TYP
11
14
13
12
4X
(0.775)
4X (0.2)
2X (0.55)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225250/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RHL0024A
PLASTIC QUAD FLATPACK- NO LEAD
(3.3)
(2.05)
2X (1.5)
SYMM
SOLDER MASK EDGE
TYP
1
24
24X (0.6)
24X (0.24)
23
2
18X (0.5)
25
SYMM
4.6
4.4
(5.3)
4X
(1.34)
METAL TYP
(R0.05) TYP
11
14
13
12
2X (0.84)
6X (0.56)
4X (0.2)
2X (0.55)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 18X
4225250/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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