CC1101EMK868-915_技术文档

CC1101

Low-Cost Low-Power Sub-1GHz RF Transceiver

(Enhanced CC1100 )

Applications

• Ultra low-power wireless applications

operating in the 315/433/868/915 MHz

ISM/SRD bands

• Wireless alarm and security systems

• Industrial monitoring and control

• Wireless sensor networks

• AMR – Automatic Meter Reading

• Home and building automation

Product Description

The RF transceiver is integrated with a highly

configurable baseband modem. The modem

supports various modulation formats and has

a configurable data rate up to 500 kBaud.

The CC1101

is a low-cost sub- 1 GHz

transceiver designed for very low-power

wireless applications. The circuit is mainly

intended for the ISM (Industrial, Scientific and

Medical) and SRD (Short Range Device)

frequency bands at 315, 433, 868, and 915

MHz, but can easily be programmed for

operation at other frequencies in the 300-348

MHz, 387-464 MHz and 779-928 MHz bands.

CC1101 provides extensive hardware support

for packet handling, data buffering, burst

transmissions, clear channel assessment, link

quality indication, and wake-on-radio.

The main operating parameters and the 64-

byte transmit/receive FIFOs of CC1101 can be

controlled via an SPI interface. In a typical

system, the CC1101 will be used together with a

microcontroller and a few additional passive

components.

CC1101 is an improved and code compatible

version of the CC1100 RF transceiver. The

main improvements on the CC1101 include:

•

Improved spurious response

Better close-in phase noise improving

Adjacent Channel Power (ACP)

performance

•

Higher input saturation level

1

2

3

4

5

15

14

13

12

11

CC1101

Improved output power ramping

Extended frequency bands of

operation, i.e.

CC1100: 400-464 MHz and 800-928

MHz

CC1101: 387-464 MHz and 779-928

MHz

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Page 1 of 93

CC1101

Key Features

•

Programmable Preamble Quality Indicator

(PQI) for improved protection against false

sync word detection in random noise

Support for automatic Clear Channel

Assessment (CCA) before transmitting (for

listen-before-talk systems)

Support for per-package Link Quality

Indication (LQI)

Optional automatic whitening and de-

whitening of data

RF Performance

•

High sensitivity (–111 dBm at 1.2 kBaud,

868 MHz, 1% packet error rate)

Low current consumption (14.7 mA in RX,

1.2 kBaud, 868 MHz)

Programmable output power up to +10

dBm for all supported frequencies

Excellent receiver selectivity and blocking

performance

Programmable data rate from 1.2 to 500

kBaud

Frequency bands: 300-348 MHz, 387-464

MHz and 779-928 MHz

•

Low-Power Features

•

400 nA sleep mode current consumption

Fast startup time: 240us from sleep to RX

or TX mode (measured on EM reference

design [5] and [6])

Analog Features

•

Wake-on-radio functionality for automatic

low-power RX polling

Separate 64-byte RX and TX data FIFOs

(enables burst mode data transmission)

•

2-FSK, GFSK, and MSK supported as well

as OOK and flexible ASK shaping

Suitable for frequency hopping systems

•

due to

synthesizer: 90us settling time

Automatic Frequency Compensation

a

fast settling frequency

General

•

(AFC) can be used to align the frequency

synthesizer to the received center

frequency

•

Few external components: Completely on-

chip frequency synthesizer, no external

filters or RF switch needed

Green package: RoHS compliant and no

antimony or bromine

Small size (QLP 4x4 mm package, 20

pins)

Suited for systems targeting compliance

with EN 300 220 (Europe) and FCC CFR

Part 15 (US).

Integrated analog temperature sensor

•

Digital Features

•

Flexible support for packet oriented

systems: On-chip support for sync word

detection, address check, flexible packet

length, and automatic CRC handling

Efficient SPI interface: All registers can be

programmed with one “burst” transfer

Digital RSSI output

Programmable channel filter bandwidth

Programmable Carrier Sense (CS)

indicator

•

Support

for

asynchronous

and

•

synchronous serial receive/transmit mode

for backwards compatibility with existing

radio communication protocols

•

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Page 2 of 93

CC1101

Abbreviations

Abbreviations used in this data sheet are described below.

ACP

ADC

AFC

Adjacent Channel Power

MSK

N/A

Minimum Shift Keying

Not Applicable

Analog to Digital Converter

Automatic Frequency Compensation

NRZ

Non Return to Zero (Coding)

AGC

AMR

ASK

Automatic Gain Control

Automatic Meter Reading

Amplitude Shift Keying

OOK

PA

PCB

On-Off Keying

Power Amplifier

Printed Circuit Board

BER

BT

Bit Error Rate

PD

Power Down

Bandwidth-Time product

Clear Channel Assessment

Code of Federal Regulations

Cyclic Redundancy Check

Carrier Sense

PER

PLL

Packet Error Rate

CCA

CFR

CRC

CS

Phase Locked Loop

Power-On Reset

POR

PQI

Preamble Quality Indicator

Preamble Quality Threshold

PQT

PTAT

QLP

QPSK

RC

CW

Continuous Wave (Unmodulated Carrier)

Direct Current

Proportional To Absolute Temperature

Quad Leadless Package

Quadrature Phase Shift Keying

Resistor-Capacitor

DC

DVGA

ESR

FCC

FEC

FIFO

FHSS

2-FSK

GFSK

IF

Digital Variable Gain Amplifier

Equivalent Series Resistance

Federal Communications Commission

Forward Error Correction

First-In-First-Out

RF

Radio Frequency

RSSI

RX

Received Signal Strength Indicator

Receive, Receive Mode

Surface Aqustic Wave

Surface Mount Device

Signal to Noise Ratio

Frequency Hopping Spread Spectrum

Binary Frequency Shift Keying

Gaussian shaped Frequency Shift Keying

Intermediate Frequency

In-Phase/Quadrature

SAW

SMD

SNR

SPI

Serial Peripheral Interface

Short Range Devices

To Be Defined

I/Q

SRD

TBD

T/R

ISM

LC

Industrial, Scientific, Medical

Inductor-Capacitor

Transmit/Receive

LNA

LO

Low Noise Amplifier

TX

Transmit, Transmit Mode

Ultra High frequency

Local Oscillator

UHF

VCO

WOR

XOSC

XTAL

LSB

LQI

Least Significant Bit

Voltage Controlled Oscillator

Wake on Radio, Low power polling

Crystal Oscillator

Link Quality Indicator

MCU

MSB

Microcontroller Unit

Most Significant Bit

Crystal

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Page 3 of 93

CC1101

Table Of Contents

APPLICATIONS..................................................................................................................................................1

PRODUCT DESCRIPTION................................................................................................................................1

KEY FEATURES .................................................................................................................................................2

RF PERFORMANCE ..........................................................................................................................................2

ANALOG FEATURES ........................................................................................................................................2

DIGITAL FEATURES.........................................................................................................................................2

LOW-POWER FEATURES................................................................................................................................2

GENERAL ............................................................................................................................................................2

ABBREVIATIONS...............................................................................................................................................3

TABLE OF CONTENTS .....................................................................................................................................4

1

2

3

ABSOLUTE MAXIMUM RATINGS.....................................................................................................7

OPERATING CONDITIONS .................................................................................................................7

GENERAL CHARACTERISTICS.........................................................................................................7

ELECTRICAL SPECIFICATIONS.......................................................................................................8

4

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

C

URRENT

RF RECEIVE

RF TRANSMIT

RYSTAL

OW

REQUENCY

NALOG EMPERATURE S

C

ONSUMPTION ............................................................................................................................8

ECTION................................................................................................................................10

ECTION .............................................................................................................................12

SCILLATOR..............................................................................................................................13

OWER RC OSCILLATOR...................................................................................................................14

HARACTERISTICS..........................................................................................14

ENSOR ..............................................................................................................15

DC CHARACTERISTICS ..............................................................................................................................15

ESET .....................................................................................................................................15

S

C

L

F

A

O

P

SYNTHESIZER C

T

P

OWER-ON R

5

6

7

8

9

PIN CONFIGURATION........................................................................................................................16

CIRCUIT DESCRIPTION ....................................................................................................................17

APPLICATION CIRCUIT....................................................................................................................18

CONFIGURATION OVERVIEW........................................................................................................21

CONFIGURATION SOFTWARE........................................................................................................23

4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ..................................................23

10

10.1

10.2

C

HIP

S

TATUS

B

YTE ...................................................................................................................................25

REGISTER

A

CCESS .....................................................................................................................................25

10.3 SPI READ ..................................................................................................................................................26

10.4 TROBES .................................................................................................................................26

COMMAND S

10.5 FIFO ACCESS ............................................................................................................................................26

10.6 PATABLE ACCESS...................................................................................................................................27

11

MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ..........................................27

NTERFACE.....................................................................................................................27

INS .....................................................................................................27

EATURE ......................................................................................................28

11.1

11.2

11.3

C

G

O

ONFIGURATION

ENERAL ONTROL AND

PTIONAL ADIO ONTROL

I

C

R

STATUS P

C

F

12

13

DATA RATE PROGRAMMING..........................................................................................................28

RECEIVER CHANNEL FILTER BANDWIDTH ..............................................................................29

DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION..................................29

14

14.1

14.2

14.3

F

B

REQUENCY

O

FFSET

C

OMPENSATION........................................................................................................29

YNCHRONIZATION.............................................................................................................................29

YNCHRONIZATION..........................................................................................................................30

IT

S

YTE

S

15

PACKET HANDLING HARDWARE SUPPORT ..............................................................................30

DATA WHITENING.....................................................................................................................................31

15.1

15.2

15.3

P

ACKET

F

ORMAT.......................................................................................................................................31

ODE......................................................................................................33

ACKET

ILTERING IN

RECEIVE M

SWRS061B

Page 4 of 93

CC1101

15.4

15.5

15.6

P

ACKET

H

ANDLING IN

T

R

RANSMIT

ECEIVE

M

ODE...................................................................................................33

M

ODE .....................................................................................................34

F

IRMWARE.............................................................................................................34

16

MODULATION FORMATS.................................................................................................................35

EYING.......................................................................................................................35

EYING...........................................................................................................................35

ODULATION ........................................................................................................................35

RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ............................36

16.1

16.2

16.3

F

M

A

REQUENCY

INIMUM HIFT

MPLITUDE

SHIFT K

S

K

M

17

17.1

17.2

S

P

YNC

W

ORD

Q

UALIFIER............................................................................................................................36

REAMBLE

Q

UALITY THRESHOLD (PQT)..................................................................................................36

17.3 RSSI..........................................................................................................................................................36

17.4

17.5

17.6

C

L

ARRIER

LEAR

INK

S

ENSE (CS).................................................................................................................................38

SSESSMENT (CCA) .....................................................................................................39

NDICATOR (LQI)..............................................................................................................39

FORWARD ERROR CORRECTION WITH INTERLEAVING .....................................................39

ORRECTION (FEC)......................................................................................................39

NTERLEAVING ..........................................................................................................................................40

RADIO CONTROL................................................................................................................................41

C

HANNEL

A

Q

UALITY

I

18

18.1

18.2

FORWARD ERROR C

I

19

19.1

19.2

19.3

19.4

19.5

19.6

P

C

V

A

W

OWER-O

RYSTAL

OLTAGE

CTIVE

AKE

N

S

TART-U

P

S

EQUENCE.............................................................................................................41

ONTROL...................................................................................................................................42

ONTROL..............................................................................................................43

ODES .........................................................................................................................................43

ADIO (WOR)..........................................................................................................................43

IMING ......................................................................................................................................................44

IMER ..........................................................................................................................45

C

REGULATOR C

M

O

N

R

T

19.7 RX TERMINATION

T

20

21

22

DATA FIFO ............................................................................................................................................45

FREQUENCY PROGRAMMING........................................................................................................47

VCO .........................................................................................................................................................47

22.1 VCO AND PLL SELF-CALIBRATION ..........................................................................................................47

23

24

25

26

VOLTAGE REGULATORS .................................................................................................................48

OUTPUT POWER PROGRAMMING ................................................................................................48

SHAPING AND PA RAMPING............................................................................................................49

SELECTIVITY.......................................................................................................................................51

CRYSTAL OSCILLATOR....................................................................................................................52

27

27.1

REFERENCE SIGNAL ..................................................................................................................................53

28

29

30

EXTERNAL RF MATCH .....................................................................................................................53

PCB LAYOUT RECOMMENDATIONS.............................................................................................53

GENERAL PURPOSE / TEST OUTPUT CONTROL PINS.............................................................54

ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION..............................................56

31

31.1

31.2

A

SYNCHRONOUS

O

PERATION ....................................................................................................................56

PERATION ..........................................................................................................56

SYSTEM CONSIDERATIONS AND GUIDELINES.........................................................................56

S

YNCHRONOUS SERIAL O

32

32.1 SRD REGULATIONS...................................................................................................................................56

32.2

32.3

32.4

32.5

32.6

32.7

32.8

32.9

32.10

F

W

D

C

S

L

B

REQUENCY

IDEBAND

ATA URST

ONTINUOUS

RYSTAL RIFT

FFICIENT

H

OPPING AND

M

ULTI-CHANNEL

S

YSTEMS............................................................................57

PECTRUM........................................................................57

RANSMISSIONS...................................................................................................................57

RANSMISSIONS ..................................................................................................................58

OMPENSATION ..............................................................................................................58

ODULATION.........................................................................................................58

YSTEMS .................................................................................................................................58

YSTEMS .................................................................................................................58

OWER ................................................................................................................58

M

ODULATION NOT USING

S

PREAD S

B

T

D

C

PECTRUM

OW OST

ATTERY

NCREASING

E

M

C

S

O

PERATED

S

I

O

UTPUT P

SWRS061B

Page 5 of 93

CC1101

33

CONFIGURATION REGISTERS........................................................................................................59

33.1

33.2

33.3

C

ONFIGURATION

R

EGISTER

D

ETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE...............63

ETAILS – REGISTERS THAT OOSE ROGRAMMING IN SLEEP STATE .........83

CONFIGURATION

REGISTER

L

P

S

TATUS

REGISTER

D

ETAILS.......................................................................................................................84

PACKAGE DESCRIPTION (QLP 20).................................................................................................87

ACKAGE (QLP 20) ...........................................................................88

ROPERTIES ..............................................................................................................88

NFORMATION ........................................................................................................................88

34

34.1

34.2

34.3

34.4

34.5

RECOMMENDED PCB LAYOUT FOR P

P

S

ACKAGE

T

HERMAL P

OLDERING

I

T

RAY

S

PECIFICATION ................................................................................................................................88

PECIFICATION.................................................................................................89

CARRIER

TAPE AND REEL S

35

36

ORDERING INFORMATION..............................................................................................................89

REFERENCES .......................................................................................................................................90

GENERAL INFORMATION................................................................................................................91

37

37.1

37.2

D

OCUMENT

H

ISTORY ................................................................................................................................91

EFINITIONS ................................................................................................................91

P

RODUCT TATUS D

S

38

39

ADDRESS INFORMATION.................................................................................................................92

TI WORLDWIDE TECHNICAL SUPPORT......................................................................................92

SWRS061B

Page 6 of 93

CC1101

1

Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress

exceeding one or more of the limiting values may cause permanent damage to the device.

Caution!

ESD

sensitive

device.

Precaution should be used when handling

the device in order to prevent permanent

damage.

Parameter

Min

Max

3.9

Units

Condition

Supply voltage

–0.3

V

All supply pins must have the same voltage

Voltage on any digital pin

–0.3

VDD + 0.3

max 3.9

2.0

Voltage on the pins RF_P, RF_N,

and DCOUPL

–0.3

V

Voltage ramp-up rate

Input RF level

120

+10

150

260

750

kV/µs

dBm

°C

Storage temperature range

Solder reflow temperature

ESD

–50

According to IPC/JEDEC J-STD-020C

°C

V

According to JEDEC STD 22, method A114,

Human Body Model (HBM)

ESD

400

V

According to JEDEC STD 22, C101C,

Charged Device Model (CDM)

Table 1: Absolute Maximum Ratings

2

Operating Conditions

The operating conditions for CC1101 are listed Table 2 in below.

Parameter

Min

-40

1.8

Max

85

Unit

°C

Condition

Operating temperature

Operating supply voltage

3.6

V

All supply pins must have the same voltage

Table 2: Operating Conditions

3

General Characteristics

Parameter

Min

300

387

779

1.2

26

Typ

Max

348

464

928

500

250

500

Unit

MHz

Condition/Note

Frequency range

MHz

Data rate

kBaud

2-FSK

GFSK, OOK, and ASK

(Shaped) MSK (also known as differential offset

QPSK)

Optional Manchester encoding (the data rate in kbps

will be half the baud rate)

Table 3: General Characteristics

SWRS061B

Page 7 of 93

CC1101

4

Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs

([5] and [6]).

Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a

reduction in sensitivity. See

for additional details on current consumption and sensitivity.

Parameter

Min Typ Max Unit Condition

Current consumption in power

down modes

0.2

1

Voltage regulator to digital part off, register values retained

(SLEEP state). All GDO pins programmed to 0x2F (HW to 0)

µA

0.5

Voltage regulator to digital part off, register values retained, low-

power RC oscillator running (SLEEP state with WOR enabled

100

165

9.8

Voltage regulator to digital part off, register values retained,

XOSC running (SLEEP state with MCSM0.OSC_FORCE_ONset)

Voltage regulator to digital part on, all other modules in power

down (XOFF state)

Current consumption

Automatic RX polling once each second, using low-power RC

oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate,

PLL calibration every 4^thwakeup. Average current with signal in

channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).

34.2

1.5

Same as above, but with signal in channel above carrier sense

level, 1.95 ms RX timeout, and no preamble/sync word found.

µA

Automatic RX polling every 15^thsecond, using low-power RC

oscillator, with 460kHz filter bandwidth and 250 kBaud data rate,

PLL calibration every 4^thwakeup. Average current with signal in

channel below carrier sense level (MCSM2.RX_TIME_RSSI=1).

39.3

1.7

Same as above, but with signal in channel above carrier sense

level, 29.3 ms RX timeout, and no preamble/sync word found.

µA

mA Only voltage regulator to digital part and crystal oscillator running

(IDLE state)

8.4

mA Only the frequency synthesizer is running (FSTXON state). This

currents consumption is also representative for the other

intermediate states when going from IDLE to RX or TX, including

the calibration state.

Current consumption,

315MHz

15.4

14.4

15.2

14.3

16.5

15.1

mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity

limit

mA Receive mode, 1.2 kBaud, reduced current, input well above

sensitivity limit

mA Receive mode, 38.4 kBaud, reduced current, input at sensitivity

limit

mA Receive mode,38.4 kBaud, reduced current, input well above

sensitivity limit

mA Receive mode, 250 kBaud, reduced current, input at sensitivity

limit

mA Receive mode, 250 kBaud, reduced current, input well above

sensitivity limit

27.4

15.0

12.3

mA Transmit mode, +10 dBm output power

mA Transmit mode, 0 dBm output power

mA Transmit mode, –6 dBm output power

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Page 8 of 93

CC1101

Parameter

Min Typ Max Unit Condition

Current consumption,

433MHz

16.0

15.0

15.7

15.0

17.1

15.7

mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity

limit

mA Receive mode, 1.2 kBaud, reduced current, input well above

sensitivity limit

mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity

limit

mA Receive mode, 38.4 kBaud , reduced current, input well above

sensitivity limit

mA Receive mode, 250 kBaud, reduced current, input at sensitivity

limit

mA Receive mode, 250 kBaud, reduced current, input well above

sensitivity limit

29.2

16.0

13.1

15.7

mA Transmit mode, +10 dBm output power

mA Transmit mode, 0 dBm output power

mA Transmit mode, –6 dBm output power

Current consumption,

868/915MHz

mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity

limit

14.7

15.6

14.6

16.9

15.6

mA Receive mode, 1.2 kBaud , reduced current, input well above

sensitivity limit

mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity

limit

mA Receive mode, 38.4 kBaud , reduced current, input well above

sensitivity limit

mA Receive mode, 250 kBaud , reduced current, input at sensitivity

limit

mA Receive mode, 250 kBaud , reduced current, input well above

sensitivity limit

32.3

16.8

13.1

mA Transmit mode, +10 dBm output power

mA Transmit mode, 0 dBm output power

mA Transmit mode, –6 dBm output power

Table 4: Electrical Specifications

SWRS061B

Page 9 of 93

CC1101

4.2 RF Receive Section

Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs

([5] and [6]).

Parameter

Min

Typ

Max

Unit

Condition/Note

Digital channel filter

bandwidth

58

812

kHz

User programmable. The bandwidth limits are proportional to

crystal frequency (given values assume a 26.0 MHz crystal).

315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

-111

dBm

Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 17.2 mA to 15.4 mA at

sensitivity limit. The sensitivity is typically reduced to -109 dBm

315 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1

cannot be used for data rates > 250 kBaud)

(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

-88

dBm

433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth

Receiver sensitivity

-112

dBm

Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 18.0 mA to 16.0 mA at

sensitivity limit. The sensitivity is typically reduced to -110 dBm

433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

–104

dBm

433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(MSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

-95

dBm

868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

–111

dBm

Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 18.0 mA to 15.7 mA at

sensitivity limit. The sensitivity is typically reduced to -109 dBm

FIFOTHR.CLOSE_IN_RX=0

Saturation

–14

37

dBm

dB

Adjacent channel

rejection

Desired channel 3 dB above the sensitivity limit. 100 kHz

channel spacing

Alternate channel

rejection

37

dB

Desired channel 3 dB above the sensitivity limit. 100 kHz

channel spacing

See Figure 24 for plot of selectivity versus frequency offset

IF frequency 152 kHz

Image channel

rejection,

868MHz

31

dB

Desired channel 3 dB above the sensitivity limit.

868 MHz, 38.4 kBaud data rate, sensitivity optimized

(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

Saturation

–103

–16

20

dBm

dB

Adjacent channel

rejection

Desired channel 3 dB above the sensitivity limit. 200 kHz

channel spacing

Alternate channel

rejection

30

dB

Desired channel 3 dB above the sensitivity limit. 200 kHz

channel spacing

See Figure 25 for plot of selectivity versus frequency offset

IF frequency 152 kHz

Image channel

rejection,

868MHz

23

dB

Desired channel 3 dB above the sensitivity limit.

SWRS061B

Page 10 of 93

CC1101

Parameter

Min

Typ

Max

Unit Condition/Note

868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

–94

dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 19.2 mA to 16.9 mA at

sensitivity limit. The sensitivity is typically reduced to -91 dBm

FIFOTHR.CLOSE_IN_RX=0

Saturation

–17

25

dBm

dB

Adjacent channel rejection

Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

Alternate channel

rejection

40

dB

Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

See Figure 26 for plot of selectivity versus frequency offset

Image channel rejection,

868MHz

17

dB

IF frequency 304 kHz

Desired channel 3 dB above the sensitivity limit.

915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

–111

dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 18.0 mA to 15.7 mA at

sensitivity limit. The sensitivity is typically reduced to -109

dBm

915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

–103

dBm

915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

–94

dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF=1. The typical current

consumption is then reduced from 19.2 mA to 16.9 mA at

sensitivity limit. The sensitivity is typically reduced to -91 dBm

915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1

cannot be used for data rates > 250 kBaud)

(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity

–87

dBm

Blocking

Blocking at ±2 MHz offset,

1.2 kBaud, 868 MHz

-50

-39

dBm Desired channel 3dB above the sensitivity limit.

dBm Desired channel 3dB above the sensitivity limit

dBm Desired channel 3dB above the sensitivity limit.

Blocking at ±2 MHz offset,

500 kBaud, 868 MHz

Blocking at ±10 MHz

offset, 1.2 kBaud, 868

MHz

Blocking at ±10 MHz

offset, 500 kBaud, 868

MHz

-40

dBm Desired channel 3dB above the sensitivity limit.

SWRS061B

Page 11 of 93

CC1101

Parameter

Min

Typ

Max

Unit

Condition/Note

General

Spurious emissions

-68

-66

–57

–47

dBm

25 MHz – 1 GHz

(Maximum figure is the ETSI EN 300 220 limit)

Above 1 GHz

(Maximum figure is the ETSI EN 300 220 limit)

Typical radiated spurious emission is -49 dB

measured at the VCO frequency.

RX latency

9

bit

Serial operation. Time from start of reception until

data is available on the receiver data output pin is

equal to 9 bit.

Table 5: RF Receive Section

4.3 RF Transmit Section

Tc = 25°C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1101EM reference

designs ([5] and [6]).

Parameter

Min

Typ

Max

Unit Condition/Note

Differential impedance as seen from the RF-port (RF_P and

Differential load

impedance

RF_N) towards the antenna. Follow the CC1101EM reference

design ([5] and [6]) available from theTI website.

315 MHz

122 + j31

116 + j41

86.5 + j43

+10

Ω

433 MHz

868/915 MHz

Output power,

highest setting

dBm Output power is programmable, and full range is available in all

frequency bands

(Output power may be restricted by regulatory limits. See also

Application Note AN039 [3].

Delivered to a 50Ω single-ended load via CC1101EM reference

design ([5] and [6]) RF matching network.

Output power,

lowest setting

-30

dBm Output power is programmable, and full range is available in all

frequency bands.

Delivered to a 50Ω single-ended load via CC1101EM reference

design([5] and [6]) RF matching network.

Harmonics,

radiated

Measured on CC1101EM reference designs([5] and [6]) with CW,

10dBm output power

2

^ndHarm, 433 MHz

3^rdHarm, 433 MHz

-49

-40

dBm The antennas used during the radiated measurements (SMAFF-

433 from R.W.Badland and Nearson S331 868/915) play a part in

attenuating the harmonics

2

3

^ndHarm, 868 MHz

^rdHarm, 868 MHz

-39

-64

Harmonics,

conducted

Measured with 10 dBm CW, TX frequency at 315.00 MHz,

433.00 MHz, 868.00 MHz, or 915.00 MHz

315 MHz

< -35

< -53

dBm Frequencies below 960 MHz

Frequencies above 960 MHz

433 MHz

< -43

< -45

Frequencies below 1 GHz

Frequencies above 1 GHz

868 MHz

915 MHz

< -39

< -33

SWRS061B

Page 12 of 93

CC1101

Parameter

Min

Typ

Max

Unit Condition/Note

Measured with 10 dBm CW, TX frequency at 315.00 MHz,

Spurious

emissions,

conducted

Harmonics not

included

433.00 MHz, 868.00 MHz or 915.00 MHz

< -58

< -53

dBm Frequencies below 960 MHz

Frequencies above 960 MHz

315 MHz

< -50

< -54

< -56

Frequencies below 1 GHz

Frequencies above 1 GHz

Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz

433 MHz

< -50

< -51

< -53

Frequencies below 1 GHz

Frequencies above 1 GHz

Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz.

868 MHz

All radiated spurious emissions are within the limits of ETSI. The

peak conducted spurious emission is -53 dBm at 699 MHz, which

is in a frequency band limited to -54 dBm by EN 300 220. An

alternative filter that can be used to reduce the emission at 699

MHz below -54 dBm, for conducted measurements, is shown in

Figure 4.

< -51

915 MHz

Frequencies below 960 MHz

Frequencies above 960 MHz

General

TX latency

8

bit

Serial operation. Time from sampling the data on the transmitter

data input pin until it is observed on the RF output ports.

Table 6: RF Transmit Section

4.4 Crystal Oscillator

Tc = 25°C @ VDD = 3.0 V if nothing else is stated.

Parameter

Min

Typ

26

Max

Unit Condition/Note

Crystal frequency

Tolerance

26

27

MHz

±40

ppm This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and

channel spacing / bandwidth.

ESR

100

Ω

Start-up time

150

µs

Measured on the CC1101EM reference designs ([5] and [6])

using crystal AT-41CD2 from NDK.

This parameter is to a large degree crystal dependent.

Table 7: Crystal Oscillator Parameters

SWRS061B

Page 13 of 93

CC1101

4.5 Low Power RC Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([5]

and [6]).

Parameter

Min

Typ

Max

Unit

kHz

Condition/Note

Calibrated frequency

34.7

36

Calibrated RC Oscillator frequency is XTAL

frequency divided by 750

Frequency accuracy after

calibration

±1

%

Temperature coefficient

Supply voltage coefficient

Initial calibration time

+0.5

+3

2

Frequency drift when temperature changes after

calibration

% / °C

% / V

ms

Frequency drift when supply voltage changes after

calibration

When the RC Oscillator is enabled, calibration is

continuously done in the background as long as

the crystal oscillator is running.

Table 8: RC Oscillator Parameters

4.6 Frequency Synthesizer Characteristics

Tc = 25°C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference

designs ([5] and [6]). Min figures are given using a 27 MHz crystal. Typ and max are given using a 26 MHz crystal.

Parameter

Min

397

Typ

Max

412

Unit

Hz

Condition/Note

Programmed frequency

resolution

F_XOSC

2¹⁶

/

26-27 MHz crystal.

The resolution (in Hz) is equal for all frequency

bands.

Synthesizer frequency

tolerance

±40

ppm

Given by crystal used. Required accuracy

(including temperature and aging) depends on

frequency band and channel bandwidth /

spacing.

RF carrier phase noise

PLL turn-on / hop time

–92

–98

dBc/Hz

µs

@ 50 kHz offset from carrier

@ 100 kHz offset from carrier

@ 200 kHz offset from carrier

@ 500 kHz offset from carrier

@ 1 MHz offset from carrier

@ 2 MHz offset from carrier

@ 5 MHz offset from carrier

@ 10 MHz offset from carrier

–107

–113

–119

–129

88.4

85.1

88.4

Time from leaving the IDLE state until arriving in

the RX, FSTXON or TX state, when not

performing calibration.

Crystal oscillator running.

PLL RX/TX settling time

PLL TX/RX settling time

PLL calibration time

9.3

20.7

694

9.6

21.5

721

9.6

21.5

721

Settling time for the 1·IF frequency step from RX

to TX

µs

Settling time for the 1·IF frequency step from TX

to RX

Calibration can be initiated manually or

automatically before entering or after leaving

RX/TX.

Table 9: Frequency Synthesizer Parameters

SWRS061B

Page 14 of 93

CC1101

4.7 Analog Temperature Sensor

The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10

below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature

sensor in the IDLE state.

Parameter

Min

Typ

Max

Unit

Condition/Note

0.651

0.747

0.847

0.945

2.45

0

V

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient

mV/°C Fitted from –20 °C to +80 °C

Error in calculated

temperature, calibrated

-2 ^*

2 ^*

°C

From –20 °C to +80 °C when using 2.45 mV / °C, after

1-point calibration at room temperature

^*The indicated minimum and maximum error with 1-

point calibration is based on simulated values for

typical process parameters

Current consumption

0.3

mA

increase when enabled

Table 10: Analog Temperature Sensor Parameters

4.8 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage

Logic "1" output voltage

Logic "0" input current

Logic "1" input current

Min

Max

0.7

Unit

V

Condition

0

VDD-0.7

0

VDD

0.5

V

For up to 4 mA output current

Input equals 0V

VDD-0.3

N/A

VDD

–50

50

V

nA

N/A

Input equals VDD

Table 11: DC Characteristics

4.9 Power-On Reset

When the power supply complies with the requirements in Table 12 below, proper Power-On-Reset

functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until

transmitting an SRESstrobe over the SPI interface. See Section 19.1 on page 41 for further details.

Parameter

Min Typ Max Unit Condition/Note

Power-up ramp-up time.

Power off time

5

ms

From 0V until reaching 1.8V

1

Minimum time between power-on and power-off

Table 12: Power-On Reset Requirements

SWRS061B

Page 15 of 93

CC1101

5

Pin Configuration

20 19 18 17 16

SCLK 1

SO (GDO1) 2

GDO2 3

15 AVDD

14 AVDD

13 RF_N

12 RF_P

11 AVDD

DVDD 4

DCOUPL 5

GND

Exposed die

attach pad

6

7

8

9 10

Figure 1: Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

Pin # Pin Name

Pin type

Description

1

2

SCLK

Digital Input

Digital Output

Serial configuration interface, clock input

Serial configuration interface, data output.

Optional general output pin when CSn is high

Digital output pin for general use:

SO (GDO1)

3

GDO2

Digital Output

•

Test signals

FIFO status signals

Clear Channel Indicator

Clock output, down-divided from XOSC

Serial output RX data

4

5

DVDD

Power (Digital)

1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

voltage regulator

DCOUPL

1.6 - 2.0 V digital power supply output for decoupling.

NOTE: This pin is intended for use with the CC1101 only. It can not be used

to provide supply voltage to other devices.

6

GDO0

Digital I/O

Digital output pin for general use:

(ATEST)

•

Test signals

FIFO status signals

Clear Channel Indicator

Clock output, down-divided from XOSC

Serial output RX data

Serial input TX data

Also used as analog test I/O for prototype/production testing

Serial configuration interface, chip select

7

8

9

CSn

Digital Input

Analog I/O

XOSC_Q1

AVDD

Crystal oscillator pin 1, or external clock input

1.8 - 3.6 V analog power supply connection

Power (Analog)

SWRS061B

Page 16 of 93

CC1101

Pin # Pin Name

Pin type

Description

10

11

12

XOSC_Q2

AVDD

Analog I/O

Power (Analog)

RF I/O

Crystal oscillator pin 2

1.8 -3.6 V analog power supply connection

Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

1.8 - 3.6 V analog power supply connection

Analog ground connection

RF_P

13

RF_N

RF I/O

14

15

16

17

18

19

20

AVDD

GND

Power (Analog)

Ground (Analog)

Analog I/O

RBIAS

DGUARD

GND

External bias resistor for reference current

Power supply connection for digital noise isolation

Ground connection for digital noise isolation

Serial configuration interface, data input

Power (Digital)

Ground (Digital)

Digital Input

SI

Table 13: Pinout Overview

6

Circuit Description

RADIO CONTROL

ADC

LNA

SCLK

ADC

SO (GDO1)

SI

RF_P

RF_N

FREQ

SYNTH

0

CSn

90

GDO0 (ATEST)

GDO2

PA

RC OSC

BIAS

XOSC

RBIAS

XOSC_Q1 XOSC_Q2

Figure 2: CC1101 Simplified Block Diagram

frequency synthesizer includes a completely

on-chip LC VCO and a 90 degree phase

shifter for generating the I and Q LO signals to

the down-conversion mixers in receive mode.

A simplified block diagram of CC1101 is shown

in Figure 2.

CC1101 features a low-IF receiver. The received

RF signal is amplified by the low-noise

amplifier (LNA) and down-converted in

quadrature (I and Q) to the intermediate

frequency (IF). At IF, the I/Q signals are

digitised by the ADCs. Automatic gain control

(AGC), fine channel filtering and demodulation

bit/packet synchronization are performed

digitally.

A crystal is to be connected to XOSC_Q1 and

XOSC_Q2. The crystal oscillator generates the

reference frequency for the synthesizer, as

well as clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for

configuration and data buffer access.

The digital baseband includes support for

channel configuration, packet handling, and

data buffering.

The transmitter part of CC1101 is based on

direct synthesis of the RF frequency. The

SWRS061B

Page 17 of 93

CC1101

7

Application Circuit

Only a few external components are required

for using the CC1101. The recommended

application circuits are shown in Figure 3 and

Figure 4. The external components are

described in Table 14, and typical values are

given in Table 15.

The balun and LC filter component values and

their placement are important to keep the

performance

optimized.

It

is

highly

recommended to follow the CC1101EM

reference design [5] and [6].

Crystal

Bias Resistor

The crystal oscillator uses an external crystal

with two loading capacitors (C81 and C101).

See Section 27 on page 52 for details.

The bias resistor R171 is used to set an

accurate bias current.

Additional Filtering

Balun and RF Matching

Additional external components (e.g. an RF

SAW filter) may be used in order to improve

the performance in specific applications.

The components between the RF_N/RF_P

pins and the point where the two signals are

joined together (C131, C121, L121 and L131

for the 315/433 MHz reference design [5].

L121, L131, C121, L122, C131, C122 and

L132 for the 868/915 MHz reference design

[6]) form a balun that converts the differential

RF signal on CC1101 to a single-ended RF

signal. C124 is needed for DC blocking.

Together with an appropriate LC network, the

balun components also transform the

impedance to match a 50 Ω antenna (or

cable). Suggested values for 315 MHz, 433

MHz, and 868/915 MHz are listed in Table 15.

Power Supply Decoupling

The power supply must be properly decoupled

close to the supply pins. Note that decoupling

capacitors are not shown in the application

circuit. The placement and the size of the

decoupling capacitors are very important to

achieve the optimum performance. The

CC1101EM reference design ([5] and [6])

should be followed closely.

Component

C51

Description

Decoupling capacitor for on-chip voltage regulator to digital part

Crystal loading capacitors, see Section 27 on page 52 for details

RF balun/matching capacitors

C81/C101

C121/C131

C122

RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz).

RF LC filter/matching capacitor

C123

C124

RF balun DC blocking capacitor

C125

RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna)

RF LC filter/matching capacitor/DC-block (868/915 MHz)

RF LC filter/matching capacitor (868/915 MHz)

C126

C127

L121/L131

L122

RF balun/matching inductors (inexpensive multi-layer type)

RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz).

(inexpensive multi-layer type)

L123

L124

L125

L132

R171

XTAL

RF LC filter/matching filter inductor (inexpensive multi-layer type)

RF LC filter/matching filter inductor (inexpensive multi-layer type) (868/915 MHz)

RF balun/matching inductor. (inexpensive multi-layer type)

Resistor for internal bias current reference.

26MHz - 27MHz crystal, see Section 27 on page 52 for details.

Table 14: Overview of External Components (excluding supply decoupling capacitors)

SWRS061B

Page 18 of 93

CC1101

1.8V-3.6V power supply

R171

SI

Antenna

(50 Ohm)

SCLK

1 SCLK

AVDD 15

C131

L131

SO

2 SO

(GDO1)

AVDD 14

RF_N 13

RF_P 12

AVDD 11

(GDO1)

GDO2

(optional)

C125

C123

CC1101

3 GDO2

DIE ATTACH PAD:

4 DVDD

L122

L123

C122

C121

5 DCOUPL

L121

C124

C51

GDO0

(optional)

CSn

XTAL

C81

C101

Figure 3: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply

decoupling capacitors)

Figure 4: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply

decoupling capacitors)

SWRS061B

Page 19 of 93

CC1101

Component

Value at 315MHz

Value at 433MHz

Value at

Manufacturer

868/915MHz

C51

C81

100 nF ± 10%, 0402 X5R

27 pF ± 5%, 0402 NP0

Murata GRM1555C series

C101

C121

6.8 pF ± 0.5 pF,

0402 NP0

3.9 pF ± 0.25 pF,

0402 NP0

1.0 pF ± 0.25 pF,

0402 NP0

C122

C123

C124

C125

C126

C127

C131

L121

L122

L123

L124

L125

L131

L132

12 pF ± 5%, 0402

NP0

8.2 pF ± 0.5 pF,

0402 NP0

1.5 pF ± 0.25 pF,

0402 NP0

Murata GRM1555C series

Murata LQG15HS series

6.8 pF ± 0.5 pF,

0402 NP0

5.6 pF ± 0.5 pF,

0402 NP0

3.3 pF ± 0.25 pF,

0402 NP0

220 pF ± 5%,

0402 NP0

220 pF ± 5%,

0402 NP0

100 pF ± 5%, 0402

NP0

220 pF ± 5%,

0402 NP0

220 pF ± 5%,

0402 NP0

100 pF ± 5%, 0402

NP0

2.2 pF ± 0.25%,

0402 NP0

2.2 pF ± 0.25%,

0402 NP0

6.8 pF ± 0.5 pF,

0402 NP0

3.9 pF ± 0.25 pF,

0402 NP0

1.5 pF ± 0.25 pF,

0402 NP0

33 nH ± 5%, 0402

monolithic

27 nH ± 5%, 0402

monolithic

12 nH ± 5%, 0402

monolithic

18 nH ± 5%, 0402

monolithic

22 nH ± 5%, 0402

monolithic

18 nH ± 5%, 0402

monolithic

33 nH ± 5%, 0402

monolithic

27 nH ± 5%, 0402

monolithic

12 nH ± 5%, 0402

monolithic

12 nH ± 5%, 0402

monolithic

9.1 nH ± 5%, 0402

monolithic

33 nH ± 5%, 0402

monolithic

27 nH ± 5%, 0402

monolithic

12 nH ± 5%, 0402

monolithic

18 nH ± 5%, 0402

monolithic

R171

XTAL

56 kΩ ± 1%, 0402

Koa RK73 series

NDK, AT-41CD2

26.0 MHz surface mount crystal

Table 15: Bill Of Materials for the Application Circuit

The Gerber files for the CC1101EM reference designs ([5] and [6]) are available from the TI website.

SWRS061B

Page 20 of 93

CC1101

8

Configuration Overview

CC1101 can be configured to achieve optimum

performance for many different applications.

Configuration is done using the SPI interface.

The following key parameters can be

programmed:

•

Forward Error Correction (FEC) with

interleaving

Data Whitening

•

Wake-On-Radio (WOR)

•

Power-down / power up mode

Crystal oscillator power-up / power-down

Receive / transmit mode

RF channel selection

Data rate

Modulation format

RX channel filter bandwidth

RF output power

Data buffering with separate 64-byte

receive and transmit FIFOs

Packet radio hardware support

Details of each configuration register can be

found in Section 33, starting on page 59.

Figure 5 shows a simplified state diagram that

explains the main CC1101 states, together with

typical usage and current consumption. For

detailed information on controlling the CC1101

state machine, and a complete state diagram,

see Section 19, starting on page 41.

•

SWRS061B

Page 21 of 93

CC1101

Sleep

Lowest power mode. Most

SPWD or wake-on-radio (WOR)

register values are retained.

Current consumption typ

400 nA, or typ 900 nA when

wake-on-radio (WOR) is

enabled.

SIDLE

Default state when the radio is not

receiving or transmitting. Typ.

current consumption: 1.7 mA.

CSn = 0

IDLE

SXOFF

CSn = 0

SCAL

Used for calibrating frequency

synthesizer upfront (entering

receive or transmit mode can

then be done quicker).

Transitional state. Typ. current

consumption: 8.4 mA.

All register values are

retained. Typ. current

consumption; 165 µA.

Manual freq.

synth. calibration

Crystal

oscillator off

SRX or STX or SFSTXON or wake-on-radio (WOR)

Frequency

Frequency synthesizer is turned on, can optionally be

calibrated, and then settles to the correct frequency.

Transitional state. Typ. current consumption: 8.4 mA.

synthesizer startup,

optional calibration,

settling

SFSTXON

Frequency synthesizer is on,

ready to start transmitting.

Transmission starts very

quickly after receiving the STX

command strobe.Typ. current

consumption: 8.4 mA.

Frequency

synthesizer on

STX

SRX or wake-on-radio (WOR)

STX

TXOFF_MODE = 01

SFSTXON or RXOFF_MODE = 01

Typ. current consumption:

13.1 mA at -6 dBm output,

16.8 mA at 0 dBm output,

32.8 mA at +10 dBm output.

Typ. current

consumption:

from 14.7 mA (strong

input signal) to 15.7 mA

(weak input signal).

STX or RXOFF_MODE=10

SRX or TXOFF_MODE = 11

Transmit mode

Receive mode

TXOFF_MODE = 00

RXOFF_MODE = 00

Optional transitional state. Typ.

current consumption: 8.4 mA.

In FIFO-based modes,

transmission is turned off and

this state entered if the TX

FIFO becomes empty in the

middle of a packet. Typ.

reception is turned off and this

state entered if the RX FIFO

overflows. Typ. current

TX FIFO

underflow

Optional freq.

synth. calibration

RX FIFO

overflow

consumption: 1.7 mA.

current consumption: 1.7 mA.

SFTX

SFRX

IDLE

Figure 5: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate

and MDMCFG2.DEM_DCFILT_OFF=1(current optimized). Freq. Band = 868 MHz

SWRS061B

Page 22 of 93

CC1101

9

Configuration Software

CC1101 can be configured using the SmartRF^®

Studio software [7]. The SmartRF^®Studio

software is highly recommended for obtaining

optimum register settings, and for evaluating

performance and functionality. A screenshot of

the SmartRF^®Studio user interface for CC1101

is shown in Figure 6.

After chip reset, all the registers have default

values as shown in the tables in Section 33.

The optimum register setting might differ from

the default value. After a reset all registers that

shall be different from the default value

therefore needs to be programmed through

the SPI interface.

Figure 6: SmartRF^®Studio [7] User Interface

10 4-wire Serial Configuration and Data Interface

The CSn pin must be kept low during transfers

on the SPI bus. If CSn goes high during the

transfer of a header byte or during read/write

CC1101 is configured via a simple 4-wire SPI-

compatible interface (SI, SO, SCLK and CSn)

where CC1101 is the slave. This interface is

also used to read and write buffered data. All

transfers on the SPI interface are done most

significant bit first.

from/to a register,

the transfer will be

cancelled. The timing for the address and data

transfer on the SPI interface is shown in Figure

7 with reference to Table 16.

All transactions on the SPI interface start with

a header byte containing a R/W¯ bit, a burst

access bit (B), and a 6-bit address (A₅– A₀).

When CSn is pulled low, the MCU must wait

until CC1101 SO pin goes low before starting to

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CC1101

transfer the header byte. This indicates that

the crystal is running. Unless the chip was in

the SLEEP or XOFF states, the SO pin will

always go low immediately after taking CSn

low.

Figure 7: Configuration Registers Write and Read Operations

Parameter

Description

SCLK frequency

100 ns delay inserted between address byte and data byte (single access), or

between address and data, and between each data byte (burst access).

Min

Max

10

Units

f_SCLK

-

MHz

SCLK frequency, single access

-

9

No delay between address and data byte

SCLK frequency, burst access

No delay between address and data byte, or between data bytes

6.5

t_sp,pd

t_sp

CSn low to positive edge on SCLK, in power-down mode

150

20

50

-

µs

ns

CSn low to positive edge on SCLK, in active mode

-

t_ch

Clock high

-

t_cl

Clock low

-

t_rise

t_fall

t_sd

Clock rise time

Clock fall time

5

-

Setup data (negative SCLK edge) to

Single access 55

positive edge on SCLK

(t_sdapplies between address and data bytes, and between

data bytes)

Burst access

76

-

t_hd

t_ns

Hold data after positive edge on SCLK

Negative edge on SCLK to CSn high.

20

-

ns

Table 16: SPI Interface Timing Requirements

Note: The minimum t_sp,pdfigure in Table 16 can be used in cases where the user does not read the

CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator

start-up time measured on CC1101EM reference designs ([5] and [6]) using crystal AT-41CD2 from

NDK.

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CC1101

10.1 Chip Status Byte

when the chip is in receive mode. Likewise, TX

is active when the chip is transmitting.

When the header byte, data byte, or command

strobe is sent on the SPI interface, the chip

status byte is sent by the CC1101 on the SO pin.

The status byte contains key status signals,

useful for the MCU. The first bit, s7, is the

CHIP_RDYn signal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYnsignal indicates that the crystal is

running.

The last four bits (3:0) in the status byte con-

tains FIFO_BYTES_AVAILABLE. For read

operations (the R/W¯ bit in the header byte is

set to 1), the FIFO_BYTES_AVAILABLE field

contains the number of bytes available for

reading from the RX FIFO. For write

operations (the R/W¯ bit in the header byte is

set to 0), the FIFO_BYTES_AVAILABLE field

contains the number of bytes that can be

Bits 6, 5, and 4 comprise the STATE value.

This value reflects the state of the chip. The

XOSC and power to the digital core is on in

the IDLE state, but all other modules are in

power down. The frequency and channel

configuration should only be updated when the

chip is in this state. The RX state will be active

written

to

the

TX

FIFO.

When

FIFO_BYTES_AVAILABLE=15, 15 or more

bytes are available/free.

Table 17 gives a status byte summary.

Bits Name

Description

7

CHIP_RDYn

Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4

STATE[2:0]

Indicates the current main state machine mode

Value State

Description

000

IDLE

IDLE state

(Also reported for some transitional states instead

of SETTLING or CALIBRATE)

001

010

011

100

101

110

RX

Receive mode

TX

Transmit mode

FSTXON

Fast TX ready

CALIBRATE

SETTLING

RXFIFO_OVERFLOW

Frequency synthesizer calibration is running

PLL is settling

RX FIFO has overflowed. Read out any

useful data, then flush the FIFO with SFRX

111

TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

Table 17: Status Byte Summary

10.2 Register Access

written to or read. When writing to registers,

the status byte is sent on the SO pin each time

a header byte or data byte is transmitted on

the SI pin. When reading from registers, the

status byte is sent on the SO pin each time a

header byte is transmitted on the SI pin.

The configuration registers on the CC1101 are

located on SPI addresses from 0x00 to 0x2E.

Table 35 on page 60 lists all configuration

registers. It is highly recommended to use

SmartRF^®Studio [7] to generate optimum

register settings. The detailed description of

each register is found in Section 33.1 and

33.2, starting on page 63. All configuration

registers can be both written to and read. The

R/W¯ bit controls if the register should be

Registers with consecutive addresses can be

accessed in an efficient way by setting the

burst bit (B) in the header byte. The address

bits (A₅– A₀) set the start address in an

internal address counter. This counter is

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CC1101

incremented by one each new byte (every 8

clock pulses). The burst access is either a

read or a write access and must be terminated

by setting CSn high.

the SPWD and the SXOFF strobes that are

executed when CSn goes high.

For register addresses in the range 0x30-

0x3D, the burst bit is used to select between

status registers, burst bit is one, and command

strobes, burst bit is zero (see 10.4 below).

Because of this, burst access is not available

for status registers and they must be accesses

one at a time. The status registers can only be

read.

Figure 8: SRESCommand Strobe

10.5 FIFO Access

The 64-byte TX FIFO and the 64-byte RX

FIFO are accessed through the 0x3F address.

When the R/W¯ bit is zero, the TX FIFO is

accessed, and the RX FIFO is accessed when

the R/W¯ bit is one.

10.3 SPI Read

When reading register fields over the SPI

interface while the register fields are updated

by the radio hardware (e.g. MARCSTATE or

The TX FIFO is write-only, while the RX FIFO

is read-only.

TXBYTES), there is

a small, but finite,

probability that a single read from the register

is being corrupt. As an example, the

probability of any single read from TXBYTES

being corrupt, assuming the maximum data

rate is used, is approximately 80 ppm. Refer to

the CC1101 Errata Notes [1] for more details.

The burst bit is used to determine if the FIFO

access is a single byte access or a burst

access. The single byte access method

expects a header byte with the burst bit set to

zero and one data byte. After the data byte a

new header byte is expected; hence, CSn can

remain low. The burst access method expects

one header byte and then consecutive data

bytes until terminating the access by setting

CSn high.

10.4 Command Strobes

Command Strobes may be viewed as single

byte instructions to CC1101. By addressing a

command strobe register, internal sequences

will be started. These commands are used to

disable the crystal oscillator, enable receive

mode, enable wake-on-radio etc. The 13

command strobes are listed in Table 34 on

page 59.

The following header bytes access the FIFOs:

•

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

0xBF: Single byte access to RX FIFO

0xFF: Burst access to RX FIFO

The command strobe registers are accessed

by transferring a single header byte (no data is

being transferred). That is, only the R/W¯ bit,

the burst access bit (set to 0), and the six

address bits (in the range 0x30 through 0x3D)

are written. The R/W¯ bit can be either one or

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on SO, as shown in Figure 7. This status

byte can be used to detect TX FIFO underflow

while writing data to the TX FIFO. Note that

the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted on SI, the status byte

received concurrently on SO will indicate that

one byte is free in the TX FIFO.

zero

and

will

determine

how

the

FIFO_BYTES_AVAILABLE field in the status

byte should be interpreted.

When writing command strobes, the status

byte is sent on the SO pin.

A command strobe may be followed by any

other SPI access without pulling CSn high.

However, if an SRES strobe is being issued,

one will have to waith for SO to go low again

before the next header byte can be issued as

shown in Figure 8. The command strobes are

executed immediately, with the exception of

The TX FIFO may be flushed by issuing a

SFTX command strobe. Similarly, a SFRX

command strobe will flush the RX FIFO. A

SFTX or SFRX command strobe can only be

issued in the IDLE, TXFIFO_UNDERLOW, or

RXFIFO_OVERFLOW states. Both FIFOs are

flushed when going to the SLEEP state.

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CC1101

Figure 9 gives a brief overview of different

register access types possible.

written and read from the lowest setting (0) to

the highest (7), one byte at a time. An index

counter is used to control the access to the

table. This counter is incremented each time a

byte is read or written to the table, and set to

the lowest index when CSn is high. When the

highest value is reached the counter restarts

at zero.

10.6 PATABLE Access

The 0x3E address is used to access the

PATABLE, which is used for selecting PA

power control settings. The SPI expects up to

eight data bytes after receiving the address.

By programming the PATABLE, controlled PA

power ramp-up and ramp-down can be

achieved, as well as ASK modulation shaping

for reduced bandwidth. See SmartRF^®Studio

[7] for recommended shaping / PA ramping

sequences.

The access to the PATABLE is either single

byte or burst access depending on the burst

bit. When using burst access the index counter

will count up; when reaching 7 the counter will

restart at 0. The R/W¯ bit controls whether the

access is a read or a write access.

If one byte is written to the PATABLE and this

value is to be read out then CSn must be set

high before the read access in order to set the

index counter back to zero.

See Section 24 on page 48 for details on

output power programming.

The PATABLE is an 8-byte table that defines

the PA control settings to use for each of the

eight PA power values (selected by the 3-bit

value FREND0.PA_POWER). The table is

Note that the content of the PATABLE is lost

when entering the SLEEP state, except for the

first byte (index 0).

Figure 9: Register Access Types

11 Microcontroller Interface and Pin Configuration

11.2 General Control and Status Pins

In a typical system, CC1101 will interface to a

microcontroller. This microcontroller must be

able to:

The CC1101 has two dedicated configurable

pins (GDO0 and GDO2) and one shared pin

(GDO1) that can output internal status

information useful for control software. These

pins can be used to generate interrupts on the

MCU. See Section 30 page 54 for more details

on the signals that can be programmed.

GDO1 is shared with the SO pin in the SPI

interface. The default setting for GDO1/SO is

3-state output. By selecting any other of the

programming options, the GDO1/SO pin will

become a generic pin. When CSn is low, the

pin will always function as a normal SO pin.

• Program CC1101 into different modes

• Read and write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO,

SCLK and CSn).

11.1 Configuration Interface

The microcontroller uses four I/O pins for the

SPI configuration interface (SI, SO, SCLK and

CSn). The SPI is described in Section 10 on

page 23.

In the synchronous and asynchronous serial

modes, the GDO0 pin is used as a serial TX

data input pin while in transmit mode.

The GDO0 pin can also be used for an on-chip

analog temperature sensor. By measuring the

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CC1101

voltage on the GDO0 pin with an external

ADC, the temperature can be calculated.

Specifications for the temperature sensor are

found in Section 4.7 on page 15.

the desired state according to Table 18. When

CSn goes low the state of SI and SCLK is

latched and a command strobe is generated

internally according to the pin configuration. It

is only possible to change state with this

functionality. That means that for instance RX

will not be restarted if SI and SCLK are set to

RX and CSn toggles. When CSn is low the SI

and SCLK has normal SPI functionality.

With default PTEST register setting (0x7F) the

temperature sensor output is only available

when the frequency synthesizer is enabled

(e.g. the MANCAL, FSTXON, RX, and TX

states). It is necessary to write 0xBF to the

PTEST register to use the analog temperature

sensor in the IDLE state. Before leaving the

IDLE state, the PTEST register should be

restored to its default value (0x7F).

All pin control command strobes are executed

immediately, except the SPWDstrobe, which is

delayed until CSn goes high.

CSn SCLK SI

Function

11.3 Optional Radio Control Feature

1

↓

X

0

1

X

Chip unaffected by SCLK/SI

Generates SPWDstrobe

Generates STXstrobe

The CC1101 has an optional way of controlling

the radio, by reusing SI, SCLK, and CSn from

the SPI interface. This feature allows for a

simple three-pin control of the major states of

the radio: SLEEP, IDLE, RX, and TX.

0

1

0

Generates SIDLEstrobe

Generates SRXstrobe

1

This optional functionality is enabled with the

MCSM0.PIN_CTRL_ENconfiguration bit.

SPI

mode

SPI

SPI mode (wakes up into

0

mode IDLE if in SLEEP/XOFF)

State changes are commanded as follows:

When CSn is high the SI and SCLK is set to

Table 18: Optional Pin Control Coding

12 Data Rate Programming

The data rate used when transmitting, or the

data rate expected in receive is programmed

If DRATE_M is rounded to the nearest integer

and becomes 256, increment DRATE_E and

use DRATE_M = 0.

by

the

MDMCFG3.DRATE_M

and

the

MDMCFG4.DRATE_E configuration registers.

The data rate is given by the formula below.

As the formula shows, the programmed data

rate depends on the crystal frequency.

The data rate can be set from 1.2 kBaud to

500 kBaud with the minimum step size of:

Min Data

Rate

[kBaud]

Typical Data

Rate

[kBaud]

Max Data

Rate

[kBaud]

Data rate

Step Size

[kBaud]

(

256 + DRATE _ M

)

⋅ 2^{DRATE _ E}

R_DATA

=

⋅ f_XOSC

2²⁸

0.8

3.17

6.35

12.7

25.4

50.8

101.6

203.1

406.3

1.2 / 2.4

4.8

3.17

6.35

12.7

25.4

50.8

101.6

203.1

406.3

500

0.0062

0.0124

0.0248

0.0496

0.0992

0.1984

0.3967

0.7935

1.5869

9.6

The following approach can be used to find

suitable values for a given data rate:

19.6

38.4

76.8

153.6

250

R_DATA⋅ 2²⁰

⎢

⎥

⎛

⎜

⎝

⎞

⎟

⎠

DRATE _ E = log

⎢

2

f_XOSC

⎢

⎣

⎥

⎦

R_DATA⋅ 2²⁸

f_XOSC⋅ 2^{DRATE _ E}

DRATE _ M =

− 256

500

Table 19: Data Rate Step Size

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CC1101

13 Receiver Channel Filter Bandwidth

In order to meet different channel width

requirements, the receiver channel filter is

programmable. The MDMCFG4.CHANBW_E and

MDMCFG4.CHANBW_M configuration registers

control the receiver channel filter bandwidth,

which scales with the crystal oscillator

frequency. The following formula gives the

relation between the register settings and the

channel filter bandwidth:

For best performance, the channel filter

bandwidth should be selected so that the

signal bandwidth occupies at most 80% of the

channel filter bandwidth. The channel centre

tolerance due to crystal accuracy should also

be subtracted from the signal bandwidth. The

following example illustrates this:

With the channel filter bandwidth set to

500 kHz, the signal should stay within 80% of

500 kHz, which is 400 kHz. Assuming

915 MHz frequency and ±20 ppm frequency

uncertainty for both the transmitting device and

the receiving device, the total frequency

uncertainty is ±40 ppm of 915MHz, which is

±37 kHz. If the whole transmitted signal

bandwidth is to be received within 400kHz, the

transmitted signal bandwidth should be

maximum 400kHz – 2·37 kHz, which is

326 kHz.

f_XOSC

BW_channel

=

8⋅(4 + CHANBW _ M )·2^{CHANBW_ E}

The CC1101 supports the following channel filter

bandwidths:

MDMCFG4.CHANBW_E

MDMCFG4.

CHANBW_M

00

01

10

11

102

81

00

01

10

11

812

650

541

464

406

325

270

232

203

162

135

116

68

58

Table 20: Channel Filter Bandwidths [kHz]

(Assuming a 26MHz crystal)

14 Demodulator, Symbol Synchronizer, and Data Decision

If the FOCCFG.FOC_BS_CS_GATE bit is set,

CC1101 contains an advanced and highly

configurable demodulator. Channel filtering

and frequency offset compensation is

performed digitally. To generate the RSSI level

(see Section 17.3 for more information) the

signal level in the channel is estimated. Data

filtering is also included for enhanced

performance.

the offset compensator will freeze until carrier

sense asserts. This may be useful when the

radio is in RX for long periods with no traffic,

since the algorithm may drift to the boundaries

when trying to track noise.

The tracking loop has two gain factors, which

affects the settling time and noise sensitivity of

the algorithm. FOCCFG.FOC_PRE_K sets the

gain before the sync word is detected, and

FOCCFG.FOC_POST_K selects the gain after

the sync word has been found.

14.1 Frequency Offset Compensation

When using 2-FSK, GFSK, or MSK

modulation, the demodulator will compensate

for the offset between the transmitter and

receiver frequency, within certain limits, by

estimating the centre of the received data.

This value is available in the FREQEST status

register. Writing the value from FREQEST into

Note that frequency offset compensation is not

supported for ASK or OOK modulation.

14.2 Bit Synchronization

FSCTRL0.FREQOFF

synthesizer is

according to the estimated frequency offset.

the

frequency

adjusted

The bit synchronization algorithm extracts the

clock from the incoming symbols. The

algorithm requires that the expected data rate

is programmed as described in Section 12 on

page 28. Re-synchronization is performed

continuously to adjust for error in the incoming

symbol rate.

automatically

The tracking range of the algorithm is

selectable as fractions of the channel

bandwidth with the FOCCFG.FOC_LIMIT

configuration register.

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CC1101

14.3 Byte Synchronization

correlation threshold can be set to 15/16,

16/16, or 30/32 bits match. The sync word can

be further qualified using the preamble quality

indicator mechanism described below and/or a

carrier sense condition. The sync word is

configured through the SYNC1 and SYNC0

registers.

Byte synchronization is achieved by

a

continuous sync word search. The sync word

is a 16 bit configurable field (can be repeated

to get a 32 bit) that is automatically inserted at

the start of the packet by the modulator in

transmit mode. The demodulator uses this

field to find the byte boundaries in the stream

of bits. The sync word will also function as a

system identifier, since only packets with the

correct predefined sync word will be received if

the sync word detection in RX is enabled in

register MDMCFG2 (see Section 17.1).. The

sync word detector correlates against the

user-configured 16 or 32 bit sync word. The

In order to make false detections of sync

words less likely,

a

mechanism called

preamble quality indication (PQI) can be used

to qualify the sync word. A threshold value for

the preamble quality must be exceeded in

order for a detected sync word to be accepted.

See Section 17.2 on page 36 for more details.

15 Packet Handling Hardware Support

The CC1101 has built-in hardware support for

•

One byte address check.

Packet length check (length byte checked

packet oriented radio protocols.

against

length).

a

programmable maximum

In transmit mode, the packet handler can be

configured to add the following elements to the

packet stored in the TX FIFO:

•

De-whitening

De-interleaving and decoding

•

A programmable number of preamble

bytes

Optionally, two status bytes (see Table 21 and

Table 22) with RSSI value, Link Quality

Indication, and CRC status can be appended

in the RX FIFO.

A two byte synchronization (sync) word.

Can be duplicated to give a 4-byte sync

word (recommended). It is not possible to

only insert preamble or only insert a sync

word.

Bit Field Name

Description

•

A CRC checksum computed over the data

field.

7:0 RSSI

RSSI value

Table 21: Received Packet Status Byte 1

(first byte appended after the data)

The recommended setting is 4-byte preamble

and 4-byte sync word, except for 500 kBaud

data rate where the recommended preamble

length is 8 bytes.

Bit Field Name

CRC_OK

Description

7

1: CRC for received data OK

(or CRC disabled)

In addition, the following can be implemented

on the data field and the optional 2-byte CRC

checksum:

0: CRC error in received data

Indicating the link quality

6:0 LQI

•

Whitening of the data with

sequence.

Forward error correction by the use of

interleaving and coding of the data

(convolutional coding).

a

PN9

Table 22: Received Packet Status Byte 2

(second byte appended after the data)

Note that register fields that control the packet

handling features should only be altered when

CC1101 is in the IDLE state.

In receive mode, the packet handling support

will de-construct the data packet by

implementing the following (if enabled):

•

Preamble detection.

Sync word detection.

CRC computation and CRC check.

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CC1101

15.1 Data Whitening

receiver. With CC1101, this can be done

automatically

by

setting

From a radio perspective, the ideal over the air

data are random and DC free. This results in

the smoothest power distribution over the

occupied bandwidth. This also gives the

regulation loops in the receiver uniform

operation conditions (no data dependencies).

PKTCTRL0.WHITE_DATA=1. All data, except

the preamble and the sync word, are then

XOR-ed with a 9-bit pseudo-random (PN9)

sequence before being transmitted, as shown

in Figure 10. At the receiver end, the data are

XOR-ed with the same pseudo-random

sequence. This way, the whitening is reversed,

and the original data appear in the receiver.

The PN9 sequence is initialized to all 1’s.

Real world data often contain long sequences

of zeros and ones. Performance can then be

improved by whitening the data before

transmitting, and de-whitening the data in the

Figure 10: Data Whitening in TX Mode

15.2 Packet Format

•

Optional length byte

Optional address byte

Payload

The format of the data packet can be

configured and consists of the following items

(see Figure 11):

Optional 2 byte CRC

•

Preamble

Synchronization word

Optional data whitening

Optionally FEC encoded/decoded

Optional CRC-16 calculation

Legend:

Inserted automatically in TX,

processed and removed in RX.

Optional user-provided fields processed in TX,

processed but not removed in RX.

Preamble bits

(1010...1010)

Data field

Unprocessed user data (apart from FEC

and/or whitening)

8

8 x n bits

16/32 bits

8 x n bits

16 bits

bits bits

Figure 11: Packet Format

SWRS061B

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CC1101

The preamble pattern is an alternating

sequence of ones and zeros (10101010…).

The minimum length of the preamble is

programmable. When enabling TX, the

modulator will start transmitting the preamble.

When the programmed number of preamble

bytes has been transmitted, the modulator will

send the sync word and then data from the TX

FIFO if data is available. If the TX FIFO is

empty, the modulator will continue to send

preamble bytes until the first byte is written to

the TX FIFO. The modulator will then send the

sync word and then the data bytes. The

number of preamble bytes is programmed with

the MDMCFG1.NUM_PREAMBLEvalue.

Note that the minimum packet length

supported (excluding the optional length byte

and CRC) is one byte of payload data.

15.2.1 Arbitrary Length Field Configuration

The packet length register, PKTLEN, can be

reprogrammed during receive and transmit. In

combination with fixed packet length mode

(PKTCTRL0.LENGTH_CONFIG=0) this opens

the possibility to have a different length field

configuration than supported for variable

length packets (in variable packet length mode

the length byte is the first byte after the sync

word). At the start of reception, the packet

length is set to a large value. The MCU reads

out enough bytes to interpret the length field in

the packet. Then the PKTLEN value is set

according to this value. The end of packet will

occur when the byte counter in the packet

handler is equal to the PKTLEN register. Thus,

the MCU must be able to program the correct

length, before the internal counter reaches the

packet length.

The synchronization word is a two-byte value

set in the SYNC1 and SYNC0 registers. The

sync word provides byte synchronization of the

incoming packet. A one-byte synch word can

be emulated by setting the SYNC1value to the

preamble pattern. It is also possible to emulate

a

32

bit

sync

word

by

using

MDMCFG2.SYNC_MODEset to 3 or 7. The sync

word will then be repeated twice.

15.2.2 Packet Length > 255

CC1101 supports both constant packet length

protocols and variable length protocols.

Variable or fixed packet length mode can be

used for packets up to 255 bytes. For longer

packets, infinite packet length mode must be

used.

Also the packet automation control register,

PKTCTRL0, can be reprogrammed during TX

and RX. This opens the possibility to transmit

and receive packets that are longer than 256

bytes and still be able to use the packet

handling hardware support. At the start of the

packet, the infinite packet length mode

(PKTCTRL0.LENGTH_CONFIG=2) must be

active. On the TX side, the PKTLEN register is

set to mod(length, 256). On the RX side the

MCU reads out enough bytes to interpret the

length field in the packet and sets the PKTLEN

register to mod(length, 256). When less than

256 bytes remains of the packet the MCU

disables infinite packet length mode and

activates fixed packet length mode. When the

internal byte counter reaches the PKTLEN

value, the transmission or reception ends (the

radio enters the state determined by

TXOFF_MODE or RXOFF_MODE). Automatic

CRC appending/checking can also be used

(by setting PKTCTRL0.CRC_EN=1).

Fixed packet length mode is selected by

setting PKTCTRL0.LENGTH_CONFIG=0. The

desired packet length is set by the PKTLEN

register.

In

variable

packet

length

mode,

PKTCTRL0.LENGTH_CONFIG=1, the packet

length is configured by the first byte after the

sync word. The packet length is defined as the

payload data, excluding the length byte and

the optional CRC. The PKTLEN register is

used to set the maximum packet length

allowed in RX. Any packet received with a

length byte with a value greater than PKTLEN

will be discarded.

With PKTCTRL0.LENGTH_CONFIG=2, the

packet length is set to infinite and transmission

and reception will continue until turned off

manually. As described in the next section, this

can be used to support packet formats with

different length configuration than natively

supported by CC1101. One should make sure

that TX mode is not turned off during the

transmission of the first half of any byte. Refer

to the CC1101 Errata Notes [1] for more details.

When for example a 600-byte packet is to be

transmitted, the MCU should do the following

(see also Figure 12)

•

Set PKTCTRL0.LENGTH_CONFIG=2.

Pre-program the PKTLEN register to

mod(600, 256) = 88.

SWRS061B

Page 32 of 93

CC1101

•

Transmit at least 345 bytes (600 - 255), for

example by filling the 64-byte TX FIFO six

times (384 bytes transmitted).

•

The transmission ends when the packet

counter reaches 88. A total of 600 bytes

are transmitted.

Set PKTCTRL0.LENGTH_CONFIG=0.

Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again

0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................

600 bytes transmitted and

received

Fixed packet length

enabled when less than

256 bytes remains of

packet

Infinite packet length enabled

Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88

Figure 12: Packet Length > 255

15.3 Packet Filtering in Receive Mode

receive mode restarted (regardless of the

MCSM1.RXOFF_MODEsetting).

CC1101 supports three different types of

packet-filtering; address filtering, maximum

length filtering, and CRC filtering.

15.3.3 CRC Filtering

15.3.1 Address Filtering

The filtering of a packet when CRC check fails

is

enabled

by

setting

Setting PKTCTRL1.ADR_CHK to any other

value than zero enables the packet address

filter. The packet handler engine will compare

the destination address byte in the packet with

the programmed node address in the ADDR

register and the 0x00 broadcast address when

PKTCTRL1.ADR_CHK=10 or both 0x00 and

PKTCTRL1.CRC_AUTOFLUSH=1. The CRC

auto flush function will flush the entire RX

FIFO if the CRC check fails. After auto flushing

the RX FIFO, the next state depends on the

MCSM1.RXOFF_MODEsetting.

When using the auto flush function, the

maximum packet length is 63 bytes in variable

packet length mode and 64 bytes in fixed

packet length mode. Note that the maximum

allowed packet length is reduced by two bytes

0xFF

broadcast

addresses

when

PKTCTRL1.ADR_CHK=11. If the received

address matches a valid address, the packet is

received and written into the RX FIFO. If the

address match fails, the packet is discarded

and receive mode restarted (regardless of the

MCSM1.RXOFF_MODEsetting).

when

PKTCTRL1.APPEND_STATUS

is

enabled, to make room in the RX FIFO for the

two status bytes appended at the end of the

packet. Since the entire RX FIFO is flushed

when the CRC check fails, the previously

received packet must be read out of the FIFO

before receiving the current packet. The MCU

must not read from the current packet until the

CRC has been checked as OK.

If the received address matches a valid

address when using infinite packet length

mode and address filtering is enabled, 0xFF

will be written into the RX FIFO followed by the

address byte and then the payload data.

15.3.2 Maximum Length Filtering

15.4 Packet Handling in Transmit Mode

In

variable

packet

length

mode,

the

PKTCTRL0.LENGTH_CONFIG=1,

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

length is enabled. The length byte has a value

equal to the payload of the packet (including

PKTLEN.PACKET_LENGTH register value is

used to set the maximum allowed packet

length. If the received length byte has a larger

value than this, the packet is discarded and

SWRS061B

Page 33 of 93

CC1101

the optional address byte). If address

recognition is enabled on the receiver, the

second byte written to the TX FIFO must be

the address byte. If fixed packet length is

enabled, then the first byte written to the TX

FIFO should be the address (if the receiver

uses address recognition).

Next, the packet handler optionally checks the

address and only continues the reception if the

address matches. If automatic CRC check is

enabled, the packet handler computes CRC

and matches it with the appended CRC

checksum.

At the end of the payload, the packet handler

will optionally write two extra packet status

bytes (see Table 21 and Table 22) that contain

CRC status, link quality indication, and RSSI

value.

The modulator will first send the programmed

number of preamble bytes. If data is available

in the TX FIFO, the modulator will send the

two-byte (optionally 4-byte) sync word and

then the payload in the TX FIFO. If CRC is

enabled, the checksum is calculated over all

the data pulled from the TX FIFO and the

result is sent as two extra bytes following the

payload data. If the TX FIFO runs empty

before the complete packet has been

15.6 Packet Handling in Firmware

When implementing a packet oriented radio

protocol in firmware, the MCU needs to know

when a packet has been received/transmitted.

Additionally, for packets longer than 64 bytes

the RX FIFO needs to be read while in RX and

the TX FIFO needs to be refilled while in TX.

This means that the MCU needs to know the

number of bytes that can be read from or

written to the RX FIFO and TX FIFO

respectively. There are two possible solutions

to get the necessary status information:

transmitted,

the

radio

will

enter

TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed

will not restart TX mode.

If whitening is enabled, everything following

the sync words will be whitened. This is done

before the optional FEC/Interleaver stage.

Whitening

is

enabled

by

setting

a) Interrupt Driven Solution

PKTCTRL0.WHITE_DATA=1.

In both RX and TX one can use one of the

GDO pins to give an interrupt when a sync

word has been received/transmitted and/or

If FEC/Interleaving is enabled, everything

following the sync words will be scrambled by

the interleaver and FEC encoded before being

modulated. FEC is enabled by setting

MDMCFG1.FEC_EN=1.

when

a

complete packet has been

received/transmitted

(IOCFGx.GDOx_CFG=0x06). In addition, there

are

IOCFGx.GDOx_CFG

associated with

(IOCFGx.GDOx_CFG=0x00

IOCFGx.GDOx_CFG=0x01) and two that are

2

configurations

for

that

RX

the

are

FIFO

and

register

the

15.5 Packet Handling in Receive Mode

In receive mode, the demodulator and packet

handler will search for a valid preamble and

the sync word. When found, the demodulator

has obtained both bit and byte synchronism

and will receive the first payload byte.

associated

with

the

TX

FIFO

and

(IOCFGx.GDOx_CFG=0x02

IOCFGx.GDOx_CFG=0x03) that can be used

as interrupt sources to provide information on

how many bytes are in the RX FIFO and TX

FIFO respectively. See Table 33.

If FEC/Interleaving is enabled, the FEC

decoder will start to decode the first payload

byte. The interleaver will de-scramble the bits

before any other processing is done to the

data.

b) SPI Polling

The PKTSTATUS register can be polled at a

given rate to get information about the current

GDO2 and GDO0 values respectively. The

RXBYTES and TXBYTES registers can be

polled at a given rate to get information about

the number of bytes in the RX FIFO and TX

FIFO respectively. Alternatively, the number of

bytes in the RX FIFO and TX FIFO can be

read from the chip status byte returned on the

If whitening is enabled, the data will be de-

whitened at this stage.

When variable packet length mode is enabled,

the first byte is the length byte. The packet

handler stores this value as the packet length

and receives the number of bytes indicated by

the length byte. If fixed packet length mode is

used, the packet handler will accept the

programmed number of bytes.

SWRS061B

Page 34 of 93

CC1101

MISO line each time a header byte, data byte,

or command strobe is sent on the SPI bus.

is a small, but finite, probability that a single

read from registers PKTSTATUS , RXBYTES

and TXBYTES is being corrupt. The same is

the case when reading the chip status byte.

It is recommended to employ an interrupt

driven solution as high rate SPI polling will

reduce the RX sensitivity. Furthermore, as

explained in Section 10.3 and the CC1101

Errata Notes [1], when using SPI polling there

Refer to the TI website for SW examples ([8]

and [9]).

16 Modulation Formats

16.2 Minimum Shift Keying

CC1101 supports amplitude, frequency, and

phase shift modulation formats. The desired

When using MSK¹, the complete transmission

(preamble, sync word, and payload) will be

MSK modulated.

modulation

format

is

set

in

the

MDMCFG2.MOD_FORMAT register.

Optionally, the data stream can be Manchester

coded by the modulator and decoded by the

demodulator. This option is enabled by setting

MDMCFG2.MANCHESTER_EN=1. Manchester

encoding is not supported at the same time as

using the FEC/Interleaver option.

Phase shifts are performed with a constant

transition time.

The fraction of a symbol period used to

change the phase can be modified with the

DEVIATN.DEVIATION_M setting. This is

equivalent to changing the shaping of the

symbol.

16.1 Frequency Shift Keying

The MSK modulation format implemented in

CC1101 inverts the sync word and data

compared to e.g. signal generators.

2-FSK can optionally be shaped by

Gaussian filter with BT = 1, producing a GFSK

modulated signal.

a

The frequency deviation is programmed with

the DEVIATION_M and DEVIATION_E values

in the DEVIATN register. The value has an

exponent/mantissa form, and the resultant

deviation is given by:

16.3 Amplitude Modulation

CC1101 supports two different forms of

amplitude modulation: On-Off Keying (OOK)

and Amplitude Shift Keying (ASK).

OOK modulation simply turns on or off the PA

to modulate 1 and 0 respectively.

f_xosc

2¹⁷

f_dev

=

⋅(8 + DEVIATION _ M )⋅2^{DEVIATION _ E}

The ASK variant supported by the CC1101

allows programming of the modulation depth

(the difference between 1 and 0), and shaping

of the pulse amplitude. Pulse shaping will

produce a more bandwidth constrained output

spectrum.

The symbol encoding is shown in Table 23.

Format

Symbol

Coding

2-FSK/GFSK

‘0’

‘1’

– Deviation

+ Deviation

Table 23: Symbol Encoding for 2-FSK/GFSK

Modulation

1

Identical to offset QPSK with half-sine

shaping (data coding may differ)

SWRS061B

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CC1101

17 Received Signal Qualifiers and Link Quality Information

A “Preamble Quality Reached” signal can be

observed on one of the GDO pins by setting

IOCFGx.GDOx_CFG=8. It is also possible to

determine if preamble quality is reached by

checking the PQT_REACHED bit in the

PKTSTATUS register. This signal / bit asserts

when the received signal exceeds the PQT.

CC1101 has several qualifiers that can be used

to increase the likelihood that a valid sync

word is detected.

17.1 Sync Word Qualifier

If sync word detection in RX is enabled in

register MDMCFG2the CC1101 will not start filling

the RX FIFO and perform the packet filtering

described in Section 15.3 before a valid sync

word has been detected. The sync word

qualifier mode is set by MDMCFG2.SYNC_MODE

and is summarized in Table 24. Carrier sense

is described in Section 17.4.

17.3 RSSI

The RSSI value is an estimate of the signal

power level in the chosen channel. This value

is based on the current gain setting in the RX

chain and the measured signal level in the

channel.

In RX mode, the RSSI value can be read

continuously from the RSSI status register until

the demodulator detects a sync word (when

sync word detection is enabled). At that point

the RSSI readout value is frozen until the next

time the chip enters the RX state. The RSSI

value is in dBm with ½dB resolution. The RSSI

update rate, f_RSSI, depends on the receiver

filter bandwidth (BW_channeldefined in Section

13) and AGCCTRL0.FILTER_LENGTH.

MDMCFG2.

Sync Word Qualifier Mode

SYNC_MODE

000

001

010

011

100

No preamble/sync

15/16 sync word bits detected

16/16 sync word bits detected

30/32 sync word bits detected

No preamble/sync, carrier sense

above threshold

2⋅ BW_channel

101

110

111

15/16 + carrier sense above threshold

16/16 + carrier sense above threshold

30/32 + carrier sense above threshold

f_RSSI

=

8⋅2^{FILTER _ LENGTH}

If PKTCTRL1.APPEND_STATUSis enabled the

last RSSI value of the packet is automatically

added to the first byte appended after the

payload.

Table 24: Sync Word Qualifier Mode

17.2 Preamble Quality Threshold (PQT)

The RSSI value read from the RSSI status

register is a 2’s complement number. The

following procedure can be used to convert the

RSSI reading to an absolute power level

(RSSI_dBm).

The Preamble Quality Threshold (PQT) sync-

word qualifier adds the requirement that the

received sync word must be preceded with a

preamble with

a

quality above the

programmed threshold.

1) Read the RSSI status register

Another use of the preamble quality threshold

is as a qualifier for the optional RX termination

timer. See Section 19.7 on page 45 for details.

2) Convert the reading from a hexadecimal

number to a decimal number (RSSI_dec)

3) If RSSI_dec ≥ 128 then RSSI_dBm =

The preamble quality estimator increases an

internal counter by one each time a bit is

received that is different from the previous bit,

and decreases the counter by 8 each time a

bit is received that is the same as the last bit.

The threshold is configured with the register

field PKTCTRL1.PQT. A threshold of 4·PQTfor

this counter is used to gate sync word

detection. By setting the value to zero, the

preamble quality qualifier of the synch word is

disabled.

(RSSI_dec - 256)/2 – RSSI_offset

4) Else if RSSI_dec < 128 then RSSI_dBm =

(RSSI_dec)/2 – RSSI_offset

Table 25 gives typical values for the

RSSI_offset.

Figure 13 and Figure 14 shows typical plots of

RSSI reading as a function of input power

level for different data rates.

SWRS061B

Page 36 of 93

CC1101

Data rate [kBaud]

RSSI_offset [dB], 433 MHz

RSSI_offset [dB], 868 MHz

1.2

38.4

250

500

74

Table 25: Typical RSSI_offset Values

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Power [dBm]

1.2 kBaud

38.4 kBaud

250 kBaud

500 kBaud

Figure 13: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Input Power [dBm]

1.2 kBaud

500 kBaud

250 kBaud

38.4 kBaud

Figure 14: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz

SWRS061B

Page 37 of 93

CC1101

17.4 Carrier Sense (CS)

It is strongly recommended to use SmartRF^®

Studio to generate the correct MAGN_TARGET

setting.

Carrier Sense (CS) is used as a sync word

qualifier and for CCA and can be asserted

based on two conditions, which can be

individually adjusted:

Table 26 and Table 27 show the typical RSSI

readout values at the CS threshold at 2.4

kBaud and 250 kBaud data rate respectively.

The default CARRIER_SENSE_ABS_THR=0 (0

dB) and MAGN_TARGET=3 (33 dB) have been

used.

•

CS is asserted when the RSSI is above a

programmable absolute threshold, and de-

asserted when RSSI is below the same

threshold (with hysteresis).

For other data rates the user must generate

similar tables to find the CS absolute

threshold.

•

CS is asserted when the RSSI has

increased with a programmable number of

dB from one RSSI sample to the next, and

de-asserted when RSSI has decreased

with the same number of dB. This setting

is not dependent on the absolute signal

level and is thus useful to detect signals in

environments with time varying noise floor.

MAX_DVGA_GAIN[1:0]

00

-97.5

-94

01

-91.5

-88

10

11

-79.5

-76

000

001

010

011

100

101

110

111

-85.5

-82.5

-78.5

-76.5

-73.5

-72

Carrier Sense can be used as a sync word

qualifier that requires the signal level to be

higher than the threshold for a sync word

search to be performed. The signal can also

be observed on one of the GDO pins by

setting IOCFGx.GDOx_CFG=14 and in the

status register bit PKTSTATUS.CS.

-90.5

-88

-84.5

-82.5

-80

-72.5

-70.5

-68

-85.5

-84

-78

-66

-82

-76

-70

-64

-79

-73.5

-67

-61

Other uses of Carrier Sense include the TX-if-

CCA function (see Section 17.5 on page 39)

and the optional fast RX termination (see

Section 19.7 on page 45).

Table 26: Typical RSSI Value in dBm at CS

Threshold with Default MAGN_TARGETat 2.4

kBaud, 868 MHz

CS can be used to avoid interference from

other RF sources in the ISM bands.

MAX_DVGA_GAIN[1:0]

17.4.1 CS Absolute Threshold

00

01

-84.5

-82

10

-78.5

-76

-72

-70

-68

-66

-64

-62

11

-72.5

-70

-66

-64

-62

-60

-58

-56

The absolute threshold related to the RSSI

value depends on the following register fields:

000

001

010

011

100

101

110

111

-90.5

-88

•

AGCCTRL2.MAX_LNA_GAIN

-84.5

-82.5

-80.5

-78

-78.5

-76.5

-74.5

-72

AGCCTRL2.MAX_DVGA_GAIN

AGCCTRL1.CARRIER_SENSE_ABS_THR

AGCCTRL2.MAGN_TARGET

-76.5

-74.5

-70

For a given AGCCTRL2.MAX_LNA_GAIN

-68

and AGCCTRL2.MAX_DVGA_GAIN setting the

absolute threshold can be adjusted ±7 dB in

Table 27: Typical RSSI Value in dBm at CS

Threshold with Default MAGN_TARGETat 250

kBaud, 868 MHz

steps

of

1

dB

using

CARRIER_SENSE_ABS_THR.

The MAGN_TARGET setting is a compromise

between blocker tolerance/selectivity and

sensitivity. The value sets the desired signal

level in the channel into the demodulator.

Increasing this value reduces the headroom

for blockers, and therefore close-in selectivity.

If the threshold is set high, i.e. only strong

signals are wanted, the threshold should be

adjusted upwards by first reducing the

MAX_LNA_GAIN

value

and

then

the

SWRS061B

Page 38 of 93

CC1101

command is sent on the SPI interface). This

feature is called TX-if-CCA. Four CCA

requirements can be programmed:

MAX_DVGA_GAIN value. This will reduce

power consumption in the receiver front end,

since the highest gain settings are avoided.

•

Always (CCA disabled, always goes to TX)

If RSSI is below threshold

17.4.2 CS Relative Threshold

The relative threshold detects sudden changes

in the measured signal level. This setting is not

dependent on the absolute signal level and is

thus useful to detect signals in environments

with a time varying noise floor. The register

field AGCCTRL1.CARRIER_SENSE_REL_THR

is used to enable/disable relative CS, and to

select threshold of 6 dB, 10 dB, or 14 dB RSSI

change.

Unless currently receiving a packet

Both the above (RSSI below threshold and

not currently receiving a packet)

17.6 Link Quality Indicator (LQI)

The Link Quality Indicator is a metric of the

current quality of the received signal. If

PKTCTRL1.APPEND_STATUS is enabled, the

value is automatically added to the last byte

appended after the payload. The value can

also be read from the LQIstatus register. The

LQI gives an estimate of how easily a received

signal can be demodulated by accumulating

the magnitude of the error between ideal

constellations and the received signal over the

64 symbols immediately following the sync

17.5 Clear Channel Assessment (CCA)

The Clear Channel Assessment (CCA) is used

to indicate if the current channel is free or

busy. The current CCA state is viewable on

any of the GDO pins by setting

IOCFGx.GDOx_ CFG=0x09.

MCSM1.CCA_MODE selects the mode to use

when determining CCA.

word. LQI is best used as

a

relative

When the STXor SFSTXONcommand strobe is

given while CC1101 is in the RX state, the TX or

FSTXON state is only entered if the clear

channel requirements are fulfilled. The chip will

otherwise remain in RX (if the channel

becomes available, the radio will not enter TX

or FSTXON state before a new strobe

measurement of the link quality (a high value

indicates a better link than what a low value

does), since the value is dependent on the

modulation format.

18 Forward Error Correction with Interleaving

PER = 1− (1− BER)^{packet _ length}

18.1 Forward Error Correction (FEC)

CC1101 has built in support for Forward Error

a lower BER can be used to allow longer

packets, or a higher percentage of packets of

a given length, to be transmitted successfully.

Finally, in realistic ISM radio environments,

transient and time-varying phenomena will

produce occasional errors even in otherwise

good reception conditions. FEC will mask such

errors and, combined with interleaving of the

coded data, even correct relatively long

periods of faulty reception (burst errors).

Correction (FEC). To enable this option, set

MDMCFG1.FEC_ENto 1. FEC is only supported

in

fixed

packet

length

mode

(PKTCTRL0.LENGTH_CONFIG=0). FEC is

employed on the data field and CRC word in

order to reduce the gross bit error rate when

operating

near

the

sensitivity

limit.

Redundancy is added to the transmitted data

in such a way that the receiver can restore the

original data in the presence of some bit

errors.

The FEC scheme adopted for CC1101 is

convolutional coding, in which n bits are

generated based on k input bits and the m

most recent input bits, forming a code stream

able to withstand a certain number of bit errors

between each coding state (the m-bit window).

The use of FEC allows correct reception at a

lower SNR, thus extending communication

range if the receiver bandwidth remains

constant. Alternatively, for a given SNR, using

FEC decreases the bit error rate (BER). As the

packet error rate (PER) is related to BER by:

SWRS061B

Page 39 of 93

CC1101

The convolutional coder is a rate 1/2 code with

a constraint length of m = 4. The coder codes

one input bit and produces two output bits;

hence, the effective data rate is halved. I.e. to

transmit at the same effective datarate when

using FEC, it is necessary to use twice as high

over-the-air datarate. This will require a higher

receiver bandwidth, and thus reduce

sensitivity. In other words the improved

reception by using FEC and the degraded

sensitivity from a higher receiver bandwidth

will be counteracting factors.

4 matrices. In the transmitter, the data bits

from the rate ½ convolutional coder are written

into the rows of the matrix, whereas the bit

sequence to be transmitted is read from the

columns of the matrix. Conversely, in the

receiver, the received symbols are written into

the columns of the matrix, whereas the data

passed onto the convolutional decoder is read

from the rows of the matrix.

When FEC and interleaving is used at least

one extra byte is required for trellis

termination. In addition, the amount of data

transmitted over the air must be a multiple of

the size of the interleaver buffer (two bytes).

The packet control hardware therefore

automatically inserts one or two extra bytes at

the end of the packet, so that the total length

of the data to be interleaved is an even

number. Note that these extra bytes are

invisible to the user, as they are removed

before the received packet enters the RX

FIFO.

18.2 Interleaving

Data received through radio channels will

often experience burst errors due to

interference and time-varying signal strengths.

In order to increase the robustness to errors

spanning multiple bits, interleaving is used

when FEC is enabled. After de-interleaving, a

continuous span of errors in the received

stream will become single errors spread apart.

When FEC and interleaving is used the

minimum data payload is 2 bytes.

CC1101 employs matrix interleaving, which is

illustrated in Figure 15. The on-chip

interleaving and de-interleaving buffers are 4 x

Interleaver

Write buffer

Interleaver

Read buffer

Packet

Engine

FEC

Encoder

Modulator

Interleaver

Write buffer

Interleaver

Read buffer

FEC

Decoder

Packet

Engine

Demodulator

Figure 15: General Principle of Matrix Interleaving

SWRS061B

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CC1101

19 Radio Control

SIDLE

SPWD

| SWOR

SLEEP

0

CAL_COMPLETE

MANCAL

3,4,5

IDLE

1

CSn = 0

| WOR

SXOFF

SCAL

CSn = 0

XOFF

2

SRX

| STX | SFSTXON | WOR

FS_WAKEUP

6,7

FS_AUTOCAL = 01

&

SRX

| STX | SFSTXON | WOR

FS_AUTOCAL = 00 | 10 | 11

&

CALIBRATE

8

SRX

| STX | SFSTXON | WOR

CAL_COMPLETE

SETTLING

9,10,11

SFSTXON

FSTXON

18

STX

SRX

| WOR

SRX

TXOFF_MODE=01

STX

SFSTXON

|

RXOFF_MODE = 01

RXTX_SETTLING

21

STX

|

RXOFF_MODE = 10

( STX

| SFSTXON ) & CCA

|

RXOFF_MODE = 01 | 10

TX

19,20

RX

13,14,15

TXOFF_MODE = 10

RXOFF_MODE = 11

SRX

| TXOFF_MODE = 11

TXRX_SETTLING

16

RXOFF_MODE = 00

&

FS_AUTOCAL = 10 | 11

TXOFF_MODE = 00

&

FS_AUTOCAL = 10 | 11

TXFIFO_UNDERFLOW

RXFIFO_OVERFLOW

CALIBRATE

12

TXOFF_MODE = 00

RXOFF_MODE = 00

&

FS_AUTOCAL = 00 | 01

&

FS_AUTOCAL = 00 | 01

TX_UNDERFLOW

22

RX_OVERFLOW

17

SFTX

SFRX

IDLE

1

Figure 16: Complete Radio Control State Diagram

readable in the MARCSTATE status register.

This register is primarily for test purposes.

CC1101 has a built-in state machine that is used

to switch between different operational states

(modes). The change of state is done either by

using command strobes or by internal events

such as TX FIFO underflow.

19.1 Power-On Start-Up Sequence

When the power supply is turned on, the

system must be reset. This is achieved by one

of the two sequences described below, i.e.

automatic power-on reset (POR) or manual

reset.

A simplified state diagram, together with

typical usage and current consumption, is

shown in Figure 5 on page 22. The complete

radio control state diagram is shown in Figure

16. The numbers refer to the state number

SWRS061B

Page 41 of 93

CC1101

After the automatic power-on reset or manual

reset it is also recommended to change the

signal that is output on the GDO0 pin. The

default setting is to output a clock signal with a

frequency of CLK_XOSC/192, but to optimize

performance in TX and RX an alternative GDO

setting should be selected from the settings

found in Table 33 on page 55.

•

Pull CSn low and wait for SO to go low

(CHIP_RDYn).

•

Issue the SRESstrobe on the SI line.

When SO goes low again, reset is

complete and the chip is in the IDLE state.

XOSC and voltage regulator switched on

40 us

19.1.1 Automatic POR

CSn

A power-on reset circuit is included in the

CC1101. The minimum requirements stated in

Table 12 must be followed for the power-on

reset to function properly. The internal power-

up sequence is completed when CHIP_RDYn

goes low. CHIP_RDYn is observed on the SO

pin after CSn is pulled low. See Section 10.1

for more details on CHIP_RDYn.

SO

XOSC Stable

SRES

SI

Figure 18: Power-On Reset with SRES

When the CC1101 reset is completed the chip

will be in the IDLE state and the crystal

oscillator will be running. If the chip has had

sufficient time for the crystal oscillator to

stabilize after the power-on-reset the SO pin

will go low immediately after taking CSn low. If

CSn is taken low before reset is completed the

SO pin will first go high, indicating that the

crystal oscillator is not stabilized, before going

low as shown in Figure 17.

Note that the above reset procedure is only

required just after the power supply is first

turned on. If the user wants to reset the CC1101

after this, it is only necessary to issue an SRES

command strobe.

19.2 Crystal Control

The crystal oscillator (XOSC) is either

automatically controlled or always on, if

MCSM0.XOSC_FORCE_ONis set.

In the automatic mode, the XOSC will be

turned off if the SXOFF or SPWD command

strobes are issued; the state machine then

goes to XOFF or SLEEP respectively. This

can only be done from the IDLE state. The

XOSC will be turned off when CSn is released

(goes high). The XOSC will be automatically

turned on again when CSn goes low. The

state machine will then go to the IDLE state.

The SO pin on the SPI interface must be

pulled low before the SPI interface is ready to

be used; as described in Section 10.1 on page

25.

Figure 17: Power-On Reset

19.1.2 Manual Reset

The other global reset possibility on CC1101

uses the SRES command strobe. By issuing

this strobe, all internal registers and states are

set to the default, IDLE state. The manual

power-up sequence is as follows (see Figure

18):

If the XOSC is forced on, the crystal will

always stay on even in the SLEEP state.

•

Set SCLK = 1 and SI = 0, to avoid

potential problems with pin control mode

(see Section 11.3 on page 28).

Crystal oscillator start-up time depends on

crystal ESR and load capacitances. The

electrical specification for the crystal oscillator

can be found in Section 4.4 on page 13.

•

Strobe CSn low / high.

Hold CSn high for at least 40µs relative to

pulling CSn low

SWRS061B

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CC1101

19.3 Voltage Regulator Control

•

FSTXON: Frequency synthesizer on and

ready at the TX frequency. Activate TX

with STX .

The voltage regulator to the digital core is

controlled by the radio controller. When the

chip enters the SLEEP state, which is the state

with the lowest current consumption, the

voltage regulator is disabled. This occurs after

CSn is released when a SPWD command

strobe has been sent on the SPI interface. The

chip is now in the SLEEP state. Setting CSn

low again will turn on the regulator and crystal

oscillator and make the chip enter the IDLE

state.

•

TX: Start sending preamble

RX: Start search for a new packet

Similarly, when TX is active the chip will

remain in the TX state until the current packet

has been successfully transmitted. Then the

state will change as indicated by the

MCSM1.TXOFF_MODE setting. The possible

destinations are the same as for RX.

When wake on radio is enabled, the WOR

module will control the voltage regulator as

described in Section 19.5.

The MCU can manually change the state from

RX to TX and vice versa by using the

command strobes. If the radio controller is

currently in transmit and the SRX strobe is

used, the current transmission will be ended

and the transition to RX will be done.

19.4 Active Modes

CC1101 has two active modes: receive and

transmit. These modes are activated directly

by the MCU by using the SRX and STX

command strobes, or automatically by Wake

on Radio.

If the radio controller is in RX when the STX or

SFSTXONcommand strobes are used, the TX-

if-CCA function will be used. If the channel is

not clear, the chip will remain in RX. The

MCSM1.CCA_MODE

conditions for clear channel assessment. See

Section 17.5 on page 39 for details.

The frequency synthesizer must be calibrated

regularly. CC1101 has one manual calibration

option (using the SCAL strobe), and three

automatic calibration options, controlled by the

MCSM0.FS_AUTOCALsetting:

setting

controls

the

The SIDLE command strobe can always be

used to force the radio controller to go to the

IDLE state.

•

Calibrate when going from IDLE to either

RX or TX (or FSTXON)

Calibrate when going from either RX or TX

to IDLE automatically

19.5 Wake On Radio (WOR)

The optional Wake on Radio (WOR)

functionality enables CC1101 to periodically

wake up from SLEEP and listen for incoming

packets without MCU interaction.

Calibrate every fourth time when going

from either RX or TX to IDLE automatically

If the radio goes from TX or RX to IDLE by

issuing an SIDLEstrobe, calibration will not be

performed. The calibration takes a constant

number of XOSC cycles (see Table 28 for

timing details).

When the WOR strobe command is sent on

the SPI interface, the CC1101 will go to the

SLEEP state when CSn is released. The RC

oscillator must be enabled before the WOR

strobe can be used, as it is the clock source

for the WOR timer. The on-chip timer will set

CC1101 into IDLE state and then RX state. After

a programmable time in RX, the chip will go

back to the SLEEP state, unless a packet is

received. See Figure 19 and Section 19.7 for

details on how the timeout works.

When RX is activated, the chip will remain in

receive mode until a packet is successfully

received or the RX termination timer expires

(see Section 19.7). Note: the probability that a

false sync word is detected can be reduced by

using PQT, CS, maximum sync word length,

and sync word qualifier mode as described in

Section 17. After a packet is successfully

received the radio controller will then go to the

state indicated by the MCSM1.RXOFF_MODE

setting. The possible destinations are:

Set the CC1101 into the IDLE state to exit WOR

mode.

CC1101 can be set up to signal the MCU that a

packet has been received by using the GDO

pins. If

•

IDLE

a

packet is received, the

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CC1101

19.5.1 RC Oscillator and Timing

MCSM1.RXOFF_MODE

will determine the

behaviour at the end of the received packet.

When the MCU has read the packet, it can put

the chip back into SLEEP with the SWORstrobe

from the IDLE state. The FIFO will loose its

contents in the SLEEP state.

The frequency of the low-power RC oscillator

used for the WOR functionality varies with

temperature and supply voltage. In order to

keep the frequency as accurate as possible,

the RC oscillator will be calibrated whenever

possible, which is when the XOSC is running

and the chip is not in the SLEEP state. When

the power and XOSC is enabled, the clock

used by the WOR timer is a divided XOSC

clock. When the chip goes to the sleep state,

the RC oscillator will use the last valid

calibration result. The frequency of the RC

oscillator is locked to the main crystal

frequency divided by 750.

The WOR timer has two events, Event 0 and

Event 1. In the SLEEP state with WOR

activated, reaching Event 0 will turn on the

digital regulator and start the crystal oscillator.

Event 1 follows Event 0 after a programmed

timeout.

The time between two consecutive Event 0 is

programmed with a mantissa value given by

WOREVT1.EVENT0 and WOREVT0.EVENT0,

In applications where the radio wakes up very

often, typically several times every second, it

is possible to do the RC oscillator calibration

and

an

exponent

value

set

by

WORCTRL.WOR_RES. The equation is:

750

once

and

then

turn

off

calibration

t_Event0

=

⋅ EVENT0⋅ 2^{5⋅WOR _ RES}

(WORCTRL.RC_CAL=0) to reduce the current

consumption. This requires that RC oscillator

calibration values are read from registers

RCCTRL0_STATUS and RCCTRL1_STATUS

and written back to RCCTRL0 and RCCTRL1

respectively. If the RC oscillator calibration is

turned off it will have to be manually turned on

again if temperature and supply voltage

changes.

f_XOSC

The Event 1 timeout is programmed with

WORCTRL.EVENT1. Figure 19 shows the

timing relationship between Event 0 timeout

and Event 1 timeout.

Refer to Application Note AN047 [4] for further

details.

19.6 Timing

The radio controller controls most of the timing

in CC1101, such as synthesizer calibration, PLL

lock time, and RX/TX turnaround times. Timing

from IDLE to RX and IDLE to TX is constant,

dependent on the auto calibration setting.

RX/TX and TX/RX turnaround times are

constant. The calibration time is constant

18739 clock periods. Table 28 shows timing in

crystal clock cycles for key state transitions.

Figure 19: Event 0 and Event 1 Relationship

The time from the CC1101 enters SLEEP state

until the next Event0 is programmed to appear

(t_SLEEPin Figure 19) should be larger than

11.08 ms when using a 26 MHz crystal and

10.67 ms when a 27 MHz crystal is used. If

t_SLEEPis less than 11.08 (10.67) ms there is a

chance that the consecutive Event 0 will occur

Power on time and XOSC start-up times are

variable, but within the limits stated in Table 7.

Note that in a frequency hopping spread

spectrum or a multi-channel protocol the

calibration time can be reduced from 721 µs to

approximately 150 µs. This is explained in

Section 32.2.

750

seconds

⋅128

f_XOSC

too early. Application Note AN047 [4] explains

in detail the theory of operation and the

different registers involved when using WOR,

as well as highlighting important aspects when

using WOR mode.

SWRS061B

Page 44 of 93

CC1101

If the system can expect the transmission to

have started when enabling the receiver, the

MCSM2.RX_TIME_RSSIfunction can be used.

The radio controller will then terminate RX if

the first valid carrier sense sample indicates

no carrier (RSSI below threshold). See Section

17.4 on page 38 for details on Carrier Sense.

Description

XOSC

Periods

26 MHz

Crystal

IDLE to RX, no calibration

IDLE to RX, with calibration

2298

88.4µs

809µs

88.4µs

~21037

2298

IDLE to TX/FSTXON, no

calibration

IDLE to TX/FSTXON, with

calibration

~21037

809µs

For ASK/OOK modulation, lack of carrier

sense is only considered valid after eight

TX to RX switch

560

21.5µs

9.6µs

0.1µs

721µs

symbol

periods.

Thus,

the

MCSM2.RX_TIME_RSSI function can be used

in ASK/OOK mode when the distance between

“1” symbols is 8 or less.

RX to TX switch

250

RX or TX to IDLE, no calibration

RX or TX to IDLE, with calibration

Manual calibration

2

~18739

If RX terminates due to no carrier sense when

the MCSM2.RX_TIME_RSSI function is used,

or if no sync word was found when using the

MCSM2.RX_TIME timeout function, the chip

will always go back to IDLE if WOR is disabled

and back to SLEEP if WOR is enabled.

Otherwise, the MCSM1.RXOFF_MODE setting

determines the state to go to when RX ends.

This means that the chip will not automatically

go back to SLEEP once a sync word has been

received. It is therefore recommended to

always wake up the microcontroller on sync

word detection when using WOR mode. This

can be done by selecting output signal 6 (see

Table 33 on page 55) on one of the

programmable GDO output pins, and

programming the microcontroller to wake up

on an edge-triggered interrupt from this GDO

pin.

Table 28: State Transition Timing

19.7 RX Termination Timer

CC1101 has optional functions for automatic

termination of RX after a programmable time.

The main use for this functionality is wake-on-

radio (WOR), but it may be useful for other

applications. The termination timer starts when

in RX state. The timeout is programmable with

the MCSM2.RX_TIME setting. When the timer

expires, the radio controller will check the

condition for staying in RX; if the condition is

not met, RX will terminate.

The programmable conditions are:

•

MCSM2.RX_TIME_QUAL=0:

receive if sync word has been found

Continue

•

MCSM2.RX_TIME_QUAL=1:

receive if sync word has been found or

preamble quality is above threshold (PQT)

Continue

20 Data FIFO

value, since an RX FIFO underflow will result

in an error in the data read out of the RX FIFO.

The CC1101 contains two 64 byte FIFOs, one

for received data and one for data to be

transmitted. The SPI interface is used to read

from the RX FIFO and write to the TX FIFO.

Section 10.5 contains details on the SPI FIFO

access. The FIFO controller will detect

overflow in the RX FIFO and underflow in the

TX FIFO.

The chip status byte that is available on the

SO pin while transferring the SPI header

contains the fill grade of the RX FIFO if the

access is a read operation and the fill grade of

the TX FIFO if the access is a write operation.

Section 10.1 on page 25 contains more details

on this.

When writing to the TX FIFO it is the

responsibility of the MCU to avoid TX FIFO

overflow. A TX FIFO overflow will result in an

error in the TX FIFO content.

The number of bytes in the RX FIFO and TX

FIFO can be read from the status registers

RXBYTES.NUM_RXBYTES

and

Likewise, when reading the RX FIFO the MCU

must avoid reading the RX FIFO past its empty

TXBYTES.NUM_TXBYTES respectively. If a

received data byte is written to the RX FIFO at

the exact same time as the last byte in the RX

SWRS061B

Page 45 of 93

CC1101

FIFO is read over the SPI interface, the RX

FIFO pointer is not properly updated and the

last read byte is duplicated. To avoid this

problem one should never empty the RX FIFO

before the last byte of the packet is received.

NUM_RXBYTES

GDO

53 54 55 56 57 56 55 54 53

NUM_TXBYTES

GDO

6

7

8

9

10

9

8

7

6

For packet lengths less than 64 bytes it is

recommended to wait until the complete

packet has been received before reading it out

of the RX FIFO.

Figure 20: FIFO_THR=13vs. Number of

Bytes in FIFO (GDOx_CFG=0x00in RX and

GDOx_CFG=0x02in TX)

If the packet length is larger than 64 bytes the

MCU must determine how many bytes can be

read

from

the

RX

FIFO

(RXBYTES.NUM_RXBYTES-1) and the following

software routine can be used:

FIFO_THR

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Bytes in TX FIFO

Bytes in RX FIFO

61

57

53

49

45

41

37

33

29

25

21

17

13

9

4

8

1. Read

RXBYTES.NUM_RXBYTES

12

16

20

24

28

32

36

40

44

48

52

56

60

64

repeatedly at a rate guaranteed to be at

least twice that of which RF bytes are

received until the same value is returned

twice; store value in n.

2. If n < # of bytes remaining in packet, read

n-1 bytes from the RX FIFO.

3. Repeat steps 1 and 2 until n = # of bytes

remaining in packet.

4. Read the remaining bytes from the RX

FIFO.

The 4-bit FIFOTHR.FIFO_THRsetting is used

to program threshold points in the FIFOs.

Table 29 lists the 16 FIFO_THR settings and

the corresponding thresholds for the RX and

TX FIFOs. The threshold value is coded in

opposite directions for the RX FIFO and TX

FIFO. This gives equal margin to the overflow

and underflow conditions when the threshold

is reached.

5

1

Table 29: FIFO_THRSettings and the

Corresponding FIFO Thresholds

Overflow

margin

A signal will assert when the number of bytes

in the FIFO is equal to or higher than the

programmed threshold. This signal can be

viewed on the GDO pins (see Table 33 on

page 55).

FIFO_THR=13

Figure 21 shows the number of bytes in both

the RX FIFO and TX FIFO when the threshold

signal toggles, in the case of FIFO_THR=13.

Figure 20 shows the signal as the respective

FIFO is filled above the threshold, and then

drained below.

56 bytes

FIFO_THR=13

Underflow

8 bytes

margin

RXFIFO

TXFIFO

Figure 21: Example of FIFOs at Threshold

SWRS061B

Page 46 of 93

CC1101

21 Frequency Programming

The base or start frequency is set by the 24 bit

frequency word located in the FREQ2, FREQ1,

and FREQ0 registers. This word will typically

be set to the centre of the lowest channel

frequency that is to be used.

The frequency programming in CC1101 is

designed to minimize the programming

needed in a channel-oriented system.

To set up a system with channel numbers, the

desired channel spacing is programmed with

the

MDMCFG0.CHANSPC_M

and

The desired channel number is programmed

with the 8-bit channel number register,

CHANNR.CHAN, which is multiplied by the

channel offset. The resultant carrier frequency

is given by:

MDMCFG1.CHANSPC_E registers. The channel

spacing registers are mantissa and exponent

respectively.

f_XOSC

2¹⁶

f_carrier

=

⋅

(

FREQ + CHAN ⋅

(

256 + CHANSPC _ M

)

⋅ 2^{CHANSPC _ E−2}))

Note that the SmartRF^®Studio software [7]

automatically calculates the optimum

FSCTRL1.FREQ_IF register setting based on

channel spacing and channel filter bandwidth.

With a 26 MHz crystal the maximum channel

spacing is 405 kHz. To get e.g. 1 MHz channel

spacing one solution is to use 333 kHz

channel spacing and select each third channel

in CHANNR.CHAN.

If any frequency programming register is

altered when the frequency synthesizer is

running, the synthesizer may give an

undesired response. Hence, the frequency

programming should only be updated when

the radio is in the IDLE state.

The preferred IF frequency is programmed

with the FSCTRL1.FREQ_IF register. The IF

frequency is given by:

f_XOSC

f_IF

=

⋅ FREQ _ IF

2¹⁰

22 VCO

The VCO is completely integrated on-chip.

calibration is initiated when the SCAL

command strobe is activated in the IDLE

mode.

22.1 VCO and PLL Self-Calibration

Note that the calibration values are maintained

in SLEEP mode, so the calibration is still valid

after waking up from SLEEP mode (unless

supply voltage or temperature has changed

significantly).

The VCO characteristics will vary with

temperature and supply voltage changes, as

well as the desired operating frequency. In

order to ensure reliable operation, CC1101

includes frequency synthesizer self-calibration

circuitry. This calibration should be done

regularly, and must be performed after turning

on power and before using a new frequency

(or channel). The number of XOSC cycles for

completing the PLL calibration is given in

Table 28 on page 45.

To check that the PLL is in lock the user can

program register IOCFGx.GDOx_CFG to 0x0A

and use the lock detector output available on

the GDOx pin as an interrupt for the MCU (x =

0,1, or 2). A positive transition on the GDOx

pin means that the PLL is in lock. As an

alternative the user can read register FSCAL1.

The PLL is in lock if the register content is

different from 0x3F. Refer also to the CC1101

Errata Notes [1]. For more robust operation the

source code could include a check so that the

PLL is re-calibrated until PLL lock is achieved

if the PLL does not lock the first time.

The calibration can be initiated automatically

or manually. The synthesizer can be

automatically calibrated each time the

synthesizer is turned on, or each time the

synthesizer is turned off automatically. This is

configured with the MCSM0.FS_AUTOCAL

register setting. In manual mode, the

SWRS061B

Page 47 of 93

CC1101

23 Voltage Regulators

Setting the CSn pin low turns on the voltage

regulator to the digital core and starts the

crystal oscillator. The SO pin on the SPI

interface must go low before the first positive

edge of SCLK. (setup time is given in Table

16).

CC1101 contains several on-chip linear voltage

regulators, which generate the supply voltage

needed by low-voltage modules. These

voltage regulators are invisible to the user, and

can be viewed as integral parts of the various

modules. The user must however make sure

that the absolute maximum ratings and

required pin voltages in Table 1 and Table 13

are not exceeded. The voltage regulator for

the digital core requires one external

decoupling capacitor.

If the chip is programmed to enter power-down

mode, (SPWDstrobe issued), the power will be

turned off after CSn goes high. The power and

crystal oscillator will be turned on again when

CSn goes low.

The voltage regulator output should only be

used for driving the CC1101.

24 Output Power Programming

The RF output power level from the device

has two levels of programmability, as

illustrated in Figure 22. Firstly, the special

PATABLE register can hold up to eight user

selected output power settings. Secondly, the

3-bit FREND0.PA_POWER value selects the

PATABLE entry to use. This two-level

functionality provides flexible PA power ramp

up and ramp down at the start and end of

transmission, as well as ASK modulation

shaping. All the PA power settings in the

If OOK modulation is used, the logic 0 and

logic 1 power levels shall be programmed to

index 0 and 1 respectively.

Table 30 contains recommended PATABLE

settings for various output levels and

frequency bands. Using PA settings from 0x61

to 0x6F is not recommended. See Section

10.6 on page 27 for PATABLE programming

details.

Table 31 contains output power and current

consumption for default PATABLE setting

(0xC6). PATABLE must be programmed in

burst mode if you want to write to other entries

than PATABLE[0].

PATABLE

from index

0

up to the

FREND0.PA_POWERvalue are used.

The power ramping at the start and at the end

of a packet can be turned off by setting

FREND0.PA_POWER

program the desired output power to index 0 in

the PATABLE.

to zero and then

Note that all content of the PATABLE, except

for the first byte (index 0) is lost when entering

the SLEEP state.

SWRS061B

Page 48 of 93

CC1101

315 MHz

Current

433 MHz

Current

868 MHz

Current

915 MHz

Current

Output

Power

[dBm]

Setting Consumption, Setting Consumption, Setting Consumption, Setting Consumption,

Typ. [mA]

-30

-20

-15

-10

-5

0x12

0x0D

0x1C

0x34

0x69

0x51

0x85

0xCB

0xC2

10.9

0x12

0x0E

0x1D

0x34

0x68

0x60

0x84

0xC8

0xC0

11.9

0x03

0x0F

0x1E

0x27

0x67

0x50

0x81

0xCB

0xC2

12.1

0x03

0x0E

0x1E

0x27

0x39

0x8E

0xCD

0xC7

0xC0

12.0

11.4

12.4

12.7

12.6

12.0

13.1

13.4

13.5

14.4

15.0

14.9

12.8

13.8

14.4

17.7

0

15.0

15.9

16.9

16.7

5

18.3

19.4

21.0

24.3

7

22.1

24.2

26.8

26.9

10

26.9

29.1

32.4

31.8

Table 30: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands

315 MHz

433 MHz

868 MHz

915 MHz

Default Output Current

Output Current

Power

Setting [dBm]

Power

Consumption, Power

Typ. [mA] [dBm]

Consumption, Power

Typ. [mA] [dBm]

Consumption,

Typ. [mA]

[dBm]

0xC6 8.5

24.4

7.8

25.2 8.5

29.5 7.2

27.4

Table 31: Output Power and Current Consumption for Default PATABLE Setting

25 Shaping and PA Ramping

With ASK modulation, up to eight power

settings are used for shaping. The modulator

contains a counter that counts up when

transmitting a one and down when transmitting

a zero. The counter counts at a rate equal to 8

times the symbol rate. The counter saturates

at FREND0.PA_POWER and 0 respectively.

This counter value is used as an index for a

lookup in the power table. Thus, in order to

utilize the whole table, FREND0.PA_POWER

should be 7 when ASK is active. The shaping

of the ASK signal is dependent on the

configuration of the PATABLE.

Figure 23 shows some examples of ASK

shaping.

SWRS061B

Page 49 of 93

CC1101

PATABLE(7)[7:0]

PATABLE(6)[7:0]

PATABLE(5)[7:0]

PATABLE(4)[7:0]

PATABLE(3)[7:0]

PATABLE(2)[7:0]

PATABLE(1)[7:0]

PATABLE(0)[7:0]

The PA uses this

setting.

Settings 0 to PA_POWER are

used during ramp-up at start of

transmission and ramp-down at

end of transmission, and for

ASK/OOK modulation.

Index into PATABLE(7:0)

The SmartRF® Studio software

should be used to obtain optimum

PATABLE settings for various

output powers.

e.g 6

PA_POWER[2:0]

in FREND0 register

Figure 22: PA_POWERand PATABLE

Output Power

PATABLE[7]

PATABLE[6]

PATABLE[5]

PATABLE[4]

PATABLE[3]

PATABLE[2]

PATABLE[1]

PATABLE[0]

Time

1

0

1

0

1

0

Bit Sequence

FREND0.PA_POWER = 3

FREND0.PA_POWER = 7

Figure 23: Shaping of ASK Signal

SWRS061B

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CC1101

26 Selectivity

Figure 24 to Figure 26 show the typical selectivity performance (adjacent and alternate rejection).

50.0

40.0

30.0

20.0

10.0

0.0

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.4

0.5

-10.0

-20.0

Frequency offset [MHz]

Figure 24: Typical Selectivity at 1.2 kBaud Data Rate, 868 MHz, GFSK, 5.2 kHz Deviation. IF

Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz

50.0

40.0

30.0

20.0

10.0

0.0

-1.0 -0.8 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

0.1

0.2

0.4 0.5

0.8

1.0

-10.0

-20.0

Frequency offset [MHz]

Figure 25: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, GFSK, 20 kHz Deviation. IF

Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz

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CC1101

50.0

40.0

30.0

20.0

10.0

0.0

-3.00

-2.25

1.50

-1.00

-0.75

0.00

0.75

1.00

1.50

2.25

3.00

-10.0

-20.0

Frequency offset [MHz]

Figure 26: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 304kHz

and the Digital Channel Filter Bandwidth is 540 kHz

27 Crystal Oscillator

A crystal in the frequency range 26-27 MHz

must be connected between the XOSC_Q1

and XOSC_Q2 pins. The oscillator is designed

for parallel mode operation of the crystal. In

addition, loading capacitors (C81 and C101)

for the crystal are required. The loading

capacitor values depend on the total load

capacitance, C_L, specified for the crystal. The

total load capacitance seen between the

crystal terminals should equal C_Lfor the

crystal to oscillate at the specified frequency.

The crystal oscillator circuit is shown in Figure

27. Typical component values for different

values of C_Lare given in Table 32.

The crystal oscillator is amplitude regulated.

This means that a high current is used to start

up the oscillations. When the amplitude builds

up, the current is reduced to what is necessary

to maintain approximately 0.4 Vpp signal

swing. This ensures a fast start-up, and keeps

the drive level to a minimum. The ESR of the

crystal should be within the specification in

order to ensure a reliable start-up (see Section

4.4 on page 13).

1

C_L=

+ C_parasitic

1

+

C₈₁C₁₀₁

The initial tolerance, temperature drift, aging

and load pulling should be carefully specified

in order to meet the required frequency

accuracy in a certain application.

The parasitic capacitance is constituted by pin

input capacitance and PCB stray capacitance.

Total parasitic capacitance is typically 2.5 pF.

XOSC_Q1

XOSC_Q2

XTAL

C81

C101

Figure 27: Crystal Oscillator Circuit

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CC1101

Component

C81

C_L= 10 pF

15 pF

C_L= 13 pF

22 pF

C_L= 16 pF

27 pF

C101

15 pF

22 pF

27 pF

Table 32: Crystal Oscillator Component Values

27.1 Reference Signal

XOSC_Q1 input. The sine wave must be

connected to XOSC_Q1 using serial

a

The chip can alternatively be operated with a

reference signal from 26 to 27 MHz instead of

a crystal. This input clock can either be a full-

swing digital signal (0 V to VDD) or a sine

wave of maximum 1 V peak-peak amplitude.

The reference signal must be connected to the

capacitor. When using a full-swing digital

signal this capacitor can be omitted. The

XOSC_Q2 line must be left un-connected. C81

and C101 can be omitted when using a

reference signal.

28 External RF Match

The

passive

matching/filtering

network

The balanced RF input and output of CC1101

share two common pins and are designed for

a simple, low-cost matching and balun network

on the printed circuit board. The receive- and

transmit switching at the CC1101 front-end is

controlled by a dedicated on-chip function,

eliminating the need for an external RX/TX-

switch.

connected to CC1101 should have the following

differential impedance as seen from the RF-

port (RF_P and RF_N) towards the antenna:

Z

_{out 315 MHz}= 122 + j31 Ω

_{out 433 MHz}= 116 + j41 Ω

_{out 868/915 MHz}= 86.5 + j43 Ω

A few passive external components combined

with the internal RX/TX switch/termination

circuitry ensures match in both RX and TX

mode.

To ensure optimal matching of the CC1101

differential output it is recommended to follow

the CC1101EM reference design ([5] or [6]) as

closely as possible. Gerber files for the

reference designs are available for download

from the TI website.

Although CC1101 has

a

balanced RF

input/output, the chip can be connected to a

single-ended antenna with few external low

cost capacitors and inductors.

29 PCB Layout Recommendations

The top layer should be used for signal

routing, and the open areas should be filled

with metallization connected to ground using

several vias.

(splattering, solder balling). Using “tented” vias

reduces the solder paste coverage below

100%.

See Figure 28 for top solder resist and top

paste masks.

The area under the chip is used for grounding

and shall be connected to the bottom ground

plane with several vias. In the CC1101EM

reference designs ([5] and [6]) we have placed

5 vias inside the exposed die attached pad.

These vias should be “tented” (covered with

solder mask) on the component side of the

PCB to avoid migration of solder through the

vias during the solder reflow process.

Each decoupling capacitor should be placed

as close as possible to the supply pin it is

supposed to decouple. Each decoupling

capacitor should be connected to the power

line (or power plane) by separate vias. The

best routing is from the power line (or power

plane) to the decoupling capacitor and then to

the CC1101 supply pin. Supply power filtering is

very important.

The solder paste coverage should not be

100%. If it is, out gassing may occur during the

reflow process, which may cause defects

Each decoupling capacitor ground pad should

be connected to the ground plane using a

SWRS061B

Page 53 of 93

CC1101

separate via. Direct connections between

neighboring power pins will increase noise

coupling and should be avoided unless

absolutely necessary.

Precaution should be used when placing the

microcontroller in order to avoid noise

interfering with the RF circuitry.

A CC1101DK Development Kit with a fully

assembled CC1101EM Evaluation Module is

available. It is strongly advised that this

reference layout is followed very closely in

order to get the best performance. The

schematic, BOM and layout Gerber files are all

available from the TI website ([5] and [6]).

The external components should ideally be as

small as possible (0402 is recommended) and

surface

mount

devices

are

highly

recommended. Please note that components

smaller than those specified may have

differing characteristics.

Figure 28: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias

30 General Purpose / Test Output Control Pins

The three digital output pins GDO0, GDO1,

and GDO2 are general control pins configured

IOCFG0 register. The voltage on the GDO0

pin is then proportional to temperature. See

Section 4.7 on page 15 for temperature sensor

specifications.

with

IOCFG0.GDO0_CFG,

IOCFG1.GDO1_CFG, and IOCFG2.GDO3_CFG

respectively. Table 33 shows the different

signals that can be monitored on the GDO

pins. These signals can be used as inputs to

the MCU. GDO1 is the same pin as the SO pin

on the SPI interface, thus the output

programmed on this pin will only be valid when

CSn is high. The default value for GDO1 is 3-

stated, which is useful when the SPI interface

is shared with other devices.

If the IOCFGx.GDOx_CFG setting is less than

0x20 and IOCFGx_GDOx_INV is 0 (1), the

GDO0 and GDO2 pins will be hardwired to 0

(1) and the GDO1 pin will be hardwired to 1

(0) in the SLEEP state. These signals will be

hardwired until the CHIP_RDYn signal goes

low.

If the IOCFGx.GDOx_CFG setting is 0x20 or

higher the GDO pins will work as programmed

also in SLEEP state. As an example, GDO1 is

The default value for GDO0 is a 135-141 kHz

clock output (XOSC frequency divided by

192). Since the XOSC is turned on at power-

on-reset, this can be used to clock the MCU in

systems with only one crystal. When the MCU

is up and running, it can change the clock

frequency by writing to IOCFG0.GDO0_CFG.

high

impedance

in

all

states

if

IOCFG1.GDO1_CFG=0x2E.

An on-chip analog temperature sensor is

enabled by writing the value 128 (0x80) to the

SWRS061B

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CC1101

GDOx_CFG[5:0]

Description

Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

is drained below the same threshold.

Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is

reached. De-asserts when the RX FIFO is empty.

Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX

FIFO is below the same threshold.

Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO

threshold.

4 (0x04)

5 (0x05)

Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.

Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.

Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert

when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.

Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO.

Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.

Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To

check for PLL lock the lock detector output should be used as an interrupt for the MCU.

Serial Clock. Synchronous to the data in synchronous serial mode.

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B) In RX mode, data is set up on the falling edge by CC1101 when GDOx_INV=

0.

In TX mode, data is sampled by CC1101 on the rising edge of the serial clock when GDOx_INV=0.

12 (0x0C) Serial Synchronous Data Output. Used for synchronous serial mode.

13 (0x0D) Serial Data Output. Used for asynchronous serial mode.

14 (0x0E) Carrier sense. High if RSSI level is above threshold.

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

23 (0x17)

24 (0x18)

25 (0x19)

CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode.

Reserved – used for test.

RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.

RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.

Reserved – used for test.

26 (0x1A) Reserved – used for test.

PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch

27 (0x1B)

in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2Finstead.

LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX

switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2Finstead.

28 (0x1C)

29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.

30 (0x1E) Reserved – used for test.

31 (0x1F)

32 (0x20)

33 (0x21)

34 (0x22)

35 (0x23)

36 (0x24)

37 (0x25)

38 (0x26)

39 (0x27)

40 (0x28)

41 (0x29)

Reserved – used for test.

WOR_EVNT0

WOR_EVNT1

Reserved – used for test.

CLK_32k

Reserved – used for test.

CHIP_RDYn

42 (0x2A) Reserved – used for test.

43 (0x2B) XOSC_STABLE

44 (0x2C) Reserved – used for test.

45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).

46 (0x2E) High impedance (3-state)

47 (0x2F)

48 (0x30)

49 (0x31)

50 (0x32)

51 (0x33)

52 (0x34)

53 (0x35)

54 (0x36)

55 (0x37)

56 (0x38)

57 (0x39)

HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch.

CLK_XOSC/1

CLK_XOSC/1.5

CLK_XOSC/2

CLK_XOSC/3

CLK_XOSC/4

Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any

CLK_XOSC/6

time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must

CLK_XOSC/8

be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.

CLK_XOSC/12

CLK_XOSC/16

CLK_XOSC/24

To optimize rf performance, these signal should not be used while the radio is in RX or TX mode.

58 (0x3A) CLK_XOSC/32

59 (0x3B) CLK_XOSC/48

60 (0x3C) CLK_XOSC/64

61 (0x3D) CLK_XOSC/96

62 (0x3E) CLK_XOSC/128

63 (0x3F)

CLK_XOSC/192

Table 33: GDOx Signal Selection (x = 0, 1, or 2)

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CC1101

31 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have

been included in the CC1101 to provide

backward compatibility with previous Chipcon

products and other existing RF communication

systems. For new systems, it is recommended

to use the built-in packet handling features, as

they can give more robust communication,

significantly offload the microcontroller, and

simplify software development.

for the asynchronous stream is that the error in

the bit period must be less than one eighth of

the programmed data rate.

31.2 Synchronous Serial Operation

Setting

PKTCTRL0.PKT_FORMAT

to

1

enables synchronous serial mode. In the

synchronous serial mode, data is transferred

on a two wire serial interface. The CC1101

provides a clock that is used to set up new

data on the data input line or sample data on

the data output line. Data input (TX data) is the

GDO0 pin. This pin will automatically be

configured as an input when TX is active. The

data output pin can be any of the GDO pins;

this is set by the IOCFG0.GDO0_CFG,

IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG

fields.

31.1 Asynchronous Operation

For backward compatibility with systems

already using the asynchronous data transfer

from other Chipcon products, asynchronous

transfer is also included in CC1101. When

asynchronous transfer is enabled, several of

the support mechanisms for the MCU that are

included in CC1101 will be disabled, such as

packet handling hardware, buffering in the

FIFO, and so on. The asynchronous transfer

mode does not allow the use of the data

whitener, interleaver, and FEC, and it is not

possible to use Manchester encoding.

Preamble and sync word insertion/detection

may or may not be active, dependent on the

sync mode set by the MDMCFG2.SYNC_MODE.

If preamble and sync word is disabled, all

other packet handler features and FEC should

also be disabled. The MCU must then handle

preamble and sync word insertion and

detection in software. If preamble and sync

word insertion/detection is left on, all packet

handling features and FEC can be used. One

exception is that the address filtering feature is

unavailable in synchronous serial mode.

Note that MSK is not supported for

asynchronous transfer.

Setting

PKTCTRL0.PKT_FORMAT

to

3

enables asynchronous serial mode.

In TX, the GDO0 pin is used for data input (TX

data). Data output can be on GDO0, GDO1, or

GDO2. This is set by the IOCFG0.GDO0_CFG,

IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG

fields.

When using the packet handling features in

synchronous serial mode, the CC1101 will insert

and detect the preamble and sync word and

the MCU will only provide/get the data

The CC1101 modulator samples the level of the

asynchronous input 8 times faster than the

programmed data rate. The timing requirement

payload.

This

is

equivalent

to

the

recommended FIFO operation mode.

32 System Considerations and Guidelines

32.1 SRD Regulations

part 15 (USA). A summary of the most

important aspects of these regulations can be

found in Application Note AN001 [2].

International regulations and national laws

regulate the use of radio receivers and

transmitters. Short Range Devices (SRDs) for

license free operation below 1 GHz are usually

operated in the 433 MHz, 868 MHz or 915

MHz frequency bands. The CC1101 is

specifically designed for such use with its 300 -

348 MHz, 387 - 464 MHz, and 779 - 928 MHz

operating ranges. The most important

regulations when using the CC1101 in the 433

MHz, 868 MHz, or 915 MHz frequency bands

are EN 300 220 (Europe) and FCC CFR47

Please note that compliance with regulations is

dependent on complete system performance.

It is the customer’s responsibility to ensure that

the system complies with regulations.

SWRS061B

Page 56 of 93

CC1101

32.2 Frequency Hopping and Multi-

Channel Systems

time is reduced from approximately 720 µs to

approximately 150 µs. The blanking interval

between each frequency hop is then

approximately 240 us.

The 433 MHz, 868 MHz, or 915 MHz bands

are shared by many systems both in industrial,

office, and home environments. It is therefore

recommended to use frequency hopping

spread spectrum (FHSS) or a multi-channel

protocol because the frequency diversity

makes the system more robust with respect to

interference from other systems operating in

the same frequency band. FHSS also combats

multipath fading.

There is a trade off between blanking time and

memory space needed for storing calibration

data in non-volatile memory. Solution 2) above

gives the shortest blanking interval, but

requires more memory space to store

calibration

values.

Solution

3)

gives

approximately 570 µs smaller blanking interval

than solution 1).

Note that the recommended settings for

TEST0.VCO_SEL_CAL_EN will change with

frequency. This means that one should always

use SmartRF^®Studio [7] to get the correct

settings for a specific frequency before doing a

calibration, regardless of which calibration

method is being used.

CC1101 is highly suited for FHSS or multi-

channel systems due to its agile frequency

synthesizer and effective communication

interface. Using the packet handling support

and data buffering is also beneficial in such

systems as these features will significantly

offload the host controller.

Charge pump current, VCO current, and VCO

capacitance array calibration data is required

for each frequency when implementing

frequency hopping for CC1101. There are 3

ways of obtaining the calibration data from the

chip:

It must be noted that the TESTn registers (n=

0, 1, or 2) content is not retained in SLEEP

state, and thus it is necessary to re-write these

registers when returning from the SLEEP

state.

1) Frequency hopping with calibration for each

hop. The PLL calibration time is approximately

720 µs. The blanking interval between each

frequency hop is then approximately 810 us.

32.3 Wideband Modulation not using

Spread Spectrum

Digital modulation systems under FFC part

15.247 includes 2-FSK and GFSK modulation.

A maximum peak output power of 1W (+30

dBm) is allowed if the 6 dB bandwidth of the

modulated signal exceeds 500 kHz. In

addition, the peak power spectral density

conducted to the antenna shall not be greater

than +8 dBm in any 3 kHz band.

2) Fast frequency hopping without calibration

for each hop can be done by calibrating each

frequency at startup and saving the resulting

FSCAL3, FSCAL2, and FSCAL1register values

in MCU memory. Between each frequency

hop, the calibration process can then be

replaced by writing the FSCAL3, FSCAL2and

FSCAL1 register values corresponding to the

next RF frequency. The PLL turn on time is

approximately 90 µs. The blanking interval

between each frequency hop is then

approximately 90 us. The VCO current

calibration result available in FSCAL2 is not

dependent on the RF frequency. Neither is the

charge pump current calibration result

available in FSCAL3. The same value can

therefore be used for all frequencies.

Operating at high data rates and frequency

separation, the CC1101 is suited for systems

targeting compliance with digital modulation

system as defined by FFC part 15.247. An

external power amplifier is needed to increase

the output above +10 dBm.

32.4 Data Burst Transmissions

The high maximum data rate of CC1101 opens

up for burst transmissions. A low average data

rate link (e.g. 10 kBaud), can be realized using

a higher over-the-air data rate. Buffering the

data and transmitting in bursts at high data

rate (e.g. 500 kBaud) will reduce the time in

active mode, and hence also reduce the

average current consumption significantly.

Reducing the time in active mode will reduce

the likelihood of collisions with other systems

in the same frequency range.

3) Run calibration on a single frequency at

startup. Next write 0 to FSCAL3[5:4] to

disable the charge pump calibration. After

writing to FSCAL3[5:4] strobe SRX (or STX)

with MCSM0.FS_AUTOCAL=1 for each new

frequency hop. That is, VCO current and VCO

capacitance calibration is done but not charge

pump current calibration. When charge pump

current calibration is disabled the calibration

SWRS061B

Page 57 of 93

CC1101

32.5 Continuous Transmissions

32.8 Low Cost Systems

In data streaming applications the CC1101

opens up for continuous transmissions at 500

kBaud effective data rate. As the modulation is

done with a closed loop PLL, there is no

limitation in the length of a transmission (open

loop modulation used in some transceivers

often prevents this kind of continuous data

streaming and reduces the effective data rate).

As the CC1101 provides 500 kBaud multi-

channel performance without any external

filters, a very low cost system can be made.

A differential antenna will eliminate the need

for a balun, and the DC biasing can be

achieved in the antenna topology, see Figure 3

and Figure 4.

A HC-49 type SMD crystal is used in the

CC1101EM reference designs ([5] and [6]).

Note that the crystal package strongly

influences the price. In a size constrained PCB

design a smaller, but more expensive, crystal

may be used.

32.6 Crystal Drift Compensation

The CC1101 has

a

very fine frequency

resolution (see Table 9). This feature can be

used to compensate for frequency offset and

drift.

32.9 Battery Operated Systems

The frequency offset between an ‘external’

transmitter and the receiver is measured in the

CC1101 and can be read back from the

FREQEST status register as described in

Section 14.1. The measured frequency offset

can be used to calibrate the frequency using

the ‘external’ transmitter as the reference. That

is, the received signal of the device will match

the receiver’s channel filter better. In the same

way the centre frequency of the transmitted

signal will match the ‘external’ transmitter’s

signal.

In low power applications, the SLEEP state

with the crystal oscillator core switched off

should be used when the CC1101 is not active.

It is possible to leave the crystal oscillator core

running in the SLEEP state if start-up time is

critical.

The WOR functionality should be used in low

power applications.

32.10 Increasing Output Power

In some applications it may be necessary to

extend the link range. Adding an external

power amplifier is the most effective way of

doing this.

32.7 Spectrum Efficient Modulation

CC1101 also has the possibility to use Gaussian

shaped 2-FSK (GFSK). This spectrum-shaping

feature improves adjacent channel power

(ACP) and occupied bandwidth. In ‘true’ 2-FSK

systems with abrupt frequency shifting, the

spectrum is inherently broad. By making the

frequency shift ‘softer’, the spectrum can be

made significantly narrower. Thus, higher data

rates can be transmitted in the same

bandwidth using GFSK.

The power amplifier should be inserted

between the antenna and the balun, and two

T/R switches are needed to disconnect the PA

in RX mode. See Figure 29.

Antenna

Filter

P

A

Balun

CC1101

T/R

switch

T/R

switch

Figure 29: Block Diagram of CC1101 Usage with External Power Amplifier

SWRS061B

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CC1101

33 Configuration Registers

There are also 12 Status registers, which are

listed in Table 36. These registers, which are

read-only, contain information about the status

of CC1101.

The configuration of CC1101 is done by

programming 8-bit registers. The optimum

configuration data based on selected system

parameters are most easily found by using the

SmartRF^®Studio software [7]. Complete

descriptions of the registers are given in the

following tables. After chip reset, all the

registers have default values as shown in the

tables. The optimum register setting might

differ from the default value. After a reset all

registers that shall be different from the default

value therefore needs to be programmed

through the SPI interface.

The two FIFOs are accessed through one 8-bit

register. Write operations write to the TX FIFO,

while read operations read from the RX FIFO.

During the header byte transfer and while

writing data to a register or the TX FIFO, a

status byte is returned on the SO line. This

status byte is described in Table 17 on page

25.

Table 37 summarizes the SPI address space.

The address to use is given by adding the

base address to the left and the burst and

read/write bits on the top. Note that the burst

bit has different meaning for base addresses

above and below 0x2F.

There are 13 command strobe registers, listed

in Table 34. Accessing these registers will

initiate the change of an internal state or

mode. There are 47 normal 8-bit configuration

registers, listed in Table 35. Many of these

registers are for test purposes only, and need

not be written for normal operation of CC1101.

Address

Strobe

Name

Description

0x30

0x31

SRES

Reset chip.

SFSTXON

Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):

Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).

0x32

0x33

SXOFF

SCAL

Turn off crystal oscillator.

Calibrate frequency synthesizer and turn it off. SCALcan be strobed from IDLE mode without

setting manual calibration mode (MCSM0.FS_AUTOCAL=0)

0x34

0x35

SRX

STX

Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.

In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.

If in RX state and CCA is enabled: Only go to TX if channel is clear.

0x36

0x38

SIDLE

SWOR

Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.

Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if

WORCTRL.RC_PD=0.

0x39

0x3A

0x3B

0x3C

0x3D

SPWD

SFRX

SFTX

Enter power down mode when CSn goes high.

Flush the RX FIFO buffer. Only issue SFRXin IDLE or RXFIFO_OVERFLOW states.

Flush the TX FIFO buffer. Only issue SFTXin IDLE or TXFIFO_UNDERFLOW states.

SWORRST Reset real time clock to Event1 value.

SNOP No operation. May be used to get access to the chip status byte.

Table 34: Command Strobes

SWRS061B

Page 59 of 93

CC1101

Preserved in

SLEEP State

Details on

Page Number

Address

Register

Description

Yes

63

GDO2output pin configuration

GDO1output pin configuration

0x00

0x01

IOCFG2

IOCFG1

63

GDO0output pin configuration

RX FIFO and TX FIFO thresholds

Sync word, high byte

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

IOCFG0

FIFOTHR

SYNC1

Yes

No

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

SYNC0

Sync word, low byte

PKTLEN

Packet length

PKTCTRL1 Packet automation control

PKTCTRL0 Packet automation control

ADDR

CHANNR

FSCTRL1

FSCTRL0

FREQ2

Device address

Channel number

Frequency synthesizer control

Frequency control word, high byte

Frequency control word, middle byte

Frequency control word, low byte

FREQ1

FREQ0

MDMCFG4 Modem configuration

MDMCFG3 Modem configuration

MDMCFG2 Modem configuration

MDMCFG1 Modem configuration

MDMCFG0 Modem configuration

DEVIATN

MCSM2

Modem deviation setting

Main Radio Control State Machine configuration

Frequency Offset Compensation configuration

Bit Synchronization configuration

AGC control

MCSM1

MCSM0

FOCCFG

BSCFG

AGCTRL2

AGCTRL1

AGCTRL0

AGC control

WOREVT1 High byte Event 0 timeout

WOREVT0 Low byte Event 0 timeout

WORCTRL Wake On Radio control

FREND1

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

RCCTRL1

RCCTRL0

FSTEST

PTEST

Front end RX configuration

Front end TX configuration

Frequency synthesizer calibration

RC oscillator configuration

Frequency synthesizer calibration control

Production test

No

AGCTEST

TEST2

AGC test

No

Various test settings

No

TEST1

Various test settings

No

TEST0

Various test settings

No

Table 35: Configuration Registers Overview

SWRS061B

Page 60 of 93

CC1101

Address

Register

PARTNUM

VERSION

FREQEST

LQI

Description

Details on page number

84

85

86

0x30 (0xF0)

0x31 (0xF1)

0x32 (0xF2)

0x33 (0xF3)

0x34 (0xF4)

0x35 (0xF5)

0x36 (0xF6)

0x37 (0xF7)

0x38 (0xF8)

Part number for CC1101

Current version number

Frequency Offset Estimate

Demodulator estimate for Link Quality

Received signal strength indication

Control state machine state

High byte of WOR timer

RSSI

MARCSTATE

WORTIME1

WORTIME0

PKTSTATUS

Low byte of WOR timer

Current GDOx status and packet status

Current setting from PLL calibration

module

0x39 (0xF9)

0x3A (0xFA)

0x3B (0xFB)

VCO_VC_DAC

TXBYTES

Underflow and number of bytes in the TX

FIFO

86

Overflow and number of bytes in the RX

FIFO

RXBYTES

0x3C (0xFC) RCCTRL1_STATUS Last RC oscillator calibration result

0x3D (0xFD) RCCTRL0_STATUS Last RC oscillator calibration result

86

87

Table 36: Status Registers Overview

SWRS061B

Page 61 of 93

CC1101

Write

Single Byte

+0x00

Read

Burst

+0x40

Single Byte

+0x80

Burst

+0xC0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

IOCFG2

IOCFG1

IOCFG0

FIFOTHR

SYNC1

SYNC0

PKTLEN

PKTCTRL1

PKTCTRL0

ADDR

CHANNR

FSCTRL1

FSCTRL0

FREQ2

FREQ1

FREQ0

MDMCFG4

MDMCFG3

MDMCFG2

MDMCFG1

MDMCFG0

DEVIATN

MCSM2

MCSM1

MCSM0

FOCCFG

BSCFG

AGCCTRL2

AGCCTRL1

AGCCTRL0

WOREVT1

WOREVT0

WORCTRL

FREND1

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

RCCTRL1

RCCTRL0

FSTEST

PTEST

AGCTEST

TEST2

TEST1

TEST0

SRES

SFSTXON

SXOFF

SCAL

SRX

STX

SIDLE

SRES

PARTNUM

VERSION

FREQEST

LQI

SFSTXON

SXOFF

SCAL

SRX

STX

SIDLE

RSSI

MARCSTATE

WORTIME1

WORTIME0

PKTSTATUS

VCO_VC_DAC

TXBYTES

SWOR

SPWD

SFRX

SFTX

SWORRST

SNOP

SWOR

SPWD

SFRX

SFTX

RXBYTES

SWORRST RCCTRL1_STATUS

SNOP

PATABLE

RX FIFO

RCCTRL0_STATUS

PATABLE

TX FIFO

PATABLE

TX FIFO

RX FIFO

SWRS061B

Page 62 of 93

CC1101

Table 37: SPI Address Space

33.1 Configuration Register Details – Registers with preserved values in SLEEP state

0x00: IOCFG2 – GDO2Output Pin Configuration

Bit

Field Name

Reset

R/W

Description

7

6

Reserved

R0

0

R/W

Invert output, i.e. select active low (1) / high (0)

GDO2_INV

GDO2_CFG[5:0]

5:0

41 (0x29)

R/W

Default is CHP_RDYn(See Table 33 on page 55).

0x01: IOCFG1 – GDO1Output Pin Configuration

Bit

Field Name

Reset

R/W

Description

7

6

GDO_DS

0

R/W

Set high (1) or low (0) output drive strength on the GDO pins.

Invert output, i.e. select active low (1) / high (0)

GDO1_INV

GDO1_CFG[5:0]

5:0

46 (0x2E)

R/W

Default is 3-state (See Table 33 on page 55).

0x02: IOCFG0 – GDO0Output Pin Configuration

Bit

Field Name

Reset

R/W

Description

7

TEMP_SENSOR_ENABLE

0

R/W

Enable analog temperature sensor. Write 0 in all other register

bits when using temperature sensor.

6

0

R/W

Invert output, i.e. select active low (1) / high (0)

GDO0_INV

5:0

63 (0x3F)

Default is CLK_XOSC/192 (See Table 33 on page 55).

GDO0_CFG[5:0]

It is recommended to disable the clock output in initialization,

in order to optimize RF performance.

SWRS061B

Page 63 of 93

CC1101

0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds

Bit

Field Name

Reset

R/W

Description

7:6

6

Reserved

0

R/W

Write 0 for compatibility with possible future extensions

ADC_RETENTION

0: TEST1 = 0x31 and TEST2 = 0x88 when waking up from SLEEP

1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP

For more details, please see DN010 [10]

5:4

CLOSE_IN_RX [1:0]

0 (00)

R/W

Setting RX Attenuation, Typical Values

0 (00)

1 (01)

2 (10)

3 (11)

0dB

6dB

12dB

18dB

3:0

FIFO_THR[3:0]

7 (0111)

R/W

Set the threshold for the TX FIFO and RX FIFO. The threshold is

exceeded when the number of bytes in the FIFO is equal to or higher

than the threshold value.

Setting

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Bytes in TX FIFO

Bytes in RX FIFO

61

57

53

49

45

41

37

33

29

25

21

17

13

9

4

8

12

16

20

24

28

32

36

40

44

48

52

56

60

64

5

1

0x04: SYNC1 – Sync Word, High Byte

Bit

Field Name

Reset

R/W

Description

7:0

SYNC[15:8]

211 (0xD3)

R/W

8 MSB of 16-bit sync word

0x05: SYNC0 – Sync Word, Low Byte

Bit

Field Name

Reset

R/W

Description

7:0

SYNC[7:0]

145 (0x91)

R/W

8 LSB of 16-bit sync word

SWRS061B

Page 64 of 93

CC1101

0x06: PKTLEN – Packet Length

Bit

Field Name

Reset

R/W

Description

7:0

PACKET_LENGTH 255 (0xFF)

R/W

Indicates the packet length when fixed packet length mode is enabled.

If variable packet length mode is used, this value indicates the

maximum packet length allowed.

0x07: PKTCTRL1 – Packet Automation Control

Bit

Field Name

Reset

R/W

Description

7:5

PQT[2:0]

0 (0x00)

R/W

Preamble quality estimator threshold. The preamble quality estimator

increases an internal counter by one each time a bit is received that is

different from the previous bit, and decreases the counter by 8 each time

a bit is received that is the same as the last bit.

A threshold of 4·PQTfor this counter is used to gate sync word detection.

When PQT=0 a sync word is always accepted.

4

3

Reserved

0

R0

CRC_AUTOFLUSH

R/W

Enable automatic flush of RX FIFO when CRC in not OK. This requires

that only one packet is in the RXIFIFO and that packet length is limited to

the RX FIFO size.

2

APPEND_STATUS

ADR_CHK[1:0]

1

R/W

When enabled, two status bytes will be appended to the payload of the

packet. The status bytes contain RSSI and LQI values, as well as CRC

OK.

1:0

0 (00)

Controls address check configuration of received packages.

Setting Address check configuration

0 (00)

1 (01)

2 (10)

3 (11)

No address check

Address check, no broadcast

Address check and 0 (0x00) broadcast

Address check and 0 (0x00) and 255 (0xFF)

broadcast

SWRS061B

Page 65 of 93

CC1101

0x08: PKTCTRL0 – Packet Automation Control

Bit Field Name

Reset

R/W Description

7

6

Reserved

R0

WHITE_DATA

1

R/W Turn data whitening on / off

0: Whitening off

1: Whitening on

5:4 PKT_FORMAT[1:0]

0 (00)

R/W Format of RX and TX data

Setting Packet format

0 (00)

1 (01)

Normal mode, use FIFOs for RX and TX

Synchronous serial mode, used for backwards

compatibility. Data in on GDO0

Random TX mode; sends random data using PN9

generator. Used for test.

Works as normal mode, setting 0 (00), in RX.

2 (10)

3 (11)

Asynchronous serial mode. Data in on GDO0 and

Data out on either of the GDO0 pins

3

2

Reserved

CRC_EN

0

1

R0

R/W 1: CRC calculation in TX and CRC check in RX enabled

0: CRC disabled for TX and RX

1:0 LENGTH_CONFIG[1:0]

1 (01)

R/W Configure the packet length

Setting Packet length configuration

0 (00)

Fixed packet length mode. Length configured in

PKTLENregister

1 (01)

Variable packet length mode. Packet length

configured by the first byte after sync word

2 (10)

3 (11)

Infinite packet length mode

Reserved

0x09: ADDR – Device Address

Bit Field Name

Reset

R/W Description

7:0 DEVICE_ADDR[7:0]

0 (0x00)

R/W Address used for packet filtration. Optional broadcast addresses are 0

(0x00) and 255 (0xFF).

0x0A: CHANNR – Channel Number

Bit Field Name

Reset

0 (0x00)

R/W Description

7:0 CHAN[7:0]

R/W The 8-bit unsigned channel number, which is multiplied by the

channel spacing setting and added to the base frequency.

SWRS061B

Page 66 of 93

CC1101

0x0B: FSCTRL1 – Frequency Synthesizer Control

Bit

Field Name

Reset

R/W

Description

7:5

4:0

Reserved

R0

FREQ_IF[4:0]

15 (0x0F)

R/W

The desired IF frequency to employ in RX. Subtracted from FS base

frequency in RX and controls the digital complex mixer in the demodulator.

f_XOSC

2¹⁰

f_IF

=

⋅ FREQ _ IF

The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz

crystal.

0x0C: FSCTRL0 – Frequency Synthesizer Control

Bit

Field Name

Reset

R/W

Description

7:0

FREQOFF[7:0]

0 (0x00)

R/W

Frequency offset added to the base frequency before being used by the

frequency synthesizer. (2s-complement).

Resolution is F_XTAL/2¹⁴(1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz,

dependent of XTAL frequency.

0x0D: FREQ2 – Frequency Control Word, High Byte

Bit

Field Name

Reset

R/W

Description

7:6

FREQ[23:22]

0 (00)

R

FREQ[23:22]is always 0 (the FREQ2register is less than 36 with 26-27

MHz crystal)

5:0

FREQ[21:16]

30 (0x1E)

R/W

FREQ[23:22]is the base frequency for the frequency synthesiser in

increments of F_XOSC/2¹⁶.

f_XOSC

2¹⁶

f_carrier

=

⋅ FREQ

[23 : 0

]

0x0E: FREQ1 – Frequency Control Word, Middle Byte

Bit

Field Name

Reset

R/W

Description

7:0

FREQ[15:8]

196 (0xC4) R/W

Ref. FREQ2register

0x0F: FREQ0 – Frequency Control Word, Low Byte

Bit Field Name

Reset

R/W

Description

7:0 FREQ[7:0]

236 (0xEC) R/W

Ref. FREQ2register

SWRS061B

Page 67 of 93

CC1101

0x10: MDMCFG4 – Modem Configuration

Bit Field Name

Reset

R/W

Description

7:6 CHANBW_E[1:0]

5:4 CHANBW_M[1:0]

2 (0x02)

0 (0x00)

R/W

Sets the decimation ratio for the delta-sigma ADC input stream and thus

the channel bandwidth.

f_XOSC

BW_channel

=

8⋅(4 + CHANBW _ M )·2^{CHANBW _ E}

The default values give 203 kHz channel filter bandwidth, assuming a 26.0

MHz crystal.

3:0 DRATE_E[3:0]

12 (0x0C)

R/W

The exponent of the user specified symbol rate

0x11: MDMCFG3 – Modem Configuration

Bit Field Name

Reset

R/W

Description

7:0 DRATE_M[7:0]

34 (0x22)

R/W

The mantissa of the user specified symbol rate. The symbol rate is

configured using an unsigned, floating-point number with 9-bit mantissa

and 4-bit exponent. The 9^thbit is a hidden ‘1’. The resulting data rate is:

(

256 + DRATE _ M

⋅2^{DRATE _ E}

)

R_DATA

=

⋅ f_XOSC

2²⁸

The default values give a data rate of 115.051 kBaud (closest setting to

115.2 kBaud), assuming a 26.0 MHz crystal.

SWRS061B

Page 68 of 93

CC1101

0x12: MDMCFG2 – Modem Configuration

Bit Field Name

DEM_DCFILT_OFF

Reset

R/W

Description

7

0

R/W

Disable digital DC blocking filter before demodulator.

0 = Enable (better sensitivity)

1 = Disable (current optimized). Only for data rates

≤ 250 kBaud

The recommended IF frequency changes when the DC blocking is

disabled. Please use SmartRF^®Studio [7] to calculate correct register

setting.

6:4 MOD_FORMAT[2:0] 0 (000)

R/W

The modulation format of the radio signal

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Modulation format

2-FSK

GFSK

-

ASK/OOK

-

MSK

ASK is only supported for output powers up to -1 dBm

MSK is only supported for datarates above 26 kBaud

Enables Manchester encoding/decoding.

0 = Disable

3

MANCHESTER_EN

0

R/W

1 = Enable

2:0 SYNC_MODE[2:0]

2 (010)

Combined sync-word qualifier mode.

The values 0 (000) and 4 (100) disables preamble and sync word

transmission in TX and preamble and sync word detection in RX.

The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word

transmission in TX and 16-bits sync word detection in RX. Only 15 of 16

bits need to match in RX when using setting 1 (001) or 5 (101). The values

3 (011) and 7 (111) enables repeated sync word transmission in TX and

32-bits sync word detection in RX (only 30 of 32 bits need to match).

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

Sync-word qualifier mode

No preamble/sync

15/16 sync word bits detected

16/16 sync word bits detected

30/32 sync word bits detected

No preamble/sync, carrier-sense

above threshold

5 (101)

6 (110)

7 (111)

15/16 + carrier-sense above threshold

16/16 + carrier-sense above threshold

30/32 + carrier-sense above threshold

SWRS061B

Page 69 of 93

CC1101

0x13: MDMCFG1– Modem Configuration

Bit

Field Name

Reset

R/W

Description

7

FEC_EN

0

R/W

Enable Forward Error Correction (FEC) with interleaving for

packet payload

0 = Disable

1 = Enable (Only supported for fixed packet length mode, i.e.

PKTCTRL0.LENGTH_CONFIG=0)

6:4

NUM_PREAMBLE[2:0]

2 (010)

R/W

Sets the minimum number of preamble bytes to be transmitted

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Number of preamble bytes

2

3

4

6

8

12

16

24

3:2

1:0

Reserved

R0

CHANSPC_E[1:0]

2 (10)

R/W

2 bit exponent of channel spacing

0x14: MDMCFG0– Modem Configuration

Bit

Field Name

Reset

R/W

Description

7:0

CHANSPC_M[7:0]

248 (0xF8)

R/W

8-bit mantissa of channel spacing. The channel spacing is

multiplied by the channel number CHANand added to the base

frequency. It is unsigned and has the format:

f_XOSC

2¹⁸

∆f_CHANNEL

=

⋅

(

256 + CHANSPC _ M

⋅2^{CHANSPC _ E}

)

The default values give 199.951 kHz channel spacing (the

closest setting to 200 kHz), assuming 26.0 MHz crystal

frequency.

SWRS061B

Page 70 of 93

CC1101

0x15: DEVIATN – Modem Deviation Setting

Bit Field Name

Reset

R/W

Description

7

Reserved

6:4 DEVIATION_E[2:0]

Reserved

2:0 DEVIATION_M[2:0]

R0

4 (0x04)

7 (111)

R/W

R0

Deviation exponent

3

R/W

When MSK modulation is enabled:

Sets fraction of symbol period used for phase change. Refer to the

SmartRF^®Studio software [7] for correct deviation setting when using

MSK.

When 2-FSK/GFSK modulation is enabled:

Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The

resulting frequency deviation is given by:

f_xosc

2¹⁷

f_dev

=

⋅(8 + DEVIATION _ M )⋅2^{DEVIATION _ E}

The default values give ±47.607 kHz deviation, assuming 26.0 MHz crystal

frequency.

SWRS061B

Page 71 of 93

CC1101

0x16: MCSM2 – Main Radio Control State Machine Configuration

Bit Field Name

Reset

R/W

Description

7:5 Reserved

R0

Reserved

4

RX_TIME_RSSI

0

R/W

Direct RX termination based on RSSI measurement (carrier sense). For

ASK/OOK modulation, RX times out if there is no carrier sense in the first 8

symbol periods.

3

RX_TIME_QUAL

R/W

When the RX_TIMEtimer expires, the chip checks if sync word is found

when RX_TIME_QUAL=0, or either sync word is found or PQI is set when

RX_TIME_QUAL=1.

2:0 RX_TIME[2:0]

7 (111)

Timeout for sync word search in RX for both WOR mode and normal RX

operation. The timeout is relative to the programmed EVENT0timeout.

The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is

the crystal oscillator frequency in MHz:

Setting WOR_RES = 0

0 (000) 3.6058

WOR_RES = 1

18.0288

9.0144

WOR_RES = 2

32.4519

16.2260

8.1130

WOR_RES = 3

46.8750

23.4375

11.7188

5.8594

1 (001) 1.8029

2 (010) 0.9014

4.5072

3 (011) 0.4507

2.2536

4.0565

4 (100) 0.2254

1.1268

2.0282

2.9297

5 (101) 0.1127

0.5634

1.0141

1.4648

6 (110) 0.0563

0.2817

0.5071

0.7324

7 (111) Until end of packet

As an example, EVENT0=34666, WOR_RES=0and RX_TIME=6corresponds to 1.96 ms RX timeout, 1 s polling interval

and 0.195% duty cycle. Note that WOR_RESshould be 0 or 1 when using WOR because using WOR_RES> 1 will give a

very low duty cycle. In applications where WOR is not used all settings of WOR_REScan be used.

The duty cycle using WOR is approximated by:

WOR_RES=0

WOR_RES=1

1.95%

9765ppm

4883ppm

2441ppm

NA

Setting

0 (000) 12.50%

1 (001) 6.250%

2 (010) 3.125%

3 (011) 1.563%

4 (100) 0.781%

5 (101) 0.391%

6 (110) 0.195%

7 (111) NA

NA

Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator

periods. WOR mode does not need to be enabled.

The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0,

decreasing to the 7MSBs of EVENT0 with RX_TIME=6.

SWRS061B

Page 72 of 93

CC1101

0x17: MCSM1– Main Radio Control State Machine Configuration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:4 CCA_MODE[1:0]

3 (11)

R/W

Selects CCA_MODE; Reflected in CCA signal

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Clear channel indication

Always

If RSSI below threshold

Unless currently receiving a packet

If RSSI below threshold unless currently

receiving a packet

3:2 RXOFF_MODE[1:0]

0 (00)

R/W

Select what should happen when a packet has been received

Setting

0 (00)

Next state after finishing packet reception

IDLE

FSTXON

TX

1 (01)

2 (10)

3 (11)

Stay in RX

It is not possible to set RXOFF_MODEto be TX or FSTXON and at the same

time use CCA.

1:0 TXOFF_MODE[1:0]

0 (00)

R/W

Select what should happen when a packet has been sent (TX)

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Next state after finishing packet transmission

IDLE

FSTXON

Stay in TX (start sending preamble)

RX

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CC1101

0x18: MCSM0– Main Radio Control State Machine Configuration

Bit

Field Name

Reset

R/W

Description

7:6

5:4

Reserved

R0

FS_AUTOCAL[1:0]

0 (00)

R/W

Automatically calibrate when going to RX or TX, or back to IDLE

Setting When to perform automatic calibration

0 (00)

1 (01)

Never (manually calibrate using SCALstrobe)

When going from IDLE to RX or TX (or FSTXON)

When going from RX or TX back to IDLE

automatically

2 (10)

3 (11)

Every 4^thtime when going from RX or TX to IDLE

automatically

In some automatic wake-on-radio (WOR) applications, using setting 3 (11)

can significantly reduce current consumption.

3:2

PO_TIMEOUT

1 (01)

R/W

Programs the number of times the six-bit ripple counter must expire after

XOSC has stabilized before CHP_RDYngoes low.

If XOSC is on (stable) during power-down, PO_TIMEOUTshould be set so

that the regulated digital supply voltage has time to stabilize before

CHP_RDYngoes low (PO_TIMEOUT=2recommended). Typical start-up

time for the voltage regulator is 50 us.

If XOSC is off during power-down and the regulated digital supply voltage

has sufficient time to stabilize while waiting for the crystal to be stable,

PO_TIMEOUTcan be set to 0. For robust operation it is recommended to

use PO_TIMEOUT=2.

Setting Expire count

Timeout after XOSC start

Approx. 2.3 – 2.4 µs

Approx. 37 – 39 µs

0 (00)

1 (01)

2 (10)

3 (11)

1

16

64

256

Approx. 149 – 155 µs

Approx. 597 – 620 µs

Exact timeout depends on crystal frequency.

Enables the pin radio control option

1

0

PIN_CTRL_EN

0

R/W

XOSC_FORCE_ON

Force the XOSC to stay on in the SLEEP state.

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CC1101

0x19: FOCCFG – Frequency Offset Compensation Configuration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5

FOC_BS_CS_GATE

1

R/W

If set, the demodulator freezes the frequency offset compensation and clock

recovery feedback loops until the CS signal goes high.

4:3 FOC_PRE_K[1:0]

2 (10)

R/W

The frequency compensation loop gain to be used before a sync word is

detected.

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Freq. compensation loop gain before sync word

K

2K

3K

4K

2

FOC_POST_K

1

R/W

The frequency compensation loop gain to be used after a sync word is

detected.

Setting

Freq. compensation loop gain after sync word

0

1

Same as FOC_PRE_K

K/2

1:0 FOC_LIMIT[1:0]

2 (10)

The saturation point for the frequency offset compensation algorithm:

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Saturation point (max compensated offset)

±0 (no frequency offset compensation)

±BW_CHAN/8

±BW_CHAN/4

±BW_CHAN/2

Frequency offset compensation is not supported for ASK/OOK; Always use

FOC_LIMIT=0 with these modulation formats.

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CC1101

0x1A: BSCFG – Bit Synchronization Configuration

Bit Field Name

Reset

R/W

Description

7:6 BS_PRE_KI[1:0]

1 (01)

R/W

The clock recovery feedback loop integral gain to be used before a sync word

is detected (used to correct offsets in data rate):

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Clock recovery loop integral gain before sync word

K_I

2K_I

3K_I

4K_I

5:4 BS_PRE_KP[1:0]

2 (10)

R/W

The clock recovery feedback loop proportional gain to be used before a sync

word is detected.

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Clock recovery loop proportional gain before sync word

K_P

2K_P

3K_P

4K_P

3

2

BS_POST_KI

BS_POST_KP

1

R/W

The clock recovery feedback loop integral gain to be used after a sync word is

detected.

Setting

Clock recovery loop integral gain after sync word

0

1

Same as BS_PRE_KI

K_I/2

1

The clock recovery feedback loop proportional gain to be used after a sync

word is detected.

Setting

Clock recovery loop proportional gain after sync word

0

1

Same as BS_PRE_KP

K_P

1:0 BS_LIMIT[1:0]

0 (00)

The saturation point for the data rate offset compensation algorithm:

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Data rate offset saturation (max data rate difference)

±0 (No data rate offset compensation performed)

±3.125% data rate offset

±6.25% data rate offset

±12.5% data rate offset

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CC1101

0x1B: AGCCTRL2 – AGC Control

Bit

Field Name

Reset

R/W

Description

7:6

MAX_DVGA_GAIN[1:0]

0 (00)

R/W

Reduces the maximum allowable DVGA gain.

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Allowable DVGA settings

All gain settings can be used

The highest gain setting can not be used

The 2 highest gain settings can not be used

The 3 highest gain settings can not be used

5:3

MAX_LNA_GAIN[2:0]

0 (000)

R/W

Sets the maximum allowable LNA + LNA 2 gain relative to the

maximum possible gain.

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Maximum allowable LNA + LNA 2 gain

Maximum possible LNA + LNA 2 gain

Approx. 2.6 dB below maximum possible gain

Approx. 6.1 dB below maximum possible gain

Approx. 7.4 dB below maximum possible gain

Approx. 9.2 dB below maximum possible gain

Approx. 11.5 dB below maximum possible gain

Approx. 14.6 dB below maximum possible gain

Approx. 17.1 dB below maximum possible gain

2:0

MAGN_TARGET[2:0]

3 (011)

R/W

These bits set the target value for the averaged amplitude from the

digital channel filter (1 LSB = 0 dB).

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Target amplitude from channel filter

24 dB

27 dB

30 dB

33 dB

36 dB

38 dB

40 dB

42 dB

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Page 77 of 93

CC1101

0x1C: AGCCTRL1 – AGC Control

Bit Field Name

Reset

R/W Description

7

6

Reserved

R0

AGC_LNA_PRIORITY

1

R/W Selects between two different strategies for LNA and LNA 2

gain adjustment. When 1, the LNA gain is decreased first.

When 0, the LNA 2 gain is decreased to minimum before

decreasing LNA gain.

5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00)

R/W Sets the relative change threshold for asserting carrier sense

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Carrier sense relative threshold

Relative carrier sense threshold disabled

6 dB increase in RSSI value

10 dB increase in RSSI value

14 dB increase in RSSI value

3:0 CARRIER_SENSE_ABS_THR[3:0]

0

R/W Sets the absolute RSSI threshold for asserting carrier sense.

The 2-complement signed threshold is programmed in steps of

1 dB and is relative to the MAGN_TARGET setting.

(0000)

Setting

Carrier sense absolute threshold

(Equal to channel filter amplitude when AGC

has not decreased gain)

-8 (1000)

-7 (1001)

…

Absolute carrier sense threshold disabled

7 dB below MAGN_TARGETsetting

…

-1 (1111)

0 (0000)

1 (0001)

…

1 dB below MAGN_TARGETsetting

At MAGN_TARGETsetting

1 dB above MAGN_TARGETsetting

…

7 (0111)

7 dB above MAGN_TARGETsetting

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Page 78 of 93

CC1101

0x1D: AGCCTRL0 – AGC Control

Bit Field Name

Reset

R/W

Description

7:6 HYST_LEVEL[1:0]

2 (10)

R/W

Sets the level of hysteresis on the magnitude deviation (internal AGC

signal that determine gain changes).

Setting Description

0 (00)

1 (01)

No hysteresis, small symmetric dead zone, high gain

Low hysteresis, small asymmetric dead zone, medium

gain

Medium hysteresis, medium asymmetric dead zone,

medium gain

2 (10)

3 (11)

Large hysteresis, large asymmetric dead zone, low

gain

5:4 WAIT_TIME[1:0]

1 (01)

R/W

Sets the number of channel filter samples from a gain adjustment

has been made until the AGC algorithm starts accumulating new

samples.

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Channel filter samples

8

16

24

32

3:2 AGC_FREEZE[1:0]

0 (00)

R/W

Control when the AGC gain should be frozen.

Setting Function

0 (00)

1 (01)

Normal operation. Always adjust gain when required.

The gain setting is frozen when a sync word has been

found.

Manually freeze the analogue gain setting and

continue to adjust the digital gain.

2 (10)

3 (11)

Manually freezes both the analogue and the digital

gain setting. Used for manually overriding the gain.

1:0 FILTER_LENGTH[1:0]

1 (01)

R/W

Sets the averaging length for the amplitude from the channel filter.

Sets the OOK/ASK decision boundary for OOK/ASK reception.

Setting Channel filter

samples

OOK decision

0 (00)

1 (01)

2 (10)

3 (11)

8

4 dB

16

32

64

8 dB

12 dB

16 dB

0x1E: WOREVT1 – High Byte Event0 Timeout

Bit Field Name

Reset

R/W Description

7:0 EVENT0[15:8]

135 (0x87)

R/W

High byte of EVENT0timeout register

750

t_Event0

=

⋅ EVENT0⋅2^{5⋅WOR _ RES}

f _XOSC

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Page 79 of 93

CC1101

0x1F: WOREVT0 –Low Byte Event0 Timeout

Bit

Field Name

Reset

R/W

Description

7:0

EVENT0[7:0]

107 (0x6B)

R/W

Low byte of EVENT0timeout register.

The default EVENT0value gives 1.0s timeout, assuming a 26.0 MHz

crystal.

0x20: WORCTRL – Wake On Radio Control

Bit

Field Name

Reset

R/W

Description

7

RC_PD

1

R/W

Power down signal to RC oscillator. When written to 0, automatic initial

calibration will be performed

6:4

EVENT1[2:0]

7 (111)

R/W

Timeout setting from register block. Decoded to Event 1 timeout. RC

oscillator clock frequency equals F_XOSC/750, which is 34.7 – 36 kHz,

depending on crystal frequency. The table below lists the number of clock

periods after Event 0 before Event 1 times out.

Setting t_Event1

0 (000) 4 (0.111 – 0.115 ms)

1 (001) 6 (0.167 – 0.173 ms)

2 (010) 8 (0.222 – 0.230 ms)

3 (011) 12 (0.333 – 0.346 ms)

4 (100) 16 (0.444 – 0.462 ms)

5 (101) 24 (0.667 – 0.692 ms)

6 (110) 32 (0.889 – 0.923 ms)

7 (111) 48 (1.333 – 1.385 ms)

Enables (1) or disables (0) the RC oscillator calibration.

3

RC_CAL

1

R/W

R0

2

Reserved

WOR_RES

1:0

0 (00)

R/W

Controls the Event 0 resolution as well as maximum timeout of the WOR

module and maximum timeout under normal RX operation::

Setting Resolution (1 LSB)

Max timeout

0 (00)

1 (01)

2 (10)

3 (11)

1 period (28µs – 29µs)

1.8 – 1.9 seconds

2⁵periods (0.89ms –0.92 ms) 58 – 61 seconds

2¹⁰periods (28 – 30 ms)

2¹⁵periods (0.91 – 0.94 s)

31 – 32 minutes

16.5 – 17.2 hours

Note that WOR_RESshould be 0 or 1 when using WOR because

WOR_RES> 1 will give a very low duty cycle.

In normal RX operation all settings of WOR_REScan be used.

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CC1101

0x21: FREND1 – Front End RX Configuration

Bit

Field Name

Reset

R/W

Description

7:6

5:4

3:2

1:0

LNA_CURRENT[1:0]

1 (01)

2 (10)

R/W

Adjusts front-end LNA PTAT current output

Adjusts front-end PTAT outputs

LNA2MIX_CURRENT[1:0]

LODIV_BUF_CURRENT_RX[1:0]

MIX_CURRENT[1:0]

Adjusts current in RX LO buffer (LO input to mixer)

Adjusts current in mixer

0x22: FREND0 – Front End TX Configuration

Bit

Field Name

Reset

R/W

Description

7:6

5:4

Reserved

R0

LODIV_BUF_CURRENT_TX[1:0]

1 (0x01)

R/W

Adjusts current TX LO buffer (input to PA). The value to

use in this field is given by the SmartRF^®Studio software

[7].

3

Reserved

R0

2:0

PA_POWER[2:0]

0 (0x00)

R/W

Selects PA power setting. This value is an index to the

PATABLE, which can be programmed with up to 8 different

PA settings. In OOK/ASK mode, this selects the PATABLE

index to use when transmitting a ‘1’. PATABLE index zero

is used in OOK/ASK when transmitting a ‘0’. The PATABLE

settings from index ‘0’ to the PA_POWERvalue are used for

ASK TX shaping, and for power ramp-up/ramp-down at the

start/end of transmission in all TX modulation formats.

0x23: FSCAL3 – Frequency Synthesizer Calibration

Bit

Field Name

Reset

R/W

Description

7:6

FSCAL3[7:6]

2 (0x02)

R/W

Frequency synthesizer calibration configuration. The value

to write in this field before calibration is given by the

SmartRF^®Studio software.

5:4

3:0

CHP_CURR_CAL_EN[1:0]

FSCAL3[3:0]

2 (0x02)

9 (1001)

R/W

Enable charge pump calibration stage when 1

Frequency synthesizer calibration result register. Digital bit

vector defining the charge pump output current, on an

exponential scale: IOUT = I₀·2^{FSCAL3[3:0]/4}

Fast frequency hopping without calibration for each hop

can be done by calibrating upfront for each frequency and

saving the resulting FSCAL3, FSCAL2and FSCAL1register

values. Between each frequency hop, calibration can be

replaced by writing the FSCAL3, FSCAL2and FSCAL1

register values corresponding to the next RF frequency.

SWRS061B

Page 81 of 93

CC1101

0x24: FSCAL2 – Frequency Synthesizer Calibration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5

VCO_CORE_H_EN

0

R/W

Choose high (1) / low (0) VCO

4:0 FSCAL2[4:0]

10 (0x0A)

Frequency synthesizer calibration result register. VCO current calibration

result and override value

Fast frequency hopping without calibration for each hop can be done by

calibrating upfront for each frequency and saving the resulting FSCAL3,

FSCAL2and FSCAL1register values. Between each frequency hop,

calibration can be replaced by writing the FSCAL3, FSCAL2and FSCAL1

register values corresponding to the next RF frequency.

0x25: FSCAL1 – Frequency Synthesizer Calibration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:0 FSCAL1[5:0]

32 (0x20)

R/W

Frequency synthesizer calibration result register. Capacitor array setting

for VCO coarse tuning.

Fast frequency hopping without calibration for each hop can be done by

calibrating upfront for each frequency and saving the resulting FSCAL3,

FSCAL2and FSCAL1register values. Between each frequency hop,

calibration can be replaced by writing the FSCAL3, FSCAL2and FSCAL1

register values corresponding to the next RF frequency.

0x26: FSCAL0 – Frequency Synthesizer Calibration

Bit Field Name

Reset

R/W

Description

7

Reserved

R0

6:0 FSCAL0[6:0]

13 (0x0D)

R/W

Frequency synthesizer calibration control. The value to use in this

register is given by the SmartRF^®Studio software [7].

0x27: RCCTRL1 – RC Oscillator Configuration

Bit Field Name

Reset

R/W

Description

7

Reserved

0

R0

6:0 RCCTRL1[6:0]

65 (0x41)

R/W

RC oscillator configuration.

0x28: RCCTRL0 – RC Oscillator Configuration

Bit Field Name

Reset

R/W

Description

7

Reserved

0

R0

6:0 RCCTRL0[6:0]

0 (0x00)

R/W

RC oscillator configuration.

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Page 82 of 93

CC1101

33.2 Configuration Register Details – Registers that Loose Programming in SLEEP State

0x29: FSTEST – Frequency Synthesizer Calibration Control

Bit Field Name

Reset

R/W

Description

7:0 FSTEST[7:0]

89 (0x59)

R/W

For test only. Do not write to this register.

0x2A: PTEST – Production Test

Bit Field Name

Reset

R/W

Description

7:0 PTEST[7:0]

127 (0x7F) R/W

Writing 0xBF to this register makes the on-chip temperature sensor

available in the IDLE state. The default 0x7F value should then be

written back before leaving the IDLE state.

Other use of this register is for test only.

0x2B: AGCTEST – AGC Test

Bit Field Name

Reset

R/W

Description

7:0 AGCTEST[7:0]

63 (0x3F)

R/W

For test only. Do not write to this register.

0x2C: TEST2 – Various Test Settings

Bit Field Name

Reset

R/W

Description

The value to use in this register is given by the SmartRF^®Studio

software [7]. This register will be forced to 0x88 or 0x81 when it wakes

up from SLEEP mode, depending on the configuration of FIFOTHR.

ADC_RETENTION.

7:0 TEST2[7:0]

136 (0x88) R/W

0x2D: TEST1 – Various Test Settings

Bit Field Name

Reset

R/W

Description

The value to use in this register is given by the SmartRF^®Studio

software [7]. This register will be forced to 0x31 or 0x35 when it wakes

up from SLEEP mode, depending on the configuration of FIFOTHR.

ADC_RETENTION.

7:0 TEST1[7:0]

49 (0x31)

R/W

0x2E: TEST0 – Various Test Settings

Bit Field Name

Reset

R/W

Description

The value to use in this register is given by the SmartRF^®Studio

software [7].

7:2 TEST0[7:2]

2 (0x02)

R/W

1

0

VCO_SEL_CAL_EN

TEST0[0]

1

R/W

Enable VCO selection calibration stage when 1

The value to use in this register is given by the SmartRF^®Studio

software [7].

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Page 83 of 93

CC1101

33.3 Status Register Details

0x30 (0xF0): PARTNUM – Chip ID

Bit Field Name

Reset

R/W

Description

7:0 PARTNUM[7:0]

0 (0x00)

R

Chip part number

0x31 (0xF1): VERSION – Chip ID

Bit Field Name

Reset

R/W

Description

7:0 VERSION[7:0]

4 (0x04)

R

Chip version number.

0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator

Bit Field Name

Reset

R/W

Description

7:0 FREQOFF_EST

R

The estimated frequency offset (2’s complement) of the carrier. Resolution is

F_XTAL/2¹⁴(1.59 - 1.65 kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL

frequency.

Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK

modulation. This register will read 0 when using ASK or OOK modulation.

0x33 (0xF3): LQI – Demodulator Estimate for Link Quality

Bit Field Name

Reset

R/W

Description

7

CRC OK

R

The last CRC comparison matched. Cleared when entering/restarting RX

mode.

6:0 LQI_EST[6:0]

R

The Link Quality Indicator estimates how easily a received signal can be

demodulated. Calculated over the 64 symbols following the sync word

0x34 (0xF4): RSSI – Received Signal Strength Indication

Bit Field Name

Reset

R/W

Description

7:0 RSSI

R

Received signal strength indicator

SWRS061B

Page 84 of 93

CC1101

0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State

Bit

Field Name

Reset

R/W

Description

7:5

4:0

Reserved

R0

R

MARC_STATE[4:0]

Main Radio Control FSM State

Value

State name

SLEEP

State (Figure 16, page 41)

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

SLEEP

IDLE

XOFF

VCOON_MC

REGON_MC

MANCAL

VCOON

MANCAL

FS_WAKEUP

CALIBRATE

SETTLING

CALIBRATE

RX

REGON

STARTCAL

BWBOOST

FS_LOCK

IFADCON

12 (0x0C) ENDCAL

13 (0x0D) RX

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

RX_END

RX

RX_RST

RX

TXRX_SWITCH

RXFIFO_OVERFLOW

FSTXON

TXRX_SETTLING

RXFIFO_OVERFLOW

FSTXON

TX

TX_END

TX

RXTX_SWITCH

TXFIFO_UNDERFLOW

RXTX_SETTLING

TXFIFO_UNDERFLOW

Note: it is not possible to read back the SLEEP or XOFF state numbers

because setting CSn low will make the chip enter the IDLE mode from the

SLEEP or XOFF states.

0x36 (0xF6): WORTIME1 – High Byte of WOR Time

Bit

Field Name

Reset

R/W

Description

7:0

TIME[15:8]

R

High byte of timer value in WOR module

0x37 (0xF7): WORTIME0 – Low Byte of WOR Time

Bit

Field Name

Reset

R/W

Description

7:0

TIME[7:0]

R

Low byte of timer value in WOR module

SWRS061B

Page 85 of 93

CC1101

0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status

Bit Field Name

Reset

R/W

Description

7

CRC_OK

R

The last CRC comparison matched. Cleared when entering/restarting RX

mode.

6

5

4

3

2

CS

R

Carrier sense

PQT_REACHED

CCA

Preamble Quality reached

Channel is clear

SFD

Sync word found

Current GDO2 value. Note: the reading gives the non-inverted value

irrespective of what IOCFG2.GDO2_INVis programmed to.

GDO2

It is not recommended to check for PLL lock by reading PKTSTATUS[2]

with GDO2_CFG=0x0A.

1

0

Reserved

R0

R

Current GDO0 value. Note: the reading gives the non-inverted value

irrespective of what IOCFG0.GDO0_INVis programmed to.

GDO0

It is not recommended to check for PLL lock by reading PKTSTATUS[0]

with GDO0_CFG=0x0A.

0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module

Bit Field Name

Reset R/W

Description

7:0 VCO_VC_DAC[7:0]

R

Status register for test only.

0x3A (0xFA): TXBYTES – Underflow and Number of Bytes

Bit Field Name

Reset R/W

Description

7

TXFIFO_UNDERFLOW

R

6:0 NUM_TXBYTES

Number of bytes in TX FIFO

0x3B (0xFB): RXBYTES – Overflow and Number of Bytes

Bit Field Name

Reset R/W

Description

7

RXFIFO_OVERFLOW

R

6:0 NUM_RXBYTES

Number of bytes in RX FIFO

0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result

Bit Field Name

Reset

R/W

Description

7

Reserved

R0

R

6:0 RCCTRL1_STATUS[6:0]

Contains the value from the last run of the RC oscillator calibration

routine.

For usage description refer to AN047 [4]

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Page 86 of 93

CC1101

0x3D (0xFC): RCCTRL0_STATUS – Last RC Oscillator Calibration Result

Bit Field Name

Reset

R/W

Description

7

Reserved

R0

R

6:0 RCCTRL0_STATUS[6:0]

Contains the value from the last run of the RC oscillator calibration

routine.

For usage description refer to Aplication Note AN047 [4].

34 Package Description (QLP 20)

All dimensions are in millimetres, angles in degrees. NOTE: The CC1101 is available in RoHS

lead-free package only.

Figure 30: Package Dimensions Drawing

Package

Type

A

A1

A2

D

D1

D2

E

E1

E2

L

T

b

e

0.75

0.85

0.95

0.005

0.025

0.045

0.55

0.65

0.75

3.90

4.00

4.10

3.65

3.75

3.85

3.90

4.00

4.10

3.65

3.75

3.85

0.45

0.55

0.65

0.190

0.18

0.23

0.30

Min

Typ.

Max

2.40

0.50

QLP 20 (4x4)

0.245

Table 38: Package Dimensions

SWRS061B

Page 87 of 93

CC1101

34.1 Recommended PCB Layout for Package (QLP 20)

Figure 31: Recommended PCB Layout for QLP 20 Package

Note: Figure 31 is an illustration only and not to scale. There are five 10 mil via holes distributed

symmetrically in the ground pad under the package. See also the CC1101EM reference designs

([5] and [6]).

34.2 Package Thermal Properties

Thermal Resistance

Air velocity [m/s]

Rth,j-a [K/W]

0

40.4

Table 39: Thermal Properties of QLP 20 Package

34.3 Soldering Information

The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed.

34.4 Tray Specification

CC1101 can be delivered in standard QLP 4x4 mm shipping trays.

Tray Specification

Package

QLP 20

Tray Width

135.9mm

Tray Height

7.62mm

Tray Length

322.6mm

Units per Tray

490

Table 40: Tray Specification

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CC1101

34.5 Carrier Tape and Reel Specification

Carrier tape and reel is in accordance with EIA Specification 481.

Tape and Reel Specification

Package

Tape Width

Component

Pitch

Hole

Pitch

Reel

Diameter

Units per Reel

2500

QLP 20

12 mm

8 mm

4 mm

13 inches

Table 41: Carrier Tape and Reel Specification

35 Ordering Information

TI Part Number

Description

Minimum Order

Quantity (MOQ)

CC1101RTK

490 (tray)

CC1101 QLP20 RoHS Pb-free 490/tray

CC1101 QLP20 RoHS Pb-free 2500/T&R

CC1101 - 433 MHz Development Kit

CC1101RTKR

2,500 (tape and reel)

CC1101DK433

1

CC1101DK868-915

CC1101EMK433

CC1101EMK868-915

CC1101 - 868/915 MHz Development Kit

CC1101 - 433 MHz Evaluation Module Kit

CC1101 - 868/915 MHz Evaluation Module Kit

Table 42: Ordering Information

SWRS061B

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CC1101

36 References

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

CC1101 Errata Notes (swrz020.pdf)

AN001 SRD Regulations for Licence Free Transceiver Operation (swra090.pdf)

AN039 Using the CC1100 in the European 433 and 868 MHz ISM Bands (swra054.pdf)

AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf)

CC1101EM 315 - 433 MHz Reference Design 1.0 (swrr043.zip)

CC1101EM 868 – 915 MHz Reference Design 2.0 (swrr044.zip)

SmartRF^®Studio (swrc046.zip)

CC1100 CC2500 Examples Libraries (swrc021.zip)

CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User

Manual (swru109.pdf)

[10] DN010 Close-in Reception with CC1101 (swra147.pdf)

SWRS061B

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CC1101

37 General Information

37.1 Document History

Revision

Date

Description/Changes

Changed name on DN009 Close-in Reception with CC1101 to DN010 Close-in

Reception with CC1101.

SWRS061B

2007.06.05

Added info regarding how to reduce spurious emission at 699 MHz. Changes

regarding this was done the following places: Table: RF Transmit Section, Figure 4:

Typical Application and Evaluation Circuit 868/915 MHz, Table 14: Overview of

External Components, and Table 15: Bill Of Materials for the Application Circuit.

Changes made to Figure 18: Power-On Reset with SRES

SWRS061A

SWRS061

2007.06.30 Initial release.

2007.04.16 First preliminary data sheet release

Table 43: Document History

37.2 Product Status Definitions

Data Sheet Identification

Product Status

Definition

Advance Information

Planned or Under

Development

This data sheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

Engineering Samples This data sheet contains preliminary data, and

and Pre-Production

Prototypes

supplementary data will be published at a later date.

Chipcon reserves the right to make changes at any

time without notice in order to improve design and

supply the best possible product. The product is not

yet fully qualified at this point.

No Identification Noted

Obsolete

Full Production

This data sheet contains the final specifications.

Chipcon reserves the right to make changes at any

time without notice in order to improve design and

supply the best possible product.

Not In Production

This data sheet contains specifications on a product

that has been discontinued by Chipcon. The data

sheet is printed for reference information only.

Table 44: Product Status Definitions

SWRS061B

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CC1101

38 Address Information

Texas Instruments Norway AS

Gaustadalléen 21

N-0349 Oslo

NORWAY

Tel: +47 22 95 85 44

Fax: +47 22 95 85 46

Web site: http://www.ti.com/lpw

39 TI Worldwide Technical Support

Internet

TI Semiconductor Product Information Center Home Page:

TI Semiconductor KnowledgeBase Home Page:

support.ti.com

support.ti.com/sc/knowledgebase

Product Information Centers

Americas

Phone:

+1(972) 644-5580

Fax:

+1(972) 927-6377

Internet/Email:

support.ti.com/sc/pic/americas.htm

Europe, Middle East and Africa

Phone:

Belgium (English)

Finland (English)

France

+32 (0) 27 45 54 32

+358 (0) 9 25173948

+33 (0) 1 30 70 11 64

+49 (0) 8161 80 33 11

180 949 0107

Germany

Israel (English)

Italy

800 79 11 37

Netherlands (English)

Russia

+31 (0) 546 87 95 45

+7 (0) 95 363 4824

+34 902 35 40 28

Spain

Sweden (English)

United Kingdom

Fax:

+46 (0) 8587 555 22

+44 (0) 1604 66 33 99

+49 (0) 8161 80 2045

support.ti.com/sc/pic/euro.htm

Internet:

Japan

Fax

International

Domestic

+81-3-3344-5317

0120-81-0036

Internet/Email International

support.ti.com/sc/pic/japan.htm

www.tij.co.jp/pic

Domestic

SWRS061B

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CC1101

Asia

Phone

International

Domestic

Australia

China

+886-2-23786800

Toll-Free Number

1-800-999-084

800-820-8682

Hong Kong

India

800-96-5941

+91-80-51381665 (Toll)

001-803-8861-1006

080-551-2804

Indonesia

Korea

Malaysia

New Zealand

Philippines

Singapore

Taiwan

1-800-80-3973

0800-446-934

1-800-765-7404

800-886-1028

0800-006800

Thailand

001-800-886-0010

+886-2-2378-6808

tiasia@ti.com or ti-china@ti.com

support.ti.com/sc/pic/asia.htm

Fax

Email

Internet

SWRS061B

Page 93 of 93


型号：	CC1101EMK868-915
厂家：	TEXAS INSTRUMENTS
描述：	Low-Cost Low-Power Sub-1GHz RF Transceiver 低成本低功耗（低于1GHz）射频收发器射频
文件：	总94页 (文件大小：981K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC1101EMK868-915 [TI]

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