CC1310F64RHBR [TI]
具有 128kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M3 低于 1GHz 无线 MCU | RHB | 32 | -40 to 85;
| 型号： | CC1310F64RHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 128kB 闪存的 SimpleLink™ 32 位 Arm Cortex-M3 低于 1GHz 无线 MCU | RHB | 32 | -40 to 85 无线 闪存 |
| 文件： | 总70页 (文件大小：3668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
CC1310 SimpleLink™ 超低功耗低于 1GHz 无线 MCU
1 器件概述
1.1 特性
1
空白
• 微控制器
– 性能强大的 Arm® Cortex®-M3 处理器
– EEMBC CoreMark®评分：142
– EEMBC ULPBench™评分：158
– 时钟速率最高可达 48MHz
空白
• 外部系统
– 片上内部直流/直流转换器
– 无缝集成 SimpleLink™CC1190 范围扩展器
• 低功耗
– 32KB、64KB 和 128KB 系统内可编程闪存
– 宽电源电压范围：1.8 至 3.8V
– RX：5.4mA
– 8KB 缓存静态随机存取存储器 (SRAM)
（或用作通用 RAM）
– 20KB 超低泄漏 SRAM
– 2 引脚 cJTAG 和 JTAG 调试
– 支持无线 (OTA) 升级
– TX（+10dBm 时）：13.4mA
– Coremark 运行时的 48MHz 有源模式微控制器
(MCU)：2.5mA (51µA/MHz)
– 有源模式 MCU：48.5 CoreMark/mA
– 有源模式传感器控制器（24 MHz）：
0.4mA + 8.2μA/MHz
• 超低功耗传感器控制器
– 可独立于系统其余部分自主运行
– 16 位架构
– 传感器控制器，每秒唤醒一次来执行一次 12 位
ADC 采样：0.95µA
– 待机电流：0.7μA（实时时钟 (RTC) 运行，RAM
和 CPU 保持）
– 2KB 超低泄漏代码和数据 SRAM
• 有效的代码尺寸架构，在 ROM 中放置
TI-RTOS、驱动程序、引导加载程序的部件
• 与 RoHS 兼容的封装
– 关断电流：185nA（发生外部事件时唤醒）
• 射频 (RF) 部分
– 7mm × 7mm RGZ VQFN48 封装（30 个通用输
入/输出 (GPIO)）
– 5mm × 5mm RHB VQFN32 封装（15 个
GPIO）
– 4mm × 4mm RSM VQFN32 封装（10 个
GPIO）
– 出色的接收器灵敏度：远距离模式下为
–124dBm；50kbps 时为 –110dBm
– 出色的可选择性 (±100kHz)：56dB
– 出色的阻断性能 (±10MHz)：
90dB
• 外设
– 可编程输出功率：时最高可达 +9dBm
– 单端或差分 RF 接口
– 所有数字外设引脚均可连接任意 GPIO
– 四个通用定时器模块
（8 × 16 位或 4 × 32 位，均采用脉宽调制
(PWM)）
– 12 位模数转换器 (ADC)、200MSPS、8 通道模
拟多路复用器
– 适用于符合全球射频规范的系统
– ETSI EN 300 220 和 EN 303 204（欧洲）
– FCC CFR47 第 15 部分（美国）
– ARIB STD-T108（日本）
– 无线 M-Bus (EN 13757-4) 和 IEEE®802.15.4g
– 持续时间比较器
– 超低功耗时钟比较器
– 可编程电流源
– UART
– 2 个同步串行接口 (SSI)（SPI、MICROWIRE 和
TI）
– I2C、I2S
– 实时时钟 (RTC)
– AES-128 安全模块
– 真随机数发生器 (TRNG)
– 支持八个电容感测按钮
– 集成温度传感器
空白
PHY
• 工具和开发环境
– 功能全面的低成本开发套件
– 针对不同 RF 配置的多种参考设计
– 数据包监听器 PC 软件
– Sensor Controller Studio
– SmartRF™Studio
– SmartRF Flash Programmer 2
– IAR Embedded Workbench®（适用于 Arm）
– Code Composer Studio™(CCS) IDE
– CCS UniFlash
空白
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS181
CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
www.ti.com.cn
1.2 应用
•
315、433、470、500、779、868、915、
920MHz 工业、科学和医疗 (ISM) 及短程设备
(SRD) 系统
•
•
•
无线传感器网络
有源射频识别 (RFID)
IEEE 802.15.4g、支持 IP 的智能对象
(6LoWPAN)、无线仪表总线、KNX 系统、
Wi-SUN™及专有系统
•
信道间隔为 50kHz 至 5MHz 的
低功耗无线系统
•
•
•
•
•
家庭和楼宇自动化
无线警报和安全系统
工业用监控和控制
智能电网和自动抄表
无线医疗保健 应用
•
•
•
•
能量收集 应用
电子货架标签 (ESL)
远距离传感器 应用
热量分配表
1.3 说明
CC1310 器件是一款经济高效型超低功耗低于 1GHz 射频器件，由 德州仪器 (TI)™倾力打造，属于
SimpleLink™ 微控制器 (MCU) 平台的组成部分。该平台包含 Wi-Fi®、低功耗 Bluetooth®、低于 1GHz、以
太网、 Zigbee®、Thread 和主机 MCU。所有这些器件均共用一个简单易用的通用开发环境，其中包含单个
核心软件开发套件 (SDK) 和丰富的工具集。借助一次性集成的 SimpleLink 平台，用户可以将产品组合中的
任何器件组合添加到自己的设计中，从而在设计要求变更时实现 100% 代码重用。有关更多信息，请访问
www.ti.com.cn/simplelink。
凭借极低的有源射频和 MCU 电流消耗以及灵活的低功耗模式，CC1310 器件可确保卓越的电池寿命，并能
够在小型纽扣电池供电的情况下以及在能量采集应用中实现远距离 工作。
CC1310 器件是 CC13xx 和 CC26xx 系列经济高效型超低功耗无线 MCU 中的一员，能够支持低于 1GHz 射
频。CC1310 器件在一个支持多个物理层和射频标准的平台上将灵活的超低功耗射频收发器与强大的
48MHz Arm® Cortex®-M3 微控制器结合在一起。专用无线电控制器 (Cortex®-M0) 可处理存储在 ROM 或
RAM 中的低级射频协议命令，因而可确保超低功耗和灵活性。CC1310 器件在实现低功耗的同时不以牺牲
射频性能为代价；CC1310 器件具有出色的灵敏度和稳健性（选择性和阻断性）性能。
CC1310 器件是高度集成的真正的单芯片解决方案，整合了完整的射频系统和片上直流/直流转换器。
传感器可由专用的超低功耗自主 MCU 以超低功耗方式进行处理（该 MCU 可配置为处理模拟和数字传感
器），因此主 MCU (Arm® Cortex®-M3) 能够最大限度延长睡眠时间。
CC1310 器件的电源和时钟管理系统以及无线电系统需要采用特定配置并由软件处理才能正确运行，这已在
TI-RTOS 中实现。TI 建议将此软件框架用于该器件的全部应用开发过程。完整的 TI-RTOS 和设备驱动程序
均有免费的源代码可供使用。
2
器件概述
版权 © 2015–2018, Texas Instruments Incorporated
CC1310
www.ti.com.cn
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
器件信息(1)
封装
器件型号
封装尺寸（标称值）
7.00mm × 7.00mm
5.00mm × 5.00mm
4.00mm x 4.00mm
7.00mm × 7.00mm
5.00mm × 5.00mm
4.00mm x 4.00mm
7.00mm × 7.00mm
5.00mm × 5.00mm
4.00mm × 4.00mm
CC1310F128RGZ
CC1310F128RHB
CC1310F128RSM
CC1310F64RGZ
CC1310F64RHB
CC1310F64RSM
CC1310F32RGZ
CC1310F32RHB
CC1310F32RSM
VQFN (48)
VQFN (32)
VQFN (32)
VQFN (48)
VQFN (32)
VQFN (32)
VQFN (48)
VQFN (32)
VQFN (32)
(1) 详细信息请见节 9。
版权 © 2015–2018, Texas Instruments Incorporated
器件概述
3
CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
www.ti.com.cn
1.4 功能框图
图 1-1 所示为 CC1310 器件框图。
SimpleLinkTM CC1310 Wireless MCU
cJTAG
RF core
ROM
Main CPU:
ADC
ADC
Digital PLL
32-, 64-,
128-KB
Flash
ARM®
Cortex®-M3
DSP Modem
8-KB
Cache
4-KB
SRAM
ARM®
Cortex®-M0
20-KB
SRAM
ROM
Sensor Controller
General Peripherals / Modules
Sensor Controller
Engine
I2C
4x 32-Bit Timers
2x SSI (SPI,µW,TI)
Watchdog Timer
TRNG
UART
12-Bit ADC, 200ks/s
2x Analog Comparators
SPI / I2C Digital Sensor IF
Constant Current Source
Time-to-Digital Converter
2-KB SRAM
I2S
10 / 15 / 30 GPIOs
AES
Temp. / Batt. Monitor
RTC
32 ch. mDMA
DC-DC Converter
Copyright © 2016, Texas Instruments Incorporated
图 1-1. CC1310 框图
4
器件概述
版权 © 2015–2018, Texas Instruments Incorporated
CC1310
www.ti.com.cn
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
内容
1
器件概述.................................................... 1
5.17 DC Characteristics .................................. 29
5.18 Thermal Characteristics............................. 30
5.19 Timing and Switching Characteristics ............... 30
5.20 Typical Characteristics .............................. 34
Detailed Description ................................... 38
6.1 Overview ............................................ 38
6.2 Main CPU ........................................... 38
6.3 RF Core ............................................. 39
6.4 Sensor Controller ................................... 40
6.5 Memory.............................................. 41
6.6 Debug ............................................... 41
6.7 Power Management................................. 42
6.8 Clock Systems ...................................... 43
6.9 General Peripherals and Modules .................. 43
6.10 Voltage Supply Domains............................ 44
6.11 System Architecture................................. 44
Application, Implementation, and Layout ......... 45
7.1 Application Information.............................. 45
7.2 TI Design or Reference Design ..................... 46
器件和文档支持 .......................................... 46
8.1 器件命名规则 ........................................ 47
8.2 工具和软件 .......................................... 48
8.3 文档支持............................................. 50
8.4 德州仪器 (TI) 低功耗射频网站....................... 50
8.5 其他信息............................................. 50
8.6 社区资源............................................. 50
8.7 商标.................................................. 51
8.8 静电放电警告 ........................................ 51
8.9 出口管制提示 ........................................ 51
8.10 术语表 ............................................... 51
机械、封装和可订购信息................................ 51
9.1 封装信息............................................. 51
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 4
修订历史记录............................................... 6
Device Comparison ..................................... 7
3.1 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagram – RSM Package ........................ 8
4.2 Signal Descriptions – RSM Package................. 9
4.3 Pin Diagram – RHB Package ....................... 10
4.4 Signal Descriptions – RHB Package................ 11
4.5 Pin Diagram – RGZ Package ....................... 12
4.6 Signal Descriptions – RGZ Package................ 13
Specifications ........................................... 15
5.1 Absolute Maximum Ratings......................... 15
5.2 ESD Ratings ........................................ 15
5.3 Recommended Operating Conditions............... 15
5.4 Power Consumption Summary...................... 16
5.5 RF Characteristics .................................. 16
6
2
3
4
5
7
8
5.6
5.7
5.8
5.9
Receive (RX) Parameters, 861 MHz to 1054 MHz . 17
Receive (RX) Parameters, 431 MHz to 527 MHz .. 23
Transmit (TX) Parameters, 861 MHz to 1054 MHz . 25
Transmit (TX) Parameters, 431 MHz to 527 MHz .. 26
5.10 PLL Parameters..................................... 26
5.11 ADC Characteristics................................. 26
5.12 Temperature Sensor ................................ 28
5.13 Battery Monitor...................................... 28
5.14 Continuous Time Comparator....................... 28
5.15 Low-Power Clocked Comparator ................... 28
5.16 Programmable Current Source ..................... 29
9
版权 © 2015–2018, Texas Instruments Incorporated
内容
5
CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
www.ti.com.cn
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from October 27, 2016 to July 13, 2018
Page
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•
•
已添加 Code Composer Studio UniFlash.......................................................................................... 1
已更改 描述部分....................................................................................................................... 2
Changed Table 3-1 ................................................................................................................... 7
Changed Figure 4-1 .................................................................................................................. 8
Changed Figure 4-2................................................................................................................. 10
Added support for split supply rail to Section 5.3 ............................................................................... 15
Changed Operating supply voltage ............................................................................................... 15
Added test conditions at 433.92 MHz to Section 5.4 ........................................................................... 16
Moved footnote to specific values in Section 5.5 ............................................................................... 16
Changed footnote in Section 5.5 .................................................................................................. 16
Changed test conditions for Receiver sensitivity, 50 kbps in Section 5.6 ................................................... 17
Added parameters to Section 5.6 ................................................................................................. 17
Added Receiver sensitivity parameters to Section 5.7 ......................................................................... 23
Changed ............................................................................................................................. 31
Changed footnote in ................................................................................................................ 31
已添加 “软件”部分 ................................................................................................................... 48
Changes from October 28, 2015 to October 27, 2016
Page
•
•
•
•
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•
•
•
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•
已添加 32KB 和 64KB 至系统内可编程闪存的特性要点 ......................................................................... 1
已更改 至正确引脚数（位于特性要点 与 RoHS 兼容的封装 .................................................................... 1
已更改 CC1310 框图 ................................................................................................................. 4
Changed Figure 4-2, corrected typo in pin name ............................................................................... 10
Changed the table note in Section 5.1 from: VDDS to: ground ............................................................... 15
Changed ESD ratings for all pins in Section 5.2 ................................................................................ 15
Added OOK modulation power consumption to Section 5.4 .................................................................. 16
Added OOK modulation sensitivity to Section 5.6 .............................................................................. 22
Added receive parameters for 431-MHz to 527-MHz band in Section 5.7 .................................................. 23
Added transmit parameters for 431-MHz to 527-MHz band in Section 5.9 ................................................. 26
Changed ADC reference voltage to correct value in Section 5.11 ........................................................... 27
Added thermal characteristics for RHB and RSM packages in Section 5.18 ............................................... 30
Changed Standby MCU Current Consumption, 32-kHz Clock, RAM and MCU Retention by extending the
temperature .......................................................................................................................... 34
Changed BOD restriction footnote in Table 6-2—restriction does not apply to die revision B and later................. 42
Added Section 6.10 ................................................................................................................. 44
已更改 图 8-1 ........................................................................................................................ 47
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Changes from September 30, 2015 to October 28, 2015
Page
•
Added the RSM and RHB packages ............................................................................................... 8
Changes from August 31, 2015 to September 30, 2015
Page
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•
已更改 器件状态，从“产品预览”更改为“量产数据”................................................................................ 1
Removed the RSM and RHB packages ........................................................................................... 8
6
修订历史记录
Copyright © 2015–2018, Texas Instruments Incorporated
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
3 Device Comparison
Table 3-1 lists the device family overview.
Table 3-1. Device Family Overview
FLASH
(KB)
RAM
(KB)
DEVICE
RADIO SUPPORT
GPIOs
PACKAGE SIZE
CC1310F128RGZ
CC1310F64RGZ
CC1310F32RGZ
CC1310F128RHB
CC1310F64RHB
CC1310F32RHB
CC1310F128RSM
CC1310F64RSM
CC1310F32RSM
128
64
20
16
16
20
16
16
20
16
16
30
30
30
15
15
15
10
10
10
Proprietary, Wireless M-Bus,
IEEE 802.15.4g
RGZ (7 mm × 7 mm VQFN48)
32
128
64
Proprietary, Wireless M-Bus,
IEEE 802.15.4g
RHB (5 mm × 5 mm VQFN32)
RSM (4 mm × 4 mm VQFN32)
32
128
64
Proprietary, Wireless M-Bus,
IEEE 802.15.4g
32
RGZ (7 mm × 7 mm VQFN48)
RHB (5 mm × 5 mm VQFN32)
RSM (4 mm × 4 mm VQFN32)
Sub-1 GHz
Bluetooth low energy
CC1350
128
128
20
10-30
RGZ (7 mm × 7 mm VQFN48)
RHB (5 mm × 5 mm VQFN32)
RSM (4 mm × 4 mm VQFN32)
YFV (2.7 mm × 2.7 mm DSBGA34)
Bluetooth 5 low energy
2.4-GHz proprietary FSK-based formats
CC2640R2
20
10-31
Sub-1 GHz
Proprietary, Wireless M-Bus,
IEEE 802.15.4g
CC1312R
CC1352R
352
352
80
80
30
28
RGZ (7 mm × 7 mm VQFN48)
RGZ (7 mm × 7 mm VQFN48)
Dual-band (2.4-GHz and Sub-1 GHz)
Multiprotocol
Multiprotocol
Bluetooth 5 low energy
Zigbee
CC2652R
352
80
31
RGZ (7 mm × 7 mm VQFN48)
Thread
2.4-GHz proprietary FSK-based formats
3.1 Related Products
Wireless Connectivity The wireless connectivity portfolio offers a wide selection of low-power RF
solutions suitable for a broad range of application. The offerings range from fully customized
solutions to turnkey offerings with precertified hardware and software (protocol).
Sub-1 GHz Long-range, low power wireless connectivity solutions are offered in a wide range of
Sub-1 GHz ISM bands.
Companion Products Review products that are frequently purchased or used with this product.
Copyright © 2015–2018, Texas Instruments Incorporated
Device Comparison
7
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
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4 Terminal Configuration and Functions
4.1 Pin Diagram – RSM Package
Figure 4-1 shows the RSM pinout diagram.
DIO_8 25
DIO_9 26
16 DIO_4
15 DIO_3
VDDS 27
14 JTAG_TCKC
13 JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 28
VSS 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10 DIO_2
9
DIO_1
Figure 4-1. RSM (4-mm × 4-mm) Pinout, 0.4-mm Pitch
Top View
I/O pins marked in Figure 4-1 in bold have high-drive capabilities; they are as follows:
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•
•
•
•
•
Pin 8, DIO_0
Pin 9, DIO_1
Pin 10, DIO_2
Pin 13, JTAG_TMSC
Pin 15, DIO_3
Pin 16, DIO_4
I/O pins marked in Figure 4-1 in italics have analog capabilities; they are as follows:
•
•
•
•
•
Pin 22, DIO_5
Pin 23, DIO_6
Pin 24, DIO_7
Pin 25, DIO_8
Pin 26, DIO_9
8
Terminal Configuration and Functions
Copyright © 2015–2018, Texas Instruments Incorporated
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
4.2 Signal Descriptions – RSM Package
Table 4-1. Signal Descriptions – RSM Package
PIN
TYPE
DESCRIPTION
NAME
NO.
18
12
8
DCDC_SW
DCOUPL
DIO_0
Power
Power
Output from internal DC/DC(1)
1.27-V regulated digital-supply decoupling capacitor(2)
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, high-drive capability, JTAG_TDO
GPIO, high-drive capability, JTAG_TDI
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
Ground; exposed ground pad
Digital I/O
DIO_1
9
Digital I/O
DIO_2
10
15
16
22
23
24
25
26
–
Digital I/O
DIO_3
Digital I/O
DIO_4
Digital I/O
DIO_5
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Power
DIO_6
DIO_7
DIO_8
DIO_9
EGP
JTAG_TMSC
JTAG_TCKC
RESET_N
13
14
21
Digital I/O
JTAG TMSC
JTAG TCKC(3)
Digital I/O
Digital input
Reset, active low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RX_TX
4
RF I/O
Power
Power
Power
Power
Power
Optional bias pin for the RF LNA
1.8-V to 3.8-V main chip supply(1)
1.8-V to 3.8-V GPIO supply(1)
VDDS
27
11
19
28
32
VDDS2
VDDS_DCDC
VDDR
1.8-V to 3.8-V DC/DC supply
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4)
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5)
VDDR_RF
3, 7, 17,
20, 29
VSS
Power
Ground
X32K_Q1
X32K_Q2
X24M_N
X24M_P
5
6
Analog I/O
Analog I/O
Analog I/O
Analog I/O
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
30
31
(1) See the technical reference manual listed in 节 8.3 for more details.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™
Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
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4.3 Pin Diagram – RHB Package
Figure 4-2 shows the RHB pinout diagram.
DIO_12 25
DIO_13 26
DIO_14 27
VDDS 28
16 DIO_6
15 DIO_5
14 JTAG_TCKC
13 JTAG_TMSC
12 DCOUPL
11 VDDS2
VDDR 29
X24M_N 30
X24M_P 31
VDDR_RF 32
10 DIO_4
9
DIO_3
Figure 4-2. RHB (5-mm × 5-mm) Pinout, 0.5-mm Pitch
Top View
I/O pins marked in Figure 4-2 in bold have high-drive capabilities; they are as follows:
•
•
•
•
•
Pin 8, DIO_2
Pin 9, DIO_3
Pin 10, DIO_4
Pin 15, DIO_5
Pin 16, DIO_6
I/O pins marked in Figure 4-2 in italics have analog capabilities; they are as follows:
•
•
•
•
•
•
•
•
Pin 20, DIO_7
Pin 21, DIO_8
Pin 22, DIO_9
Pin 23, DIO_10
Pin 24, DIO_11
Pin 25, DIO_12
Pin 26, DIO_13
Pin 27, DIO_14
10
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4.4 Signal Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
PIN
TYPE
DESCRIPTION
NAME
NO.
17
12
6
DCDC_SW
DCOUPL
DIO_0
Power
Power
Output from internal DC/DC(1)
1.27-V regulated digital-supply decoupling(2)
Digital I/O
GPIO, Sensor Controller
DIO_1
7
Digital I/O
GPIO, Sensor Controller
DIO_2
8
Digital I/O
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, Sensor Controller, high-drive capability
GPIO, high-drive capability, JTAG_TDO
GPIO, high-drive capability, JTAG_TDI
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, Analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
GPIO, Sensor Controller, analog
Ground; exposed ground pad
DIO_3
9
Digital I/O
DIO_4
10
15
16
20
21
22
23
24
25
26
27
–
Digital I/O
DIO_5
Digital I/O
DIO_6
Digital I/O
DIO_7
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Digital or analog I/O
Power
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
EGP
JTAG_TMSC
JTAG_TCKC
RESET_N
13
14
19
Digital I/O
JTAG TMSC, high-drive capability
JTAG TCKC(3)
Digital I/O
Digital input
Reset, active low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RX_TX
3
RF I/O
Power
Optional bias pin for the RF LNA
VDDR
29
32
28
11
18
30
31
4
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4)
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5)
1.8-V to 3.8-V main chip supply(1)
VDDR_RF
VDDS
Power
Power
VDDS2
Power
1.8-V to 3.8-V GPIO supply(1)
VDDS_DCDC
X24M_N
X24M_P
X32K_Q1
X32K_Q2
Power
1.8-V to 3.8-V DC/DC supply
Analog I/O
Analog I/O
Analog I/O
Analog I/O
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
5
32-kHz crystal oscillator pin 2
(1) For more details, see the technical reference manual listed in 节 8.3.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™
Wireless MCU Technical Reference Manual.
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
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4.5 Pin Diagram – RGZ Package
Figure 4-3 shows the RGZ pinout diagram.
DIO_24 37
DIO_25 38
DIO_26 39
DIO_27 40
DIO_28 41
DIO_29 42
24 JTAG_TMSC
23 DCOUPL
22 VDDS3
21 DIO_15
DIO_14
DIO_13
DIO_12
DIO_11
DIO_10
DIO_9
20
19
18
17
16
15
14
DIO_30
43
VDDS 44
VDDR 45
X24M_N 46
X24M_P 47
VDDR_RF 48
DIO_8
13 VDDS2
Figure 4-3. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch
Top View
I/O pins marked in Figure 4-3 in bold have high-drive capabilities; they are as follows:
•
•
•
•
•
•
Pin 10, DIO_5
Pin 11, DIO_6
Pin 12, DIO_7
Pin 24, JTAG_TMSC
Pin 26, DIO_16
Pin 27, DIO_17
I/O pins marked in Figure 4-3 in italics have analog capabilities; they are as follows:
•
•
•
•
•
•
•
•
Pin 36, DIO_23
Pin 37, DIO_24
Pin 38, DIO_25
Pin 39, DIO_26
Pin 40, DIO_27
Pin 41, DIO_28
Pin 42, DIO_29
Pin 43, DIO_30
12
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
4.6 Signal Descriptions – RGZ Package
Table 4-3. Signal Descriptions – RGZ Package
PIN
TYPE
DESCRIPTION
NAME
NO.
33
23
6
DCDC_SW
DCOUPL
DIO_1
Power
Output from internal DC/DC(1)(2)
Power
1.27-V regulated digital-supply (decoupling capacitor)(2)
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
GPIO, Sensor Controller
DIO_2
7
GPIO, Sensor Controller
DIO_3
8
GPIO, Sensor Controller
DIO_4
9
GPIO, Sensor Controller
DIO_5
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
–
GPIO, Sensor Controller, high-drive capability
DIO_6
GPIO, Sensor Controller, high-drive capability
DIO_7
GPIO, Sensor Controller, high-drive capability
DIO_8
GPIO
DIO_9
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
EGP
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
GPIO
GPIO
GPIO
GPIO
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Digital or analog I/O GPIO, Sensor Controller, analog
Power
Ground; exposed ground pad
JTAG TMSC, high-drive capability
JTAG TCKC(3)
JTAG_TMSC
JTAG_TCKC
RESET_N
24
25
35
Digital I/O
Digital I/O
Digital input
Reset, active-low. No internal pullup.
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_N
RF_P
2
1
RF I/O
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
(1) See technical reference manual listed in 节 8.3 for more details.
(2) Do not supply external circuitry from this pin.
(3) For design consideration regrading noise immunity for this pin, see the JTAG Interface chapter in the CC13x0, CC26x0 SimpleLink™
Wireless MCU Technical Reference Manual.
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Table 4-3. Signal Descriptions – RGZ Package (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
45
48
44
13
22
34
46
47
3
VDDR
Power
Power
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(4)
1.7-V to 1.95-V supply, connect to output of internal DC/DC(2)(5)
1.8-V to 3.8-V main chip supply(1)
1.8-V to 3.8-V DIO supply(1)
VDDR_RF
VDDS
Power
VDDS2
Power
VDDS3
Power
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
X24M_N
X24M_P
RX_TX
Power
1.8-V to 3.8-V DC/DC supply
Analog I/O
Analog I/O
RF I/O
24-MHz crystal oscillator pin 1
24-MHz crystal oscillator pin 2
Optional bias pin for the RF LNA
X32K_Q1
X32K_Q2
4
Analog I/O
Analog I/O
32-kHz crystal oscillator pin 1
5
32-kHz crystal oscillator pin 2
(4) If internal DC/DC is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC is not used, this pin must be connected to VDDR for supply from the main LDO.
14
Terminal Configuration and Functions
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
Supply voltage (VDDS, VDDS2, and VDDS3)
Voltage on any digital pin(3)(4)
4.1
V
V
V
VDDSn + 0.3, max 4.1
Voltage on crystal oscillator pins X32K_Q1, X32K_Q2, X24M_N, and X24M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Voltage on ADC input (Vin) Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
Input RF level
V
VDDS / 2.9
10
dBm
°C
Storage temperature (Tstg
)
–40
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) Including analog-capable DIO.
(4) Each pin is referenced to a specific VDDSn (VDDS, VDDS2 or VDDS3). For a pin-to-VDDS mapping table, see Table 6-3.
5.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged device model (CDM), per JESD22-C101(2)
All pins
All pins
±3000
±500
VESD
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Ambient temperature
–40
1.8
1.8
1.9
0
85
3.8
3.8
3.8
100
20
°C
V
Operating supply voltage (VDDS)
For operation in battery-powered and
Operating supply voltages (VDDS2 and VDDS3) 3.3-V systems (internal DC/DC can be
VDDS < 2.7 V
V
used to minimize power consumption)
Operating supply voltages (VDDS2 and VDDS3)
VDDS ≥ 2.7 V
V
Rising supply voltage slew rate
mV/µs
mV/µs
mV/µs
Falling supply voltage slew rate
Falling supply voltage slew rate, with low-power flash setting(1)
0
3
No limitation for negative temperature gradient, or outside
standby mode
Positive temperature gradient in standby(2)
5
°C/s
(1) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see ).
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5.4 Power Consumption Summary
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design unless otherwise noted. Tc = 25°C, VDDS = 3.6 V
with DC/DC enabled, unless otherwise noted. Using boost mode (increasing VDDR to 1.95 V), will increase currents in this
table by 15% (does not apply to TX 14-dBm setting where this current is already included).
PARAMETER
TEST CONDITIONS
TYP
100
185
0.7
UNIT
Reset. RESET_N pin asserted or VDDS below power-on-reset
threshold
nA
Shutdown. No clocks running, no retention
Standby. With RTC, CPU, RAM, and (partial) register retention.
RCOSC_LF
Standby. With RTC, CPU, RAM, and (partial) register retention.
XOSC_LF
µA
0.8
Idle. Supply Systems and RAM powered.
Active. MCU running CoreMark at 48 MHz
Active. MCU running CoreMark at 48 MHz
Active. MCU running CoreMark at 24 MHz
Radio RX, 868 MHz
570
1.2 mA + 25.5 µA/MHz
2.5
1.9
mA
Core current
consumption
Icore
5.5
mA
mA
mA
Radio TX, 10-dBm output power, (G)FSK, 868 MHz
Radio TX, OOK modulation, 10-dBm output power, AVG
13.4
11.2
Radio TX, boost mode (VDDR = 1.95 V), 14-dBm output power,
(G)FSK, 868 MHz
23.5
14.8
25.1
13.2
mA
mA
mA
mA
Radio TX, OOK modulation, boost mode (VDDR = 1.95 V), 14-
dBm, AVG
Radio TX, boost mode (VDDR = 1.95 V), 15-dBm output power,
(G)FSK, measured on CC1310EM-7XD-4251, 433.92 MHz
Radio TX, 10-dBm output power, measured on CC1310EM-
7XD-4251, 433.92 MHz
PERIPHERAL CURRENT CONSUMPTION(1)(2)(3)
Peripheral power
domain
Delta current with domain enabled
20
13
Serial power domain
Delta current with domain enabled
Delta current with power domain enabled,
clock enabled, RF core idle
RF core
237
µDMA
Timers
I2C
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
Delta current with clock enabled, module idle
130
113
12
Iperi
µA
I2S
36
SSI
93
UART
164
(1) Adds to core current Icore for each peripheral unit activated
(2) Iperi is not supported in standby or shutdown modes.
(3) Measured at 3.0 V
5.5 RF Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
287(1)
359(1)
431
TYP
MAX UNIT
351(1)
439(1)
Frequency bands
527 MHz
878(1)
718(1)
861
1054
(1) These frequency bands are functionally verified. Radio settings for specific physical layer parameters can be made available upon
request.
16
Specifications
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5.6 Receive (RX) Parameters, 861 MHz to 1054 MHz
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Data rate
Up to 4 Mbps
bps
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode), BER = 10–3
Data rate offset tolerance,
IEEE 802.15.4g PHY
1600
1.5
ppm
Data rate step size
bps
Digital channel filter programmable
bandwidth
Using VCO divide by 5 setting
40
4000 kHz
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode), BER = 10–2. 868 MHz and 915 MHz
Receiver sensitivity, 50 kbps
Receiver saturation
–110
10
dBm
dBm
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode), BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Selectivity, ±200 kHz, 50 kbps
Selectivity, ±400 kHz, 50 kbps
Blocking ±1 MHz, 50 kbps
Blocking ±2 MHz, 50 kbps
Blocking ±5 MHz, 50 kbps
Blocking ±10 MHz, 50 kbps
44, 47
48, 53
59, 62
64, 65
67, 68
dB
dB
dB
dB
dB
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
76, 76
–70
dB
dBm
dB
Spurious emissions 1 GHz to 13 GHz
(VCO leakage at 3.5 GHz) and
30 MHz to 1 GHz
Conducted emissions measured according to
ETSI EN 300 220
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), 50 kbps
44
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode). Starting from the sensitivity limit. This range will
give an accuracy of ±2 dB.
RSSI dynamic range
RSSI accuracy
95
±2
dB
dB
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode). Starting from the sensitivity limit across the given
dynamic range.
GFSK, 175-kHz deviation, 1.243-MHz RX bandwidth,
BER = 10–2
Receiver sensitivity, 500 kbps
Blocking, ±2 MHz, 500 kbps
–97
dBm
dB
Wanted signal 3 dB above sensitivity limit. 500 kbps,
GFSK, 175-kHz deviation, 1.243-MHz RX bandwidth,
BER = 10–2
35, 36
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Receive (RX) Parameters, 861 MHz to 1054 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal 3 dB above sensitivity limit. 500 kbps,
GFSK, 175-kHz deviation, 1.243-MHz RX bandwidth,
BER = 10–2
Blocking, ±10 MHz, 500 kbps
55, 47
dB
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
Receiver sensitivity, long-range mode,
5 kbps
DSSS = 2, 49-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHz
.
–119
–120
dBm
dBm
dBm
dB
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
Receiver sensitivity, long-range mode,
2.5 kbps
DSSS = 4, 49-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHz
.
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
Receiver sensitivity, long-range mode,
1.25 kbps
DSSS = 8, 49-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHz
.
–121
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Selectivity, ±100 kHz, long-range mode,
5 kbps
47, 47
54, 55
57, 56
68, 67
74, 74
85, 85
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Selectivity, ±200 kHz, long-range mode,
5 kbps
dB
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Selectivity, ±300 kHz, long-range mode,
5 kbps
dB
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Blocking, ±1 MHz, long-range mode,
5 kbps
dB
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Blocking, ±2 MHz, long-range mode,
5 kbps
dB
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
Blocking, ±10 MHz, long-range mode,
5 kbps
dB
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), long-range
mode, 5 kbps
Wanted signal 3 dB above sensitivity limit. 20 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 2,
49-kHz RX bandwidth, BER = 10–2
52
–111
dB
dBm
dB
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, wM-BUS S2-mode,
32.768 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Selectivity, ±200 kHz, wM-BUS
S2-mode, 32.768 kbps
42, 43
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Selectivity, ±400 kHz, wM-BUS
S2-mode, 32.768 kbps
41, 47
43, 52
52, 55
68, 72
dB
dB
dB
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Blocking, ±1 MHz, wM-BUS S2-mode,
32.768 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Blocking, ±2 MHz, wM-BUS S2-mode,
32.768 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
Blocking, ±10 MHz, wM-BUS S2-mode,
32.768 kbps
18
Specifications
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CC1310
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
Receive (RX) Parameters, 861 MHz to 1054 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), wM-BUS
S2-mode, 32.768 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 868.3 MHz, 32.768 ksym/s, Manchester coding,
FSK, 50-kHz deviation, 196-kHz RX bandwidth,
BER = 10–2
43
dB
Receiver sensitivity, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
–107
dBm
dB
Wanted signal 3 dB above sensitivity limit.
Selectivity, ±400 kHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
41, 46
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Selectivity, ±800 kHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
41, 50
43, 51
51, 53
55, 61
dB
dB
dB
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±1 MHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±2 MHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±5 MHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±10 MHz, wM-BUS C-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, NRZ coding, FSK,
67, 68
–105
dB
dBm
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Receiver sensitivity, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Selectivity, ±400 kHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
41, 46
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Selectivity, ±800 kHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
41, 50
42, 51
51, 52
54, 60
67, 68
–109
dB
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±1 MHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±2 MHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±5 MHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit.
Blocking, ±10 MHz, wM-BUS T-mode,
100 kbps
fRF = 868.95 MHz, 100 ksym/s, 3 out of 6 coding, FSK,
dB
45-kHz deviation, 196-kHz RX bandwidth, BER = 10–2
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 8, 622-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, WideBand-DSSS
(WB-DSSS), 30 kbps
dBm
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 8, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±1 MHz, WB-DSSS, 30 kbps
Blocking, ±2 MHz, WB-DSSS, 30 kbps
57, 57
58, 58
dB
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 8, 622-kHz RX bandwidth,
BER = 10–2
Copyright © 2015–2018, Texas Instruments Incorporated
Specifications
19
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
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Receive (RX) Parameters, 861 MHz to 1054 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 8, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±5 MHz, WB-DSSS, 30 kbps
59, 57
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 8, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±10 MHz, WB-DSSS, 30 kbps
71, 68
–108
dB
dBm
dB
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 4, 622-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, WideBand-DSSS
(WB-DSSS), 60 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 4, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±1 MHz, WB-DSSS, 60 kbps
Blocking, ±2 MHz, WB-DSSS, 60 kbps
Blocking, ±5 MHz, WB-DSSS, 60 kbps
Blocking, ±10 MHz, WB-DSSS, 60 kbps
56, 56
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 4, 622-kHz RX bandwidth,
BER = 10–2
57, 57
57, 56
dB
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 4, 622-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 4, 622-kHz RX bandwidth,
BER = 10–2
70, 67
–106
dB
dBm
dB
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 2, 622-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, WideBand-DSSS
(WB-DSSS), 120 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 2, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±1 MHz, WB-DSSS, 120 kbps
Blocking, ±2 MHz, WB-DSSS, 120 kbps
Blocking, ±5 MHz, WB-DSSS, 120 kbps
Blocking, ±10 MHz, WB-DSSS, 120 kbps
54, 54
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 2, 622-kHz RX bandwidth,
BER = 10–2
55, 55
55, 54
dB
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 2, 622-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 2, 622-kHz RX bandwidth,
BER = 10–2
69, 65
–105
dB
dBm
dB
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 1, 622-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, WideBand-DSSS
(WB-DSSS), 240 kbps
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 1, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±1 MHz, WB-DSSS, 240 kbps
Blocking, ±2 MHz, WB-DSSS, 240 kbps
53, 53
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 1, 622-kHz RX bandwidth,
BER = 10–2
53, 54
dB
20
Specifications
Copyright © 2015–2018, Texas Instruments Incorporated
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CC1310
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
Receive (RX) Parameters, 861 MHz to 1054 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 1, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±5 MHz, WB-DSSS, 240 kbps
53, 54
dB
Wanted signal 3 dB above sensitivity limit.
fRF = 915 MHz, 480 ksym/s, GFSK, 195-kHz deviation,
FEC (half rate), DSSS = 1, 622-kHz RX bandwidth,
BER = 10–2
Blocking, ±10 MHz, WB-DSSS, 240 kbps
68, 64
dB
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, 10 kbps
Selectivity, ±100 kHz, 10 kbps
–114
dBm
dB
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
40, 40
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
Selectivity, ±200 kHz, 10 kbps
Selectivity, ±400 kHz, 10 kbps
Blocking, ±2 MHz, 10 kbps
Blocking, ±10 MHz, 10 kbps
46, 44
50, 45
62, 61
76, 72
dB
dB
dB
dB
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), 10 kbps
Wanted signal 3 dB above sensitivity limit. 10 kbps,
GFSK, 19-kHz deviation, 78-kHz RX bandwidth,
BER = 10–2
43
–114
dB
dBm
dB
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Receiver sensitivity, 4.8 kbps
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Selectivity, ±100 kHz, 4.8 kbps
44, 43
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Selectivity, ±200 kHz, 4.8 kbps
Selectivity, ±400 kHz, 4.8 kbps
Blocking, ±2 MHz, 4.8 kbps
Blocking, ±10 MHz, 4.8 kbps
49, 48
52, 49
64, 63
73, 72
dB
dB
dB
dB
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), 4.8 kbps
Wanted signal 3 dB above sensitivity limit. 4.8 kbps,
GFSK, 5.2-kHz deviation, 49-kHz RX bandwidth,
BER = 10–2
43
–116
dB
dBm
dB
Receiver sensitivity, CC1101 compatible GFSK, 5.2-kHz deviation (commonly used settings on
mode, 2.4 kbps
CC1101), 49-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit. 2.4 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Selectivity, ±100 kHz, CC1101
compatible mode, 2.4 kbps
45, 44
Wanted signal 3 dB above sensitivity limit. 2.4 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Selectivity, ±200 kHz, CC1101
compatible mode, 2.4 kbps
51, 47
dB
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Specifications
21
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Receive (RX) Parameters, 861 MHz to 1054 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Wanted signal 3 dB above sensitivity limit. 2.4 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Blocking, ±2 MHz, CC1101 compatible
mode, 2.4 kbps
63, 62
dB
Wanted signal 3 dB above sensitivity limit. 2.4 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Blocking, ±10 MHz, CC1101 compatible
mode, 2.4 kbps
76, 71
45
dB
dB
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), CC1101
compatible mode, 2.4 kbps
Wanted signal 3 dB above sensitivity limit. 2.4 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Receiver sensitivity, CC1101 compatible GFSK, 5.2-kHz deviation (commonly used settings on
mode, 1.2 kbps
–117
dBm
dB
CC1101), 49-kHz RX bandwidth, BER = 10–2
Wanted signal 3 dB above sensitivity limit. 1.2 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Selectivity, ±100 kHz, CC1101
compatible mode, 1.2 kbps
45, 44
Wanted signal 3 dB above sensitivity limit. 1.2 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Selectivity, ±200 kHz, CC1101
compatible mode, 1.2 kbps
51, 47
63, 62
81, 81
dB
dB
dB
Wanted signal 3 dB above sensitivity limit. 1.2 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Blocking, ±2 MHz, CC1101 compatible
mode, 1.2 kbps
Wanted signal 3 dB above sensitivity limit. 1.2 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
Blocking, ±10 MHz, CC1101 compatible
mode, 1.2 kbps
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), CC1101
compatible mode, 1.2 kbps
Wanted signal 3 dB above sensitivity limit. 1.2 kbps,
GFSK, 5.2-kHz deviation (commonly used settings on
CC1101), 49-kHz RX bandwidth, BER = 10–2
45
dB
10 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
Receiver sensitivity, legacy long-range
mode, 625 bps
DSSS = 8, 40-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHz.
.
–124
56, 56
62, 65
73, 77
79, 79
dBm
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Selectivity, ±100 kHz, legacy long-range
mode, 625 bps
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Selectivity, ±200 kHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±1 MHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±2 MHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±10 MHz, legacy long-range
mode, 625 bps
91, 91
–115
dB
4.8 kbps, OOK, 40-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHz
.
Receiver sensitivity, OOK, 4.8 kbps
dBm
22
Specifications
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ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
5.7 Receive (RX) Parameters, 431 MHz to 527 MHz
Measured on the Texas Instruments CC1310EM-7XD-4251 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 433.92 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. This frequency band is supported on die Revision B and later.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode), BER = 10–2
Receiver sensitivity, 50 kbps
–110
dBm
50 kbps, GFSK, 25-kHz deviation, 100-kHz RX bandwidth
(same modulation format as IEEE 802.15.4g mandatory
mode), BER = 10–2
Receiver saturation
10
dBm
dB
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Selectivity, ±200 kHz, 50 kbps
40, 42
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Selectivity, ±400 kHz, 50 kbps
Blocking ±1 MHz, 50 kbps
Blocking ±2 MHz, 50 kbps
Blocking ±10 MHz, 50 kbps
42, 50
53, 58
59, 60
dB
dB
dB
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
74, 74
–74
dB
dBm
dB
Spurious emissions 1 GHz to 13 GHz
(VCO leakage at 3.5 GHz) and
30 MHz to 1 GHz
Conducted emissions measured according to
ETSI EN 300 220
Wanted signal 3 dB above sensitivity limit. 50 kbps,
GFSK, 25-kHz deviation, 100-kHz RX bandwidth (same
modulation format as IEEE 802.15.4g mandatory mode),
BER = 10–2
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), 50 kbps
43
Receiver sensitivity, long-range mode,
5 kbps
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
–119
–120
–121
dBm
dBm
dBm
DSSS = 2, 49-kHz RX bandwidth, BER = 10–2. 433 MHz
Receiver sensitivity, long-range mode,
2.5 kbps
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
DSSS = 4, 49-kHz RX bandwidth, BER = 10–2. 433 MHz
Receiver sensitivity, long-range mode,
1.25 kbps
20 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
DSSS = 8, 49-kHz RX bandwidth, BER = 10–2. 433 MHz
10 ksym/s, GFSK, 5-kHz deviation, FEC (half rate),
Receiver sensitivity, legacy long-range
mode, 625 bps
DSSS = 8, 40-kHz RX bandwidth, BER = 10–2
868 MHz and 915 MHZ.
.
–124
57, 58
56, 60
68, 73
74, 74
88, 89
dBm
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Selectivity, ±100 kHz, legacy long-range
mode, 625 bps
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Selectivity, ±200 kHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±1 MHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±2 MHz, legacy long-range
mode, 625 bps
dB
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
Blocking ±10 MHz, legacy long-range
mode, 625 bps
dB
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Receive (RX) Parameters, 431 MHz to 527 MHz (continued)
Measured on the Texas Instruments CC1310EM-7XD-4251 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 433.92 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. This frequency band is supported on die Revision B and later.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Image rejection (image compensation
enabled, the image compensation is
calibrated in production), legacy long-
range mode, 625 bps
Wanted signal 3 dB above sensitivity limit. 10 ksym/s,
GFSK, 5-kHz deviation, FEC (half rate), DSSS = 8,
40-kHz RX bandwidth, BER = 10–2
55
dB
24
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5.8 Transmit (TX) Parameters, 861 MHz to 1054 MHz
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 868 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDDR = 1.95 V
Maximum output power, boost mode
Minimum VDDS for boost mode is 2.1 V
868 MHz and 915 MHz
14
dBm
Maximum output power
868 MHz and 915 MHz
12
24
dBm
dB
Output power programmable range
Output power variation
Tested at +10-dBm setting
+14 dBm
±0.9
±0.5
dB
Output power variation, boost mode
dB
Transmitting +14 dBm
ETSI restricted bands
<–59
<–51
30 MHz to 1 GHz
Spurious emissions
Transmitting +14 dBm
outside ETSI restricted bands
dBm
dBm
(excluding harmonics)(1)
Transmitting +14 dBm
measured in 1-MHz bandwidth (ETSI)
1 GHz to 12.75 GHz
Second harmonic
Third harmonic
<–37
Transmitting +14 dBm, conducted
868 MHz, 915 MHz
–52, –55
–58, –55
–56, –56
<–66
Transmitting +14 dBm, conducted
868 MHz, 915 MHz
Harmonics
Transmitting +14 dBm, conducted
868 MHz, 915 MHz
Fourth harmonic
30 MHz to 88 MHz
(within FCC restricted bands)
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
88 MHz to 216 MHz
(within FCC restricted bands)
<–65
216 MHz to 960 MHz
(within FCC restricted bands)
Spurious emissions
out-of-band,
<–65
dBm
915 MHz(1)
960 MHz to 2390 MHz and
above 2483.5 MHz (within
FCC restricted band)
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
<–52
<–43
1 GHz to 12.75 GHz
(outside FCC restricted
bands)
Below 710 MHz
(ARIB T-108)
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
Transmitting +14 dBm, conducted
<–50
<–60
<–57
<–57
<–59
<–45
710 MHz to 900 MHz
(ARIB T-108)
900 MHz to 915 MHz
(ARIB T-108)
Spurious emissions
out-of-band,
dBm
920.6 MHz(1)
930 MHz to 1000 MHz
(ARIB T-108)
1000 MHz to 1215 MHz
(ARIB T-108)
Above 1215 MHz
(ARIB T-108)
(1) Suitable for systems targeting compliance with EN 300 220, EN 54-25, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
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5.9 Transmit (TX) Parameters, 431 MHz to 527 MHz
Measured on the Texas Instruments CC1310EM-7XD-4251 reference design with Tc = 25°C, VDDS = 3.0 V, DC/DC enabled,
fRF = 433.92 MHz, unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path. This frequency band is supported on die Revision B and later.
PARAMETER
Maximum output power, boost mode
Maximum output power
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDDR = 1.95 V
Minimum VDDS for boost mode is 2.1 V
15
dBm
14
dBm
Transmitting +10 dBm, 433 MHz
Inside ETSI restricted bands
<–63
30 MHz to 1 GHz
Transmitting +10 dBm, 433 MHz
Outside ETSI restricted bands
<–39
<–52
Spurious emissions
Transmitting +10 dBm, 433 MHz
Outside ETSI restricted bands, measured
in 1-MHz bandwidth (ETSI)
dBm
(excluding harmonics)(1)
1 GHz to 12.75 GHz
Transmitting +10 dBm, 433 MHz
Inside ETSI restricted bands, measured in
1-MHz bandwidth (ETSI)
<–58
(1) Suitable for systems targeting compliance with EN 300 220, EN 54-25, EN 303 204, FCC CFR47 Part 15, ARIB STD-T108.
5.10 PLL Parameters
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V
PARAMETER
TEST CONDITIONS
±100-kHz offset
MIN
TYP
–101
–108
–115
–124
–131
–140
–98
MAX
UNIT
±200-kHz offset
±400-kHz offset
±1000-kHz offset
±2000-kHz offset
±10000-kHz offset
±100-kHz offset
±200-kHz offset
±400-kHz offset
±1000-kHz offset
±2000-kHz offset
±10000-kHz offset
Phase noise in the 868-MHz band
dBc/Hz
–106
–114
–122
–130
–140
Phase noise in the 915-MHz band
dBc/Hz
5.11 ADC Characteristics
Tc = 25°C, VDDS = 3.0 V, DC/DC disabled. Input voltage scaling enabled, unless otherwise noted.(1)
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
12
Bits
Sample rate
Offset
200 ksamples/s
Internal 4.3-V equivalent reference(2)
Internal 4.3-V equivalent reference(2)
2.1
LSB
LSB
Gain error
–0.14
Differential
nonlinearity
DNL(3)
INL(4)
>–1
±2
LSB
LSB
Integral nonlinearity
(1) Using IEEE Std 1241™ 2010 for terminology and test methods.
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V. Applied voltage must be within the absolute
maximum ratings (see Section 5.1) at all times.
(3) No missing codes. Positive DNL typically varies from 0.3 to 1.7, depending on the device (see Figure 5-7).
(4) For a typical example, see Figure 5-6.
26
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ADC Characteristics (continued)
Tc = 25°C, VDDS = 3.0 V, DC/DC disabled. Input voltage scaling enabled, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone
10.0
VDDS as reference, 200 ksamples/s, 9.6-kHz input
tone
Effective number of
bits
10.2
11.1
ENOB
Bits
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input
tone
Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone
–65
–72
VDDS as reference, 200 ksamples/s, 9.6-kHz input
tone
Total harmonic
distortion
THD
dB
dB
dB
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input
tone
Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone
–75
62
63
SINAD
and
SNDR
VDDS as reference, 200 ksamples/s, 9.6-kHz input
tone
Signal-to-noise and
distortion ratio
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input
tone
Internal 4.3-V equivalent reference(2), 200 ksamples/s,
9.6-kHz input tone
69
74
75
VDDS as reference, 200 ksamples/s, 9.6-kHz input
tone
Spurious-free
dynamic range
SFDR
Internal 1.44-V reference, voltage scaling disabled,
32 samples average, 200 ksamples/s, 300-Hz input
tone
75
Conversion time
Current consumption Internal 4.3-V equivalent reference(2)
Including sampling time
5
0.66
0.75
µs
mA
mA
Current consumption VDDS as reference
Equivalent fixed internal reference(voltage scaling
(2)
enabled)
Reference voltage
Reference voltage
For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include
the gain/offset compensation factors stored in FCFG1.
4.3
V
V
Fixed internal reference (input voltage scaling
(2)
disabled).
For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include
the gain/offset compensation factors stored in FCFG1.
This value is derived from the scaled value (4.3 V) as
follows:
1.48
Vref = 4.3 V × 1408 / 4095
VDDS as reference (Also known as RELATIVE) (input
voltage scaling enabled)
Reference voltage
Reference voltage
VDDS
V
V
VDDS as reference (Also known as RELATIVE) (input
voltage scaling disabled)
VDDS / 2.82
200 ksamples/s, voltage scaling enabled. Capacitive
input, input impedance depends on sampling frequency
and sampling time
Input Impedance
>1
MΩ
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5.12 Temperature Sensor
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Range
4
–40
85
°C
Accuracy
±5
°C
Supply voltage coefficient(1)
3.2
°C/V
(1) Automatically compensated when using supplied driver libraries.
5.13 Battery Monitor
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
50
1.8
3.8
Accuracy
13
mV
5.14 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
VDDS
VDDS
UNIT
V
Input voltage range
External reference voltage
0
V
Internal reference voltage
Offset
DCOUPL as reference
1.27
3
V
mV
mV
µs
Hysteresis
<2
Decision time
Current consumption when enabled(1)
Step from –10 mV to 10 mV
0.72
8.6
µA
(1) Additionally, the bias module must be enabled when running in standby mode.
5.15 Low-Power Clocked Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
Input voltage range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
VDDS
V
Clock frequency
32.8
kHz
Internal reference voltage, VDDS / 2
Internal reference voltage, VDDS / 3
Internal reference voltage, VDDS / 4
Internal reference voltage, DCOUPL / 1
Internal reference voltage, DCOUPL / 2
Internal reference voltage, DCOUPL / 3
Internal reference voltage, DCOUPL / 4
Offset
1.49 to 1.51
1.01 to 1.03
0.78 to 0.79
1.25 to 1.28
0.63 to 0.65
0.42 to 0.44
0.33 to 0.34
<2
V
V
V
V
V
V
V
mV
Hysteresis
<5
mV
Decision time
Step from –50 mV to 50 mV
1
clock-cycle
nA
Current consumption when enabled
362
28
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5.16 Programmable Current Source
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.25 to 20
0.25
MAX UNIT
Current source programmable output range
Resolution
µA
µA
Including current source at maximum
programmable output
Current consumption(1)
23
µA
(1) Additionally, the bias module must be enabled when running in standby mode.
5.17 DC Characteristics
PARAMETER
TA = 25°C, VDDS = 1.8 V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.32
1.32
1.54
0.26
1.58
0.21
71.7
21.1
V
V
0.32
0.32
V
IOCURR = 1
V
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
µA
µA
GPIO pulldown current
IH = 0, transition between reading 0 and reading
1
GPIO high/low input transition, no hysteresis
0.88
V
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
IH = 1, transition voltage for input read as 1 → 0
1.07
0.74
V
V
IH = 1, difference between 0 → 1
and 1 → 0 voltage transition points
GPIO input hysteresis
0.33
V
TA = 25°C, VDDS = 3.0 V
GPIO VOH at 8-mA load
GPIO VOL at 8-mA load
GPIO VOH at 4-mA load
GPIO VOL at 4-mA load
TA = 25°C, VDDS = 3.8 V
GPIO pullup current
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.68
0.33
2.72
0.28
V
V
V
V
IOCURR = 1
Input mode, pullup enabled, Vpad = 0 V
277
113
µA
µA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
IH = 0, transition between reading 0 and reading
1
GPIO high/low input transition, no hysteresis
1.67
V
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
IH = 1, transition voltage for input read as 0 → 1
IH = 1, transition voltage for input read as 1 → 0
1.94
1.54
V
V
IH = 1, difference between 0 → 1 and 1 → 0
voltage transition points
GPIO input hysteresis
0.4
V
Lowest GPIO input voltage reliably interpreted as
a High
VIH
VIL
0.8 VDDS(1)
VDDS(1)
Highest GPIO input voltage reliably interpreted
as a Low
0.2
(1) Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in 节 8.3 for more details.
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5.18 Thermal Characteristics
CC1310
RSM
(VQFN)
RHB
(VQFN)
RGZ
(VQFN)
THERMAL METRIC(1)
UNIT(2)
32 PINS
36.9
30.3
7.6
32 PINS
32.8
24.0
6.8
48 PINS
29.6
15.7
6.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
0.3
0.3
ψJB
7.4
6.8
6.2
RθJC(bot) Junction-to-case (bottom) thermal resistance
2.1
1.9
1.9
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
5.19 Timing and Switching Characteristics
5.19.1 Reset Timing
Table 5-1. Reset Timing
PARAMETER
MIN TYP
MAX UNIT
RESET_N low duration
1
µs
5.19.2 Wakeup Timing
Table 5-2. Wakeup Timing
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted. The times listed here do not include RTOS overhead.
PARAMETER
MCU, Idle → Active
TEST CONDITIONS
MIN
TYP
14
MAX
UNIT
µs
MCU, Standby → Active
MCU, Shutdown → Active
174
1097
µs
µs
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5.19.3 Clock Specifications
Table 5-3. 24-MHz Crystal Oscillator (XOSC_HF)
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.Section 5.19.1
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
Ω
ESR equivalent series resistanceSection 5.19.2
ESR equivalent series resistanceSection 5.19.2
6 pF < CL ≤ 9 pF
5 pF < CL ≤ 6 pF
20
80
Ω
Relates to load capacitance
(CL in Farads)
2
LM motional inductanceSection 5.19.2
< 1.6 × 10–24 / CL
H
CL crystal load capacitanceSection 5.19.2
Crystal frequencySection 5.19.2
Start-up time
5
9
pF
MHz
µs
24
150
Table 5-4. 32.768-kHz Crystal Oscillator (XOSC_LF)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted.(1)
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
Crystal frequency
ESR equivalent series resistance
Crystal load capacitance (CL)
100
12
6
pF
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
Table 5-5. 48-MHz RC Oscillator (RCOSC_HF)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted.
MIN
TYP
48
MAX
UNIT
Frequency
MHz
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Startup time
±1%
±0.25%
5
µs
(1) Accuracy relative to the calibration source (XOSC_HF)
Table 5-6. 32-kHz RC Oscillator (RCOSC_LF)
Measured on the Texas Instruments CC1310EM-7XD-7793 reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise
noted.
MIN
TYP
32.768
50
MAX
UNIT
kHz
Calibrated frequency(1)
Temperature coefficient
ppm/°C
(1) The frequency accuracy of the Real Time Clock (RTC) is not directly dependent on the frequency accuracy of the 32-kHz RC Oscillator.
The RTC can be calibrated by measuring the frequency error of RCOSC_LF relative to XOSC_HF and compensating for the RTC tick
speed.
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5.19.4 Flash Memory Characteristics
Table 5-7. Flash Memory Characteristics
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
k Cycles
mA
Supported flash erase cycles before failure
Flash page or sector erase current
Flash page or sector erase time(1)
Flash page or sector size
100
Average delta current
12.6
8
ms
4
KB
Flash write current
Flash write time(1)
Average delta current, 4 bytes at a time
4 bytes at a time
8.15
8
mA
µs
(1) This number is dependent on flash aging and increases over time and erase cycles.
5.19.5 Synchronous Serial Interface (SSI) Characteristics
Table 5-8. Synchronous Serial Interface (SSI) Characteristics
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
NO.
PARAMETER
MIN
TYP
MAX
UNIT
S1
tclk_per
tclk_high
tclk_low
SSIClk cycle time
12
65024 system clocks
S2(1)
S3(1)
SSIClk high time
SSIClk low time
0.5 × tclk_per
0.5 × tclk_per
(1) See the SSI timing diagrams, Figure 5-1, Figure 5-2, and Figure 5-3.
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
32
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S2
S1
SSIClk
SSIFss
SSITx
SSIRx
S3
MSB
LSB
8-bit control
0
MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
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5.20 Typical Characteristics
7
6
5
4
3
2
1
0
5
Active Mode Current
4.5
4
3.5
3
2.5
2
-40
-20
0
20
40
60
80
100110
1.8
2.3
2.8
VDDS (V)
3.3
3.8
Temperature (èC)
D037
D007
Figure 5-5. Standby MCU Current Consumption, 32-kHz Clock,
RAM and MCU Retention
Figure 5-4. Active Mode (MCU) Current Consumption vs
Supply Voltage (VDDS)
2
1.5
1
1
0.5
0
0
-1
-2
-0.5
-1
0
500 1000 1500 2000 2500 3000 3500 4000
Digital Output Code
0
500 1000 1500 2000 2500 3000 3500 4000
Digital Output Code
D007
D008
Figure 5-6. SoC ADC, Integral Nonlinearity vs
Digital Output Code
Figure 5-7. SoC ADC, Differential Nonlinearity vs
Digital Output Code
1007.5
1006.4
1006.2
1006
1007
1006.5
1006
1005.8
1005.6
1005.4
1005.2
1005
1005.5
1005
1004.5
1004
1003.5
1004.8
-40
-20
0
20
40
60
80
100
1.8
2.3
2.8
VDDS (V)
3.3
3.8
Termperature (èC)
D036
D012
Figure 5-9. SoC ADC Output vs Temperature
(Fixed Input, Internal Reference, No Scaling)
Figure 5-8. SoC ADC Output vs Supply Voltage
(Fixed Input, Internal Reference, No Scaling)
34
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-106
-106.5
-107
-107.5
-108
-108.5
-109
-109.5
-110
-110.5
-111
863
865
867
869
871
873
875 876
Frequency (MHz)
D011
Figure 5-11. RX (50-kbps) Sensitivity vs Frequency
Figure 5-10. RX, (50-kbps) Packet Error Rate (PER) vs
Input RF Level vs Frequency Offset, 868 MHz
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
-10
-10
-10
-10
-8
-6
-4
-2
0
2
4
6
8
10
-8
-6
-4
-2
0
2
4
6
8
10
Frequency offset (MHz)
Frequency offset (MHz)
D012
D013
Figure 5-12. RX (50-kbps) Selectivity 868 MHz
Figure 5-13. RX (50-kbps) Selectivity 915 MHz
-106
6
5.8
5.6
5.4
5.2
5
-106.5
-107
-107.5
-108
-108.5
-109
-109.5
-110
-110.5
-111
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
-40
-20
0
20
40
60
80 90
Temperaure (°C)
D014
D015
Figure 5-14. RX (50-kbps) Current Consumption vs
Temperature 868 MHz
Figure 5-15. RX (50-kbps) Sensitivity vs Temperature 868 MHz
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11
10.5
10
9.5
9
-106.2
-106.8
-107.4
-108
8.5
8
-108.6
-109.2
-109.8
-110.4
-111
7.5
7
6.5
6
5.5
5
1.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperaure (°C)
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
D016
D019
Figure 5-16. RX (50-kbps) Sensitivity vs Temperature 915 MHz
Figure 5-17. RX (50-kbps) Current Consumption vs
Supply Voltage 915 MHz
-106
-106.5
-107
23
22.9
22.8
22.7
22.6
22.5
22.4
22.3
22.2
22.1
22
-107.5
-108
-108.5
-109
-109.5
-110
-110.5
-111
-40
-20
0
20
40
60
80
100
1.8
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
Temperature (èC)
D003
D020
DCDC On, 3.6 V
Figure 5-19. TX Current Consumption With Maximum
Output Power vs Temperature 868 MHz
Figure 5-18. RX (50-kbps) Sensitivity vs Supply Voltage 868 MHz
14.8
11
10.8
10.6
10.4
10.2
10
14.6
14.4
14.2
14
9.8
9.6
9.4
9.2
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
D017
D018
Figure 5-20. TX Maximum Output vs Temperature 868 MHz
Figure 5-21. TX 10-dBm Output Power vs Temperature 868 MHz
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40
14.8
14.7
14.6
14.5
14.4
14.3
14.2
14.1
14
35
30
25
20
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VDDS (V)
VDDS (V)
D021
D022
Figure 5-22. TX Current Consumption Maximum Output Power
Figure 5-23. TX Maximum Output Power
vs
vs
Supply Voltage 868 MHz
Supply Voltage 915 MHz
11
10.8
10.6
10.4
10.2
10
9.8
9.6
9.4
9.2
1.8
2
2.2 2.4 2.6 2.8
VDDS (V)
3
3.2 3.4 3.6 3.8
D023
Figure 5-24. TX 10-dBm Output Power
vs
Supply Voltage 868 MHz
SPACER
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6 Detailed Description
6.1 Overview
节 1.4 shows a block diagram of the core modules of the CC13xx product family.
6.2 Main CPU
The CC1310 SimpleLink Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the
application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
The CM3 features include the following:
•
•
•
32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
Outstanding processing performance combined with fast interrupt handling
ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
–
–
Single-cycle multiply instruction and hardware divide
Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
–
Unaligned data access, enabling data to be efficiently packed into memory
•
•
•
•
•
•
•
•
•
•
•
•
Fast code execution permits slower processor clock or increases sleep mode time
Harvard architecture characterized by separate buses for instruction and data
Efficient processor core, system, and memories
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Enhanced system debug with extensive breakpoint and trace capabilities
Serial wire trace reduces the number of pins required for debugging and tracing
Migration from the ARM7™ processor family for better performance and power efficiency
Optimized for single-cycle flash memory use
Ultra-low power consumption with integrated sleep modes
1.25 DMIPS per MHz
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6.3 RF Core
The RF core is a highly flexible and capable radio system that interfaces the analog RF and baseband
circuits, handles data to and from the system side, and assembles the information bits in a given packet
structure.
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the
main CPU and leaving more resources for the user application. The RF core offers a high-level,
command-based API to the main CPU.
The RF core supports a wide range of modulation formats, frequency bands, and accelerator features,
which include the following:
•
Wide range of data rates:
From 625 bps (offering long range and high robustness) to as high as 4 Mbps
Wide range of modulation formats:
–
•
–
–
–
Multilevel (G) FSK and MSK
On-Off Keying (OOK) with optimized shaping to minimize adjacent channel leakage
Coding-gain support for long range
•
Dedicated packet handling accelerators:
–
–
–
–
Forward error correction
Data whitening
802.15.4g mode-switch support
Automatic CRC
•
•
•
•
Automatic listen-before-talk (LBT) and clear channel assist (CCA)
Digital RSSI
Highly configurable channel filtering, supporting channel spacing schemes from 40 kHz to 4 MHz
High degree of flexibility, offering a future-proof solution
The RF core interfaces a highly flexible radio, with a high-performance synthesizer that can support a wide
range of frequency bands.
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6.4 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals
in this domain may be controlled by the Sensor Controller Engine, which is a proprietary power-optimized
CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby significantly
reducing power consumption and offloading the main CM3 CPU.
A PC-based development tool called Sensor Controller Studio is used to write, test, and debug code for
the Sensor Controller. The tool produces C driver source code, which the System CPU application uses to
control and exchange data with the Sensor Controller. Typical use cases may be (but are not limited to)
the following:
•
•
•
•
•
•
•
Analog sensors using integrated ADC
Digital sensors using GPIOs with bit-banged I2C or SPI
Capacitive sensing
Waveform generation
Pulse counting
Key scan
Quadrature decoder for polling rotational sensors
The peripherals in the Sensor Controller include the following:
•
The low-power clocked comparator can be used to wake the device from any state in which the
comparator is active. A configurable internal reference can be used with the comparator. The output of
the comparator can also be used to trigger an interrupt or the ADC.
•
Capacitive sensing functionality is implemented through the use of a constant current source, a time-
to-digital converter, and a comparator. The continuous time comparator in this block can also be used
as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller takes
care of baseline tracking, hysteresis, filtering, and other related functions.
•
•
The ADC is a 12-bit, 200-ksamples/s ADC with 8 inputs and a built-in voltage reference. The ADC can
be triggered by many different sources, including timers, I/O pins, software, the analog comparator,
and the RTC.
The analog modules can be connected to up to eight different GPIOs (see Table 6-1).
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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Table 6-1. GPIOs Connected to the Sensor Controller(1)
CC13x0
ANALOG CAPABLE
7 × 7 RGZ
5 × 5 RHB
4 × 4 RSM
DIO NUMBER
DIO NUMBER
DIO NUMBER
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
30
29
28
27
26
25
24
23
7
14
13
12
11
9
9
8
7
6
5
2
1
0
10
8
7
4
6
3
5
2
4
1
3
0
2
1
0
(1) Depending on the package size, up to 15 pins can be connected to the Sensor Controller. Up to eight
of these pins can be connected to analog modules.
6.5 Memory
The flash memory provides nonvolatile storage for code and data. The flash memory is in-system
programmable.
The SRAM (static RAM) is split into two 4-KB blocks and two 6-KB blocks and can be used to store data
and execute code. Retention of the RAM contents in standby mode can be enabled or disabled
individually for each block to minimize power consumption. In addition, if flash cache is disabled, the 8-KB
cache can be used as general-purpose RAM.
The ROM provides preprogrammed, embedded TI-RTOS kernel and Driverlib. The ROM also contains a
bootloader that can be used to reprogram the device using SPI or UART.
6.6 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1)
interface.
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6.7 Power Management
To minimize power consumption, the CC1310 device supports a number of power modes and power-
management features (see Table 6-2).
Table 6-2. Power Modes
SOFTWARE-CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Active
Off
Off
Off
Off
Flash
SRAM
Radio
On
Available
On
Off
On
On
Off
Off
Available
Available
On
Off
Off
Off
Supply System
On
Duty Cycled
0.6 µA
174 µs
Partial
Full
Off
Off
Current
1.2 mA + 25.5 µA/MHz
570 µA
14 µs
Full
185 nA
1015 µs
No
0.1 µA
1015 µs
No
Wake-up Time to CPU Active(1)
Register Retention
SRAM Retention
–
Full
Full
Full
No
No
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
High-Speed Clock
Low-Speed Clock
Off
Off
Off
Off
Off
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
Available
Available
Active
Available
Available
Available
Available
Available
Active
Off
Available
Available
Available
Available
Duty Cycled(2)
Active
Off
Off
Off
Off
Sensor Controller
Wake-up on RTC
Off
Off
Wake-up on Pin Edge
Wake-up on Reset Pin
Brown Out Detector (BOD)
Power On Reset (POR)
Available
Available
Off
Off
Available
N/A
Active
Active
Active
N/A
(1) Not including RTOS overhead.
(2) The Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold
between two recharge periods while in STANDBY may cause the BOD to lock the device upon wakeup until a Reset/POR releases it.
To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the
specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a
battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply
voltage again (for example, inserting new batteries). This restriction does not apply to CC1310 die revision B or later.
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
any available clock source (see Table 6-2).
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event returns the processor to active mode.
In standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or
Sensor Controller event is required to return the device to active mode. MCU peripherals with retention do
not need to be reconfigured when waking up again, and the CPU continues execution from where it went
into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller),
and the I/Os are latched with the value they had before entering shutdown mode. A change of state on
any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger.
The CPU can differentiate between reset in this way and reset-by-reset pin or POR by reading the reset
status register. The only state retained in this mode is the latched I/O state and the flash memory
contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independent of the main CPU. This means that the main CPU does not have to wake up, for
example to execute an ADC sample or poll a digital sensor over SPI, thus saving both current and wake-
up time that would otherwise be wasted. The Sensor Controller Studio lets the user configure the Sensor
Controller and choose which peripherals are controlled and which conditions wake up the main CPU.
6.8 Clock Systems
The CC1310 device supports two external and two internal clock sources.
A 24-MHz external crystal is required as the frequency reference for the radio. This signal is doubled
internally to create a 48-MHz clock.
The 32.768-kHz crystal is optional. The low-speed crystal oscillator is designed for use with a 32.768-kHz
watch-type crystal.
The internal high-speed RC oscillator (48-MHz) can be used as a clock source for the CPU subsystem.
The internal low-speed RC oscillator (32-kHz) can be used as a reference if the low-power crystal
oscillator is not used.
The 32-kHz clock source can be used as external clocking reference through GPIO.
6.9 General Peripherals and Modules
The I/O controller controls the digital I/O pins and contains multiplexer circuitry to assign a set of
peripherals to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five
GPIOs have high-drive capabilities, which are marked in bold in Section 4.
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's
synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz.
The UART implements a universal asynchronous receiver and transmitter function. The UART supports
flexible baud-rate generation up to a maximum of 3 Mbps.
Timer 0 is a general-purpose timer module (GPTM) that provides two 16-bit timers. The GPTM can be
configured to operate as a single 32-bit timer, dual 16-bit timers, or as a PWM module.
Timer 1, Timer 2, and Timer 3 are also GPTMs; each timer is functionally equivalent to Timer 0.
In addition to these four timers, a separate timer in the RF core handles timing for RF protocols; the RF
timer can be synchronized to the RTC.
The I2S interface is used to handle digital audio (for more information, see the CC13x0, CC26x0
SimpleLink™ Wireless MCU Technical Reference Manual).
The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave.
The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys,
initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring
oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
The watchdog timer is used to regain control if the system fails due to a software error after an external
device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a
predefined time-out value is reached.
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The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to
offload data-transfer tasks from the CM3 CPU, thus allowing for more efficient use of the processor and
the available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals.
The µDMA controller has dedicated channels for each supported on-chip module and can be programmed
to automatically perform transfers between peripherals and memory when the peripheral is ready to
transfer more data.
Some features of the µDMA controller follow (this is not an exhaustive list):
•
•
Highly flexible and configurable channel operation of up to 32 channels
Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-
peripheral
•
Data sizes of 8, 16, and 32 bits
The AON domain contains circuitry that is always enabled, except when in shutdown mode (where the
digital supply is off). This circuitry includes the following:
•
The RTC can be used to wake the device from any state where it is active. The RTC contains three
compare registers and one capture register. With software support, the RTC can be used for clock and
calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be
compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used
instead of a crystal.
•
The battery monitor and temperature sensor are accessible by software and provide a battery status
indication as well as a coarse temperature measure.
6.10 Voltage Supply Domains
The CC1310 device can interface to two or three different voltage domains depending on the package
type. On-chip level converters ensure correct operation as long as the signal voltage on each input/output
pin is set with respect to the corresponding supply pin (VDDS, VDDS2, or VDDS3). Table 6-3 lists the pin-
to-VDDS mapping.
Table 6-3. Pin Function to VDDS Mapping Table
Package
VQFN 7 × 7 (RGZ)
VQFN 5 × 5 (RHB)
VQFN 4 × 4 (RSM)
DIO 23–30
Reset_N
DIO 7–14
Reset_N
DIO 5–9
Reset_N
VDDS(1)
VDDS2
DIO 0–6
JTAG_TCKC
JTAG_TMSC
DIO 0–4
JTAG_TCKC
JTAG_TMSC
DIO 1–11
DIO 12–22
JTAG_TCKC
JTAG_TMSC
VDDS3
NA
NA
(1) The VDDS_DCDC pin must always be connected to the same voltage as the VDDS pin.
6.11 System Architecture
Depending on the product configuration, the CC1310 device can function as a wireless network processor
(WNP – a device running the wireless protocol stack, with the application running on a separate host
MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the ARM CM3
core inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second
case, the application must be written according to the application framework supplied with the wireless
protocol stack.
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7 Application, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Application Information
Few external components are required for the operation of the CC1310 device. Figure 7-1 shows a typical
application circuit.
The board layout greatly influences the RF performance of the CC1310 device.
On the Texas Instruments CC1310EM-7XD-7793 reference design, the optimal differential impedance
seen from the RF pins into the balun and filter and antenna is 44 + j15.
Red = Not Necessary if Internal Bias is Used
Antenna
(50 ꢀ)
Pin 3 (RXTX)
Optional Inductor.
Only Needed for
DCDC Operation
Pin 2 (RF N)
Pin 1 (RF P)
DC Block
Differential Operation
Antenna
(50 ꢀ)
Red = Not Necessary if Internal Bias is Used
CC13xx
Pin 3 (RXTX)
Pin 3 (RXTX)
(GND exposed die
DC Block
Pin 1 (RF P)
Pin 2 (RF N)
Pin 1 (RF P)
attached pad)
Single-Ended Operation
Red = Not Necessary if Internal Bias is Used
Pin 3 (RXTX)
Antenna
(50 ꢀ)
24-MHz Crystal
(Load Capacitors
on Chip)
DC Block
Pin 2 (RF N)
Single-Ended
Operation With
Antenna Diversity
Antenna
(50 ꢀ)
DC Block
Pin 1 (RF P)
Figure 7-1 does not show decoupling capacitors for power pins. For a complete reference design, see the product
folder on www.ti.com.
Figure 7-1. CC1310 Application Circuits
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7.2 TI Design or Reference Design
The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
Humidity and Temperature Sensor Node for Sub-1 GHz Star Networks Enabling 10+ Year Coin Cell
Battery LifeSPACER
This reference design uses TI's nano-power system timer, boost converter, SimpleLink™
ultra-low-power Sub-1GHzwireless MCU platform, and humidity-sensing technologies to
demonstrate an ultra-low-power method to duty-cycle sensor end nodes leading to extremely
long battery life. The TI Design includes techniques for system design, detailed test results,
and information to get the design operating running quickly.
SimpleLink™ Sub-1 GHz Sensor to Cloud Gateway Reference Design for TI-RTOS SystemsSPACE
R
This reference design demonstrates how to connect sensors to the cloud over a long-range
Sub-1 GHz wireless network, suitable for industrial settings such as building control and
asset tracking. The solution is based on a TI-RTOS gateway. This design provides a
complete end-to-end solution for creating a Sub-1 GHz sensor network with an Internet of
Things (IoT) gateway solution and cloud connectivity. The gateway solution is based on the
low-power, SimpleLink™ Wi-Fi® CC3220 wireless microcontroller (MCU), which hosts the
gateway application and the SimpleLink Sub-1 GHz CC1310/CC1312R or the multi-band
CC1350/ CC1352R wireless MCU as the MAC Co-Processor. The reference design also
includes sensor node example applications running on the SimpleLink Sub-1 GHz
CC1312R/CC1310 and multi-band CC1352R/CC1350 wireless MCUs.
Low-Power Wireless M-Bus Communications Module Reference DesignSPACER
This reference design explains how to use the TI wireless M-Bus stack for CC1310 and
CC1350 wireless MCUs and integrate it into a smart meter or data-collector product. This
software stack is compatible with the Open Metering System (OMS) v3.0.1 specification.
This design offers ready-to-use binary images for any of the wireless M-Bus S-, T-, or C-
modes at 868 MHz with unidirectional (meter) or bidirectional configurations (both meter and
data collector).
Low-Power Water Flow Measurement With Inductive Sensing Reference DesignSPACER
This reference design demonstrates a highly-integrated solution for this application using an
inductive sensing technique enabled by the CC1310/CC1350 SimpleLink™ Wireless MCU
and FemtoFET™ MOSFET. This reference design also provides the platform for integration
of wireless communications such as wireless M-Bus, Sigfox™, or a proprietary protocol.
Heat Cost Allocator with wM-Bus at 868 MHz Reference DesignSPACER
This reference design implements a heat cost allocator system following the EN834 standard
with the ‘two-sensor measurement method’. The solution achieves better than 0.5 degrees
Celsius accuracy across a range of +20 to +85°C. Two analog temperature sensors are
available as matched pairs to eliminate the need for calibration during manufacturing and
lowering OEM system cost. The CC1310 wireless MCU provides a single-chip solution for
heat measurement (control of the two temperature sensors) and RF communications
(example code using 868 MHz wM-Bus S, T and C-modes “Meter” device).
Sub-1 GHz Sensor to Cloud Industrial IoT Gateway Reference Design for Linux Systems SPACER
This reference design demonstrates how to connect sensors to the cloud over a long-range
Sub-1 GHz wireless network, suitable for industrial settings such as building control and
asset tracking. This design provides a complete end-to-end solution for creating a Sub-1
GHz sensor network with an Internet of Things (IoT) gateway solution and cloud connectivity.
The gateway solution is based on the low-power, SimpleLink™ Wi-Fi® CC3220 wireless
microcontroller (MCU), which hosts the gateway application and the SimpleLink Sub-1 GHz
CC1312R/CC1310 or the multi-band CC1352R/CC1350 wireless MCU as the MAC Co-
Processor.
8 器件和文档支持
TI 提供大量的开发工具。下面介绍用于评估器件性能、生成代码以及开发解决方案的工具和软件。
8.1 器件命名规则
46
器件和文档支持
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: CC1310
CC1310
www.ti.com.cn
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
为了标明产品开发周期的各个产品阶段，TI 为所有部件号和/或日期代码添加了前缀。每个器件都具有以下
三个前缀/标识中的一个：X、P 或无（无前缀）（例如 CC1310 正在批量生产，因此未分配前缀/标识）。
器件开发进化流程：
X
试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。
原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。
完全合格的芯片模型的生产版本。
P
无
生产器件已进行完全特性化，并且器件的质量和可靠性已经完全论证。TI 的标准保修证书适用。
预测显示原型器件（X 或者 P）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定义，
德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的产品器件将被使用。
TI 器件的命名规则还包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如 RGZ）。
要获得 CC1310 器件（采用RSM (4mm × 4mm)、RHB (5mm × 5mm) 或 RGZ (7mm × 7mm) 封装类型）的
订购部件号，请参见本文档的封装选项附录（TI 网站 www.ti.com），或者联系您的 TI 销售代表。
(R/T)
CC1310 Fxxx
XXX
PREFIX
X = Experimental device
Blank = Qualified device
R = Large Reel
T = Small Reel
DEVICE
SimpleLink™ Ultra-Low-Power
Dual-Band Wireless MCU
PACKAGE
FLASH SIZE
32KB
64KB
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RHB = 32-pin VQFN
RSM = 32-pin VQFN
128KB
图 8-1. 器件命名规则
版权 © 2015–2018, Texas Instruments Incorporated
器件和文档支持
47
提交文档反馈意见
产品主页链接: CC1310
CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
www.ti.com.cn
8.2 工具和软件
开发套件:
SimpleLink™ 低于 1GHz CC1310 无线 MCU LaunchPad™ 开发套件 空白
SimpleLink™ 低于 1GHz CC1310 无线微控制器 (MCU) LaunchPad™ 开发套件是具有低于
1GHz 无线电模块（因此可提供远距离连接）的首个 LaunchPad 套件，在单芯片上整合了 32
位 Arm® Cortex®-M3 处理器。
CC1310 器件是一款面向低功耗远距离 无线应用的无线 MCU。CC1310 无线 MCU 包含一个
以 48MHz 频率运行的 32 位 Arm Cortex-M3 处理器作为主处理器，还包含丰富的外设功能
集，其中包括一个独特的超低功耗传感器控制器。该传感器控制器非常适合连接外部传感器，
还适合用于在系统其余部分处于睡眠模式的情况下自主收集模拟和数字数据。
软件：
SimpleLink™ CC13x0 SDK 空白
SimpleLink™ 低于 1GHz CC13x0 软件开发套件 (SDK) 为低于 1GHz CC1310 和双频带
CC1350 无线 MCU 提供全面的低于 1GHz 软件包，并且包括以下内容：
•
TI 15.4-Stack - 面向低于 1GHz ISM 频带（433MHz、868MHz 和 915MHz）的基于 IEEE
802.15.4e/g 的星形拓扑网络解决方案。
•
•
支持专有解决方案 - 基于射频驱动器和 EasyLink 抽象层的低于 1GHz 的专有射频示例。
低功耗蓝牙 – 支持所有蓝牙核心规范 4.2 特性 的堆栈以及为使用双频带 CC1350 无线
MCU 的客户提供支持的 BLE 微堆栈。
SimpleLink CC13x0 SDK 是 TI 的 SimpleLink MCU 平台的一部分，可提供统一的开发环境，
为客户开发有线和无线应用提供灵活的硬件、软件和 工具选项。有关 SimpleLink MCU 平台的
更多信息，请访问 www.ti.com.cn/simplelink。
软件工具：
SmartRF™ Studio 7 空白
SmartRF™ Studio 是一款 PC 应用程序，可帮助无线电系统的设计人员在设计过程的早期阶
段轻松评估 RF-IC。
•
•
•
•
测试无线数据包收发功能，连续波收发功能
将相关数据写入支持的评估板或调试器，评估定制板上的 RF 性能
可以不搭配任何硬件使用，但此时只能生成、编辑并导出无线配置设置
可与德州仪器 (TI) CC1310 系列 RF-IC 的多款开发套件搭配使用
Sensor Controller Studio 空白
Sensor Controller Studio
CC1310 中的一款专用功率优化型 CPU，可独立于系统 CPU 状态自主执行简单的后台任务。
为
CC1310 传感器控制器提供开发环境。此传感器控制器是
•
•
•
允许使用 C 语言这类编程语言实现传感器控制器任务算法
输出传感器控制器接口驱动程序，其中整合了生成的传感器控制器机械代码和相关定义
通过使用集成传感器控制器任务测试和调试功能实现快速开发这有助于实现有效的传感器
数据和算法验证可视化。
48
器件和文档支持
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提交文档反馈意见
产品主页链接: CC1310
CC1310
www.ti.com.cn
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
IDE 和编译器：
Code Composer Studio™ IDE 空白
•
•
•
•
带有项目管理工具和编辑器的集成开发环境 (IDE)
Code Composer Studio (CCS) 6.1 及更高版本内置支持 CC1310 系列器件的功能。
优先支持的 XDS 调试器：XDS100v3、XDS110 和 XDS200
与 TI-RTOS 高度集成，支持 TI-RTOS 对象视图
Code Composer Studio™ Cloud IDE 空白
Code Composer Studio™ (CCS) Cloud 是基于 Web 的 IDE，可用于创建、编辑和构建 CCS
及 Energia 项目。成功构建项目后，您可以在互联 LaunchPad™ 开发套件上下载并运行该项
目。CCS Cloud 现在支持 基本调试， 包括设置断点和查看变量值等功能。
CCS UniFlash 空白
CCS UniFlash 是一个独立的工具，可用于在 TI MCU 上对片上闪存进行编程。UniFlash 具有
GUI、命令行和脚本接口。CCS UniFlash 免费提供。
用于 Arm® 的 IAR Embedded Workbench
•
带有项目管理工具和编辑器的集成开发环境
•
•
•
•
IAR EWARM 7.30.3 及更高版本内置支持 CC1310 系列器件的功能。
支持大量调试器，包括支持 XDS100v3、XDS200、IAR I-jet®和 SEGGER J-Link™
带有项目管理工具和编辑器的集成开发环境
适用于 TI-RTOS 的 RTOS 插件
有关 CC1310 平台开发支持工具的完整列表，请访问德州仪器 (TI) 网站 www.ti.com.cn。有关定价和购买信
息，请联系最近的 TI 销售办事处或授权分销商。
版权 © 2015–2018, Texas Instruments Incorporated
器件和文档支持
49
提交文档反馈意见
产品主页链接: CC1310
CC1310
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
www.ti.com.cn
8.3 文档支持
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹 (CC1310)。单击右上角的“通知我”进行注册，
即可每周接收产品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
下面列出了介绍 CC2650CC1310CC2640R2F 器件、相关外设和其他技术材料的最新文档。
勘误表
《CC1310 SimpleLink™ 超低功耗低于 1GHz 无线 MCU 器件修订版 B、A器件勘误表》
技术参考手册
《CC13xx、CC26xx SimpleLink™ 无线 MCU 技术参考手册》
参考指南
《CC26xx/CC13xx 电源管理软件开发者参考指南》
8.4 德州仪器 (TI) 低功耗射频网站
TI 的低功耗射频网站提供所有最新产品、应用和设计笔记、FAQ 部分、新闻资讯以及活动更新。请访问
www.ti.com/longrange。
8.5 其他信息
德州仪器 (TI) 为汽车、工业和消费类应用中所使用的专有应用和标准无线 应用 提供各种经济实用的低功耗
射频 解决方案。其中包括适用于 1GHz 以下频段和 2.4GHz 频段的射频收发器、射频发送器、射频前端和
片上系统以及各种软件解决方案。
此外，德州仪器 (TI) 还提供广泛的相关支持，例如开发工具、技术文档、参考设计、应用专业技术、客户支
持、第三方服务以及大学计划。
低功耗射频 E2E 在线社区设有技术支持论坛并提供视频和博客，您有机会在此与全球同领域工程师交流互
动。
凭借丰富的供选产品解决方案、可实现的最终应用以及广泛的技术支持，德州仪器 (TI) 能够为您提供最全面
的低功耗射频产品组合。
8.6 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com
中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI 嵌入式处理器维基网页 德州仪器 (TI) 嵌入式处理器维基网站。此网站的建立是为了帮助开发人员从德州
仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体知识的创新
和增长。
50
器件和文档支持
版权 © 2015–2018, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: CC1310
CC1310
www.ti.com.cn
ZHCSEB0D –SEPTEMBER 2015–REVISED JULY 2018
8.7 商标
SimpleLink, SmartRF, Code Composer Studio, 德州仪器 (TI), FemtoFET, E2E are trademarks of Texas
Instruments.
ARM7 is a trademark of ARM Limited (or its subsidiaries).
Arm, Cortex, Thumb are registered trademarks of Arm Limited (or its subsidiaries).
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
ULPBench is a trademark of Embedded Microprocessor Benchmark Consortium.
CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium.
IAR Embedded Workbench, I-jet are registered trademarks of IAR Systems AB.
IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated.
IEEE is a registered trademark of Institute of Electrical and Electronics Engineers, Incorporated.
J-Link is a trademark of SEGGER Microcontroller GmbH.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
Wi-SUN is a trademark of Wi-SUN Alliance, Inc.
Zigbee is a registered trademark of Zigbee Alliance.
All other trademarks are the property of their respective owners.
8.8 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.9 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
8.10 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
9 机械、封装和可订购信息
9.1 封装信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015–2018, Texas Instruments Incorporated
机械、封装和可订购信息
51
提交文档反馈意见
产品主页链接: CC1310
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RGZ
RGZ
RHB
RHB
RSM
RSM
RGZ
RGZ
RHB
RHB
RSM
RSM
RGZ
RGZ
RHB
RHB
RSM
Qty
(1)
(2)
(3)
(4/5)
(6)
CC1310F128RGZR
CC1310F128RGZT
CC1310F128RHBR
CC1310F128RHBT
CC1310F128RSMR
CC1310F128RSMT
CC1310F32RGZR
CC1310F32RGZT
CC1310F32RHBR
CC1310F32RHBT
CC1310F32RSMR
CC1310F32RSMT
CC1310F64RGZR
CC1310F64RGZT
CC1310F64RHBR
CC1310F64RHBT
CC1310F64RSMR
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
48
48
32
32
32
32
48
48
32
32
32
32
48
48
32
32
32
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CC1310
F128
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CC1310
F128
CC1310
F128
CC1310
F128
CC1310
F128
CC1310
F128
CC1310
F32
CC1310
F32
CC1310
F32
CC1310
F32
CC1310
F32
CC1310
F32
CC1310
F64
CC1310
F64
CC1310
F64
CC1310
F64
3000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
Addendum-Page 1
CC1310
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F64
CC1310F64RSMT
ACTIVE
VQFN
RSM
32
250
RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 85
CC1310
F64
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC1310F128RGZR
CC1310F128RGZT
CC1310F128RHBR
CC1310F128RHBR
CC1310F128RHBT
CC1310F128RHBT
CC1310F128RSMR
CC1310F128RSMT
CC1310F32RHBR
CC1310F32RHBT
CC1310F32RSMT
CC1310F64RHBR
CC1310F64RHBT
CC1310F64RSMR
CC1310F64RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RHB
RHB
RHB
RHB
RSM
RSM
RHB
RHB
RSM
RHB
RHB
RSM
RSM
48
48
32
32
32
32
32
32
32
32
32
32
32
32
32
2500
250
330.0
180.0
330.0
330.0
180.0
180.0
330.0
180.0
330.0
180.0
180.0
330.0
180.0
330.0
180.0
16.4
16.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
3000
250
5.3
5.3
1.1
5.3
5.3
1.1
5.3
5.3
1.1
250
5.3
5.3
1.1
3000
250
4.25
4.25
5.3
4.25
4.25
5.3
1.15
1.15
1.1
3000
250
5.3
5.3
1.1
250
4.25
5.3
4.25
5.3
1.15
1.1
3000
250
5.3
5.3
1.1
3000
250
4.25
4.25
4.25
4.25
1.15
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC1310F128RGZR
CC1310F128RGZT
CC1310F128RHBR
CC1310F128RHBR
CC1310F128RHBT
CC1310F128RHBT
CC1310F128RSMR
CC1310F128RSMT
CC1310F32RHBR
CC1310F32RHBT
CC1310F32RSMT
CC1310F64RHBR
CC1310F64RHBT
CC1310F64RSMR
CC1310F64RSMT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RHB
RHB
RHB
RHB
RSM
RSM
RHB
RHB
RSM
RHB
RHB
RSM
RSM
48
48
32
32
32
32
32
32
32
32
32
32
32
32
32
2500
250
367.0
210.0
336.6
367.0
210.0
210.0
367.0
210.0
367.0
210.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
336.6
367.0
185.0
185.0
367.0
185.0
367.0
185.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
31.8
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
250
3000
250
3000
250
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
CC1310F128RHBR
CC1310F128RHBT
CC1310F128RSMR
CC1310F128RSMR
CC1310F128RSMT
CC1310F128RSMT
CC1310F32RGZR
CC1310F32RGZR
CC1310F32RGZT
CC1310F32RGZT
CC1310F32RHBR
CC1310F32RHBR
CC1310F32RHBT
CC1310F32RHBT
CC1310F32RSMT
CC1310F64RGZR
CC1310F64RGZT
RHB
RHB
RSM
RSM
RSM
RSM
RGZ
RGZ
RGZ
RGZ
RHB
RHB
RHB
RHB
RSM
RGZ
RGZ
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
32
32
32
32
32
32
48
48
48
48
32
32
32
32
32
48
48
3000
250
14 x 35
14 x 35
14 x 35
14 x 35
14 x 35
14 x 35
26 x 10
26 x 10
26 x 10
26 x 10
14 x 35
14 x 35
14 x 35
14 x 35
14 x 35
26 x 10
26 x 10
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
8.8
8.8
8.8
8.8
8.8
8.8
7.9
7.9
7.9
7.9
7.9
7.9
10
8.15
8.15
3000
3000
250
8.15
8.15
8.15
250
8.15
2500
2500
250
315 135.9 7620 11.8
315 135.9 7620 11.8
315 135.9 7620 11.8
315 135.9 7620 11.8
10.35
10.35
10.35
10.35
8.15
10
10
250
10
3000
3000
250
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
8.8
8.8
8.8
8.8
8.8
7.9
7.9
7.9
7.9
7.9
10
8.15
8.15
250
8.15
250
8.15
2500
250
315 135.9 7620 11.8
315 135.9 7620 11.8
10.35
10.35
10
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Mar-2023
Device
Package Package Pins SPQ Unit array
Max
L (mm)
W
K0
P1
CL
CW
Name
Type
matrix temperature
(°C)
(mm) (µm) (mm) (mm) (mm)
CC1310F64RHBR
CC1310F64RHBT
CC1310F64RSMR
CC1310F64RSMR
CC1310F64RSMT
RHB
RHB
RSM
RSM
RSM
VQFN
VQFN
VQFN
VQFN
VQFN
32
32
32
32
32
3000
250
14 x 35
14 x 35
14 x 35
14 x 35
14 x 35
150
150
150
150
150
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
315 135.9 7620
8.8
8.8
8.8
8.8
8.8
7.9
7.9
7.9
7.9
7.9
8.15
8.15
8.15
8.15
8.15
3000
3000
250
Pack Materials-Page 4
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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