CC2550_技术文档

CC2550

Single Chip Low Cost Low Power RF Transmitter

Applications

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer Electronics

• Wireless game controllers

• Wireless audio

Product Description

The main operating parameters and the 64-

byte transmit FIFO of CC2550 can be controlled

via an SPI interface. In a typical system, the

CC2550 will be used together with a micro-

controller and a few passive components.

CC2550 is part of Chipcon’s 4^thgeneration

technology platform based on 0.18 µm CMOS

technology.

The CC2550 is a low cost true single chip 2.4

GHz transmitter designed for very low power

wireless applications. The circuit is intended

for the ISM (Industrial, Scientific and Medical)

and SRD (Short Range Device) frequency

band at 2400-2483.5 MHz.

The RF transmitter is integrated with a highly

configurable baseband modulator which has a

configurable data rate up to 500 kbps.

Performance can be increased by enabling a

Forward Error Correction option, which is

integrated in the modulator.

The CC2550 provides extensive hardware

support for packet handling, data buffering and

burst transmissions.

This data sheet contains preliminary data, and supplementary data will be published at a later

date. Chipcon reserves the right to make changes at any time without notice in order to improve

design and supply the best possible product. The product is not fully qualified at this point.

Key Features

FCC CFR47 Part 15 (US), and ARIB STD-

T66 (Japan)

•

Small size (QLP 4x4 mm package, 16

pins)

•

Many powerful digital features allow a

high-performance RF system to be made

using an inexpensive microcontroller

Efficient SPI interface: All registers can be

programmed with one “burst” transfer

Integrated analog temperature sensor

Lead-free “green“ package

Flexible support for packet oriented

systems: On chip support for sync word

insertion, flexible packet length and

automatic CRC handling

•

True single chip 2.4 GHz RF transmitter

Frequency range: 2400-2483.5 MHz

Programmable data rate up to 500 kbps

Low current consumption

Programmable output power up to +1 dBm

Very few external components: Totally on-

chip frequency synthesizer, no external

filters needed

Programmable baseband modulator

Ideal for multi-channel operation

Configurable packet handling hardware

Suitable for frequency hopping systems

due to a fast settling frequency synthesizer

Optional Forward Error Correction with

interleaving

•

OOK supported

FSK, GFSK and MSK supported.

Optional automatic whitening of data

Support for asynchronous transparent

transmit mode for backwards compatibility

•

64-byte TX data FIFO

Suited for systems compliant with EN 300

328 and EN 300 440 class 2 (Europe),

with

existing

radio

communication

protocols

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 1 of 54

CC2550

Table of Contents

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES ..........................................................................................................................................1

TABLE OF CONTENTS ..............................................................................................................................2

ABBREVIATIONS........................................................................................................................................4

1

2

3

ABSOLUTE MAXIMUM RATINGS..............................................................................................4

OPERATING CONDITIONS ..........................................................................................................5

GENERAL CHARACTERISTICS..................................................................................................5

ELECTRICAL SPECIFICATIONS................................................................................................5

4

4.1

4.2

4.3

4.4

4.5

4.6

4.7

C

URRENT

RF TRANSMIT

RYSTAL

REQUENCY

NALOG EMPERATURE S

C

ONSUMPTION .....................................................................................................................5

ECTION ........................................................................................................................6

SCILLATOR.........................................................................................................................6

HARACTERISTICS.....................................................................................7

ENSOR .........................................................................................................7

DC CHARACTERISTICS .........................................................................................................................8

ESET.................................................................................................................................8

S

C

F

A

O

SYNTHESIZER C

T

P

OWER ON R

5

6

7

8

9

PIN CONFIGURATION...................................................................................................................8

CIRCUIT DESCRIPTION ...............................................................................................................9

APPLICATION CIRCUIT.............................................................................................................10

CONFIGURATION OVERVIEW.................................................................................................12

CONFIGURATION SOFTWARE.................................................................................................13

4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...........................................13

10

10.1

10.2

C

HIP

S

TATUS

B

YTE ............................................................................................................................15

REGISTERS

A

CCESS ............................................................................................................................15

10.3 SPI READ ...........................................................................................................................................16

10.4 TROBES ..........................................................................................................................16

COMMAND S

10.5 FIFO ACCESS .....................................................................................................................................16

10.6 PATABLE ACCESS............................................................................................................................16

11

11.1

11.2

MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ...................................17

NTERFACE..............................................................................................................17

INS ..............................................................................................17

C

G

ONFIGURATION

I

ENERAL ONTROL AND STATUS P

C

12

DATA RATE PROGRAMMING...................................................................................................18

PACKET HANDLING HARDWARE SUPPORT .......................................................................18

13

13.1

13.2

13.3

D

ATA WHITENING...............................................................................................................................18

ACKET FORMAT ................................................................................................................................19

ODE............................................................................................21

P

ACKET

HANDLING IN TRANSMIT M

14

MODULATION FORMATS..........................................................................................................21

EYING................................................................................................................21

EYING....................................................................................................................21

ODULATION .................................................................................................................21

FORWARD ERROR CORRECTION WITH INTERLEAVING ..............................................22

ORRECTION (FEC)...............................................................................................22

NTERLEAVING ...................................................................................................................................22

RADIO CONTROL.........................................................................................................................23

14.1

14.2

14.3

F

M

A

REQUENCY

INIMUM HIFT

MPLITUDE

SHIFT K

S

K

M

15

15.1

15.2

FORWARD ERROR C

I

16

16.1

16.2

16.3

16.4

16.5

P

C

V

A

T

OWER-O

RYSTAL

OLTAGE

CTIVE

N

S

TART-U

P

S

EQUENCE......................................................................................................23

ONTROL............................................................................................................................24

ONTROL.......................................................................................................24

ODE ....................................................................................................................................25

C

REGULATOR C

M

IMING ...............................................................................................................................................25

17

18

DATA FIFO .....................................................................................................................................25

FREQUENCY PROGRAMMING.................................................................................................26

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 2 of 54

CC2550

19

VCO ..................................................................................................................................................27

19.1 VCO AND PLL SELF-CALIBRATION ...................................................................................................27

20

21

VOLTAGE REGULATORS ..........................................................................................................27

OUTPUT POWER PROGRAMMING .........................................................................................28

CRYSTAL OSCILLATOR.............................................................................................................29

22

22.1

REFERENCE SIGNAL ...........................................................................................................................30

23

24

EXTERNAL RF MATCH ..............................................................................................................30

GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................30

ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................32

25

25.1

25.2

A

S

SYNCHRONOUS OPERATION..............................................................................................................32

YNCHRONOUS SERIAL OPERATION ....................................................................................................32

SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................32

26

26.1 SRD REGULATIONS............................................................................................................................32

26.2

26.3

26.4

26.5

26.6

26.7

26.8

26.9

F

W

D

C

REQUENCY

IDEBAND

ATA URST

ONTINUOUS

PECTRUM FFICIENT M

H

OPPING AND

M

ULTI-CHANNEL

S

YSTEMS.....................................................................32

PECTRUM ................................................................33

RANSMISSIONS............................................................................................................33

RANSMISSIONS ...........................................................................................................33

ODULATION..................................................................................................33

YSTEMS ..........................................................................................................................34

YSTEMS ..........................................................................................................34

OWER .............................................................................................................34

CONFIGURATION REGISTERS.................................................................................................34

ETAILS .................................................................................................38

TATUS REGISTER DETAILS.................................................................................................................46

PACKAGE DESCRIPTION (QLP 16)..........................................................................................49

ECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 16).....................................................................50

M

ODULATION NOT

U

SING PREAD S

S

B

T

S

L

E

OW

ATTERY

NCREASING

COST S

B

I

O

PERATED

S

O

UTPUT P

27

27.1

27.2

CONFIGURATION REGISTER D

S

28

28.1

28.2

28.3

28.4

28.5

R

P

S

T

C

ACKAGE THERMAL PROPERTIES ........................................................................................................50

OLDERING INFORMATION..................................................................................................................50

RAY SPECIFICATION..........................................................................................................................51

ARRIER TAPE AND REEL SPECIFICATION ...........................................................................................51

29

ORDERING INFORMATION.......................................................................................................51

GENERAL INFORMATION.........................................................................................................51

30

30.1

30.2

D

OCUMENT

H

ISTORY .........................................................................................................................51

EFINITIONS .........................................................................................................52

P

RODUCT TATUS D

S

31

32

ADDRESS INFORMATION..........................................................................................................53

TI WORLDWIDE TECHNICAL SUPPORT...............................................................................53

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 3 of 54

CC2550

Abbreviations

Abbreviations used in this data sheet are described below.

ACP

ADC

AGC

AMR

ARIB

ASK

BER

BT

Adjacent Channel Power

Analog to Digital Converter

Automatic Gain Control

MSK

NA

Minimum Shift Keying

Not Applicable

LO

Local Oscillator

Automatic Meter Reading

Association of Radio Industries and Businesses

Amplitude Shift Keying

OOK

PA

On Off Keying

Power Amplifier

Printed Circuit Board

Power Down

PCB

PD

Bit Error Rate

Bandwidth-Time product

Code of Federal Regulations

Cyclic Redundancy Check

Direct Current

PER

PLL

QPSK

QLP

RF

Packet Error Rate

Phase Locked Loop

CFR

CRC

DC

Quadrature Phase Shift Keying

Quad Leadless Package

Radio Frequency

ESR

FCC

FEC

FHSS

FIFO

FSK

GFSK

I/Q

Equivalent Series Resistance

Federal Communications Commission

Forward Error Correction

Frequency Hopping Spread Spectrum

First-In-First-Out

RX

Receive, Receive Mode

Surface Mount Device

Signal to Noise Ratio

Serial Peripheral Interface

Short Range Device

SMD

SNR

SPI

Frequency Shift Keying

SRD

TX

Gaussian shaped Frequency Shift Keying

In-Phase/Quadrature

Transmit, Transmit Mode

Voltage Controlled Oscillator

Wireless Local Area Networks

Crystal Oscillator

VCO

WLAN

XOSC

XTAL

ISM

Industrial, Scientific and Medical

Inductor-Capacitor

LC

LO

Local Oscillator

Crystal

MCU

Microcontroller Unit

1

Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress

exceeding one or more of the limiting values may cause permanent damage to the device.

Caution!

ESD

sensitive

device.

Precaution should be used when handling

the device in order to prevent permanent

damage.

Parameter

Min

Max

Units

Condition

Supply voltage

–0.3

3.6

V

All supply pins must have the same voltage

Voltage on any digital pin

–0.3

–50

VDD+0.3,

max 3.6

Voltage on the pins RF_P, RF_N

and DCOUPL

2.0

V

Storage temperature range

Solder reflow temperature

ESD

150

260

°C

V

According to IPC/JEDEC J-STD-020C

<500

According to JEDEC STD 22, method A114,

Human Body Model

Table 1: Absolute maximum ratings

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 4 of 54

CC2550

2

Operating Conditions

The operating conditions for CC2550 are listed Table 2 in below.

Parameter

Min

–40

1.8

Max

85

Unit

°C

Condition

Operating temperature

Operating supply voltage

3.6

V

All supply pins must have the same voltage

Table 2: Operating conditions

3

General Characteristics

Parameter

Min

Typ

Max

Unit

Condition/Note

Frequency range

2400

2483.5

MHz

There will be spurious signals at n/2·crystal oscillator

frequency (n is an integer number). RF frequencies at

n/2·crystal oscillator frequency should therefore not be

used (e.g. 2405, 2418, 2444, 2457, 2470 and 2483 MHz

when using a 26 MHz crystal). Please refer to the CC2550

Errata Note for more details.

Data rate

1.2

26

500

250

500

kbps

FSK

GFSK and OOK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (halves the data rate).

Table 3: General characteristics

4

Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter

Min Typ Max Unit Condition

Current consumption in power

down modes

200

160

nA

Voltage regulator to digital part off (SLEEP state)

Voltage regulator to digital part on, all other modules in power

down (XOFF state)

µA

Current consumption

1.4

7.3

mA Only voltage regulator to digital part and crystal oscillator running

(IDLE state)

mA Only the frequency synthesizer running (after going from IDLE

until reaching TX state, and frequency calibration states)

Current consumption, TX states

11.2

14.7

19.4

21.3

mA Transmit mode, –12 dBm output power (TX state)

mA Transmit mode, -6 dBm output power (TX state)

mA Transmit mode, 0 dBm output power (TX state)

mA Transmit mode, +1 dBm output power (TX state)

Table 4: Current consumption

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 5 of 54

CC2550

4.2 RF Transmit Section

Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2550EM reference

design.

Parameter

Min

Typ

Max

Unit

Condition/Note

Differential load

impedance

80 + j74

Differential impedance as seen from the RF-port (RF_P

and RF_N) towards the antenna. Follow the CC2550EM

reference design available from the TI and Chipcon

websites.

Ω

Output power, highest

setting

+1

dBm

Output power is programmable and is available across the

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM

reference RF matching network.

Output power, lowest

setting

–30

Output power is programmable and is available across the

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM

reference RF matching network.

Adjacent channel

power

–19

–39

dBc

1 MHz channel spacing (±1 MHz from carrier) and 500

kbps MSK.

Alternate channel

power

1 MHz channel spacing (±2 MHz from carrier) and 500

kbps MSK.

Spurious emissions

25 MHz – 1 GHz

–36

–54

dBm

47-74, 87.5-118, 174-

230, 470-862 MHz

1800-1900 MHz

At 2·RF and 3·RF

–47

–41

–30

dBm

Restricted band in Europe

Restricted bands in USA

Otherwise above 1

GHz

Table 5: RF transmit parameters

4.3 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter

Min

Typ

26

Max

Unit

MHz

ppm

Condition/Note

Crystal frequency

Tolerance

26

27

±40

This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and

channel spacing / bandwidth.

ESR

100

Ω

Start-up time

300

µs

Measured on CC2550 EM reference design.

Table 6: Crystal oscillator parameters

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 6 of 54

CC2550

4.4 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter

Min

Typ

Max

Unit

Condition/Note

Programmed

frequency resolution

397

F_XOSC

2¹⁶

/

427

Hz

26-27 MHz crystal.

Synthesizer frequency

tolerance

±40

ppm

Given by crystal used. Required accuracy (including

temperature and aging) depends on frequency band and

channel bandwidth / spacing.

RF carrier phase noise

–74

–77

–97

dBc/Hz @ 50 kHz offset from carrier

dBc/Hz @ 100 kHz offset from carrier

dBc/Hz @ 200 kHz offset from carrier

dBc/Hz @ 1 MHz offset from carrier

dBc/Hz @ 2 MHz offset from carrier

dBc/Hz @ 5 MHz offset from carrier

dBc/Hz @ 10 MHz offset from carrier

–106

–114

–117

88.4

PLL turn-on / hop time

PLL calibration time

Time from leaving the IDLE state until arriving in the

FSTXON or TX state, when not performing calibration.

Crystal oscillator running.

µs

18739

0.72

XOSC

cycles

Calibration can be initiated manually or automatically

before entering or after leaving RX/TX.

0.69

0.72

ms

Min/typ/max time is for 27/26/26 MHz crystal frequency.

Table 7: Frequency synthesizer parameters

4.5 Analog Temperature Sensor

The characteristics of the analog temperature sensor are listed in Table 8 below. Note that it is

necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE

state.

Parameter

Min

Typ

Max

Unit

Condition/Note

0.660

0.755

0.859

0.958

2.54

0

V

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient

mV/°C Fitted from –20°C to +80°C

°C

Error in calculated

temperature, calibrated

-2 ^*

2 ^*

From –20°C to +80°C when using 2.54 mV / °C,

after 1-point calibration at room temperature

^*The indicated minimum and maximum error with 1-

point calibration is based on simulated values for

typical process parameters

Current consumption

0.3

mA

increase when enabled

Table 8: Analog temperature sensor parameters

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 7 of 54

CC2550

4.6 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage

Logic "1" output voltage

Logic "0" input current

Logic "1" input current

Min

0

Max

0.7

Unit

V

Condition

VDD-0.7

0

VDD

0.5

V

For up to 4 mA output current

Input equals 0 V

VDD-0.3

NA

VDD

-50

V

nA

NA

50

Input equals VDD

Table 9: DC characteristics

4.7 Power On Reset

When the power supply complies with the requirements in Table 10 below, proper Power-On-

Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state

until transmitting an SRESstrobe over the SPI interface. See Section 16.1 on page 23 for further

details.

Parameter

Min Typ Max Unit Condition/Note

Power-up ramp-up time.

Power off time

5

ms

From 0 V until reaching 1.8 V

1

Minimum time between power off and power-on.

Table 10: Power-on reset requirements

5

Pin Configuration

16 15 14 13

SCLK 1

SO (GDO1) 2

DVDD 3

12 AVDD

11 RF_N

10 RF_P

DCOUPL 4

9

CSn

GND

Exposed die

attach pad

5

6

7

8

Figure 1: Pinout top view

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 8 of 54

CC2550

Pin # Pin name

Pin type

Description

1

2

SCLK

Digital Input

Digital Output

Serial configuration interface, clock input

Serial configuration interface, data output.

Optional general output pin when CSnis high

SO (GDO1)

3

4

DVDD

Power (Digital)

1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

voltage regulator

DCOUPL

1.6 - 2.0 V digital power supply output for decoupling.

NOTE: This pin is intended for use with the CC2550 only. It can not be

used to provide supply voltage to other devices.

5

6

7

8

XOSC_Q1

AVDD

Analog I/O

Power (Analog)

Analog I/O

Digital I/O

Crystal oscillator pin 1, or external clock input

1.8 - 3.6 V analog power supply connection

Crystal oscillator pin 2

XOSC_Q2

GDO0

Digital output pin for general use:

•

Test signals

FIFO status signals

Clock output, down-divided from XOSC

Serial input TX data

(ATEST)

Also used as analog test I/O for prototype/production testing

Serial configuration interface, chip select

Positive RF output signal from PA

9

CSn

Digital Input

RF Output

10

11

12

13

14

15

16

RF_P

RF_N

AVDD

RBIAS

DGUARD

SI

RF Output

Negative RF output signal from PA

Power (Analog)

Analog I/O

1.8 - 3.6 V analog power supply connection

External bias resistor for reference current

Power supply connection for digital noise isolation

Serial configuration interface, data input

Power (Digital)

Digital Input

Table 11: Pinout overview

6

Circuit Description

RADIO CONTROL

SCLK

RF_P

RF_N

FREQ

SYNTH

SO (GDO1)

PA

SI

CSn

GDO0 (ATEST)

BIAS

XOSC

RBIAS XOSC_Q1 XOSC_Q2

Figure 2: CC2550 simplified block diagram

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 9 of 54

CC2550

XOSC_Q2. The crystal oscillator generates the

reference frequency for the synthesizer, as

well as clocks for the digital part.

A simplified block diagram of CC2550 is shown

in Figure 2.

The CC2550 transmitter is based on direct

synthesis of the RF frequency.

A 4-wire SPI serial interface is used for

configuration and data buffer access.

The frequency synthesizer includes

completely on-chip LC VCO.

a

The digital baseband includes support for

channel configuration, packet handling and

data buffering.

A crystal is to be connected to XOSC_Q1 and

7

Application Circuit

Only a few external components are required

for using the CC2550. The recommended

application circuit is shown in Figure 3. The

external components are described in Table

12, and typical values are given in Table 13.

13. The balun and LC filter component values

and their placement are important to keep the

performance

optimized.

It

is

highly

recommended to follow the CC2550EM

reference design.

Crystal

Bias resistor

The crystal oscillator uses an external crystal

with two loading capacitors (C51 and C71).

See Section 22 on page 29 for details.

The bias resistor R141 is used to set an

accurate bias current.

Balun and RF matching

Power supply decoupling

C102, C112, L101 and L111 form a balun that

converts the differential RF signal on CC2550

to a single-ended RF signal. C101 and C111

are needed for DC blocking. Together with an

The power supply must be properly decoupled

close to the supply pins. Note that decoupling

capacitors are not shown in the application

circuit. The placement and the size of the

decoupling capacitors are very important to

achieve the optimum performance. The

CC2550EM reference design should be

followed closely.

appropriate

LC

network,

the

balun

components also transform the impedance to

match a 50 Ω antenna (or cable). Component

values for the RF balun and LC network are

easily found using the SmartRF^®Studio

software. Suggested values are listed in Table

Component

C41

Description

100 nF decoupling capacitor for on-chip voltage regulator to digital part

Crystal loading capacitors, see Section 22 on page 29 for details

RF balun DC blocking capacitors

C51/C71

C101/C111

C102/C112

C103/C104

L101/L111

L102

RF balun/matching capacitors

RF LC filter/matching capacitors

RF balun/matching inductors (inexpensive multi-layer type)

RF LC filter inductor (inexpensive multi-layer type)

Resistor for internal bias current reference

R141

XTAL

26-27 MHz crystal, see Section 22 on page 29 for details

Table 12: Overview of external components (excluding supply decoupling capacitors)

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 10 of 54

CC2550

1.8V-3.6V power supply

R141

SI

Antenna

(50 Ohm)

L111

SCLK

1 SCLK

AVDD 12

C111

C101

C112

SO

(GDO1)

2 SO (GDO1)

CC2550 ^{RF_N 11}

3 DVDD

RF_P 10

L102

C103

DIE ATTACH PAD:

L101

C102

DCOUPL

C104

4

CSn 9

C41

Alternative:

Folded dipole PCB

antenna (no external

components needed)

GDO0

(optional)

CSn

XTAL

C51

C71

Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)

Component

C41

Value

Manufacturer

100 nF±10%, 0402 X5R

27 pF±5%, 0402 NP0

100 pF±5%, 0402 NP0

1.0 pF±0.25pF, 0402 NP0

1.8 pF±0.25pF, 0402 NP0

Murata GRM15 series

Murata LQG15 series

Koa RK73 series

C51

C71

C101

C102

C103

C104

C111

C112

L101

1.5 pF±0.25pF, 0402 NP0

100 pF±5%, 0402 NP0

1.0 pF±0.25pF, 0402 NP0

1.2 nH±0.3nH, 0402 monolithic

56 kΩ±1%, 0402

L102

L111

R141

XTAL

26.0 MHz surface mount crystal

NDK, AT-41CD2

Table 13: Bill of Materials for the application circuit

In the CC2550EM reference design, LQG15

The Gerber files for the CC2550EM reference

design are available from the TI and Chipcon

websites.

series inductors from Murata have been used.

Measurements have been performed with

multi-layer inductors from other manufacturers

(e.g. Würth) and the measurement results

were the same as when using the Murata part.

PRELIMINARY Data Sheet (Rev.1.2)

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Page 11 of 54

CC2550

8

Configuration Overview

CC2550 can be configured to achieve optimum

performance for many different applications.

Configuration is done using the SPI interface.

The following key parameters can be

programmed:

•

Forward Error Correction with interleaving

Data Whitening

Details of each configuration register can be

found in Section 27, starting on page 34.

•

Power-down / power up mode

Crystal oscillator power-up / power – down

Transmit mode

RF channel selection

Data rate

Modulation format

RF output power

Data buffering with 64-byte transmit FIFO

Packet radio hardware support

Figure 4 shows a simplified state diagram that

explains the main CC2550 states, together with

typical usage and current consumption. For

detailed information on controlling the CC2550

state machine, and a complete state diagram,

see Section 16, starting on page 23.

Figure 4: Simplified state diagram, with typical usage and current consumption

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 12 of 54

CC2550

9

Configuration Software

CC2550 can be configured using the SmartRF^®

Studio software, available for download from

http://www.ti.com. The SmartRF^®Studio

software is highly recommended for obtaining

optimum register settings, and for evaluating

performance and functionality. A screenshot of

the SmartRF^®Studio user interface for CC2550

is shown in Figure 5.

Figure 5: SmartRF^®Studio user interface

10

4-wire Serial Configuration and Data Interface

and data transfer on the SPI interface is shown

in Figure 6 with reference to Table 14.

CC2550 is configured via a simple 4-wire SPI-

compatible interface (SI, SO, SCLK and CSn)

where CC2550 is the slave. This interface is

also used to read and write buffered data. All

address and data transfer on the SPI interface

is done most significant bit first.

When CSn goes low, the MCU must wait until

the CC2550 SO pin goes low before starting to

transfer the header byte. This indicates that

the voltage regulator has stabilized and the

crystal is running. Unless the chip is in the

SLEEP or XOFF states or an SRES command

strobe is issued, the SOpin will always go low

immediately after taking CSnlow.

All transactions on the SPI interface start with

a header byte containing a read/write bit, a

burst access bit and a 6-bit address.

During address and data transfer, the CSn pin

(Chip Select, active low) must be kept low. If

CSn goes high during the access, the transfer

will be cancelled. The timing for the address

Figure 7 gives a brief overview of different

register access types possible.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 13 of 54

CC2550

t_sp

t_ch

t_cl

t_sd

t_hd

t_ns

SCLK:

CSn:

Write to register:

X

A6

S6

A5

S5

A4

S4

A3

S3

A2

A1

S1

A0

S0

X

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D 0

W

X

0

W

SI

S7

S2

S7

S6

S5

S4

S3

S2

S1

S0

S7

Hi-Z

SO

Read from register:

X

A6

S6

A5

S5

A4

S4

A3

S3

A2

S2

A1

S1

A0

S0

X

1

SI

S7

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D 0

R

Hi-Z

R

SO

Figure 6: Configuration registers write and read operations

Parameter

Description

Min

Max

Units

f_SCLK

-

10

MHz

SCLKfrequency

100 ns delay inserted between address byte and data byte (single access), or between

address and data, and between each data byte (burst access).

9

MHz

SCLKfrequency, single access

No delay between address and data byte

6.5

SCLKfrequency, burst access

No delay between address and data byte, or between data bytes

t_sp,pd

t_sp

200

20

-

µs

CSnlow to positive edge on SCLK, in power-down mode

ns

CSnlow to positive edge on SCLK, in active mode

t_ch

t_cl

Clock high

50

-

ns

Clock low

t_rise

t_fall

t_sd

Clock rise time

Clock fall time

5

-

Single access

55

76

Setup data (negative SCLK edge) to

positive edge on SCLK

Burst access

-

(t_sdapplies between address and data bytes, and

between data bytes)

t_hd

t_ns

20

-

ns

Hold data after positive edge on SCLK

Negative edge on SCLKto CSnhigh

Table 14: SPI interface timing requirements

Figure 7: Register access types

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 14 of 54

CC2550

10.1 Chip Status Byte

should only be updated when the chip is in this

state. The TX state will be active when the

chip is transmitting.

When the header byte, data byte or command

strobe is sent on the SPI interface, the chip

status byte is sent by the CC2550 on the SO

pin. The status byte contains key status

signals, useful for the MCU. The first bit, s7, is

the CHIP_RDYnsignal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYn signal indicates that the crystal is

running and the regulated digital supply

voltage is stable.

The last four bits (3:0) in the status byte con-

tains FIFO_BYTES_AVAILABLE. This field

contains the number of bytes free for writing

into

the

TX

FIFO.

When

FIFO_BYTES_AVAILABLE=15, 15 or more

bytes are free.

Table 15 gives a status byte summary.

Bits 6, 5 and 4 comprise the STATEvalue. This

value reflects the state of the chip. The XOSC

and power to the digital core is on in the IDLE

state, but all other modules are in power down.

The frequency and channel configuration

Bits Name

Description

7

CHIP_RDYn

Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4

STATE[2:0]

Indicates the current main state machine mode

Value State

Description

000

001

Idle

IDLE state

(Also reported for some transitional states instead

of SETTLING or CALIBRATE)

Not used

(RX)

Not used, included for software compatibility

with CC2500 transceiver

010

011

100

101

110

TX

Transmit mode

FSTXON

CALIBRATE

SETTLING

Fast TX ready

Frequency synthesizer calibration is running

PLL is settling

Not used

Not used, included for software compatibility

(RXFIFO_OVERFLOW)

with CC2500 transceiver

111

TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO. If FIFO_BYTES_AVAILABLE=15, it

indicates that 15 or more bytes are free.

Table 15: Status byte summary

10.2 Registers Access

is sent on the SOpin each time a header byte

or data byte is transmitted on the SI pin.

When reading from registers, the status byte is

sent on the SOpin each time a header byte is

transmitted on the SIpin.

The configuration registers on the CC2550 are

located on SPI addresses from 0x00to 0x2F.

Table 24 on page 36 lists all configuration

registers. The detailed description of each

register is found in Section 27.1, starting on

page 38. All configuration registers can be

both written and read. The read/write bit

controls if the register should be written or

read. When writing to registers, the status byte

Registers with consecutive addresses can be

accessed in an efficient way by setting the

burst bit in the address header. The address

sets the start address in an internal address

counter. This counter is incremented by one

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 15 of 54

CC2550

each new byte (every 8 clock pulses). The

burst access is either a read or a write access

and must be terminated by setting CSnhigh.

For register addresses in the range 0x30-

0x3D, the “burst” bit is used to select between

status registers and command strobes (see

below). The status registers can only be read.

Burst read is not available for status registers,

so they must be read one at a time.

Figure 8: SRES command strobe

10.5 FIFO Access

10.3 SPI Read

The 64-byte TX FIFO is accessed through the

0x3F address. When the read/write bit is zero,

the TX FIFO is accessed. The TX FIFO is

write-only.

When reading register fields over the SPI

interface while the register fields are updated

by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite,

probability that a single read from the register

is being corrupt. As an example, the probability

of any single read from TXBYTES being

corrupt, assuming the maximum data rate is

used, is approximately 80 ppm. Refer to the

CC2550 Errata Note for more details.

The burst bit is used to determine if FIFO

access is single byte or a burst access. The

single byte access method expects address

with burst bit set to zero and one data byte.

After the data byte a new address is expected;

hence, CSncan remain low. The burst access

method expects one address byte and then

consecutive data bytes until terminating the

access by setting CSnhigh.

10.4 Command Strobes

The following header bytes access the FIFO:

Command strobes may be viewed as single

byte instructions to CC2550. By addressing a

command strobe register, internal sequences

will be started. These commands are used to

disable the crystal oscillator, enable transmit

mode, flush the TX FIFO etc. The 9 command

strobes are listed in Table 23 on page 35.

•

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte

(see Section 10.1) is output for each new data

byte on SO, as shown in Figure 6. This status

byte can be used to detect TX FIFO underflow

while writing data to the TX FIFO. Note that

the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX

FIFO is transmitted to the SI pin, the status

byte received concurrently on the SO pin will

indicate that one byte is free in the TX FIFO.

The command strobe registers are accessed

in the same way as for a register write

operation, but no data is transferred. That is,

only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30

through 0x3D) are written.

When writing command strobes, the status

byte is sent on the SOpin.

A command strobe may be followed by any

other SPI access without pulling CSn high.

After issuing an SRES command strobe the

next command strobe can be issued when the

SO pin goes low as shown in Figure 8. The

command strobes are executed immediately,

with the exception of the SPWDand the SXOFF

strobes that are executed when CSn goes

high.

The transmit FIFO may be flushed by issuing a

SFTX command strobe. The FIFO is cleared

when going to the SLEEP state.

10.6 PATABLE Access

The 0x3E address is used to access the

PATABLE, which is used for selecting PA

power control settings. The SPI expects up to

eight data bytes after receiving the address.

By programming the PATABLE, controlled PA

power ramp-up and ramp-down can be

achieved. See Section 21 on page 28 for

output power programming details.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 16 of 54

CC2550

The PATABLE is an 8-byte table that defines

the PA control settings to use for each of the

eight PA power values (selected by the 3-bit

value FREND0.PA_POWER). The table is

written and read from the lowest setting (0) to

the highest (7), one byte at a time. An index

counter is used to control the access to the

table. This counter is incremented each time a

byte is read or written to the table, and set to

the lowest index when CSn is high. When the

highest value is reached the counter restarts at

0.

If one byte is written to the PATABLE and this

value is to be read out then CSn must be set

high before the read access in order to set the

index counter back to zero.

Note that the content of the PATABLE is lost

when entering the SLEEP state.

The access to the PATABLE is either single

byte or burst access depending on the burst

bit. When using burst access the index counter

will count up; when reaching 7 the counter will

restart at 0. The read/write bit controls whether

the access is a write access (R/W=0) or a read

access (R/W=1).

11

Microcontroller Interface and Pin Configuration

pin is the SO pin in the SPI interface. The

default setting for GDO1/SO is 3-state output.

By selecting any other of the programming

options the GDO1/SO pin will become a

generic pin. When CSn is low, the pin will

always function as a normal SOpin.

In a typical system, CC2550 will interface to a

microcontroller. This microcontroller must be

able to:

• Program CC2550 into different modes

• Write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO,

SCLKand CSn)

In the synchronous and asynchronous serial

modes, the GDO0 pin is used as a serial TX

data input pin while in transmit mode.

The GDO0pin can also be used for an on-chip

analog temperature sensor. By measuring the

voltage on the GDO0pin with an external ADC,

11.1 Configuration Interface

The microcontroller uses four I/O pins for the

SPI configuration interface (SI, SO, SCLK and

CSn). The SPI is described in 13 on page 13.

the

temperature

can

be

calculated.

Specifications for the temperature sensor are

found in Section 4.5 on page 7.

With default PTEST register setting (0x7F) the

temperature sensor output is only available

when the frequency synthesizer is enabled

(e.g. the MANCAL, FSTXON and TX states).

It is necessary to write 0xBF to the PTEST

register to use the analog temperature sensor

in the IDLE state. Before leaving the IDLE

state, the PTESTregister should be restored to

its default value (0x7F).

11.2 General Control and Status Pins

The CC2550 has one dedicated configurable

pin and one shared pin that can output internal

status information useful for control software.

These pins can be used to generate interrupts

on the MCU. See Section 24 page 30 for more

details of the signals that can be programmed.

The dedicated pin is called GDO0. The shared

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 17 of 54

CC2550

12

Data Rate Programming

The data rate used when transmitting is

programmed by the MDMCFG3.DRATE_M and

If DRATE_M is rounded to the nearest integer

and becomes 256, increment DRATE_E and

use DRATE_M=0.

the

MDMCFG4.DRATE_E

configuration

registers. The data rate is given by the formula

below. As the formula shows, the programmed

data rate depends on the crystal frequency.

The data rate can programmed from 1.2 kbps

to 500 kbps with a minimum step size of:

Data rate

start

[kbps]

Typical

data rate

[kbps]

Data rate

stop [kbps]

Data rate

step size

[kbps]

(

256 + DRATE _ M

)

⋅ 2^{DRATE _ E}

R_DATA

=

⋅ f_XOSC

2²⁸

0.8

3.17

6.35

12.7

25.4

50.8

101.6

203.1

406.3

1.2/2.4

4.8

3.17

6.35

12.7

25.4

50.8

101.6

203.1

406.3

500

0.0062

0.0124

0.0248

0.0496

0.0992

0.1984

0.3967

0.7935

1.5869

The following approach can be used to find

suitable values for a given data rate:

9.6

19.6

38.4

76.8

153.6

250

R_DATA⋅ 2²⁰

⎢

⎥

⎛

⎜

⎝

⎞

⎟

⎠

DRATE _ E = log

⎢

2

f_XOSC

⎢

⎣

⎥

⎦

R_DATA⋅ 2²⁸

f_XOSC⋅ 2^{DRATE _ E}

DRATE _ M =

− 256

500

Table 16: Data rate step size

13

Packet Handling Hardware Support

13.1 Data whitening

The CC2550 has built-in hardware support for

packet oriented radio protocols.

From a radio perspective, the ideal over the air

data are random and DC free. This results in

the smoothest power distribution over the

occupied bandwidth. This also gives the

regulation loops in the receiver uniform

operation conditions (no data dependencies).

In transmit mode, the packet handler will add

the following elements to the packet stored in

the TX FIFO:

•

A programmable number of preamble

bytes.

A two byte synchronization (sync) word.

Can be duplicated to give a 4-byte sync

word.

Real world data often contain long sequences

of zeros and ones. Performance can then be

improved by whitening the data before

transmitting, and de-whitening in the receiver.

With CC2550, in combination with a CC2500 at

the receiver end, this can be done

•

Optionally whiten the data with a PN9

sequence.

Optionally Interleave and Forward Error

Code the data.

Optionally compute and add a CRC

checksum over the data field.

automatically

by

setting

PKTCTRL0

.WHITE_DATA=1. All data, except the

preamble and the sync word, are then XOR-ed

with a 9-bit pseudo-random (PN9) sequence

before being transmitted as shown in Figure 9.

At the receiver end, the data are XOR-ed with

the same pseudo-random sequence. This way,

the whitening is reversed, and the original data

appear in the receiver.

In a system where CC2550 is used as the

transmitter and CC2500 as the receiver the

recommended setting is 4-byte preamble and

4-byte sync word except for 500 kbps data rate

where the recommended preamble length is 8

bytes.

Data whitening can only be used when

PKTCTRL0.CC2400_EN= 0 (default).

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 18 of 54

CC2550

Figure 9: Data whitening in TX mode

13.2 Packet format

•

Length byte or constant programmable

packet length

Optional Address byte

Payload

The format of the data packet can be

configured and consists of the following items

(see Figure 10):

•

Optional 2 byte CRC

•

Preamble

Synchronization word

Optional data whitening

Optionally FEC encoded/decoded

Optional CRC-16 calculation

Legend:

Inserted automatically in TX,

processed and removed in RX.

Optional user-provided fields processed in TX,

processed but not removed in RX.

Preamble bits

(1010...1010)

Data field

8 x n bits

Unprocessed user data (apart from FEC

and/or whitening)

8

8 x n bits

16/32 bits

16 bits

bits bits

Figure 10: Packet format

The preamble pattern is an alternating

sequence of ones and zeros (01010101…).

The minimum length of the preamble is

programmable. When enabling TX, the

modulator will start transmitting the preamble.

When the programmed number of preamble

bytes has been transmitted, the modulator will

send the sync word and then data from the TX

FIFO if data is available. If the TX FIFO is

empty, the modulator will continue to send

preamble bytes until the first byte is written to

the TX FIFO. The modulator will then send the

sync word and then the data bytes. The

number of preamble bytes is programmed with

the MDMCFG1.NUM_PREAMBLEvalue.

The synchronization word is a two-byte value

set in the SYNC1 and SYNC0 registers. The

sync word provides byte synchronization of the

incoming packet. A one-byte synch word can

be emulated by setting the SYNC1value to the

preamble pattern. It is also possible to emulate

a

32

bit

sync

word

by

using

MDMCFG2.SYNC_MODE=3 or 7. The sync word

will then be repeated twice.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 19 of 54

CC2550

13.2.1 Arbitrary length field configuration

CC2550 supports both fixed packet length

protocols and variable packet length protocols.

Variable or fixed packet length mode can be

used for packets up to 255 bytes. For longer

packets, infinite packet length mode must be

used.

By utilizing the infinite packet length option,

arbitrary packet length is available. At the start

of the packet, the infinite mode must be active.

On the TX side, the PKTLEN register is set to

mod(length, 256). When less than 256

bytes remains of the packet the MCU disables

infinite packet length and activates fixed length

packets. When the internal byte counter

reaches the PKTLEN value, the transmission

ends. Automatic CRC appending/checking can

be used (by setting PKTCTRL0.CRC_ENto 1).

Fixed packet length mode is selected by

setting PKTCTRL0.LENGTH_CONFIG=0. The

desired packet length is set by the PKTLEN

register.

In

variable

packet

length

mode,

PKTCTRL0.LENGTH_CONFIG=1, the packet

length is configured by the first byte after the

sync word. The packet length is defined as the

payload data, excluding the length byte and

the optional automatic CRC.

When for example a 600-byte packet is to be

transmitted, the MCU should do the following

(see also Figure 11):

•

Set PKTCTRL0.LENGTH_CONFIG=2 (10).

With PKTCTRL0.LENGTH_CONFIG=2, the

packet length is set to infinite and transmission

will continue until turned off manually. The

infinite mode can be turned off while a packet

is being transmitted. As described in the next

section, this can be used to support packet

formats with different length configuration than

natively supported by CC2550.

Pre-program the PKTLEN register to

mod(600,256)=88.

•

Transmit at least 345 bytes, for example

by filling the 64-byte TX FIFO six times

(384 bytes transmitted).

•

Set PKTCTRL0.LENGTH_CONFIG=0 (00).

The transmission ends when the packet

counter reaches 88. A total of 600 bytes

are transmitted.

Figure 11: Arbitrary length field configuration

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 20 of 54

CC2550

13.3 Packet Handling in Transmit Mode

enabled, the checksum is calculated over all

the data pulled from the TX FIFO and the

result is sent as two extra bytes at the end of

the payload data.

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

length is enabled. The length byte has a value

equal to the payload of the packet (including

the optional address byte). If fixed packet

length is enabled, then the first byte written to

the TX FIFO is interpreted as the destination

address, if this feature is enabled in the device

that receives the packet.

If whitening is enabled, the length byte,

payload data and the two CRC bytes will be

whitened. This is done before the optional

FEC/Interleaver stage. Whitening is enabled

by setting PKTCTRL0.WHITE_DATA=1.

If FEC/Interleaving is enabled, the length byte,

payload data and the two CRC bytes will be

scrambled by the interleaver, and FEC

encoded before being modulated.

The modulator will first send the programmed

number of preamble bytes. If data is available

in the TX FIFO, the modulator will send the

two-byte (optionally 4-byte) sync word and

then the payload in the TX FIFO. If CRC is

14

Modulation Formats

CC2550 supports amplitude, frequency and

Format

Symbol

Coding

phase shift modulation formats. The desired

FSK\GFSK

‘0’

‘1’

– Deviation

+ Deviation

modulation

format

is

set

in

the

MDMCFG2.MOD_FORMAT register.

Optionally, the data stream can be Manchester

coded by the modulator. This option is enabled

by setting MDMCFG2.MANCHESTER_EN=1.

Manchester encoding is not supported at the

same time as using the FEC/Interleaver

option.

Table 17: Symbol encoding for FSK

modulation

14.2 Minimum Shift Keying

When using MSK¹, the complete transmission

(preamble, sync word and payload) will be

MSK modulated.

Phase shifts are performed with a constant

transition time.

14.1 Frequency Shift Keying

FSK can optionally be shaped by a Gaussian

filter with BT=1, producing a GFSK modulated

signal.

The fraction of a symbol period used to

change the phase can be modified with the

DEVIATN.DEVIATION_M setting. This is

equivalent to changing the shaping of the

symbol.

The frequency deviation is programmed with

the DEVIATION_M and DEVIATION_E values

in the DEVIATN register. The value has an

exponent/mantissa form, and the resultant

deviation is given by:

The MSK modulation format implemented in

CC2550

inverts the sync word and data

compared to e.g. signal generators.

f_xosc

⋅(8 + DEVIATION _ M )⋅2^{DEVIATION _ E}

14.3 Amplitude Modulation

f_dev

=

2¹⁷

The supported amplitude modulation On-Off

Keying (OOK) simply turns on or off the PA to

modulate 1 and 0 respectively.

The symbol encoding is shown in Table 17.

1

Identical to offset QPSK with half-sine

shaping (data coding may differ)

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 21 of 54

CC2550

15

Forward Error Correction with Interleaving

15.1 Forward Error Correction (FEC)

15.2 Interleaving

Data received through real radio channels will

often experience burst errors due to

interference and time-varying signal strengths.

In order to increase the robustness to errors

spanning multiple bits, interleaving is used

when FEC is enabled. After de-interleaving, a

continuous span of errors in the received

stream will become single errors spread apart.

CC2550 has built in support for Forward Error

Correction (FEC) that can be used with CC2500

at the receiver end. To enable this option, set

MDMCFG1.FEC_EN to 1. FEC is employed on

the data field and CRC word in order to reduce

the gross bit error rate when operating near

the sensitivity limit. Redundancy is added to

the transmitted data in such a way that the

receiver can restore the original data in the

presence of some bit errors.

CC2550 employs matrix interleaving, which is

illustrated in Figure 12. The on-chip

interleaving and de-interleaving buffers are 4 x

4 matrices. In the transmitter, the data bits are

written into the rows of the matrix, whereas the

bit sequence to be transmitted is read from the

columns of the matrix and fed to the rate ½

convolutional coder. Conversely, in a CC2500

receiver, the received symbols are written into

the columns of the matrix, whereas the data

passed onto the convolutional decoder is read

from the rows of the matrix.

The use of FEC allows correct reception at a

lower SNR, thus extending communication

range. Alternatively, for a given SNR, using

FEC decreases the bit error rate (BER). As the

packet error rate (PER) is related to BER by:

PER = 1− (1− BER)^{packet _ length}

,

a lower BER can be used to allow longer

packets, or a higher percentage of packets of

a given length, to be transmitted successfully.

Finally, in realistic ISM radio environments,

transient and time-varying phenomena will

produce occasional errors even in otherwise

good reception conditions. FEC will mask such

errors and, combined with interleaving of the

coded data, even correct relatively long

periods of faulty reception (burst errors).

When FEC and interleaving is used at least

one extra byte is required for trellis

termination. In addition, the amount of data

transmitted over the air must be a multiple of

the size of the interleaver buffer (two bytes).

The packet control hardware therefore

automatically inserts one or two extra bytes at

the end of the packet, so that the total length

of the data to be interleaved is an even

number. Note that these extra bytes are

invisible to the user, as they are removed

before the received packet enters the RX FIFO

in a CC2500.

The FEC scheme adopted for CC2550 is

convolutional coding, in which n bits are

generated based on k input bits and the m

most recent input bits, forming a code stream

able to withstand a certain number of bit errors

between each coding state (the m-bit window).

When FEC and interleaving is used the

minimum data payload is 2 bytes in fixed and

variable packet length mode.

The convolutional coder is a rate 1/2 code with

a constraint length of m=4. The coder codes

one input bit and produces two output bits;

hence, the effective data rate is halved.

Note that for the CC2500 transceiver FEC is

only supported in fixed packet length mode

(PKTCTRL0.LENGTH_CONFIG=0).

1) Storing coded

data

2) Transmitting

interleaved data

3) Receiving

interleaved data

4) Passing on data

to decoder

TX

RX

Data

Transmitter

Receiver

Figure 12: General principle of matrix interleaving

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 22 of 54

CC2550

16

Radio Control

SIDLE

SLEEP

0

SPWD

CAL_COMPLETE

CSn = 0

SXOFF

CSn = 0

MANCAL

3,4,5

IDLE

1

SCAL

XOFF

2

STX

| SFSTXON

FS_WAKEUP

6,7

FS_AUTOCAL = 01

&

STX

| SFSTXON

FS_AUTOCAL = 00 | 10 | 11

&

CALIBRATE

STX

| SFSTXON

8

CAL_COMPLETE

SETTLING

9,10,11

SFSTXON

FSTXON

18

STX

TXOFF_MODE = 01

TX

19,20

TXOFF_MODE = 10

TXFIFO_UNDERFLOW

TXOFF_MODE = 00

&

FS_AUTOCAL = 10 | 11

CALIBRATE

12

TXOFF_MODE = 00

&

FS_AUTOCAL = 00 | 01

TX_UNDERFLOW

22

SFTX

IDLE

1

Figure 13: Radio control state diagram

13. The numbers refer to the state number

readable in the MARCSTATE status register.

This functionality is primarily for test purposes.

CC2550 has a built-in state machine that is

used to switch between different operation

states (modes). The change of state is done

either by using command strobes or by

internal events such as TX FIFO underflow.

16.1 Power-On Start-Up Sequence

A simplified state diagram, together with

typical usage and current consumption, is

shown in Figure 4 on page 12. The complete

radio control state diagram is shown in Figure

When the power supply is turned on, the

system must be reset. One of the following two

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 23 of 54

CC2550

XOSC and voltage regulator switched on

40 us

sequences must be followed: Automatic

power-on reset (POR) or manual reset.

16.1.1 Automatic POR

CSn

SO

A power-on reset circuit is included in the

CC2550. The minimum requirements stated in

Section 4.7 must be followed for the power-on

reset to function properly. The internal power-

up sequence is completed when CHIP_RDYn

goes low. CHIP_RDYn is observed on the SO

pin after CSn is pulled low. See Section 10.1

for more details on CHIP_RDYn.

XOSC and voltage

regulator stabilized

SRES

SI

Figure 15: Power-on reset with SRES

When the CC2550 reset is completed the chip

will be in the IDLE state and the crystal

oscillator running. If the chip has had sufficient

time for the crystal oscillator and voltage

regulator to stabilize after the power-on-reset,

the SOpin will go low immediately after taking

CSn low. If CSn is taken low before reset is

completed the SO pin will first go high,

indicating that the crystal oscillator and voltage

regulator is not stabilized, before going low as

shown in Figure 14.

Note that the above reset procedure is only

required just after the power supply is first

turned on. If the user wants to reset the

CC2550 after this, it is only necessary to issue

an SREScommand strobe.

16.2 Crystal Control

The crystal oscillator is automatically turned on

when CSn goes low. It will be turned off if the

SXOFF or SPWD command strobes are issued;

the state machine then goes to XOFF or

SLEEP respectively. This can be done from

any state. The XOSC will be turned off when

CSnis released (goes high). The XOSC will be

automatically turned on again when CSn goes

low. The state machine will then go to the

IDLE state. The SO pin on the SPI interface

must be zero before the SPI interface is ready

to be used; as described in Section 10.1 on

page 15.

CSn

SO

XOSC and voltage

regulator stabilized

Figure 14: Power-on reset

16.1.2 Manual Reset

The other global reset possibility on CC2550 is

the SRES command strobe. By issuing this

strobe, all internal registers and states are set

to the default, IDLE state. The manual power-

up sequence is as follows (see Figure 15):

Crystal oscillator start-up time depends on

crystal ESR and load capacitances. The

electrical specification for the crystal oscillator

can be found in Section 4.3 on page 6.

16.3 Voltage Regulator Control

•

Set SCLK=1 and SI=0, to avoid potential

problems with pin control mode (see

Section 11.2 on page 17).

The voltage regulator to the digital core is

controlled by the radio controller. When the

chip enters the SLEEP state, which is the state

with the lowest current consumption, the

voltage regulator is disabled. This occurs after

CSn is released when a SPWD command

strobe has been sent on the SPI interface. The

chip is now in the SLEEP state. Setting CSn

low again will turn on the regulator and crystal

oscillator and make the chip enter the IDLE

state.

•

Strobe CSnlow / high.

Hold CSnhigh for at least 40 µs relative to

pulling CSnlow

•

Pull CSn low and wait for SO to go low

(CHIP_RDYn).

•

Issue the SRESstrobe on the SI line.

When SO goes low again, reset is

complete and the chip is in the IDLE state.

All CC2550 register values (with the exception

of the MCSM0.PO_TIMEOUT field) are lost in

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 24 of 54

CC2550

the SLEEP state. After the chip gets back to

the IDLE state, the registers will have default

(reset) contents and must be reprogrammed

over the SPI interface.

The SIDLE command strobe can always be

used to force the radio controller to go to the

IDLE state.

16.5 Timing

16.4 Active Mode

The radio controller controls most timing in

CC2550, such as synthesizer calibration and

PLL lock. Timing from IDLE to TX is constant,

dependent on the auto calibration setting. The

calibration time is constant 18739 clock

periods. Table 18 shows timing in crystal clock

cycles for key state transitions.

The active transmit mode is activated by the

MCU by using the STXcommand strobe.

The frequency synthesizer must be calibrated

regularly. CC2550 has one manual calibration

option (using the SCAL strobe), and three

automatic calibration options, controlled by the

MCSM0.FS_AUTOCALsetting:

Power on time and XOSC start-up times are

variable, but within the limits stated in Table 6.

•

Calibrate when going from IDLE to TX

(or FSTXON)

Note that in a frequency hopping spread

spectrum or a multi-channel protocol the

calibration time can be reduced from 721 µs to

approximately 150 µs. This is explained in

Section 26.2.

•

Calibrate when going from TX to IDLE

Calibrate every fourth time when going

from TX to IDLE

Description

XOSC

periods

26 MHz

crystal

The calibration takes a constant number of

XOSC cycles (see Table 18 for timing details).

Idle to TX/FSTXON, no calibration

Idle to TX/FSTXON, with calibration

TX to IDLE, no calibration

2298

88.4 µs

809 µs

0.1 µs

When TX is active, the chip will remain in the

TX state until the current packet has been

successfully transmitted. Then the state will

~21037

2

change

as

indicated

by

the

TX to IDLE, including calibration

Manual calibration

~18739

721 µs

MCSM1.TXOFF_MODE setting. The possible

destinations are:

•

IDLE

Table 18: State transition timing

FSTXON: Frequency synthesizer on

and ready at the TX frequency.

Activate TX with STX.

•

TX: Start sending preambles

17

Data FIFO

The number of bytes in the TX FIFO can also

be read from the TXBYTES.NUM_TXBYTES

status register.

The CC2550 contains a 64 byte FIFO for data

to be transmitted. The SPI interface is used for

writing to the TX FIFO. Section 10.5 contains

details on the SPI FIFO access. The FIFO

controller will detect underflow in the TX FIFO.

The 4-bit FIFOTHR.FIFO_THRsetting is used

to program the FIFO threshold point. Table 19

lists the 16 FIFO_THR settings and the

corresponding thresholds for the TX FIFO.

When writing to the TX FIFO it is the

responsibility of the MCU to avoid TX FIFO

overflow. A TX FIFO overflow will result in an

error in the TX FIFO content.

A flag will assert when the number of bytes in

the FIFO is equal to or higher than the

programmed threshold. The flag is used to

generate the FIFO status signals that can be

viewed on the GDO pins (see Section 24 on

page 30).

The chip status byte that is available on the SO

pin while transferring the SPI address contains

the fill grade of the TX FIFO. Section 10.1 on

page 15 contains more details on this.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 25 of 54

CC2550

Figure 17 shows the number of bytes in the TX

FIFO when the threshold flag toggles, in the

case of FIFO_THR=13. Figure 16 shows the

flag as the FIFO is filled above the threshold,

and then drained below.

NUM_TXBYTES

GDO

6

7

8

9

10

9

8

7

6

Figure 16: FIFO_THR=13 vs. number of bytes

in FIFO (GDOx_CFG=0x02)

FIFO_THR

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Bytes in TX FIFO

61

57

53

49

45

41

37

33

29

25

21

17

13

9

FIFO_THR=13

Underflow

8 bytes

margin

TXFIFO

5

1

Figure 17: Example of FIFO at threshold

Table 19: FIFO_THRsettings and the

corresponding FIFO thresholds

18

Frequency Programming

The base or start frequency is set by the 24 bit

frequency word located in the FREQ2, FREQ1

and FREQ0 registers. This word will typically

be set to the centre of the lowest channel

frequency that is to be used.

The frequency programming in CC2550 is

designed to minimize the programming

needed in a channel-oriented system.

To set up a system with channel numbers, the

desired channel spacing is programmed with

the

MDMCFG0.CHANSPC_M

and

The desired channel number is programmed

with the 8-bit channel number register,

CHANNR.CHAN, which is multiplied by the

channel offset. The resultant carrier frequency

is given by:

MDMCFG1.CHANSPC_E registers. The channel

spacing registers are mantissa and exponent

respectively.

f_XOSC

2¹⁶

f_carrier

=

⋅

(

FREQ + CHAN ⋅

(

256 + CHANSPC _ M

)

⋅2^{CHANSPC _ E−2}))

With a 26 MHz crystal the maximum channel

spacing is 405 kHz. To get e.g. 1 MHz channel

spacing one solution is to use 333 kHz

channel spacing and select each third channel

in CHANNR.CHAN.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 26 of 54

CC2550

If any frequency programming register is

altered when the frequency synthesizer is

running, the synthesizer may give an

undesired response. Hence, the frequency

programming should only be updated when

the radio is in the IDLE state.

19

VCO

The VCO is completely integrated on-chip.

In manual mode, the calibration is initiated

when the SCAL command strobe is activated

in the IDLE mode.

19.1 VCO and PLL Self-Calibration

The calibration values are not maintained in

The VCO characteristics will vary with

temperature and supply voltage changes, as

well as the desired operating frequency. In

order to ensure reliable operation, CC2550

includes frequency synthesizer self-calibration

circuitry. This calibration should be done

regularly, and must be performed after turning

on power and before using a new frequency

(or channel). The number of XOSC cycles for

completing the PLL calibration is given in

Table 18 on page 25.

sleep mode. Therefore, the CC2550 must be

recalibrated

after

reprogramming

the

configuration registers when the chip has been

in the SLEEP state.

To check that the PLL is in lock the user can

program register IOCFGx.GDOx_CFG to 0x0A

and use the lock detector output available on

the GDOx pin as an interrupt for the MCU (x =

0,1 or 2). A positive transition on the GDOx pin

means that the PLL is in lock. As an alternative

the user can read register FSCAL1. The PLL is

in lock if the register content is different from

0x3F. For more robust operation the source

code could include a check so that the PLL is

re-calibrated until PLL lock is achieved if the

PLL does not lock the first time.

The calibration can be initiated automatically

or manually. The synthesizer can be

automatically calibrated each time the

synthesizer is turned on, or each time the

synthesizer is turned off. This is configured

with the MCSM0.FS_AUTOCAL register setting.

20

Voltage Regulators

If the chip is programmed to enter power-down

mode, (SPWDstrobe issued), the power will be

turned off after CSngoes high. The power and

crystal oscillator will be turned on again when

CSngoes low.

CC2550 contains several on-chip linear voltage

regulators, which generate the supply voltage

needed by low-voltage modules. These

voltage regulators are invisible to the user, and

can be viewed as integral parts of the various

modules. The user must however make sure

that the absolute maximum ratings and

required pin voltages in Table 1 and Table 11

are not exceeded. The voltage regulator for

the digital core requires one external

decoupling capacitor.

The voltage regulator output should only be

used for driving the CC2550.

Setting the CSn pin low turns on the voltage

regulator to the digital core and starts the

crystal oscillator. The SO pin on the SPI

interface must go low before using the serial

interface (setup time is given in Table 14).

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 27 of 54

CC2550

21

Output Power Programming

The RF output power level from the device has

two levels of programmability, as illustrated in

Figure 18. Firstly, the special PATABLE

register can hold up to eight user selected

output power settings. Secondly, the 3-bit

The power ramping at the start and at the end

of a packet can be turned off by setting

FREND0.PA_POWER

to

0

and

then

programming the desired output power to

index 0 in the PATABLE.

FREND0.PA_POWER

value

selects

the

Table 20 contains recommended PATABLE

settings for various output levels and

frequency bands. See Section 10.6 on page

16 for PATABLEprogramming details.

PATABLE entry to use. This two-level

functionality provides flexible PA power ramp

up and ramp down at the start and end of

transmission. All the PA power settings in the

PATABLE from index

FREND0.PA_POWERvalue are used.

0

up to the

PATABLE must be programmed in burst mode

if you want to write to other entries than

PATABLE[0].

PATABLE(7)[7:0]

The PA uses this

setting.

PATABLE(6)[7:0]

PATABLE(5)[7:0]

PATABLE(4)[7:0]

PATABLE(3)[7:0]

PATABLE(2)[7:0]

PATABLE(1)[7:0]

PATABLE(0)[7:0]

Settings 0 to PA_POWER are

used during ramp-up at start of

transmission and ramp-down at

end of transmission, and for

OOK modulation.

Index into PATABLE(7:0)

The SmartRF® Studio software

should be used to obtain optimum

PATABLE settings for various

output powers.

e.g 6

PA_POWER[2:0]

in FREND0 register

Figure 18: PA_POWER and PATABLE

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 28 of 54

CC2550

Output power, typical,

+25^oC, 3.0 V [dBm]

PATABLE

value

Current consumption,

typical [mA]

(–55 or less)

–30

–28

–26

–24

–22

–20

–18

–16

–14

–12

–10

–8

0x00

0x44

0x41

0x43

0x84

0x82

0x47

0xC8

0x85

0x59

0xC6

0x97

0xD6

0x7F

0xA9

0xBF

0xEE

0xFF

8.0

9.3

9.2

9.7

9.8

9.7

10.0

11.6

10.2

11.6

11.2

12.0

12.9

14.7

16.2

18.1

19.4

21.3

–6

–4

–2

0

1

Table 20: Optimum PATABLE settings for various output power levels

22

Crystal Oscillator

A crystal in the frequency range 26-27 MHz

must be connected between the XOSC_Q1

and XOSC_Q2 pins. The oscillator is designed

for parallel mode operation of the crystal. In

addition, loading capacitors (C51 and C71) for

the crystal are required. The loading capacitor

values depend on the total load capacitance,

C_L, specified for the crystal. The total load

capacitance seen between the crystal

terminals should equal C_Lfor the crystal to

oscillate at the specified frequency.

The crystal oscillator circuit is shown in Figure

19. Typical component values for different

values of C_Lare given in Table 21.

The crystal oscillator is amplitude regulated.

This means that a high current is used to start

up the oscillations. When the amplitude builds

up, the current is reduced to what is necessary

to maintain approximately 0.4 Vpp signal

swing. This ensures a fast start-up, and keeps

the drive level to a minimum. The ESR of the

crystal should be within the specification in

order to ensure a reliable start-up (see Section

4.3 on page 6).

1

C_L=

+ C_parasitic

1

+

XOSC_Q1

XOSC_Q2

C₅₁C₇₁

XTAL

The parasitic capacitance is constituted by pin

input capacitance and PCB stray capacitance.

Total parasitic capacitance is typically 2.5 pF.

C51

C71

Figure 19: Crystal oscillator circuit

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 29 of 54

CC2550

Component

C51

C_L= 10pF

15 pF

C_L=13pF

22 pF

C_L=16pF

27 pF

C71

15 pF

22 pF

27 pF

Table 21: Crystal oscillator component values

22.1 Reference Signal

The reference signal must be connected to the

XOSC_Q1 input. The sine wave must be

The chip can alternatively be operated with a

reference signal from 26 to 27 MHz instead of

a crystal. This input clock can either be a full-

swing digital signal (0 V to VDD) or a sine

wave of maximum 1 V peak-peak amplitude.

connected to XOSC_Q1 using

a

serial

capacitor. The XOSC_Q2 line must be left un-

connected. C51 and C71 can be omitted when

using a reference signal

23

External RF Match

differential impedance as seen from the RF-

port (RF_P and RF_N) towards the antenna:

The balanced RF output of CC2550 is designed

for a simple, low-cost matching and balun

network on the printed circuit board. A few

passive external components ensure proper

matching.

Z_out= 80 + j74 Ω

To ensure optimal matching of the CC2550

differential output it is highly recommended to

follow the CC2550EM reference designs as

closely as possible. Gerber files for the

reference designs are available for download

from the TI and Chipcon websites.

Although CC2550 has a balanced RF output,

the chip can be connected to a single-ended

antenna with few external low cost capacitors

and inductors.

The

passive

matching/filtering

network

connected to CC2550 should have the following

24

General Purpose / Test Output Control Pins

The two digital output pins GDO0and GDO1are

general control pins. Their functions are

programmed by IOCFG0.GDO0_CFG and

IOCFG1.GDO1_CFG respectively. Table 22

shows the different signals that can be

monitored on the GDO pins. These signals can

be used as an interrupt to the MCU. GDO1 is

the same pin as the SO pin on the SPI

interface, thus the output programmed on this

pin will only be valid when CSn is high. The

default value for GDO1 is 3-stated, which is

useful when the SPI interface is shared with

other devices.

The default value for GDO0 is a 135-141 kHz

clock output (XOSC frequency divided by 192).

Since the XOSC is turned on at power-on-

reset, this can be used to clock the MCU in

systems with only one crystal. When the MCU

is up and running, it can change the clock

frequency by writing to IOCFG0.GDO0_CFG.

An on-chip analog temperature sensor is

enabled by writing the value 128 (0x80h) to the

IOCFG0.GDO0_CFG register. The voltage on

the GDO0 pin is then proportional to

temperature. See Section 4.5 on page 7 for

temperature sensor specifications.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 30 of 54

CC2550

GDOx_CFG[5:0] Description

0 (0x00)

1 (0x01)

Reserved – defined on the transceiver version.

Associated with the TX FIFO: Asserts when the TX FIFO is filled at or above TXFIFO_THR. De-asserts when the TX

2 (0x02)

3 (0x03)

FIFO is below TXFIFO_THR.

Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below

TXFIFO_THR.

4 (0x04)

5 (0x05)

Reserved – defined on the transceiver version.

Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.

Asserts when sync word has been sent, and de-asserts at the end of the packet. The pin will also de-assert if the TX

FIFO underflows.

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

Reserved – defined on the transceiver version.

Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To

check for PLL lock the lock detector output should be used as an interrupt for the MCU.

Serial Clock. Synchronous to the data in synchronous serial mode.

Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK when GDOx_INV=0.

10 (0x0A)

11 (0x0B)

12 (0x0C) Reserved – defined on the transceiver version.

13 (0x0D) Reserved – defined on the transceiver version.

14 (0x0E) Reserved – defined on the transceiver version.

15 (0x0F) Reserved – defined on the transceiver version.

16 (0x10) Reserved – used for test.

17 (0x11) Reserved – used for test.

18 (0x12) Reserved – used for test.

19 (0x13) Reserved – used for test.

20 (0x14) Reserved – used for test.

21 (0x15) Reserved – used for test.

22 (0x16) Reserved – defined on the transceiver version.

23 (0x17) Reserved – defined on the transceiver version.

24 (0x18) Reserved – used for test.

25 (0x19) Reserved – used for test.

26 (0x1A) Reserved – used for test.

PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA in applications

where the SLEEP state is used it is recommended to use address 47 (0x2F).

27 (0x1B)

28 (0x1C) Reserved – defined on the transceiver version.

29 (0x1D) Reserved – defined on the transceiver version.

30 (0x1E) Reserved – used for test.

31 (0x1F) Reserved – used for test.

32 (0x20) Reserved – used for test.

33 (0x21) Reserved – used for test.

34 (0x22) Reserved – used for test.

35 (0x23) Reserved – used for test.

36 (0x24) Reserved – used for test.

37 (0x25) Reserved – used for test.

38 (0x26) Reserved – used for test.

39 (0x27) Reserved – used for test.

40 (0x28) Reserved – used for test.

41 (0x29) CHIP_RDY

42 (0x2A) Reserved – used for test.

43 (0x2B) XOSC_STABLE

44 (0x2C) Reserved – used for test.

45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).

46 (0x2E) High impedance (3-state)

47 (0x2F) HW to 0 (HW1 achieved with _INV signal). Can be used to control an external PA

48 (0x30) CLK_XOSC/1

49 (0x31) CLK_XOSC/1.5

50 (0x32) CLK_XOSC/2

51 (0x33) CLK_XOSC/3

52 (0x34) CLK_XOSC/4

53 (0x35) CLK_XOSC/6

54 (0x36) CLK_XOSC/8

55 (0x37) CLK_XOSC/12

56 (0x38) CLK_XOSC/16

Note: There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any

time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be

configured to a value less than 0x30. The GDO0 default value is CLK_XOSC/192.

57 (0x39) CLK_XOSC/24

58 (0x3A) CLK_XOSC/32

59 (0x3B) CLK_XOSC/48

60 (0x3C) CLK_XOSC/64

61 (0x3D) CLK_XOSC/96

62 (0x3E) CLK_XOSC/128

63 (0x3F) CLK_XOSC/192

Table 22: GDOx signal selection (x = 0 or 1)

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 31 of 54

CC2550

25

Asynchronous and Synchronous Serial Operation

Several features and modes of operation have

been included in the CC2550 to provide

backward compatibility with previous Chipcon

products and other existing RF communication

systems. For new systems, it is recommended

to use the built-in packet handling features, as

they can give more robust communication,

significantly offload the microcontroller and

simplify software development.

The CC2550 modulator samples the level of the

asynchronous input 8 times faster than the

programmed data rate. The timing requirement

for the asynchronous stream is that the error in

the bit period must be less than one eighth of

the programmed data rate.

25.2 Synchronous serial operation

Setting

PKTCTRL0.PKT_FORMAT

to

1

enables synchronous serial operation mode. In

this operational mode the data must be NRZ

encoded (MDMCFG2.MANCHESTER_EN=0). In

synchronous serial operation mode, data is

transferred on a two wire serial interface. The

CC2550 provides a clock that is used to set up

new data on the data input line. Data input (TX

data) is the GDO0 pin. This pin will

automatically be configured as an input when

TX is active.

25.1 Asynchronous operation

For backward compatibility with systems

already using the asynchronous data transfer

from other Chipcon products, asynchronous

transfer is also included in CC2550. When

asynchronous transfer is enabled, several of

the support mechanisms for the MCU that are

included in CC2550 will be disabled, such as

packet handling hardware, buffering in the

FIFO and so on. The asynchronous transfer

mode does not allow the use of the data

whitener, interleaver and FEC.

Preamble and sync word insertion may or may

not be active, dependent on the sync mode set

by the MDMCFG3.SYNC_MODE. If preamble and

sync word is disabled, all other packet handler

features and FEC should also be disabled.

The MCU must then handle preamble and

sync word insertion in software. If preamble

and sync word insertion is left on, all packet

handling features and FEC can be used. The

CC2550 will insert the preamble and sync word

and the MCU will only provide the data

Only FSK, GFSK and OOK are supported for

asynchronous transfer.

Setting

PKTCTRL0.PKT_FORMAT

to

3

enables asynchronous transparent (serial)

mode.

In TX, the GDO0pin is used for data input (TX

data).

payload.

This

is

equivalent

to

the

The MCU must control start and stop of

transmit with the STXand SIDLEstrobes.

recommended FIFO operation mode.

26 System considerations and Guidelines

26.1 SRD Regulations

Please note that compliance with regulations

is dependent on complete system

performance. It is the customer’s responsibility

to ensure that the system complies with

regulations.

International regulations and national laws

regulate the use of radio receivers and

transmitters. Short Range Devices (SRDs) for

license free operation are allowed to operate

in the 2.45 GHz bands worldwide. The most

important regulations are EN 300 440 and EN

300 328 (Europe), FCC CFR47 part 15.247

and 15.249 (USA), and ARIB STD-T66

(Japan). A summary of the most important

aspects of these regulations can be found in

Application Note AN032 SRD regulations for

license-free transceiver operation in the 2.4

GHz band, available from the TI and Chipcon

websites.

26.2 Frequency Hopping and Multi-

Channel Systems

The 2.400 – 2.4835 GHz band is shared by

many systems both in industrial, office and

home

environments.

It

is

therefore

recommended to use frequency hopping

spread spectrum (FHSS) or a multi-channel

protocol because the frequency diversity

makes the system more robust with respect to

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 32 of 54

CC2550

interference from other systems operating in

the same frequency band. FHSS also combats

multipath fading.

A maximum peak output power of 1 W (+30

dBm) is allowed if the 6 dB bandwidth of the

modulated signal exceeds 500 kHz. In

addition, the peak power spectral density

conducted to the antenna shall not be greater

than +8 dBm in any 3 kHz band.

CC2550 is highly suited for FHSS or multi-

channel systems due to its agile frequency

synthesizer and effective communication

interface. Using the packet handling support

and data buffering is also beneficial in such

systems as these features will significantly

offload the host controller.

Operating at high data rates and high

frequency separation, the CC2550 is suited for

systems targeting compliance with digital

modulation systems as defined by FCC part

15.247. An external power amplifier is needed

to increase the output above +1 dBm.

Charge pump current, VCO current and VCO

capacitance array calibration data is required

for each frequency when implementing

frequency hopping for CC2550. There are 3

ways of obtaining the calibration data from the

chip:

26.4 Data Burst Transmissions

The high maximum data rate of CC2550 opens

up for burst transmissions. A low average data

rate link (e.g. 10 kbps), can be realized using a

higher over-the-air data rate. Buffering the

data and transmitting in bursts at high data

rate (e.g. 500 kbps) will reduce the time in

active mode, and hence also reduce the

average current consumption significantly.

Reducing the time in active mode will reduce

the likelihood of collisions with other 2.4 GHz

systems, e.g. WLAN.

1) Frequency hopping with calibration for each

hop. The PLL calibration time is approximately

720 µs.

2) Fast frequency hopping without calibration

for each hop can be done by calibrating each

frequency at startup and saving the resulting

FSCAL3, FSCAL2 and FSCAL1register values

in MCU memory. Between each frequency

hop, the calibration process can then be

replaced by writing the FSCAL3, FSCAL2 and

FSCAL1 register values corresponding to the

next RF frequency. The PLL turn on time is

approximately 90 µs.

26.5 Continuous Transmissions

In data streaming applications the CC2550

opens up for continuous transmissions at 500

kbps effective data rate. As the modulation is

done with an I/Q up-converter with LO I/Q-

signals coming from a closed loop PLL, there

is no limitation in the length of a transmission.

(Open loop modulation used in some

transceivers often prevents this kind of

continuous data streaming and reduces the

effective data rate.)

3) Run calibration on a single frequency at

startup. Next write 0 to FSCAL3[5:4] to

disable the charge pump calibration. After

writing to FSCAL3[5:4] strobe SRX (or STX)

with MCSM0.FS_AUTOCAL = 1 for each new

frequency hop. That is, VCO current and VCO

capacitance calibration is done but not charge

pump current calibration. When charge pump

current calibration is disabled the calibration

time is reduced from approximately 720 µs to

approximately 150 µs.

26.6 Spectrum Efficient Modulation

CC2500 also has the possibility to use

Gaussian shaped FSK (GFSK). This

spectrum-shaping feature improves adjacent

There is a trade off between blanking time and

memory space needed for storing calibration

data in non-volatile memory. Solution 2) above

gives the shortest blanking interval, but

requires more memory space to store

channel

power

(ACP)

and

occupied

bandwidth. In ‘true’ FSK systems with abrupt

frequency shifting, the spectrum is inherently

broad. By making the frequency shift ‘softer’,

the spectrum can be made significantly

narrower. Thus, higher data rates can be

transmitted in the same bandwidth using

GFSK.

calibration

values.

Solution

3)

gives

approximately 570 µs smaller blanking interval

than solution 1).

26.3 Wideband Modulation not Using

Spread Spectrum

Digital modulation systems under FCC part

15.247 includes FSK and GFSK modulation.

PRELIMINARY Data Sheet (Rev.1.2)

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CC2550

26.7 Low Cost Systems

26.8 Battery Operated Systems

In low power applications, the SLEEP state

should be used when the CC2550 is not active.

As the CC2550 provides 500 kbps multi-

channel performance without any external

filters, a very low cost system can be made.

A differential antenna will eliminate the need

for a balun, and the DC biasing can be

achieved in the antenna topology, see Figure

3.

26.9 Increasing Output Power

In some applications it may be necessary to

extend the link range by adding an external

power amplifier.

A HC-49 type SMD crystal is used in the

CC2550EM reference design. Note that the

crystal package strongly influences the price.

In a size constrained PCB design a smaller,

but more expensive, crystal may be used.

The power amplifier should be inserted

between the antenna and the balun as shown

in Figure 20.

Figure 20. Block diagram of CC2550 usage with external power amplifier

27

Configuration Registers

The TX FIFO is accessed through one 8-bit

register. Only write operations are allowed to

the TX FIFO.

The configuration of CC2550 is done by

programming 8-bit registers. The configuration

data based on selected system parameters

are most easily found by using the SmartRF^®

Studio software. Complete descriptions of the

registers are given in the following tables. After

chip reset, all the registers have default values

as shown in the tables.

During the address transfer and while writing

to a register or the TX FIFO, a status byte is

returned. This status byte is described in Table

15 on page 15.

Table 26 summarizes the SPI address space.

Registers that are only defined on the CC2500

transceiver are also listed. CC2500 and CC2550

are register compatible, but registers and fields

only implemented in the transceiver always

contain 0 in CC2550.

There are 9 Command Strobe Registers, listed

in Table 23. Accessing these registers will

initiate the change of an internal state or

mode. There are 29 normal 8-bit Configuration

Registers, listed in Table 24. Many of these

registers are for test purposes only, and need

not be written for normal operation of CC2550.

The address to use is given by adding the

base address to the left and the burst and

read/write bits on the top. Note that the burst

bit has different meaning for base addresses

above and below 0x2F.

There are also 6 Status registers, which are

listed in Table 25. These registers, which are

read-only, contain information about the status

of CC2550.

PRELIMINARY Data Sheet (Rev.1.2)

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Page 34 of 54

CC2550

Address Strobe Name Description

0x30

0x31

SRES

Reset chip.

SFSTXON

Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).

0x32

0x33

SXOFF

SCAL

Turn off crystal oscillator.

Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed

in IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0).

0x35

STX

Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.

0x36

0x39

SIDLE

SPWD

Exit TX and turn off frequency synthesizer.

Enter power down mode when CSngoes high.

0x3B

0x3D

SFTX

Flush the TX FIFO buffer.

SNOP

No operation. May be used to pad strobe commands to two bytes for simpler software.

Table 23: Command strobes

PRELIMINARY Data Sheet (Rev.1.2)

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Page 35 of 54

CC2550

Address

Register

Description

Details on page number

38

GDO1output pin configuration

0x01

IOCFG1

GDO0output pin configuration

FIFO threshold

0x02

0x03

0x04

0x05

0x06

0x08

0x0A

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x17

0x18

0x22

0x23

0x24

0x25

0x26

0x29

0x2A

0x2C

0x2D

0x2E

IOCFG0

FIFOTHR

SYNC1

38

39

40

41

42

43

44

45

46

Sync word, high byte

SYNC0

Sync word, low byte

PKTLEN

PKTCTRL0

CHANNR

FREQ2

Packet length

Packet automation control

Channel number

Frequency control word, high byte

Frequency control word, middle byte

Frequency control word, low byte

Modulator configuration

FREQ1

FREQ0

MDMCFG4

MDMCFG3

MDMCFG2

MDMCFG1

MDMCFG0

DEVIATN

MCSM1

MCSM0

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

FSTEST

PTEST

Modulator configuration

Modulator deviation setting

Main Radio Control State Machine configuration

Front end TX configuration

Frequency synthesizer calibration

Frequency synthesizer calibration control

Production test

TEST2

Various test settings

TEST1

Various test settings

TEST0

Various test settings

Table 24: Configuration registers overview

Address

Register

Description

Details on page number

46

47

48

0x30 (0xF0)

0x31 (0xF1)

0x35 (0xF5)

0x38 (0xF8)

0x39 (0xF9)

0x3A (0xFA)

PARTNUM

VERSION

CC2550 part number

Current version number

MARCSTATE

PKTSTATUS

VCO_VC_DAC

TXBYTES

Control state machine state

Current GDOx status and packet status

Current setting from PLL calibration module

Underflow and number of bytes in the TX FIFO

Table 25: Status registers overview

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 36 of 54

CC2550

Write

Read

Single byte

+0x80

Single byte

+0x00

Burst

+0x40

Burst

+0xC0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

IOCFG2

IOCFG1

IOCFG0

FIFOTHR

SYNC1

SYNC0

PKTLEN

PKTCTRL1

PKTCTRL0

ADDR

CHANNR

FSCTRL1

FSCTRL0

FREQ2

FREQ1

FREQ0

MDMCFG4

MDMCFG3

MDMCFG2

MDMCFG1

MDMCFG0

DEVIATN

MCSM2

MCSM1

MCSM0

FOCCFG

BSCFG

AGCCTRL2

AGCCTRL1

AGCCTRL0

WOREVT1

WOREVT0

WORCTRL

FREND1

FREND0

FSCAL3

FSCAL2

FSCAL1

FSCAL0

RCCTRL1

RCCTRL0

FSTEST

PTEST

AGCTEST

TEST2

TEST1

TEST0

SRES

SFSTXON

SXOFF

SCAL

SRES

PARTNUM

VERSION

FREQEST

LQI

SFSTXON

SXOFF

SCAL

SRX

STX

SRX

STX

RSSI

MARCSTATE

WORTIME1

WORTIME0

PKTSTATUS

VCO_VC_DAC

TXBYTES

RXBYTES

SIDLE

SAFC

SWOR

SPWD

SFRX

SFTX

SWORRST

SNOP

SIDLE

SAFC

SWOR

SPWD

SFRX

SFTX

SWORRST

SNOP

PATABLE

TX FIFO

PATABLE

TX FIFO

PATABLE

RX FIFO

PATABLE

RX FIFO

Table 26: SPI address space (greyed text: for reference only; not implemented on CC2550 )

PRELIMINARY Data Sheet (Rev.1.2)

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Page 37 of 54

CC2550

27.1 Configuration Register Details

0x01: IOCFG1 – GDO1output pin configuration

Bit

Field Name

Reset

R/W Description

7

GDO_DS

0

R/W Set high (1) or low (0) output drive strength on the

GDO pins.

6

0

R/W Invert output, i.e. select active low / high

GDO1_INV

5:0

46 (0x2E) R/W Default is 3-state (see Table 22 on page 31)

GDO1_CFG[5:0]

0x02: IOCFG0 – GDO0output pin configuration

Bit

Field Name

Reset

R/W Description

7

TEMP_SENSOR_ENABLE

0

R/W Enable analog temperature sensor. Write 0 in all

other register bits when using temperature sensor.

6

0

R/W Invert output, i.e. select active low / high

GDO0_INV

5:0

63 (0x3F)

R/W Default is CLK_XOSC/192 (see Table 22 on page

31)

GDO0_CFG[5:0]

0x03: FIFOTHR – FIFO threshold

Bit Field Name

Reset

R/W Description

7:4 Reserved

0 (0000) R/W Write 0 (0000) for compatibility with possible future

extensions.

3:0 FIFO_THR[3:0]

7 (0111) R/W Set the threshold for the TX FIFO. The threshold is

exceeded when the number of bytes in the FIFO is equal to

or higher than the threshold value.

Setting

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

Bytes in TX FIFO

61

57

53

49

45

41

37

33

29

25

21

17

13

9

5

1

PRELIMINARY Data Sheet (Rev.1.2)

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Page 38 of 54

CC2550

0x04: SYNC1– Sync word, high byte

Bit

Field Name

Reset

R/W Description

7:0

SYNC[15:8]

211 (0xD3)

R/W 8 MSB of 16-bit sync word

0x05: SYNC0 – Sync word, low byte

Bit

Field Name

Reset

R/W Description

7:0

SYNC[7:0]

145 (0x91)

R/W 8 LSB of 16-bit sync word

0x06: PKTLEN – Packet length

Bit Field Name

Reset

R/W Description

7:0 PACKET_LENGTH

255 (0xFF)

R/W Indicates the packet length when fixed length

packets are enabled.

0x08: PKTCTRL0 – Packet automation control

Bit Field Name

Reset R/W Description

7

6

Reserved

R0

WHITE_DATA

1

R/W Turn data whitening on / off

0: Whitening off

1: Whitening on

Data whitening can only be used when

PKTCTRL0.CC2400_EN = 0 (default).

5:4 PKT_FORMAT[1:0]

0 (00) R/W Format of RX and TX data

Setting Packet format

0 (00)

1 (01)

Normal mode, use TX FIFO

Serial Synchronous mode, used for backwards

compatibility

Random TX mode; sends random data using PN9

generator. Used for test.

2 (10)

3 (11)

Asynchronous transparent mode. Data in on GDO0

and Data out on either of the GDO pins

3

2

CC2400_EN

CRC_EN

0

1

R/W Enable CC2400 support. Use same CRC implementation as

CC2400.

PKTCTRL0.WHITE_DATA must be 0 if

PKTCTRL0.CC2400_EN= 1.

R/W 1: CRC calculation enabled

0: CRC disabled

1:0 LENGTH_CONFIG[1:0]

1 (01) R/W Configure the packet length

Setting Packet length configuration

0 (00)

Fixed length packets, length configured in

PKTLEN register

1 (01)

Variable length packets, packet length configured

by the first byte after sync word

2 (10)

3 (11)

Enable infinite length packets

Reserved

PRELIMINARY Data Sheet (Rev.1.2)

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Page 39 of 54

CC2550

0x0A: CHANNR – Channel number

Bit

Field Name

Reset

0 (0x00)

R/W Description

7:0

CHAN[7:0]

R/W The 8-bit unsigned channel number, which is multiplied by

the channel spacing setting and added to the base

frequency.

0x0D: FREQ2 – Frequency control word, high byte

Bit Field Name

Reset

R/W Description

7:6 FREQ[23:22]

1 (01)

R

FREQ[23:22] is always binary 01 (the FREQ2 register is in the range

85 to 95 with 26 - 27 MHz crystal)

5:0 FREQ[21:16]

30

(0x1E)

R/W FREQ[23:0] is the base frequency for the frequency synthesiser in

increments of F_XOSC/2¹⁶.

f_XOSC

2¹⁶

f_carrier

=

⋅ FREQ

[23 : 0

]

The default frequency word gives a base frequency of 2464 MHz,

assuming a 26.0 MHz crystal. With the default channel spacing

settings, the following FREQ2 values and channel numbers can be

used:

FREQ2

Base frequency

Frequency range (CHAN

numbers)

91 (0x5B)

92 (0x5C)

93 (0x5D)

94 (0x5E)

2386 MHz

2412 MHz

2438 MHz

2464 MHz

2400.2-2437 MHz (71-255)

2412-2463 MHz (0-255)

2431-2483.4 MHz (0-227)

2464-2483.4 MHz (0-97)

0x0E: FREQ1 – Frequency control word, middle byte

Bit Field Name

Reset

R/W Description

7:0 FREQ[15:8]

196 (0xC4)

R/W Ref. FREQ2 register

0x0F: FREQ0 – Frequency control word, low byte

Bit Field Name

Reset

R/W Description

7:0 FREQ[7:0]

236 (0xEC) R/W Ref. FREQ2 register

0x10: MDMCFG4 – Modulator configuration

Bit

Field Name

Reset

R/W Description

7:4

3:0

Reserved

R0

Defined on the transceiver version

DRATE_E[3:0]

12 (1100)

R/W The exponent of the user specified symbol rate

PRELIMINARY Data Sheet (Rev.1.2)

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Page 40 of 54

CC2550

0x11: MDMCFG3 – Modulator configuration

Bit

Field Name

Reset

R/W Description

7:0

DRATE_M[7:0]

34 (0x22)

R/W The mantissa of the user specified symbol rate. The symbol

rate is configured using an unsigned, floating-point number

with 9-bit mantissa and 4-bit exponent. The 9^thbit is a

hidden ‘1’. The resulting data rate is:

(

256 + DRATE _ M

⋅ 2^{DRATE _ E}

)

R_DATA

=

⋅ f_XOSC

2²⁸

The default values give a data rate of 115.051 kbps (closest

setting to 115.2 kbps), assuming a 26.0 MHz crystal.

0x12: MDMCFG2 – Modulator configuration

Bit

Field Name

Reset

R/W

Description

7

Reserved

R0

6:4

MOD_FORMAT[2:0]

1 (001)

R/W

The modulation format of the radio signal

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Modulation format

FSK

GFSK

-

OOK

-

MSK

3

MANCHESTER_EN

SYNC_MODE[2:0]

0

R/W

Enables Manchester encoding/decoding

0 = Disable

1 = Enable

2:0

2 (010)

Combined sync-word qualifier mode.

The values 0 (000) and 4 (100) disables preamble

and sync word transmission. The values 1 (001), 2

(001), 5 (101) and 6 (110) enables 16-bit sync word

transmission. The values 3 (011) and 7 (111)

enables repeated sync word transmission. The table

below lists the meaning of each mode (for

compatibility with the CC2500 transceiver):

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

Sync-word qualifier mode

No preamble/sync word

15/16 sync word bits detected

16/16 sync word bits detected

30/32 sync word bits detected

No preamble/sync, carrier-sense

above threshold

5 (101)

6 (110)

7 (111)

15/16 + carrier-sense above threshold

16/16 + carrier-sense above threshold

30/32 + carrier-sense above threshold

PRELIMINARY Data Sheet (Rev.1.2)

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Page 41 of 54

CC2550

0x13: MDMCFG1 – Modulator configuration

Bit

Field Name

Reset

R/W Description

7

FEC_EN

0

R/W Enable Forward Error Correction (FEC) with interleaving for

packet payload

0 = Disable

1 = Enable

6:4

NUM_PREAMBLE[2:0] 2 (010)

R/W Sets the minimum number of preamble bytes to be

transmitted

Setting

0 (000)

1 (001)

2 (010)

3 (011)

4 (100)

5 (101)

6 (110)

7 (111)

Number of preamble bytes

2

3

4

6

8

12

16

24

3:2

1:0

Reserved

CHANSPC_E[1:0]

R0

R/W 2 bit exponent of channel spacing

2 (10)

0x14: MDMCFG0 – Modulator configuration

Bit Field Name

Reset

R/W Description

7:0 CHANSPC_M[7:0]

248 (0xF8) R/W 8-bit mantissa of channel spacing (initial 1 assumed). The

channel spacing is multiplied by the channel number CHAN and

added to the base frequency. It is unsigned and has the format:

f_XOSC

2¹⁸

∆f_CHANNEL

=

⋅

(

256 + CHANSPC _ M

⋅2^{CHANSPC _ E}⋅CHAN

)

The default values give 199.951 kHz channel spacing (the

closest setting to 200 kHz), assuming 26.0 MHz crystal

frequency.

PRELIMINARY Data Sheet (Rev.1.2)

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CC2550

0x15: DEVIATN – Modulator deviation setting

Bit Field Name

Reset

R/W Description

7

Reserved

6:4 DEVIATION_E[2:0]

Reserved

2:0 DEVIATION_M[2:0]

R0

4 (100)

7 (111)

R/W Deviation exponent

3

R0

R/W When MSK modulation is enabled:

Sets fraction of symbol period used for phase change.

When FSK modulation is enabled:

Deviation mantissa, interpreted as a 4-bit value with MSB

implicit 1. The resulting FSK deviation is given by:

f_xosc

2¹⁷

f_dev

=

⋅(8 + DEVIATION _ M )⋅2^{DEVIATION _ E}

The default values give ±47.607 kHz deviation, assuming

26.0 MHz crystal frequency.

0x17: MCSM1 – Main Radio Control State Machine configuration

Bit

Field Name

Reset

R/W Description

7:6

5:2

1:0

Reserved

R0

Reserved

R0

Defined on the transceiver version

TXOFF_MODE[1:0]

0 (00)

R/W Select what should happen when a packet has been sent

(TX)

Setting

0 (00)

1 (01)

2 (10)

3 (11)

Next state after finishing packet transmission

IDLE

FSTXON

Stay in TX (start sending preamble)

Do not use, not implemented on CC2550

(Go to RX)

PRELIMINARY Data Sheet (Rev.1.2)

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CC2550

0x18: MCSM0 – Main Radio Control State Machine configuration

Bit

Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:4 FS_AUTOCAL[1:0]

0 (00)

R/W

Automatically calibrate when going to TX or back to IDLE

Setting When to perform automatic calibration

0 (00)

1 (01)

2 (10)

3 (11)

Never (manually calibrate using SCALstrobe)

When going from IDLE to TX (or FSTXON)

When going from TX back to IDLE

Every 4^thtime when going from TX to IDLE

3:2 PO_TIMEOUT

2 (10)

R/W

Programs the number of times the six-bit ripple counter must expire

after XOSC has stabilized before CHP_RDYn goes low.

The XOSC is off during power-down so the regulated digital supply

voltage has time to stabilize while waiting for the crystal to be stable

even with PO_TIMEOUT to 0.

Setting Expire count

Timeout after XOSC start

Approx. 2.3 – 2.4 µs

Approx. 37 – 39 µs

0 (00)

1 (01)

2 (10)

3 (11)

1

16

64

256

Approx. 149 – 155 µs

Approx. 597 – 620 µs

Exact timeout depends on crystal frequency.

In order to reduce start up time from the SLEEP state, this field is

preserved in powerdown (SLEEP state).

1:0 Reserved

R0

Defined on the transceiver version

0x22: FREND0 – Front end TX configuration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:4 LODIV_BUF_CURRENT_TX[1:0]

1 (01)

R/W

Adjusts current TX LO buffer (input to PA). The

value to use in this field is given by the SmartRF^®

Studio software.

3

Reserved

R0

2:0 PA_POWER[2:0]

0 (000)

R/W

Selects PA power setting. This value is an index to

the PATABLE, which can be programmed with up to

8 different PA settings. The PATABLE settings from

index ‘0’ to the PA_POWER value are used for

power ramp-up/ramp-down at the start/end of

transmission in all TX modulation formats.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 44 of 54

CC2550

0x23: FSCAL3 – Frequency synthesizer calibration

Bit Field Name

Reset

R/W

Description

7:6 FSCAL3[7:6]

2 (10)

R/W

Frequency synthesizer calibration configuration. The value to write

in this register before calibration is given by the SmartRF^®Studio

software.

5:4 CHP_CURR_CAL_EN[1:0]

3:0 FSCAL3[3:0]

2 (10)

R/W

Disable charge pump calibration stage when 0

9

Frequency synthesizer calibration result register.

(1001)

Fast frequency hopping without calibration for each hop can be

done by calibrating upfront for each frequency and saving the

resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between

each frequency hop, calibration can be replaced by writing the

FSCAL3, FSCAL2 and FSCAL1 register values corresponding to

the next RF frequency.

0x24: FSCAL2 – Frequency synthesizer calibration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:0 FSCAL2[5:0]

10

R/W

Frequency synthesizer calibration result register.

(0x0A)

Fast frequency hopping without calibration for each hop can be

done by calibrating upfront for each frequency and saving the

resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between

each frequency hop, calibration can be replaced by writing the

FSCAL3, FSCAL2 and FSCAL1 register values corresponding to

the next RF frequency.

0x25: FSCAL1 – Frequency synthesizer calibration

Bit Field Name

Reset

R/W

Description

7:6 Reserved

R0

5:0 FSCAL1[5:0]

32

R/W

Frequency synthesizer calibration result register.

(0x20)

Fast frequency hopping without calibration for each hop can be

done by calibrating upfront for each frequency and saving the

resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between

each frequency hop, calibration can be replaced by writing the

FSCAL3, FSCAL2 and FSCAL1 register values corresponding to

the next RF frequency.

0x26: FSCAL0 – Frequency synthesizer calibration

Bit Field Name

Reset

R/W

Description

7

Reserved

R0

6:5 Reserved

0 (00)

R0

Defined on the transceiver version

4:0 FSCAL0[4:0]

13

(0x0D)

R/W

Frequency synthesizer calibration control. The value to use in

register field is given by the SmartRF^®Studio software.

0x29: FSTEST – Frequency synthesizer calibration control

Bit Field Name

Reset

R/W Description

7:0 FSTEST[7:0]

87

R/W For test only. Do not write to this register.

(0x57)

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 45 of 54

CC2550

0x2A: PTEST – Production test

Bit Field Name

PTEST[7:0]

Reset

R/W Description

7

127

(0x7F)

R/W Writing 0xBF to this register makes the on-chip temperature sensor

available in the IDLE state. The default 0x7F value should then be

written back before leaving the IDLE state.

Other use of this register is for test only.

0x2C: TEST2 – Various test settings

Bit Field Name

Reset

R/W Description

The value to use in this register is given by the SmartRF^®Studio

software.

7:0 TEST2[7:0]

152

(0x98)

R/W

0x2D: TEST1 – Various test settings

Bit Field Name

Reset

R/W Description

The value to use in this register is given by the SmartRF^®

Studio software.

7:0 TEST1[7:0]

49 (0x31)

R/W

0x2E: TEST0 – Various test settings

Bit Field Name

Reset

R/W Description

The value to use in this register is given by the SmartRF^®

7:0 TEST0[7:0]

11 (0x0B)

R/W

Studio software.

27.2 Status register details

0x30 (0xF0): PARTNUM – Chip ID

Bit Field Name

Reset

130 (0x82)

R/W Description

Chip part number

7:0 PARTNUM[7:0]

R

0x31 (0xF1): VERSION – Chip ID

Bit Field Name

Reset

2 (0x02)

R/W Description

Chip version number.

7:0 VERSION[7:0]

R

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 46 of 54

CC2550

0x35 (0xF5): MARCSTATE – Main Radio Control State Machine state

Bit Field Name

Reset

R/W Description

7:5 Reserved

R0

4:0 MARC_STATE[4:0]

R

Main Radio Control FSM State

Value

State name

SLEEP

State (Figure 13, page 23)

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

SLEEP

IDLE

XOFF

VCOON_MC

REGON_MC

MANCAL

VCOON

MANCAL

FS_WAKEUP

CALIBRATE

SETTLING

CALIBRATE

NA

REGON

STARTCAL

BWBOOST

FS_LOCK

IFADCON

12 (0x0C) ENDCAL

13 (0x0D) NA

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

NA

FSTXON

TX

FSTXON

TX

TX_END

NA

TX

NA

TX_UNDERFLOW TX_UNDERFLOW

0x38 (0xF8): PKTSTATUS – Current GDOx status

Bit Field Name

Reset

R/W Description

7:2 Reserved

R0

R

Defined on the transceiver version

1

0

Reserved

GDO0

Current GDO0value. Note: the reading gives the non-

inverted value irrespective what IOCFG0.GDO0_INVis

programmed to.

It is not recommended to check for PLL lock by reading

PKTSTATUS[0]with GDO0_CFG= 0x0A.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 47 of 54

CC2550

0x39 (0xF9): VCO_VC_DAC – Current setting from PLL calibration module

Bit Field Name

Reset

R/W Description

R Status register for test only.

7:0 VCO_VC_DAC[7:0]

0x3A (0xFA): TXBYTES – Underflow and number of bytes

Bit Field Name

Reset

R/W Description

7

TXFIFO_UNDERFLOW

R

6:0 NUM_TXBYTES

R

Number of bytes in TX FIFO

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 48 of 54

CC2550

28

Package Description (QLP 16)

All dimensions are in millimetres, angles in degrees. NOTE: The CC2550 is available in RoHS

lead-free package only.

Figure 21: Package dimensions drawing (the actual package has 16 pins)

Package

type

A

A1

A2

D

D1

D2

E

E1

E2

L

T

b

e

Min

Typ.

Max

0.75

0.85

0.95

0.005

0.025

0.045

0.55

0.65

0.75

3.90

4.00

4.10

3.65

3.75

3.85

3.90

4.00

4.10

3.65

3.75

3.85

0.45

0.55

0.65

0.190

0.23

0.28

0.35

QLP 16 (4x4)

2.30

0.65

0.245

Table 27: Package dimensions

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 49 of 54

CC2550

28.1 Recommended PCB layout for package (QLP 16)

Figure 22: Recommended PCB layout for QLP 16 package

Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes

distributed symmetrically in the ground pad under the package. See also the CC2550EM

reference design.

28.2 Package thermal properties

Thermal resistance

Air velocity [m/s]

Rth,j-a [K/W]

0

40.1

Table 28: Thermal properties of QLP 16 package

28.3 Soldering information

The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed.

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 50 of 54

CC2550

28.4 Tray specification

CC2550 can be delivered in standard QLP 4x4 mm shipping trays.

Tray Specification

Package

QLP 16

Tray Width

125.9 mm

Tray Height

7.62 mm

Tray Length

322.6 mm

Units per Tray

490

Table 29: Tray specification

28.5 Carrier tape and reel specification

Carrier tape and reel is in accordance with EIA Specification 481.

Tape and Reel Specification

Package

Tape Width

Component

Pitch

Hole

Pitch

Reel

Diameter

Units per Reel

2500

QLP 16

12 mm

8 mm

4 mm

13 inches

Table 30: Carrier tape and reel specification

29

Ordering Information

Chipcon Part

Number

TI Part Number

Description

Minimum Order Quantity

(MOQ)

CC2550-RTY1

CC2550-RTR1

CC2500-CC2550DK

CC2550EMK

CC2550RTK

490 (tray)

CC2550 QLP16 RoHS Pb-free 490/tray

CC2550 QLP16 RoHS Pb-free 2500/T&R

CC2500_CC2550 Development Kit

CC2500 Evaluation Module Kit

CC2550RTKR

CC2500-CC2550DK

CC2550EMK

2500 (tape and reel)

1

Table 31: Ordering information

30

General Information

30.1 Document History

Revision Date

Description/Changes

Added figures to table on SPI interface timing requirements.

Added information about SPI read.

1.2

2006-06-28

Updates to text and included new figure in section on arbitrary length configuration.

Added information that RF frequencies at n/2·crystal frequency (n is an integer number)

should not be used due to spurious signals at these frequencies .

Updates to text and included new figures in section on power-on start-up sequence.

Added information about how to check for PLL lock in section on VCO.

Better explanation of some of the signals in table of GDO signal selection.

Added section on wideband modulation not using spread spectrum under section on

system considerations and guidelines.

Added more detailed information on PO_TIMEOUT in register MCSM0.

Changes to ordering information.

1.1

1.0

2005-06-27 Updated TEST1 register default value. 26-27 MHz crystal range. Added matching

information. Added information about using a reference signal instead of a crystal.

2005-01-24 First preliminary data sheet release.

Table 32: Document history

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 51 of 54

CC2550

30.2 Product Status Definitions

Data Sheet Identification

Product Status

Definition

Advance Information

Planned or Under

Development

This data sheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

Engineering Samples This data sheet contains preliminary data, and

and Pre-Production

Prototypes

supplementary data will be published at a later date.

Chipcon reserves the right to make changes at any

time without notice in order to improve design and

supply the best possible product. The product is not

yet fully qualified at this point.

No Identification Noted

Obsolete

Full Production

This data sheet contains the final specifications.

Chipcon reserves the right to make changes at any

time without notice in order to improve design and

supply the best possible product.

Not In Production

This data sheet contains specifications on a product

that has been discontinued by Chipcon. The data

sheet is printed for reference information only.

Table 33: Product status definitions

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 52 of 54

CC2550

31

Address Information

Texas Instruments Norway AS

Gaustadalléen 21

N-0349 Oslo

NORWAY

Tel: +47 22 95 85 44

Fax: +47 22 95 85 46

Web site: http://www.ti.com/lpw

32

TI Worldwide Technical Support

Internet

TI Semiconductor Product Information Center Home Page:

TI Semiconductor KnowledgeBase Home Page:

support.ti.com

support.ti.com/sc/knowledgebase

Product Information Centers

Americas

Phone:

+1(972) 644-5580

Fax:

+1(972) 927-6377

Internet/Email:

support.ti.com/sc/pic/americas.htm

Europe, Middle East and Africa

Phone:

Belgium (English)

Finland (English)

France

+32 (0) 27 45 54 32

+358 (0) 9 25173948

+33 (0) 1 30 70 11 64

+49 (0) 8161 80 33 11

180 949 0107

Germany

Israel (English)

Italy

800 79 11 37

Netherlands (English)

Russia

+31 (0) 546 87 95 45

+7 (4) 95 98 10 701

+34 902 35 40 28

Spain

Sweden (English)

United Kingdom

Fax:

+46 (0) 8587 555 22

+44 (0) 1604 66 33 99

+49 (0) 8161 80 2045

Internet:

support.ti.com/sc/pic/euro.htm

Japan

Fax

International

Domestic

+81-3-3344-5317

0120-81-0036

Internet/Email International

support.ti.com/sc/pic/japan.htm

www.tij.co.jp/pic

Domestic

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 53 of 54

CC2550

Asia

Phone

International

Domestic

Australia

China

+886-2-23786800

Toll-Free Number

1-800-999-084

800-820-8682

Hong Kong

India

800-96-5941

+91-80-51381665 (Toll)

001-803-8861-1006

080-551-2804

Indonesia

Korea

Malaysia

New Zealand

Philippines

Singapore

Taiwan

1-800-80-3973

0800-446-934

1-800-765-7404

800-886-1028

0800-006800

Thailand

001-800-886-0010

+886-2-2378-6808

tiasia@ti.com or ti-china@ti.com

support.ti.com/sc/pic/asia.htm

Fax

Email

Internet

PRELIMINARY Data Sheet (Rev.1.2)

SWRS039A

Page 54 of 54


型号：	CC2550
厂家：	TEXAS INSTRUMENTS
描述：	Single Chip Low Cost Low Power RF Transmitter 单芯片低成本低功耗射频发射器射频
文件：	总55页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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