CC2564CRVMR_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

CC2564C 双模 Bluetooth^®控制器

1 器件概述

1.1 特性

1

• TI 的单片蓝牙^®解决方案支持蓝牙基本速率 (BR)、

增强型数据速率 (EDR) 以及低功耗 (LE)；提供两种

型号：

先级处理

– 链路层拓扑散射网功能 - 可以同时作为外围设备

和中央设备

• 符合标准的蓝牙 4.2 组件（声明 ID：D032801）；

最高可兼容 HCI 层

– 最多支持 10 个器件的网络

– 最大程度提升通道利用率的时间线优化算法

• 针对尺寸受限和低成本设计进行了高度优化：

– 单端 50Ω 射频 (RF) 接口

• 最佳蓝牙 (RF) 性能（TX 功率、RX 灵敏度、阻

断）

– 封装尺寸：76 引脚，间距为 0.6

mm，8mm×8mm (VQFNP-MR)

• BR 和 EDR 特性包括：

– 最多可支持七个有源器件

– 第一类 TX 功率高达 +12dBm

– 内部温度检测和补偿，确保 RF 性能在温度范围

内变化最小，无需使用外部校准

– 适应时间最短的改进型自适应跳频 (AFH) 算法

– 散射网：支持多达三个微微网同时运行，其中一

个作为主网络，另外两个作为从网络

– 范围更大，涵盖其他仅提供低功耗模式的解决方

案范围的二倍

– 同一微微网中支持多达两条同步面向连接 (SCO)

链路

• 延长电池寿命并简化设计的高级电源管理

– 片上电源管理，包括直接连接电池

– 激活、待机和扫描蓝牙模式的功耗较低

– 可最大程度降低功耗的关断和休眠模式

• 物理接口：

– 支持所有语音空中编码 - 连续可变斜率增量

(CVSD) 编码、A 律编码、μ 律编码、改良型子带

编码 (mSBC) 以及透明编码（未编码）

– 为 HFP 1.6 宽带语音配置文件 (WBS) 或 A2DP

配置文件提供辅助模式，旨在降低主机处理负荷

和功耗

– 支持最高蓝牙数据速率的 UART 接口

– 最高速率为 4Mbps 的 UART 传输层 (H4)

– 最高速率为 4Mbps 的三线制 UART 传输层

– 以增强的 QoS 支持多种蓝牙配置文件

• 低耗能特性包括：

(H5)

– 完全可编程数字脉冲编码调制 (PCM) - 集成电路

内置音频总线 (I2S) 编解码器接口

• 支持在 MCU 和 MPU

– 多种嗅探实例紧密结合，最大程度降低功耗

– 针对低功耗模型进行独立缓冲，允许大量实施多

种不同连接，同时不影响 BR 或 EDR 性能

• CC256x 蓝牙硬件评估工具：

– 适用于 BR、EDR 和低功耗模式的内置共存和优

评估器件 RF 性能并配置服务包的 PC 应用程序

1.2 应用

•

无线音频解决方案

mPOS

•

穿戴式设备

传感器集线器，传感器网关

–

家庭与工厂自动化

医疗设备

机顶盒 (STB)

1.3 说明

TI CC2564C 器件是一款完备的 Bluetooth^®BR、EDR 和低功耗 HCI 解决方案，能够降低设计工作量并缩短

上市时间。基于 TI 第七代蓝牙核心，CC2564C 器件提供久经验证的解决方案，符合蓝牙 4.2 标准。当与微

控制器单元 (MCU) 结合使用时，该 HCI 器件可提供最佳 RF 性能，射频范围约为其他蓝牙低功耗解决方案

的两倍。此外，TI 的电源管理硬件和软件算法可显著降低所有常用蓝牙 BR、EDR 和低功耗运行模式的功

耗。

TI 双模蓝牙协议栈软件经认证并免收版税，适用于 MCU 和 MPU。 iPod (Mfi) 协议由^®附加软件包提供支

持。有关详细信息，请参见 TI 双模蓝牙协议栈。支持多种配置文件和示例应用，包括以下内容：

串行端口配置 (SPP)

高级音频分配配置 (A2DP)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SWRS199

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

音频/视频远程控制配置文件 (AVRCP)

免提配置文件 (HFP)

人机界面设备 (HID)

通用属性配置文件 (GATT)

多种蓝牙低功耗配置文件和服务

器件信息⁽¹⁾

封装

产品型号

封装尺寸

CC2564CRVM

RVM (76)

8.00mm × 8.00mm × 0.60mm

(1) 有关此类器件的详细信息，请参见节 9。

空白

）

1.4 功能框图

CC2564C

2.4-GHz

band-pass filter

Coprocessor

(See Note)

PCM-I2S

I/O

interface

Modem

arbitrator

DRP

BR/EDR

main processor

UART

HCI

Power

management

Clock

management

Power

Shutdown

Slow

clock

Fast

clock

Note: 以下技术和辅助模式无法与协处理器同时使用：蓝牙低功耗、HFP 1.6 (WBS) 辅助模式以及 A2DP 辅助模式每次仅可使

用一种技术或辅助模式。

图 1-1. 功能框图

2

器件概述

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

内容

1

器件概述.................................................... 1

6.1 Overview ............................................ 23

6.2 Functional Block Diagram........................... 23

6.3 Clock Inputs ......................................... 23

6.4 Functional Blocks.................................... 27

6.5 Bluetooth BR and EDR Features ................... 38

6.6 Bluetooth low energy Description ................... 39

6.7 Bluetooth Transport Layers ......................... 40

1.1 特性 ................................................... 1

1.2 应用 ................................................... 1

1.3 说明 ................................................... 1

1.4 功能框图 .............................................. 2

修订历史记录............................................... 3

Device Comparison ..................................... 4

3.1 Related Products ..................................... 4

Terminal Configuration and Functions ............. 5

4.1 VQFN-MR Pin Diagram............................... 5

Specifications ............................................ 8

5.1 Absolute Maximum Ratings .......................... 8

5.2 ESD Ratings.......................................... 8

5.3 Power-On Hours...................................... 8

5.4 Recommended Operating Conditions ................ 9

5.5 Power Consumption Summary ....................... 9

5.6 Electrical Characteristics............................ 11

2

3

6.8

Changes from the CC2564B Device to the

CC2564C Device.................................... 40

4

5

7

8

Applications, Implementation, and Layout........ 41

7.1

Reference Design Schematics and BOM for Power

and Radio Connections ............................. 41

7.2 PCB Layout Guidelines ............................. 43

器件和文档支持 .......................................... 47

8.1 Third-Party Products Disclaimer .................... 47

8.2 工具与软件 .......................................... 47

8.3 器件命名规则 ........................................ 47

8.4 Community Resources.............................. 47

8.5 商标.................................................. 48

8.6 静电放电警告 ........................................ 48

8.7 Glossary ............................................. 48

机械、封装和可订购信息................................ 49

5.7

Thermal Resistance Characteristics for VQFN-MR

(RVM) Package .................................... 11

5.8 Timing and Switching Characteristics............... 12

6

Detailed Description ................................... 23

9

2 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from April 8, 2016 to October 27, 2016

Page

•

已将文档状态更新至“量产数据” ..................................................................................................... 1

修订历史记录

3

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

3 Device Comparison

Table 3-1 lists the features of the CC2564C device.

Table 3-1. CC2564C Device Features

ASSISTED MODES

SUPPORTED⁽¹⁾

TECHNOLOGY SUPPORTED

DEVICE

DESCRIPTION

LOW

HFP 1.6

BR, EDR

A2DP

ENERGY

(WBS)

CC2564C

Bluetooth 4.2 + Bluetooth low energy

√

(1) The assisted modes (HFP 1.6 and A2DP) are not supported simultaneously. Furthermore, the assisted modes are not supported

simultaneously with Bluetooth low energy.

3.1 Related Products

Wireless Connectivity The wireless connectivity portfolio offers a wide selection of low-power RF

solutions suitable for a broad range of application. The offerings range from fully customized

solutions to turnkey offerings with precertified hardware and software (protocol).

Companion Products Review products that are frequently purchased or used with the CC2564C product.

Reference Designs for CC2564 The TI Designs Reference Design Library is a robust reference design

library spanning analog, embedded processor, and connectivity. Created by TI experts to

help you jump-start your system design, all TI Designs include schematic or block diagrams,

BOMs and design files to speed your time to market. Search and download designs at

ti.com/tidesigns.

4

Device Comparison

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

4 Terminal Configuration and Functions

4.1 VQFN-MR Pin Diagram

Figure 4-1 shows the bottom view of the pin diagram (VQFN-MR package).

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

DIG_LDO_OUT

HCI_CTS

DIG_LDO_OUT

VSS

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

B27

B26

B25

B24

B23

B22

B21

B20

B19

B1

B2

B3

B4

B5

B6

B7

B8

SRAM_LDO_OUT

DIG_LDO_OUT

MLDO_OUT

DIG_LDO_OUT

VSS_FREF

VDD_IO

NC

XTALM/FREFM

XTALP/FREFP

MLDO_OUT

TX_DBG

HCI_RX

NC

MLDO_IN

SLOW_CLK

VDD_IO

VSS

nSHUTD

CL1.5_LDO_IN

CL1.5_LDO_OUT

MLDO_OUT

VDD_IO

NC

ADC_PPA_LDO_OUT

BT_RF

NC

MLDO_OUT

VDD_IO

NC

B9

NC

SWRS121-002

Figure 4-1. VQFN-MR Package Pin Diagram

Bottom View

Terminal Configuration and Functions

5

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

4.1.1 Pin Attributes (VQFN-MR Package)

Table 4-1 describes the pin attributes for the VQFN-MR package.

SPACER

Table 4-1. Pin Attributes (VQFN-MR Package)

PULL AT

RESET

DEF.

I/O

NAME

NO.

DESCRIPTION

DIR.⁽¹⁾

Type⁽²⁾

I/O Signals

HY, 4

mA

AUD_CLK

B32

PD

I/O

PCM clock

Fail-safe

AUD_FSYNC

AUD_IN

A35

B34

B33

PD

I/O

I

4 mA

PCM frame-sync signal

PCM data input

Fail-safe

AUD_OUT

O

PCM data output

HCI UART clear-to-send

HCI_CTS

HCI_RX

A29

A26

PU

I

8 mA

The device is allowed to send data

when HCI_CTS is low.

HCI universal asynchronous

receiver/transmitter (UART) data

receive

HCI UART request-to-send

The host is allowed to send data when

HCI_RTS is low.

HCI_RTS

HCI_TX

A32

A33

B24

PU

O

8 mA

2 mA

HCI UART data transmit

TI internal debug messages. TI

recommends leaving an internal test

point.

TX_DBG

Clock Signals

SLOW_CLK

A25

B4

I

32.768-kHz clock in

Fail-safe

Fast clock in analog (sine wave)

Output terminal of fast-clock crystal

XTALP/FREFP

XTALM/FREFM

Fast clock in digital (square wave)

Input terminal of fast-clock crystal

A4

I

Fail-safe

Analog Signals

BT_RF

B8

A6

I/O

I

Bluetooth RF I/O

nSHUTD

PD

Shutdown input (active low)

Power and Ground Signals

ADC_PPA_LDO_OUT

A8

B6

O

I

ADC/PPA LDO output

Power amplifier (PA) LDO input

Connect directly to battery

CL1.5_LDO_IN

CL1.5_LDO_OUT

DCO_LDO_OUT

A7

O

PA LDO output

A12

DCO LDO output

A2, A3,

B15,

B26,

B27,

B35, B36

Digital LDO output

QFN pin B26 or B27 must be shorted

to other DIG_LDO_OUT pins on the

PCB.

DIG_LDO_OUT

O

Main LDO input

Connect directly to battery

MLDO_IN

B5

I

A5, A9,

B2, B7

MLDO_OUT

I/O

O

Main LDO output (1.8-V nominal)

SRAM LDO output

SRAM_LDO_OUT

B1

(1) I = input; O = output; I/O = bidirectional

(2) I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current

6

Terminal Configuration and Functions

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

Table 4-1. Pin Attributes (VQFN-MR Package) (continued)

PULL AT

RESET

DEF.

I/O

NAME

NO.

DESCRIPTION

DIR.⁽¹⁾

Type⁽²⁾

A17,

A34,

A38,

VDD_IO

B18,

I

I/O power supply (1.8-V nominal)

B19,

B21,

B22, B25

VSS

A24, A28

B11

I

Ground

VSS_DCO

VSS_FREF

DCO ground

Fast clock ground

B3

4.1.2 Connections for Unused Signals (VQFN-MR Package)

Section 4.1.2 lists the connections for unused signals for the VQFN-MR package.

SPACER

FUNCTION

PIN NUMBER

DESCRIPTION

NC

A1

Not connected

TI internal use

A10

A11

A14

A18

A19

A20

A21

A22

A23

A27

A30

A31

A40

B9

B10

B16

B17

B20

B23

A13

A15

A16

A36

A37

A39

B12

B13

B14

B29

B30

B31

B28

Terminal Configuration and Functions

7

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5 Specifications

Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board

(EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated.

5.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise indicated). All parameters are measured as follows:

VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated).

MIN

–0.5

MAX

UNIT

V⁽²⁾

V

VDD_IN

4.8

Supply voltage

VDDIO_1.8 V

2.145

Input voltage to analog pins⁽³⁾

Input voltage to all other pins

Bluetooth RF inputs

2.1

V

VDD_IO + 0.5

V

10

85

dBm

°C

(4)

Operating ambient temperature, T_A

Storage temperature, T_stg

–40

–55

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 7.1.

(3) Analog pins: BT_RF, XTALP, and XTALM

(4) The reference design supports a temperature range of –20°C to +70°C because of the operating conditions of the crystal.

5.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Power-On Hours

DEVICE

CONDITIONS

POWER-ON HOURS

15,400 (7 years)

Duty cycle = 25% active and 75% sleep

T_ambient= 85ºC

CC2564C

8

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

5.4 Recommended Operating Conditions

MIN

MAX

4.8

UNIT

VDD_IN

VDD_IO

V_IH

Power supply voltage

I/O power supply voltage

High-level input voltage

Low-level input voltage

1.7

V

1.62

0.65 × VDD_IO

0

1.92

Default condition

VDD_IO

V_IL

0.35 × VDD_IO

I/O input rise and all times,

10% to 90%—asynchronous mode

t_rand t_f

1

10

ns

I/O input rise and fall times,

10% to 90%—synchronous mode (PCM)

2.5

Condition: 0 to 0.1 MHz

Condition: 0.1 to 0.5 MHz

Condition: 0.5 to 2.5 MHz

Condition: 2.5 to 3.0 MHz

Condition: > 3.0 MHz

60

50

30

15

5

Maximum ripple on VDD_IN (sine wave) for

1.8 V (DC-DC) mode

mV_p-p

Voltage dips on VDD_IN (VBAT)

Duration = 577 µs to 2.31 ms, period = 4.6 ms

Maximum ambient operating temperature⁽¹⁾

400

85

mV

°C

(2)

–40

(1) The device can be reliably operated for 7 years at T_ambientof 85°C, assuming 25% active mode and 75% sleep mode (15,400

cumulative active power-on hours).

(2) A crystal-based solution is limited by the temperature range required for the crystal to meet 20 ppm.

5.5 Power Consumption Summary

5.5.1 Static Current Consumption

OPERATIONAL MODE

MIN

TYP

1

MAX

7

UNIT

Shutdown mode⁽¹⁾

Deep sleep mode⁽²⁾

µA

40

105

1

Total I/O current consumption in active mode

Continuous transmission—GFSK⁽³⁾

Continuous transmission—EDR⁽⁴⁾⁽⁵⁾

mA

107

112.5

(1) VBAT + VIO + V_SHUTDOWN

(2) VBAT + VIO

(3) At maximum output power dBm

(4) At maximum output power dBm

(5) Both π/4 DQPSK and 8DPSK

Specifications

9

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.5.2 Dynamic Current Consumption

5.5.2.1 Current Consumption for Different Bluetooth BR and EDR Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 10-dBm output power

OPERATIONAL MODE

MASTER AND SLAVE

Master and slave

AVERAGE CURRENT

UNIT

mA

µA

SCO link HV3

13.7

13.2

10

Extended SCO (eSCO) link EV3 64 kbps, no retransmission

eSCO link 2-EV3 64 kbps, no retransmission

GFSK full throughput: TX = DH1, RX = DH5

EDR full throughput: TX = 2-DH1, RX = 2-DH5

EDR full throughput: TX = 3-DH1, RX = 3-DH5

Sniff, four attempts, 1.28 seconds

40.5

41.2

145

320

Page or inquiry scan 1.28 seconds, 11.25 ms

µA

Page (1.28 seconds) and inquiry (2.56 seconds) scans,

11.25 ms

Master and slave

445

µA

A2DP source

Master

13.9

15.2

16.9

18.1

mA

A2DP sink

Assisted A2DP source

Assisted A2DP sink

Assisted WBS EV3; retransmit effort = 2;

maximum latency = 8 ms

Master and slave

17.5 and 18.5

11.9 and 13

mA

Assisted WBS 2EV3; retransmit effort = 2;

maximum latency = 12 ms

5.5.2.2 Current Consumption for Different Low-Energy Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, nominal unit, 10-dBm output power

AVERAGE

CURRENT

MODE

DESCRIPTION

UNIT

Advertising in all three channels

1.28-seconds advertising interval

15 bytes advertise data

Advertising, nonconnectable

114

µA

Advertising in all three channels

1.28-seconds advertising interval

15 bytes advertise data

Advertising, discoverable

Scanning

138

324

µA

Listening to a single frequency per window

1.28-seconds scan interval

11.25-ms scan window

Master role

Slave role

500-ms connection interval

0-ms slave connection latency

Empty TX and RX LL packets

169

199

Connected

10

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

5.6 Electrical Characteristics

RATING

CONDITION

At 2, 4, 8 mA

MIN

MAX

VDD_IO

UNIT

0.8 × VDD_IO

High-level output voltage, V_OH

Low-level output voltage, V_OL

V

At 0.1 mA

VDD_IO – 0.2

VDD_IO

At 2, 4, 8 mA

At 0.1 mA

0

1

0.2 × VDD_IO

0.2

V

Resistance

Capacitance

C_L= 20 pF

Typical = 6.5

Typical = 27

Typical = 100

MΩ

pF

ns

I/O input impedance

5

10

Output rise and fall times, 10% to 90% (digital pins)

PU

PD

PU

PD

3.5

9.5

50

9.7

55

PCM–I2S bus, TX_DBG

I/O pull

µA

currents

300

360

All others

50

5.7 Thermal Resistance Characteristics for VQFN-MR (RVM) Package

over operating free-air temperature range (unless otherwise noted)

THERMAL METRICS⁽¹⁾

C/W⁽²⁾

Rθ_ja

Junction-to-free-air

34.6

17.9

1.6

Rθ_jctop

Rθ_jcbottom

Rθ_jb

Junction-to-case-top

Junction-to-case-bottom

Junction-to-board

12.0

0.2

φ_jt

Junction-to-package-top

Junction-to-package-bottom

φ_jb

12.0

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.

Specifications

11

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.8 Timing and Switching Characteristics

5.8.1 Device Power Supply

The CC2564C power-management hardware and software algorithms provide significant power savings,

which is a critical parameter in an MCU-based system.

The power-management module is optimized for drawing extremely low currents.

5.8.1.1 Power Sources

The CC2564C device requires two power sources:

•

VDD_IN: main power supply for the device

VDD_IO: power source for the 1.8-V I/O ring

The HCI module includes several on-chip voltage regulators for increased noise immunity and can be

connected directly to the battery.

5.8.1.2 Device Power-Up and Power-Down Sequencing

The device includes the following power-up requirements (see Figure 5-1):

•

nSHUTD must be low. VDD_IN and VDD_IO are don't care I/O pins when nSHUTD is low. However,

signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe.

Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages

with no VDD_IO and VDD_IN.

•

VDD_IO and VDD_IN must be stable before releasing nSHUTD.

The fast clock must be stable within 20 ms of nSHUTD going high.

The slow clock must be stable within 2 ms of nSHUTD going high.

The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to

100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case,

ensure that the sequence and requirements are met.

12

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

Shut down

before

VDD_IO

removed

20 µs max

nSHUTD

VDD_IO

VDD_IN

2 ms max

SLOW CLOCK

20 ms max

FAST CLOCK

HCI_RTS

ꢀ00 ms

CC256x ready

Figure 5-1. Power-Up and Power-Down Sequencing

5.8.1.3 Power Supplies and Shutdown—Static States

The nSHUTD signal puts the device in ultra-low-power mode and performs an internal reset to the device.

The rise time for nSHUTD must not exceed 20 µs; nSHUTD must be low for a minimum of 5 ms.

To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during

shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as

described in Section 4.1.1. Table 5-1 lists and describes the static operation states.

Table 5-1. Power Modes

(1)

VDD_IN

VDD_IO⁽¹⁾

nSHUTD⁽¹⁾

PM_MODE

COMMENTS

I/O state is undefined. No I/O voltages

are allowed on nonfail-safe pins.

1

2

3

None

Asserted

Shutdown

I/O state is undefined. No I/O voltages

are allowed on nonfail-safe pins.

None

Deasserted

Asserted

Not allowed

Shutdown

I/Os are defined as tri-state pins with

internal pullup or pulldown enabled.

Present

I/O state is undefined. No I/O voltages

are allowed on nonfail-safe pins.

4

5

6

None

Present

None

Deasserted

Asserted

Not allowed

Shutdown

Present

I/O state is undefined.

I/O state is undefined. No I/O voltages

are allowed on nonfail-safe pins.

None

Deasserted

Not allowed

I/Os are defined as tri-state pins with

internal pullup or pulldown enabled.

7

8

Present

Asserted

Shutdown

Active

Deasserted

See Section 5.8.1.4.

(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a

pulldown resistor, or left NC or floating (high-impedance output stage).

Specifications

13

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.8.1.4 I/O States in Various Power Modes

CAUTION

Some device I/Os are not fail-safe (see Section 4.1.1). Fail-safe means that the

pins do not draw current from an external voltage applied to the pin when I/O

power is not supplied to the device. External voltages are not allowed on these

I/O pins when the I/O supply voltage is not supplied because of possible

damage to the device.

Table 5-2 lists the I/O states in various power modes.

Table 5-2. I/O States in Various Power Modes

SHUTDOWN⁽¹⁾

DEFAULT ACTIVE⁽¹⁾

I/O State Pull

DEEP SLEEP⁽¹⁾

I/O NAME

HCI_RX

I/O State

Pull

PU

PD

PU

I/O State

Pull

Z

I

PU

I

O

I

PU

HCI_TX

O-H

HCI_RTS

HCI_CTS

AUD_CLK

AUD_FSYNC

AUD_IN

O-H

I

PU

PD

PU

PD

I

AUD_OUT

TX_DBG

Z

O

Z

(1) I = input, O = output, Z = Hi-Z, – = no pull, PU = pullup, PD = pulldown, H = high, L = low

5.8.1.5 nSHUTD Requirements

PARAMETER

MIN

1.42

0

MAX

1.98

0.4

UNIT

(1)

V_IH

V_IL

Operation mode level

Shutdown mode level

V

(1)

Minimum time for nSHUT_DOWN low to reset the device

Rise and fall times

5

ms

µs

t_rand t_f

20

(1) An internal pulldown retains shutdown mode when no external signal is applied to this pin.

14

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

5.8.2 Clock Specifications

5.8.2.1 Slow Clock Requirements

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the

host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The

accuracy of the slow-clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the

Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms)

following the release of nSHUTD.

space

CHARACTERISTICS

CONDITION

MIN

TYP

MAX

UNIT

Input slow-clock frequency

32768

Hz

Input slow-clock accuracy

(Initial + temp + aging)

Bluetooth

±250

200

ppm

ns

Input transition time t_rand t_f

(10% to 90%)

t_rand t_f

Frequency input duty cycle

15%

50%

85%

VDD_IO

V_IH

V_IL

0.65 × VDD_IO

V peak

MΩ

Square wave,

DC-coupled

Slow-clock input voltage limits

0

1

0.35 × VDD_IO

Input impedance

Input capacitance

5

pF

5.8.2.2 External Fast Clock Crystal Requirements and Operation

space

CHARACTERISTICS

CONDITION

MIN

TYP

MAX

UNIT

f_in

Supported crystal frequencies

26, 38.4

MHz

Frequency accuracy

(Initial + temperature + aging)

±20

ppm

26 MHz, external capacitance = 8 pF

I_osc= 0.5 mA

650

490

940

710

Crystal oscillator negative resistance

Ω

26 MHz, external capacitance = 20 pF

I_osc= 2.2 mA

Specifications

15

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.8.2.3 Fast Clock Source Requirements (–40°C to +85°C)

space

CHARACTERISTICS

Supported frequencies, F_REF

Reference frequency accuracy

CONDITION

MIN

TYP

MAX

UNIT

MHz

ppm

V

26, 38.4

Initial + temp + aging

±20

0.37

2.1

V_IL

V_IH

–0.2

1.0

0.4

0.0

Square wave, DC-coupled

V

Fast-clock input voltage limits

Sine wave, AC-coupled

Sine wave, DC-coupled

1.6

V_p-p

V

1.6

Sine wave input limits, DC-coupled

1.6

Fast-clock input rise time

(as % of clock period)

Square wave, DC-coupled

10%

Duty cycle

35%

50%

65%

–123.4

–133.4

–138.4

@ offset = 1 kHz

@ offset = 10 kHz

@ offset = 100 kHz

Phase noise for 26 MHz

dBc/Hz

5.8.3 Peripherals

5.8.3.1 UART

Figure 5-2 shows the UART timing diagram.

HCI_RTS

t1

t2

t6

HCI_RX

HCI_CTS

t3

t4

HCI_TX

Start bit

Stop bit

10 bits

td_uart_swrs064

Figure 5-2. UART Timing

Table 5-3 lists the UART timing characteristics.

Table 5-3. UART Timing Characteristics

SYMBOL

CHARACTERISTICS

CONDITION

MIN

37.5

TYP

MAX UNIT

Baud rate

4000

1.5%

kbps

Baud rate accuracy per byte

Baud rate accuracy per bit

RTS low to RX_DATA on

RTS high to RX_DATA off

CTS low to TX_DATA on

CTS high to TX_DATA off

CTS-high pulse width

Receive and transmit

–2.5%

–12.5%

0

Receive and transmit

Interrupt set to 1/4 FIFO

Hardware flow control

12.5%

t1

t2

t3

t4

t6

2

µs

byte

µs

16

1

0

1

byte

bit

16

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

Figure 5-3 shows the UART data frame.

tb

TX

STR

D0

D1

Dn

PAR

STP

D2

td_uart_swrs064

Figure 5-3. Data Frame

Table 5-4 describes the symbols used in Figure 5-3.

Table 5-4. Data Frame Key

SYMBOL

STR

DESCRIPTION

Start bit

D0...Dn

PAR

Data bits (LSB first)

Parity bit (optional)

Stop bit

STP

5.8.3.2 PCM

Figure 5-4 shows the interface timing for the PCM.

T_clk

T_w

AUD_CLK

t_is

t_ih

AUD_IN / FSYNC_IN

t_op

AUD_OUT / FSYNC_OUT

td_aud_swrs064

Figure 5-4. PCM Interface Timing

Table 5-5 lists the associated PCM master parameters.

Table 5-5. PCM Master

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

244.14

(4.096 MHz)

15625

(64 kHz)

t_clk

Cycle time

ns

t_w

t_is

High or low pulse width

AUD_IN setup time

50% of T_clkmin

ns

25

0

t_ih

AUD_IN hold time

t_op

AUD_OUT propagation time

FSYNC_OUT propagation time

40-pF load

0

10

0

Specifications

17

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

Table 5-6 lists the associated PCM slave parameters.

Table 5-6. PCM Slave

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

66.67

(15 MHz)

t_clk

Cycle time

ns

t_w

T_is

t_ih

High or low pulse width

AUD_IN setup time

40% of T_clk

ns

8

0

8

0

AUD_IN hold time

t_is

AUD_FSYNC setup time

AUD_FSYNC hold time

AUD_OUT propagation time

t_ih

t_op

40-pF load

21

18

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

5.8.4 RF Performance

5.8.4.1 Bluetooth BR and EDR RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and

38.4-MHz TCXO.

5.8.4.1.1 Bluetooth Receiver—In-Band Signals

BLUETOOTH

SPECIFICATION

CHARACTERISTICS

CONDITION

MIN

TYP

MAX

UNIT

Operation frequency range

Channel spacing

2402

2480

MHz

Ω

1

50

Input impedance

GFSK, BER = 0.1%

–91.5

–90.5

–81

–95

–70

Sensitivity, dirty TX on⁽¹⁾

π/4-DQPSK, BER = 0.01%

8DPSK, BER = 0.01%

π/4-DQPSK

–94.5

–87.5

1E–7

dBm

–70

1E–6

–5

1E–5

–20

BER error floor at sensitivity +

10 dB, dirty TX off

8DPSK

GFSK, BER = 0.1%

π/4-DQPSK, BER = 0.1%

8DPSK, BER = 0.1%

Level of interferers (for n = 3, 4, and 5)

GFSK, cochannel

Maximum usable input power

Intermodulation characteristics

–10

dBm

–10

–36

–30

8

–39

11

10

11

π/4-DQPSK

9.5

13

EDR, cochannel

8DPSK

16.5

–10

–5

20

21

GFSK, adjacent ±1 MHz

EDR, adjacent ±1 MHz, (image)

GFSK, adjacent +2 MHz

EDR, adjacent, +2 MHz

GFSK, adjacent –2 MHz

EDR, adjacent –2 MHz

GFSK, adjacent ≥ |±3| MHz

EDR, adjacent ≥ |±3| MHz

–5

0

π/4-DQPSK

–5

0

8DPSK

–1

5

–38

–28

–22

–45

–44

–10

–63

–35

–30

–20

–13

–43

–36

–30

–25

–20

–13

–40

–33

C/I performance⁽²⁾

Image = –1 MHz

π/4-DQPSK

dB

8DPSK

π/4-DQPSK

8DPSK

π/4-DQPSK

8DPSK

RF return loss

dB

RX mode LO leakage

Frf = (received RF – 0.6 MHz)

–58

dBm

(1) Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast

clock.

(2) Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance.

5.8.4.1.2 Bluetooth Receiver—General Blocking

CHARACTERISTICS

CONDITION

30 to 2000 MHz

MIN

TYP

–6

UNIT

2000 to 2399 MHz

2484 to 3000 MHz

3 to 12.75 GHz

–6

Blocking performance over full range, according to Bluetooth

specification

dBm

(1)

–6

(1) Exceptions are taken out of the total 24 allowed in the Bluetooth specification.

Submit Documentation Feedback

Product Folder Links: CC2564C

Specifications

19

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.8.4.1.3 Bluetooth Transmitter—GFSK

BLUETOOTH

SPECIFICATION

CHARACTERISTICS

MIN

TYP

MAX

UNIT

VDD_IN = VBAT

12

10

Maximum RF output

power⁽¹⁾

dBm

VDD_IN = external regulator to 1.8 V

Power variation over Bluetooth band

Gain control range

–1

1

dB

30

5

Power control step

2 to 8

≤ –20

≤ –40

dB

Adjacent channel power |M–N| = 2

Adjacent channel power |M–N| > 2

–45

–50

dBm

(1) To modify maximum output power, use an HCI VS command.

5.8.4.1.4 Bluetooth Transmitter—EDR

BLUETOOTH

SPECIFICATION

CHARACTERISTICS

MIN

TYP

MAX

UNIT

VDD_IN = VBAT

5.5

π/4-DQPSK

VDD_IN = external regulator to 1.8 V

VDD_IN = VBAT

EDR output

power⁽¹⁾

dBm

8DPSK

VDD_IN = external regulator to 1.8 V

EDR relative power

–2

–1

1

–4 to +1

dB

Power variation over Bluetooth band

Gain control range

1

30

5

dB

Power control step

2 to 8

≤ –26

≤ –20

≤ –40

dB

Adjacent channel power |M–N| = 1

Adjacent channel power |M–N| = 2

Adjacent channel power |M–N| > 2

–36

–30

–42

dBc

dBm

(1) To modify maximum output power, use an NCI VS command.

5.8.4.1.5 Bluetooth Modulation—GFSK

BLUETOOTH

SPECIFICATION

CHARACTERISTICS

CONDITION

MIN

TYP MAX

UNIT

–20-dB bandwidth

GFSK

925

≤ 1000

kHz

Mod data = 4 1 s,

4 0 s:

111100001111...

F1 avg

F2 max

Δf1avg

165

130

140 to 175

kHz

Modulation characteristics

Δf2max ≥ limit for at

least 99.9% of all

Δf2max

Mod data = 1010101...

> 115

Δf2avg, Δf1avg

DH1

88%

25

> 80%

< ±25

< ±40

< 20

–25

–35

Absolute carrier frequency

drift

kHz

DH3 and DH5

35

Drift rate

15

kHz/50 µs

kHz

Initial carrier frequency

tolerance

f0–fTX

–75

+75

< ±75

20

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

5.8.4.1.6 Bluetooth Modulation—EDR

BLUETOOTH

SPECIFICATION

CHARACTERISTICS

CONDITION

MIN

TYP

MAX

UNIT

Carrier frequency stability

±5

≤ 10

±75

kHz

Initial carrier frequency tolerance

±75

π/4-DQPSK

6%

20%

13%

30%

20%

35%

25%

(1)

RMS DEVM

8DPSK

π/4-DQPSK

8DPSK

30%

20%

99% DEVM⁽¹⁾

π/4-DQPSK

8DPSK

14%

16%

(1)

Peak DEVM

(1) Maximum performance refers to maximum TX power.

5.8.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions

CHARACTERISTICS

Second harmonic⁽¹⁾

Third harmonic⁽¹⁾

CONDITION

TYP

MAX

–2

UNIT

–14

–10

–19

dBm

Measured at maximum output power

–6

Fourth harmonics⁽¹⁾

–11

(1) Meets FCC and ETSI requirements with external filter shown in Figure 7-1.

5.8.4.2 Bluetooth low energy RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL and a

38.4-MHz TCXO.

5.8.4.2.1 Bluetooth low energy Receiver—In-Band Signals

BLUETOOTH

CHARACTERISTIC

CONDITION

MIN

TYP

MAX

low energy

UNIT

SPECIFICATION

Operation frequency range

Channel spacing

2402

2480

MHz

Ω

2

50

Input impedance

Sensitivity, dirty TX on⁽¹⁾

PER = 30.8%; dirty TX on

GMSK, PER = 30.8%

–96

≤ –70

≥ –10

dBm

Maximum usable input power

–5

Level of interferers

(for n = 3, 4, 5)

Intermodulation characteristics

–30

≥ –50

dBm

GMSK, cochannel

8

–5

≤ 21

≤ 15

GMSK, adjacent ±1 MHz

GMSK, adjacent +2 MHz

GMSK, adjacent –2 MHz

GMSK, adjacent ≥ |±3| MHz

Frf = (received RF – 0.6 MHz)

C/I performance⁽²⁾

Image = –1 MHz

–45

–22

–47

–63

≤ –17

≤ –15

≤ –27

dB

RX mode LO leakage

dBm

(1) Sensitivity degradation up to 3 dB may occur where the Bluetooth low energy frequency is a harmonic of the fast clock.

(2) Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance.

Specifications

21

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

5.8.4.2.2 Bluetooth low energy Receiver—General Blocking

BLUETOOTH

low energy

SPECIFICATION

CHARACTERISTICS

CONDITION

30 to 2000 MHz

MIN

TYP

UNIT

–15

≥ –30

≥ –35

≥ –30

Blocking performance over full

range, according to Bluetooth

low energy specification⁽¹⁾

2000 to 2399 MHz

2484 to 3000 MHz

3 to 12.75 GHz

dBm

(1) Exceptions are taken out of the total 10 allowed in the Bluetooth low energy specification.

5.8.4.2.3 Bluetooth low energy Transmitter

BLUETOOTH

CHARACTERISTICS

MIN

TYP

MAX

low energy

UNIT

SPECIFICATION

VDD_IN = VBAT

12⁽¹⁾

10

≤10

RF output power

dBm

VDD_IN = External regulator to 1.8 V

Power variation over Bluetooth low energy band

Adjacent channel power |M-N| = 2

1

dB

–45

–50

≤ –20

≤ –30

dBm

Adjacent channel power |M-N| > 2

(1) To achieve the Bluetooth low energy specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and

the antenna. Otherwise, use an HCI VS command to modify the output power.

5.8.4.2.4 Bluetooth low energy Modulation

BLUETOOTH

CHARACTERISTICS

CONDITION

Mod data = 4 1s, 4 0 s:

MIN

240

185

TYP MAX

low energy

SPECIFICATION

UNIT

kHz

Δf1 avg

Δf1avg

250

260

225 to 275

1111000011110000...

Modulation

Δf2max ≥ limit for at

least 99.9% of all

Δf2max

characteristics

Mod data = 1010101...

210

0.9

≥ 185

kHz

Δf2 max

Δf2avg, Δf1avg

0.85

–25

≥ 0.8

≤ ±50

≤ 20

Absolute carrier

frequency drift

25

15

kHz

Drift rate

kHz/50 ms

Initial carrier

frequency

tolerance

–75

75

≤ ±100

kHz

5.8.4.2.5 Bluetooth low energy Transceiver, Out-Of-Band and Spurious Emissions

CHARACTERISTICS

Second harmonic⁽¹⁾

Third harmonic⁽¹⁾

CONDITION

TYP

–14

–10

–19

MAX

–2

UNIT

dBm

Measured at maximum output power

–6

Fourth harmonics⁽¹⁾

–11

(1) Meets FCC and ETSI requirements with external filter shown in Figure 7-1.

22

Specifications

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

6 Detailed Description

6.1 Overview

The CC2564C architecture comprises a DRP and a point-to-multipoint baseband core. The architecture is

based on a single-processor ARM7TDMI^®core. The device includes several on-chip peripherals to enable

easy communication with a host system and the Bluetooth BR, EDR, and low energy core.

6.2 Functional Block Diagram

CC2564C

2.4-GHz

band-pass filter

Coprocessor

(See Note)

PCM-I2S

I/O

interface

Modem

arbitrator

DRP

BR/EDR

main processor

UART

HCI

Power

management

Clock

management

Power

Shutdown

Slow

clock

Fast

clock

NOTE: The following technologies and assisted modes cannot be used simultaneously with the coprocessor: Bluetooth low

energy, assisted HFP 1.6 (WBS), and assisted A2DP. Only one technology or assisted mode can be used at a time.

Figure 6-1. CC2564C Functional Block Diagram

6.3 Clock Inputs

This section describes the available clock inputs. For specifications, see Section 5.8.2.

6.3.1 Slow Clock

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the

host or external crystal oscillator). The source must be a digital signal in the range of 0 V to 1.8 V. The

accuracy of the slow-clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the

Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms)

following the release of nSHUTD.

6.3.2 Fast Clock Using External Clock Source

An external clock source is fed to an internal pulse-shaping cell to provide the fast-clock signal for the

device. The device incorporates an internal, automatic clock-scheme detection mechanism that

automatically detects the fast-clock scheme used and configures the FREF cell accordingly. This

mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static

regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used.

The frequency variation of the fast-clock source must not exceed ±20 ppm (as defined by the Bluetooth

specification).

The external clock can be AC- or DC-coupled, sine or square wave.

Detailed Description

23

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

6.3.2.1 External F_REFDC-Coupled

Figure 6-2 and Figure 6-3 show the clock configuration when using a square wave, DC-coupled external

source for the fast-clock input.

NOTE

A shunt capacitor with a range of 10 nF must be added on the oscillator output to reject high

harmonics and shape the signal to be close to a sinusoidal waveform.

TI recommends using only a dedicated LDO to feed the oscillator. Do not use the same VIO

for the oscillator and the CC2564C device.

FREFP

CC2564C

FREFM

Figure 6-2. Clock Configuration (Square Wave, DC-Coupled)

V_Fref[V]

2.1

V_{high_min}

1.0

V_{low_max}

0.37

–0.2

t

clksqtd_wrs064

Figure 6-3. External Fast Clock (Square Wave, DC-Coupled)

Figure 6-4 and Figure 6-5 show the clock configuration when using a sine wave, DC-coupled external

source for the fast clock input.

FREFP

CC2564C

FREFM

VDD_IO

Figure 6-4. Clock Configuration (Sine Wave, DC-Coupled)

24

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

V_IN

1.6 V

VPP = 0.4 – 1.6 Vp-p

V_dc= 0.2 – 1.4 V

0

t

SWRS097-023

Figure 6-5. External Fast Clock (Sine Wave, DC-Coupled)

6.3.2.2 External F_REFSine Wave, AC-Coupled

Figure 6-6 and Figure 6-7 show the configuration when using a sine wave, AC-coupled external source for

the fast-clock input.

FREFP

68 pF

CC2564C

FREFM

VDD_IO

Figure 6-6. Clock Configuration (Sine Wave, AC-Coupled)

V_IN[V]

1 V

VPP = 0.4 – 1.6 Vp-p

0.8

0.2

0

t

–0.2

–0.8

SWRS097-022

Figure 6-7. External Fast Clock (Sine Wave, AC-Coupled)

In cases where the input amplitude is greater than 1.6 V_p-p, the amplitude can be reduced to within limits.

Using a small series capacitor forms a voltage divider with the internal input capacitance of approximately

2 pF to provide the required amplitude at the device input.

Detailed Description

25

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

6.3.2.3 Fast Clock Using External Crystal

The CC2564C device incorporates an internal crystal oscillator buffer to support a crystal-based fast-clock

scheme. The supported crystal frequencies are 26 and 38.4 MHz.

The frequency accuracy of the fast-clock source must not exceed ±20 ppm (including the accuracy of the

capacitors, as specified in the Bluetooth specification).

Figure 6-8 shows the recommended fast-clock circuitry.

CC2564C

C1

XTAL

C2

XTALM

XTALP

Oscillator

buffer

Figure 6-8. Fast-Clock Crystal Circuit

Table 6-1 lists component values for the fast-clock crystal circuit.

Table 6-1. Fast-Clock Crystal Circuit

Component Values

FREQ (MHz)

C1 (pF)⁽¹⁾

C2 (pF)⁽¹⁾

26

12

(1) To achieve the required accuracy, values for C1 and C2 must be

taken from the crystal manufacturer's data sheet and layout

considerations.

26

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

6.4 Functional Blocks

6.4.1 RF

The CC2564C device is the third generation of Bluetooth single-chip devices using DRP architecture from

TI. Modifications and new features added to the DRP further improve radio performance.

Figure 6-9 shows the DRP block diagram.

Transmitter path

Amplitude

TX digital data

Digital

ADPLL

DPA

Phase

Receiver path

IFA

RX digital data

Demodulation

Filter

ADC

LNA

SWRS092-005

Figure 6-9. DRP Block Diagram

6.4.1.1 Receiver

The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal

received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a

mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by

a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.

The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an

adaptive-decision mechanism. The demodulator includes EDR processing with:

•

State-of-the-art performance

A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK

sensitivity

•

Adaptive equalization to enhance EDR modulation

New features include:

•

LNA input range narrowed to increase blocking performance

Active spur cancellation to increase robustness to spurs

Detailed Description

27

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

6.4.1.2 Transmitter

The transmitter is an all-digital, sigma-delta phase-locked loop (ADPLL) based with a digitally controlled

oscillator (DCO) at 2.4 GHz as the RF clock. The transmitter directly modulates the digital PLL. The power

amplifier is also digitally controlled. The transmitter uses the polar-modulation technique. While the phase-

modulated control word is fed to the ADPLL, the amplitude-modulated controlled word is fed to the class-E

amplifier to generate a Bluetooth standard-compliant RF signal.

New features include:

•

Improved TX output power

LMS algorithm to improve the differential error vector magnitude (DEVM)

6.4.2 Host Controller Interface

The CC2564C device incorporates one UART module dedicated to the HCI transport layer. The HCI

transports commands, events, and ACL between the device and the host using HCI data packets.

The CC2564C device supports the H4 protocol (4-wire UART) with hardware flow control and the H5

protocol (3-wire UART) with software flow control. The CC2564C device automatically detects the protocol

on reception of the first command.

The maximum baud rate of the UART module is 4 Mbps; however, the default baud rate after power up is

set to 115.2 kbps. The baud rate can thereafter be changed with a VS command. The device responds

with a command complete event (still at 115.2 kbps), after which the baud rate change occurs.

The UART module includes the following features:

•

Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions

Transmitter underflow detection

CTS and RTS hardware flow control (H4 protocol)

XON and XOFF software flow control (H5 protocol)

Table 6-2 lists the UART module default settings.

Table 6-2. UART Module Default Settings

PARAMETER

Bit rate

VALUE

115.2 kbps

8 bits

Data length

Stop bit

1

Parity

None

28

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

6.4.2.1 4-Wire UART Interface—H4 Protocol

The H4 UART Interface includes four signals:

•

TX

RX

CTS

RTS

Flow control between the host and the CC2564C device is bytewise by hardware.

Figure 6-10 shows the H4 UART interface.

HCI_RX

HCI_TX

Host_RX

Host_TX

Host

CC2564C

HCI_CTS

HCI_RTS

Host_CTS

Host_RTS

Figure 6-10. H4 UART Interface

When the UART RX buffer of the device passes the flow control threshold, it sets the HCI_RTS signal

high to stop transmission from the host.

When the HCI_CTS signal is set high, the device stops transmission on the interface. If HCI_CTS is set

high while transmitting a byte, the device finishes transmitting the byte and stops the transmission.

The H4 protocol device includes a mechanism that handles the transition between active mode and sleep

mode. The protocol occurs through the CTS and RTS UART lines and is known as the enhanced HCI low

level (eHCILL) power-management protocol.

For more information on the H4 UART protocol, see Volume 4 Host Controller Interface, Part A UART

Transport

Layer

of

the

Bluetooth

Core

Specifications

(www.bluetooth.org/en-us/specification/adoptedspecifications).

Submit Documentation Feedback

Product Folder Links: CC2564C

Detailed Description

29

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

6.4.2.2 3-Wire UART Interface—H5 Protocol

The H5 UART interface consists of three signals (see Figure 6-11):

•

TX

RX

GND

HCI_RX

HCI_TX

Host_RX

Host_TX

Host

CC2564C

GND

Figure 6-11. H5 UART Interface

The H5 protocol supports the following features:

•

Software flow control (XON/XOFF)

Power management using the software messages:

–

WAKEUP

WOKEN

SLEEP

•

CRC data integrity check

For more information on the H5 UART protocol, see Volume 4 Host Controller Interface, Part D Three-

Wire UART Transport Layer of the Bluetooth Core Specifications

(www.bluetooth.org/en-us/specification/adoptedspecifications).

6.4.3 Digital Codec Interface

The codec interface is a fully programmable port to support seamless interfacing with different PCM and

I2S codec devices. The interface includes the following features:

•

Two voice channels

Master and slave modes

All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and µ-Law

Long and short frames

Different data sizes, order, and positions

High flexibility to support a variety of codecs

Bus sharing: Data_Out is in the Hi-Z state when the interface is not transmitting voice data.

30

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

6.4.3.1 Hardware Interface

The interface includes four signals:

•

Clock: configurable direction (input or output)

Frame_Sync and Word_Sync: configurable direction (input or output)

Data_In: input

Data_Out: output or tri-state signal

The CC2564C device can be the master of the interface when generating the Clock and Frame_Sync

signals or the slave when receiving these two signals.

For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the

maximum data burst size is 32 bits.

For master mode, the device can generate any clock frequency from 64 kHz to 4.096 MHz.

6.4.3.2 I2S

When the codec interface is configured to support the I2S protocol, these settings are recommended:

•

Bidirectional, full-duplex interface

Two time slots per frame: time slot 0 for the left channel audio data; and time slot 1 for the right

channel audio data

•

The length of each time slot is configurable up to 40 serial clock cycles, and the length of the frame is

configurable up to 80 serial clock cycles

6.4.3.3 Data Format

The data format is fully configurable:

•

The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to

640 bits when working with 1 channel. The data length can be set independently for each channel.

The data position within a frame is also configurable within 1 clock (bit) resolution and can be set

independently (relative to the edge of the Frame_Sync signal) for each channel.

The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start

with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each

channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for

sample sizes up to 24 bits.

•

Data_In and Data_Out are not required to be the same length.

The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for

permanent Hi-Z output, regardless of the data output. This configuration allows the device to be a bus

slave in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z output.

6.4.3.4 Frame-Idle Period

The codec interface handles frame-idle periods, during which the clock pauses and becomes 0 at the end

of the frame after all data are transferred.

The device supports frame-idle periods both as master and slave of the codec bus.

When the device is the master of the interface, the frame-idle period is configurable. There are two

configurable parameters:

•

Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of

the frame-idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.

•

Clk_Idle_End: indicates the time from the beginning of the frame to the end of the frame-idle period.

The time is given in multiples of clock periods.

The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.

For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.

Detailed Description

31

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts

60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period

ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the

beginning of the idle period.

Figure 6-12 shows the frame idle timing.

Frame period

Frame_Sync

Data_In

Data_Out

Frame idle

Clock

Clk_Idle_Start

Clk_Idle_End

frmidle_swrs064

Figure 6-12. Frame Idle Period

6.4.3.5 Clock-Edge Operation

The codec interface of the device can work on the rising or the falling edge of the clock and can sample

the Frame_Sync signal and the data at inversed polarity.

Figure 6-13 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.

The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore

sampled (by the device) on the next rising clock. The data from the codec is sampled (by the device) on

the falling edge of the clock.

PCM FSYNC

PCM CLK

D7

D6

D5

D4

D2

D1

D0

D3

PCM DATA IN

CC256x

SAMPLE TIME

SWRS121-004

Figure 6-13. Negative Clock Edge Operation

6.4.3.6 Two-Channel Bus Example

Figure 6-14 shows a 2-channel bus in which the two channels have different word sizes and arbitrary

positions in the bus frame.

32

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

...

Clock

FT

2

127 0

1

3

4

5

6

7

8

9

42 43 44

127 0

Fsync

MSB

bit bit bit bit bit bit bit bit

MSB

LSB

bit bit bit bit bit bit bit bit bit bit bit

10

...

Data_Out

Data_In

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

bit bit bit bit bit bit bit bit bit bit bit

10

bit bit bit bit bit bit bit bit

1

0

1

2

3

4

5

6

7

8

9

0

2

3

4

5

6

7

PCM_data_window

CH2 data

start FT = 43

CH1 data start FT = 0

CH1 data length = 11

CH2 data

length = 8

Fsync period = 128

Fsync length = 1

twochpcm_swrs064

NOTE: FT stands for frame timer.

Figure 6-14. 2-Channel Bus Timing

6.4.4 Assisted Modes

The CC2564C device contains an embedded coprocessor that can be used for multiple purposes (see 图

1-1). The CC2564C device uses the coprocessor to perform the LE functionality or to execute the

assisted HFP 1.6 (WBS) or assisted A2DP functions. Only one of these functions can be executed at a

time because they all use the same resources (that is, the coprocessor; see Table 3-1 for the modes of

operation supported by each device).

This section describes the assisted HFP 1.6 (WBS) and assisted A2DP modes of operation. These modes

of operation minimize host processing and power by taking advantage of the device coprocessor to

perform the voice and audio SBC processing required in HFP 1.6 (WBS) and A2DP profiles. This section

also compares the architecture of the assisted modes with the common implementation of the HFP 1.6

and A2DP profiles.

The assisted HFP 1.6 (WBS) and assisted A2DP modes of operation comply fully with the HFP 1.6 and

A2DP Bluetooth specifications. For more information on these profiles, see the corresponding Bluetooth

Profile Specification (www.bluetooth.org/en-us/specification/adopted-specifications).

6.4.4.1 Assisted HFP 1.6 (WBS)

The HFP 1.6 Profile Specification adds the requirement for WBS support. The WBS feature allows twice

the voice quality versus legacy voice coding schemes at the same air bandwidth (64 kbps). This feature is

achieved using a voice sampling rate of 16 kHz, a modified subband coding (mSBC) scheme, and a

packet loss concealment (PLC) algorithm. The mSBC scheme is a modified version of the mandatory

audio coding scheme used in the A2DP profile with the parameters listed in Table 6-3.

Table 6-3. mSBC Parameters

PARAMETER

Channel mode

VALUE

Mono

16 kHz

Loudness

8

Sampling rate

Allocation method

Subbands

Block length

Bitpool

15

26

Detailed Description

33

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

The assisted HFP 1.6 mode of operation implements this WBS feature on the embedded CC2564C

coprocessor. That is, the mSBC voice coding scheme and the PLC algorithm are executed in the

CC2564C coprocessor rather than in the host, thus minimizing host processing and power. One WBS

connection at a time is supported, and WBS and NBS connections cannot be used simultaneously in this

mode of operation. Figure 6-15 shows the architecture comparison between the common implementation

of the HFP 1.6 profile and the assisted HFP 1.6 solution.

HFP 1.6 Architecture

Assisted HFP 1.6 Architecture

Host Processor

16 kHz

16 bits

PCM

/

I2S

Audio

codec

HFP1.6

Profile

HFP1.6

Profile

mSBC

+ PLC

Control

Data

Bluetooth Stack

SCO

L2CAP

HCI

Control

Data

Control

HCI

16 kHz

16 bits

PCM

/

I2S

Audio

codec

5ata

CC256x

Bluetooth Controller

CC256x

Bluetooth Controller

mSBC

+ PLC

Figure 6-15. HFP 1.6 Architecture Versus Assisted HFP 1.6 Architecture

For detailed information on the HFP 1.6 profile, see the Hands-Free Profile 1.6 Specification

(www.bluetooth.org/en-us/specification/adopted-specifications).

6.4.4.2 Assisted A2DP

The advanced audio distribution profile (A2DP) enables wireless transmission of high-quality mono or

stereo audio between two devices. A2DP defines two roles:

•

A2DP source is the transmitter of the audio stream.

A2DP sink is the receiver of the audio stream.

A typical use case streams music from a tablet, phone, or PC (the A2DP source) to headphones or

speakers (the A2DP sink). This section describes the architecture of these roles and compares them with

the corresponding assisted-A2DP architecture. To use the air bandwidth efficiently, the audio data must be

compressed in a proper format. The A2DP mandates support of the SBC scheme. Other audio coding

algorithms can be used; however, both Bluetooth devices must support the same coding scheme. SBC is

the only coding scheme spread out in all A2DP Bluetooth devices; thus, it is the only coding scheme

supported in the assisted A2DP modes. Table 6-4 lists the recommended parameters for the SBC scheme

in the assisted A2DP modes.

34

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

Table 6-4. Recommended Parameters for the SBC Scheme in Assisted A2DP Modes

SBC

MID QUALITY

HIGH QUALITY

JOINT STEREO

ENCODER

SETTINGS⁽¹⁾

MONO

JOINT STEREO

MONO

Sampling

frequency

(kHz)

44.1

19

48

44.1

48

33

79

44.1

31

48

44.1

48

51

Bitpool value

18

44

35

83

29

66

53

Resulting

frame length

(bytes)

46

70

119

115

Resulting bit

rate (Kbps)

127

132

229

237

193

198

328

345

(1) Other settings: Block length = 16; allocation method = loudness; subbands = 8.

The SBC scheme supports a wide variety of configurations to adjust the audio quality. Table 6-5 through

Table 6-12 list the supported SBC capabilities in the assisted A2DP modes.

Table 6-5. Channel Modes

CHANNEL MODE

STATUS

Supported

Mono

Dual channel

Stereo

Joint stereo

Table 6-6. Sampling Frequency

SAMPLING FREQUENCY (kHz)

STATUS

Supported

16

44.1

48

Table 6-7. Block Length

BLOCK LENGTH

STATUS

Supported

4

8

12

16

Table 6-8. Subbands

SUBBANDS

STATUS

Supported

4

8

Detailed Description

35

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

Table 6-9. Allocation Method

ALLOCATION METHOD

STATUS

SNR

Supported

Loudness

Table 6-10. Bitpool Values

BITPOOL RANGE

STATUS

Supported

Assisted A2DP sink: 2–54

Assisted A2DP source: 2–57

Table 6-11. L2CAP MTU Size

L2CAP MTU SIZE (BYTES)

Assisted A2DP sink: 260–800

Assisted A2DP source: 260–1021

STATUS

Supported

Table 6-12. Miscellaneous Parameters

ITEM

A2DP content protection

AVDTP service

VALUE

Protected

STATUS

Not supported

Supported

Basic type

L2CAP mode

Basic mode

L2CAP flush

Nonflushable

For detailed information on the A2DP profile, see the A2DP Profile Specification at Adopted Bluetooth

Core Specifications.

6.4.4.2.1 Assisted A2DP Sink

The role of the A2DP sink is to receive the audio stream in an A2DP Bluetooth connection. In this role, the

A2DP layer and its underlying layers are responsible for link management and data decoding. To handle

these tasks, two logic transports are defined:

•

Control and signaling logic transport

Data packet logic transport

The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the

CC2564C device. First, the assisted A2DP implements a light L2CAP layer (L-L2CAP) and light AVDTP

layer (L-AVDTP) to defragment the packets. Then the assisted A2DP performs the SBC decoding on-chip

to deliver raw audio data through the device PCM–I2S interface. Figure 6-16 shows the comparison

between a common A2DP sink architecture and the assisted A2DP sink architecture.

36

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

A2DP Sink Architecture

Assisted A2DP Sink Architecture

Host Processor

Bluetooth Stack

Host Processor

Bluetooth Stack

44.1 kHz

48 kHz

PCM

/

I2S

Audio

codec

16 bits

A2DP

Profile

A2DP

Profile

SBC

AVDTP

L2CAP

Control

Data

Control

L2CAP

HCI

Contro

l

Control

Data

5ata

44.1 kHz

HCI

PCM

/

48 kHz

Audio

codec

16 bits

I2S

CC256x

Bluetooth Controller

CC256x

Bluetooth Controller

SBC

L-AVDTP

L-L2CAP

Figure 6-16. A2DP Sink Architecture Versus Assisted A2DP Sink Architecture

For more information on the A2DP sink role, see the A2DP Profile Specification at Adopted Bluetooth

Core Specifications.

6.4.4.2.2 Assisted A2DP Source

The role of the A2DP source is to transmit the audio stream in an A2DP Bluetooth connection. In this role,

the A2DP layer and its underlying layers are responsible for link management and data encoding. To

handle these tasks, two logic transports are defined:

•

Control and signaling logic transport

Data packet logic transport

The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the

CC2564C device. First, the assisted A2DP encodes the raw data from the CC2564C PCM–I2S interface

using an on-chip SBC encoder. Then the assisted A2DP implements an L-L2CAP layer and an L-AVDTP

layer to fragment and packetize the encoded audio data. Figure 6-17 shows the comparison between a

common A2DP source architecture and the assisted A2DP source architecture.

Detailed Description

37

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

A2DP Source Architecture

Assisted A2DP Source Architecture

Host Processor

Bluetooth Stack

44.1 kHz

48 kHz

PCM

/

I2S

Audio

codec

16 bits

A2DP

Profile

A2DP

Profile

SBC

AVDTP

/ontrol

5ata

/ontrol

L2CAP

HCI

L2CAP

HCI

/ontrol

5ata

/ontrol

5ata

44.1 kHz

48 kHz

HCI

PCM

/

I2S

Audio

codec

16 bits

CC256x

Bluetooth Controller

CC256x

Bluetooth Controller

SBC

L-AVDTP

L-L2CAP

Figure 6-17. A2DP Source Architecture Versus Assisted A2DP Source Architecture

For more information on the A2DP source role, see the A2DP Profile Specification at Adopted Bluetooth

Core Specifications.

6.5 Bluetooth BR and EDR Features

The CC2564C device complies with the Bluetooth 4.2 specification up to the HCI layer (for family

members and technology supported, see Table 3-1):

•

Up to seven active devices

Scatternet: Up to three piconets simultaneously, one as master and two as slaves

Up to two SCO links on the same piconet

Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and eSCO link

Supports typical 12-dBm TX power without an external power amplifier (PA), thus improving Bluetooth

link robustness

•

DRP single-ended 50-Ω I/O for easy RF interfacing

Internal temperature detection and compensation to ensure minimal variation in RF performance over

temperature

•

Includes a 128-bit hardware encryption accelerator as defined by the Bluetooth specifications

38

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

•

Flexible PCM and I2S digital codec interface:

–

Full flexibility of data format (linear, A-Law, µ-Law)

Data width

Data order

Sampling

Slot positioning

Master and slave modes

High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode)

•

Support for all voice air-coding

–

CVSD

A-Law

µ-Law

Transparent (uncoded)

mSBC

The CC2564C device provides an assisted mode for the HFP 1.6 (wideband speech [WBS]) profile or

A2DP profile to reduce host processing and power.

6.6 Bluetooth low energy Description

The CC2564C device complies with the Bluetooth 4.2 specification up to the HCI layer (for the family

members and technology supported, see Table 3-1):

•

Solution optimized for proximity and sports use cases

Supports up to 10 simultaneous connections

Multiple sniff instances that are tightly coupled to achieve minimum power consumption

Independent buffering for low energy, allowing large numbers of multiple connections without affecting

BR or EDR performance

•

Built-in coexistence and prioritization handling

NOTE

The assisted modes (HFP 1.6 and A2DP) are not available when Bluetooth low energy is

enabled.

Detailed Description

39

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

6.7 Bluetooth Transport Layers

Figure 6-18 shows the Bluetooth transport layers.

UART transport layer

Host controller interface

General

modules:

Data

Control

Event

HCI vendor-

specific

HCI data handler

HCI command handler

Trace

Timers

Sleep

Data

Link manager

Data

Link controller

RF

SWRS121-016

Figure 6-18. Bluetooth Transport Layers

6.8 Changes from the CC2564B Device to the CC2564C Device

The CC2564C device includes the following changes:

•

Support added for standard HCI command for WBS to replace HCI VS command sequence

Part of the Core Specification Addendum 2 (CSA2)

–

•

Easy PCM interface integration when using both WBS (16 kHz) and NBS (8 kHz)

PLC support added for NBS (8 kHz) when working at 16-kHz PCM clock

Option added to start and stop the PCM clock as master on the PCM bus even when voice call is not

active or set a timer to extend the clock after voice or audio is removed

•

Link layer topology support—Acts concurrently as peripheral and central low-energy device

AFH algorithm enhancements—Improvements to the automatic frequency hopping algorithms

40

Detailed Description

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

7 Applications, Implementation, and Layout

NOTE

Information in the following Applications section is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 Reference Design Schematics and BOM for Power and Radio Connections

Figure 7-1 shows the reference schematics for the VQFN-MR package. For complete schematics and

PCB layout guidelines, contact your TI representative.

Applications, Implementation, and Layout

41

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

Table 7-1 lists the BOM for the VQFN-MR package.

Table 7-1. Bill of Materials

REF.

DES.

MANUFACTURER

PART NUMBER

ALT

PART

QTY

VALUE

NA

DESCRIPTION

MANUFACTURER

NOTES

Chip

antenna

Copper antenna

on PCB

1

6

2

ANT1

ANT_IIFA_CC2420_32mil_MIR NA

Capacitor, ceramic; 0.1-µF

IIFA_CC2420

Capacitor

0.1 µF

1.0 µF

12 pF

0.47 µF

Kemet

C0402C104K9RACTU

JMK105BJ105KV-F

6.3-V 10% X7R 0402

Capacitor, ceramic; 1.0-µF

6.3-V 10% X5R 0402

Taiyo Yuden

Capacitor, ceramic; 12 pF

6.3-V X5R 10% 0402

Murata Electronics

Taiyo Yuden

GRM1555C1H120JZ01D

JMK105BJ474KV-F

Capacitor, ceramic; 0.47-µF

6.3-V X5R ±10% 0402

DEA162450

BT_1260B3

(TDK)

Filter, ceramic bandpass,

2.45-GHz SMD

Place brown

marking up

1

FL1

2.45 GHz

Murata Electronics

LFB212G45SG8C341

Oscillator; 32.768-kHz 15-pF

1.5-V 3.3-V SMD

Abracon

Corporation

1

OSC1

U5

32.768 kHz 15 pF

CC2564CRVM

ASH7K-32.768KHZ-T

CC2564CRVM

Optional

CC2564C dual-mode Bluetooth

controller

Texas Instruments

NDK

TZ1325D

(Tai-Saw

TST)

1

Y1

26 MHz

22 pF

Crystal, 26 MHz

NX2016SA

Capacitor, ceramic; 22-pF

25-V 5% NP0 0201

Murata Electronics

North America

GRM0335C1E220JD01D

(EXS00A-CS06025)

C31

7.2 PCB Layout Guidelines

This section describes the PCB guidelines to speed up the PCB design using the CC256x VQFN device.

Following these guidelines ensures that the design will pass Bluetooth SIG certification and also minimizes

risk for regulatory certifications including FCC, ETSI, and CE. For more information, see CC256x QFN

PCB Guidelines.

7.2.1 General PCB Guidelines

General PCB guidelines follow:

•

You must verify the recommended PCB stackup in the PCB Design guidelines.

You must verify the dimensions of the QFN PCB footprint in the QFN Package Information section of

CC256x QFN PCB Guidelines and in Section 6.

•

The decoupling capacitors must be as close as possible to the QFN device.

Applications, Implementation, and Layout

43

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

7.2.2 Power Supply Guidelines

Guidelines for the power supply follow:

•

The trace width must be at least 10 mils for the VBAT and VIO traces.

The length of the traces must be as short as possible (pin to pin).

Decoupling capacitors must be as close as possible to the QFN device:

–

The MLDO_IN capacitor must be close to pin B5.

The VDD_IO capacitor must be close to pins B18 and A17.

Guidelines for the LDOs follow:

•

The trace width for the trace between x_LDO_x pins and decoupling capacitors is at least 5 mils;

where possible, the recommended trace width is 10 mils.

•

Place the decoupling capacitor of MLDO_OUT (C20) as close as possible to pin A5.

These capacitors must close to the following pins:

–

The DIG_LDO_OUT capacitor must be close to ball B15.

The DIG_LDO_OUT capacitor must be close to ball B27.

The DIG_LDO_OUT capacitor must be close to ball B36.

•

The DIG_LDO_OUT capacitor connected to ball B36 must be isolated from the top layer GND (see the

Low-Dropout Capacitors section in CC256x QFN PCB Guidelines).

The decoupling capacitors for SRAM, ADCPPA, and CL1.5 LDO_OUT must be as close as possible to

their corresponding pins on the CC256x device.

•

Place the device and capacitors together on the top side.

The ground connection of each capacitor must be directly connected to solid ground layer (layer 2).

The capacitor that is directly connected to pin A12 should be close to the device.

Connect the DCO_LDO_OUT capacitor isolated from layer 1 ground directly to layer 2 solid ground.

Guidelines for the ground layer follow:

•

Layer 2 must be a solid ground plane.

Isolate VSS_FREF from ground on the top layer and route it directly to ground on the second layer

(see the Key VSS Ball section in CC256x QFN PCB Guidelines).

•

Isolate VSS_DCO (ball B11) from ground. Include VSS_DCO in the illustration of the DCO_LDO_OUT

capacitor (see the DCO_LDO_OUT section in CC256x QFN PCB Guidelines).

•

A minimum of 13 vias on the thermal pad are required to increase ground coupling.

Connect VSS_FREF (ball B3) directly to solid ground, not to the thermal pad.

44

Applications, Implementation, and Layout

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

7.2.3 User Interfaces

Guidelines for the UART follow:

•

The trace width for the UART must be at least 5 mils.

Run the four UART lines as a bus interface.

Determine if clocks, DC supply, or RF traces are not near these UART traces.

The ground plane on layer 2 is solid below these lines and there is ground around these traces on the

top layer.

Guidelines for the PCM follow:

•

The trace width for the PCM must be at least 5 mils.

Run the four PCM lines as a bus interface and approximately the same length.

Determine if clocks, DC supply, RF traces, and LDO capacitors are not near these PCM traces.

The ground plane on layer 2 is solid below these lines and there is ground around these traces on the

top layer.

•

Guidelines for TX_DBG follow:

Check for an accessible test point on the board from TX_DBG pin B24.

7.2.4 Clock Interfaces

Guidelines for the slow clock follow:

•

The trace width for the slow clock must be at least 5 mils.

The signal lines for the slow clock must be as short as possible.

The ground plane on layer 2 is solid below these lines and there is ground around these traces on the

top layer.

Guidelines for the fast clock follow:

•

The trace width for the fast clock must be at least 5 mils.

Ensure that crystal tuning capacitors are close to crystal pads.

Make both traces (XTALM and XTALP) parallel as much as possible and approximately the same

length.

•

The ground plane on layer 2 is solid below these lines and there is ground around these traces on the

top layer.

Applications, Implementation, and Layout

45

Submit Documentation Feedback

Product Folder Links: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

7.2.5 RF Interface

Guidelines for the RF Interface follow:

•

TI recommends using an RF shield (not mandatory).

Verify that RF traces are routed on the top layer and matched at 50 Ω with reference to ground.

Route the RF line between these NC pins:

–

NC_2 (A10)

NC_3 (A11)

NC_14 (B9)

NC_15 (B10)

These NC pins are grounded for better RF isolation.

NOTE

These pins are NC at the chip level, but TI recommends grounding them on the PCB layout

for better RF isolation.

•

Ensure the area underneath the BPF pads is grounded on layer 1 and layer 2.

Keep RF_IN and RF_OUT of the BPF pads clear of any ground fill (see the RF Trace section in

CC256x QFN PCB Guidelines).

•

Follow guidelines specified in the vendor-specific antenna design guides (including placement of

antenna).

•

Follow guidelines specified in the vendor-specific BPF design guides.

Verify that the Bluetooth RF trace is a 50-Ω, impedance-controlled trace with reference to solid ground.

Ensure that the RF trace length is as short as possible.

46

Applications, Implementation, and Layout

提交文档反馈意见

产品主页链接: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

8 器件和文档支持

8.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES

NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR

SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR

SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

8.2 工具与软件

设计套件与评估模块

CC256x Bluetooth^®硬件评估工具这款直观的用户友好型 TI 工具用于评估 TI 蓝牙芯片，能够以完整软件

包的形式从 TI 网站下载。具体而言，该工具用于通过服务包 (SP) 配置蓝牙芯片属性，同时支

持测试 RF 性能。

有关开发支持工具的完整列表，请参见 TI CC256x wiki。有关定价和购买信息，请联系最近的 TI 销售办事

处或授权分销商。

8.3 器件命名规则

为了标明产品开发周期的阶段，TI 为所有部件号分配了前缀。这些前缀代表了产品开发的发展阶段，即从工

程原型直到完全合格的生产器件。

器件开发进化流程：

X

试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。

原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。

完全合格的芯片模型的生产版本。

P

无

CC2564C xxx

x

R = Large Reel

T = Small Reel

Prefix

CC2564C

X = Experimental device

Blank = Qualified device

YM7

ZLLL G3

Package Designator

RVM = VQFNP-MR

YFV = DSBGA

Generic Part Number

Y

M

7

= Last digit of the year

= Month in hex number, 1-C for Jan-Dec

= Primary site code for ANM

= Secondary site code for ANM

Z

LLL = Assembly lot code

= Pin 1 indicator

图 8-1. CC2564C 器件命名规则

图 8-2. 芯片标记（VQFN-MR 封装）

8.4 Community Resources

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。

TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Established to help developers get started with Embedded Processors

from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

器件和文档支持

47

提交文档反馈意见

产品主页链接: CC2564C

CC2564C

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

www.ti.com.cn

8.5 商标

E2E is a trademark of Texas Instruments.

ARM7TDMI is a registered trademark of ARM Limited.

由 is a registered trademark of Apple, Inc.

蓝牙 is a registered trademark of Bluetooth SIG, Inc.

All other trademarks are the property of their respective owners.

8.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

8.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

48

器件和文档支持

提交文档反馈意见

产品主页链接: CC2564C

CC2564C

www.ti.com.cn

ZHCSFX3A –APRIL 2016–REVISED NOVEMBER 2016

9 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知

且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏

机械、封装和可订购信息

49

提交文档反馈意见

产品主页链接: CC2564C

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CC2564CRVMR
厂家：	TEXAS INSTRUMENTS
描述：	具有基本速率 (BR)、增强数据速率 (EDR) 和低功耗 (LE) 模块的 Bluetooth® 4.2 \| RVM \| 76 \| -40 to 85 电信电信集成电路
文件：	总55页 (文件大小：1343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC2564CRVMR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E