CC2651P3 [TI]
具有 352kB 闪存的 SimpleLink™ 32 位 Arm® Cortex®-M4 单协议 2.4GHz 无线 MCU;
| 型号： | CC2651P3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 352kB 闪存的 SimpleLink™ 32 位 Arm® Cortex®-M4 单协议 2.4GHz 无线 MCU 无线 闪存 |
| 文件： | 总66页 (文件大小：4168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC2651P3
ZHCSQD6 –MARCH 2022
CC2651P3 具有集成式功率放大器的
SimpleLink™ 单协议2.4GHz 无线MCU
MCU 外设
1 特性
• 数字外设可连接至任何GPIO
无线微控制器
• 四个32 位或八个16 位通用计时器
• 12 位ADC、200 ksps、8 通道
• 8 位DAC
• 功能强大的48 MHz Arm® Cortex®-M4 处理器
• 352KB 闪存程序存储器
• 32KB 超低泄漏SRAM
• 模拟比较器
• UART、SSI、I2C、I2S
• 实时时钟(RTC)
• 集成温度和电池监控器
• 8KB 缓存SRAM（也可作为通用RAM 提供）
• 可编程无线电包括对2-(G)FSK、4-(G)FSK、
MSK、低功耗Bluetooth® 5.2、IEEE 802.15.4
PHY 和MAC 的支持
安全驱动工具
• 支持无线升级(OTA)
• AES 128 位加密加速计
• 真随机数发生器(TRNG)
低功耗
• 软件开发套件(SDK) 中提供了其他加密驱动器
• MCU 功耗：
– 2.91 mA 有源模式，CoreMark®
– 61 μA/MHz（运行CoreMark 时）
– 0.8 μA 待机模式，RTC，32KB RAM
– 0.1 μA 关断模式，引脚唤醒
• 无线电功耗：
开发工具和软件
• LP-CC2651P3 开发套件
• SimpleLink™ CC13xx 和CC26xx 软件开发套件
(SDK)
• 用于简单无线电配置的SmartRF™ Studio
• SysConfig 系统配置工具
– RX：6.4 mA
– TX：7.1 mA（在0 dBm 条件下）
– TX：9.5 mA（在+5 dBm 条件下）
– TX：22 mA（在+10 dBm 条件下）
– TX：101 mA（在+20 dBm 和7x7 封装条件
下）
工作温度范围
• 片上降压直流/直流转换器
• 1.8V 至3.8V 单电源电压
• -40°C 至+105°C
无线协议支持
封装
• Zigbee®
• 7mm × 7mm RGZ VQFN48（26 个GPIO）
• 5mm × 5mm RKP VQFN40（18 个GPIO）
• 符合RoHS 标准的封装
• 低功耗Bluetooth® 5.2
• SimpleLink™ TI 15.4-stack
• 专有系统
高性能无线电
• -104 dBm（在125 kbps 低功耗Bluetooth® 下）
• 高达+20 dBm 的输出功率，具有温度补偿
法规遵从性
• 适用于符合以下标准的系统：
– ETSI EN 300 328、EN 300 440 类别2 和3
– FCC CFR47 第15 部分
– ARIB STD-T66
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS257
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
• 工业运输–资产跟踪
• 工厂自动化和控制
• 医疗
• 电子销售终端(EPOS) –电子货架标签(ESL)
• 通信设备
2 应用
• 2400 至2500 MHz ISM 和SRD 系统，1
接收带宽低至4kHz
• 楼宇自动化
– 有线网络–无线LAN 或Wi-Fi 接入点、边缘路
由器、小型企业路由器
– 楼宇安防系统–运动检测器、电子智能锁、门
窗传感器、车库门系统、网关
– HVAC –恒温器、无线环境传感器、HVAC 系
统控制器、网关
• 个人电子产品
– 家庭影院和娱乐–智能扬声器、智能显示器、
– 防火安全系统–烟雾和热量探测器、火警控制
面板(FACP)
– 视频监控–IP 网络摄像头
– 升降机和自动扶梯–升降机和自动扶梯的电梯
主控板
机顶盒
– 可穿戴设备（非医用）–智能追踪器、智能服
装
3 说明
SimpleLink™ CC2651P3 器件是一款单协议 2.4 GHz 无线微控制器 (MCU)，支持以下协议：Zigbee®、低功耗
Bluetooth®5.2、IEEE 802.15.4g、TI 15.4-Stack (2.4 GHz)。CC2651P3 基于 Arm® Cortex® M4 主处理器，针对
电网基础设施、楼宇自动化、零售自动化、个人电子产品和医疗应用中的低功耗无线通信和高级传感功能进行了
优化。
CC2651P3 具有由 Arm® Cortex® M0 驱动的软件定义无线电，支持多个物理层和射频标准。该器件支持在 2360
MHz 至 2500 MHz 频带内运行。CC2651P3 具有高效的内置 PA，支持 +10 dBm TX (21 mA) 和 +20 dBm TX
(101 mA)（7x7 封装）。 CC2651P3 接收灵敏度为 -104 dBm（对于 125 kbps 的低功耗 Bluetooth® 编码
PHY）。
在采用RTC 并保持32KB RAM 时，CC2651P3 具有0.8 μA 的低待机电流。
许多客户对产品生命周期的要求为10 至15 年或者更久，为了达到这一目标，TI 制定了产品生命周期政策，对产
品的寿命和供货连续性作出承诺。
CC2651P3 器件是 SimpleLink™ MCU 平台的一部分，包括 Wi-Fi®、低功耗 Bluetooth®、Thread、Zigbee、Wi-
SUN®、Amazon Sidewalk、mioty、Sub-1 GHz MCU 和主机 MCU。 CC2651P3 是可扩展产品系列（闪存为
32KB 至 704KB）的一部分，具有引脚对引脚兼容的封装选项。通用 SimpleLink™ CC13xx 和 CC26xx 软件开发
套件(SDK) 及SysConfig 系统配置工具支持产品系列中各器件之间的迁移。SDK 随附了丰富的软件栈、应用示例
和SimpleLink™ Academy 培训课程。如需了解更多相关信息，请访问无线连接。
器件信息
器件型号(1)
CC2651P31T0RGZR
CC2651P31T0RKPR
封装尺寸（标称值）
7.00mm × 7.00mm
5.00mm × 5.00mm
封装
VQFN (48)
VQFN (40)
(1) 如需所有可用器件的最新器件、封装和订购信息，请参阅节12 中的“封装选项附录”或访问TI 网站。
1
请参阅射频内核，了解有关支持的协议标准、模块格式和数据速率的更多详细信息。
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
4 功能方框图
RF Core
cJTAG
Main CPU
40KB
ROM
ADC
ADC
Arm® Cortex®-M4
Processor
352KB
Flash
Digital PLL
with 8KB
Cache
DSP Modem
48 MHz
SRAM
ROM
Arm® Cortex®-M0
Processor
32KB
SRAM
General Hardware Peripherals and Modules
I2C
4× 32-bit Timers
8-bit DAC
UART
SSI (SPI)
Watchdog Timer
32 ch. µDMA
RTC
12-bit ADC, 200 ks/s
Low-Power Comparator
Time-to-Digital Converter
I2S
Up to 26 GPIOs
AES & TRNG
Temperature and
Battery Monitor
LDO, Clocks, and References
Optional DC/DC Converter
图4-1. CC2651P3 功能方框图
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
Table of Contents
8.15 Peripheral Characteristics.......................................25
8.16 Typical Characteristics............................................31
9 Detailed Description......................................................39
9.1 Overview...................................................................39
9.2 System CPU............................................................. 39
9.3 Radio (RF Core)........................................................40
9.4 Memory.....................................................................41
9.5 Cryptography............................................................ 42
9.6 Timers....................................................................... 43
9.7 Serial Peripherals and I/O.........................................44
9.8 Battery and Temperature Monitor............................. 44
9.9 µDMA........................................................................44
9.10 Debug..................................................................... 44
9.11 Power Management................................................45
9.12 Clock Systems........................................................ 46
9.13 Network Processor..................................................46
10 Application, Implementation, and Layout................. 47
10.1 Reference Designs................................................. 47
11 Device and Documentation Support..........................48
11.1 Device Nomenclature..............................................48
11.2 Tools and Software..................................................49
11.3 Documentation Support.......................................... 51
11.4 支持资源..................................................................51
11.5 Trademarks............................................................. 51
11.6 Electrostatic Discharge Caution..............................52
11.7 术语表..................................................................... 52
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 功能方框图.........................................................................3
5 Revision History.............................................................. 4
6 Device Comparison.........................................................5
7 Pin Configuration and Functions...................................6
7.1 Pin Diagram –RGZ Package (Top View)..................6
7.2 Signal Descriptions –RGZ Package.........................7
7.3 Pin Diagram –RKP Package (Top View).................. 9
7.4 Signal Descriptions –RKP Package......................... 9
7.5 Connections for Unused Pins and Modules..............11
8 Specifications................................................................ 12
8.1 Absolute Maximum Ratings...................................... 12
8.2 ESD Ratings............................................................. 12
8.3 Recommended Operating Conditions.......................12
8.4 Power Supply and Modules...................................... 12
8.5 Power Consumption - Power Modes........................ 13
8.6 Power Consumption - Radio Modes......................... 14
8.7 Nonvolatile (Flash) Memory Characteristics............. 14
8.8 Thermal Resistance Characteristics......................... 14
8.9 RF Frequency Bands................................................15
8.10 Bluetooth Low Energy - Receive (RX).................... 16
8.11 Bluetooth Low Energy - Transmit (TX)....................19
8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - RX.............................20
8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - TX.............................21
8.14 Timing and Switching Characteristics..................... 22
Information.................................................................... 53
5 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2022
*
Initial Release
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
6 Device Comparison
RADIO SUPPORT
PACKAGE SIZE
FLASH
(KB)
RAM +
Cache (KB)
Device
GPIO
CC1310
CC1311R3
CC1311P3
CC1312R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32-128
352
352
352
704
352
352
704
128
352
352
352
352
352
352
704
352
704
16-20 + 8 10-30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32 + 8
32 + 8
80 + 8
144 + 8
80 + 8
80 + 8
144 + 8
20 + 8
80 + 8
80 + 8
32 + 8
32 + 8
80 + 8
80 + 8
144 + 8
80 + 8
144 + 8
22-30
26
X
X
X
30
CC1312R7
CC1352R
X
X
X
X
X
X
X
X
X
X
30
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
28
CC1352P
X
X
26
CC1352P7
CC2640R2F
CC2642R
26
10-31
31
X
X
CC2642R-Q1
CC2651R3
CC2651P3
CC2652R
31
X
X
X
X
X
X
X
X
X
X
X
X
X
X
23-31
22-26
31
X
X
X
X
X
X
X
X
X
X
X
X
X
CC2652RB
CC2652R7
CC2652P
31
31
X
X
26
CC2652P7
26
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
7 Pin Configuration and Functions
7.1 Pin Diagram –RGZ Package (Top View)
RF_P
RF_N
1
2
3
4
5
6
7
8
9
36 DIO_23
35 RESET_N
34 VDDS_DCDC
33 DCDC_SW
32 DIO_22
NC
NC
TX_20DBM_P
TX_20DBM_N
31 DIO_21
RX_TX
X32K_Q1
X32K_Q2
30 DIO_20
29 DIO_19
28 DIO_18
DIO_5 10
DIO_6 11
DIO_7 12
27 DIO_17
26 DIO_16
25 JTAG_TCKC
图7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in 图7-1 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
The following I/O pins marked in 图7-1 in italics have analog capabilities:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
7.2 Signal Descriptions –RGZ Package
表7-1. Signal Descriptions –RGZ Package
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
33
23
10
11
12
14
15
16
17
18
19
20
21
26
27
28
29
30
31
32
36
37
38
39
40
41
42
43
DCDC_SW
DCOUPL
DIO_5
Power
Power
Output from internal DC/DC converter(1)
—
For decoupling of internal 1.27 V regulated digital-supply (2)
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Digital
GPIO, high-drive capability
DIO_6
Digital
GPIO, high-drive capability
DIO_7
Digital
GPIO, high-drive capability
DIO_8
Digital
GPIO
DIO_9
Digital
GPIO
DIO_10
DIO_11
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
DIO_23
DIO_24
DIO_25
DIO_26
DIO_27
DIO_28
DIO_29
DIO_30
EGP
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
Digital
Digital
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital
GPIO
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
Digital or Analog
GND
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
Ground –exposed ground pad(3)
JTAG TMSC, high-drive capability
JTAG TCKC
—
24
25
35
—
I/O
I
JTAG_TMSC
JTAG_TCKC
RESET_N
Digital
Digital
I
Digital
Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_P
RF_N
1
2
RF
RF
—
—
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RX_TX
7
5
6
RF
RF
RF
Optional bias pin for the RF LNA
Positive high-power TX signal
Negative high-power TX signal
—
—
—
TX_20DBM_P
TX_20DBM_N
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (4) (6)
VDDR
45
Power
—
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (5) (6)
VDDR_RF
VDDS
48
44
Power
Power
—
—
1.8-V to 3.8-V main chip supply(1)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
表7-1. Signal Descriptions –RGZ Package (continued)
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
13
22
34
46
47
8
VDDS2
Power
Power
Power
Analog
Analog
Analog
Analog
1.8-V to 3.8-V DIO supply(1)
—
—
—
—
—
—
—
VDDS3
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
X48M_N
1.8-V to 3.8-V DC/DC converter supply
48-MHz crystal oscillator pin 1
48-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
X48M_P
X32K_Q1
X32K_Q2
9
(1) For more details, see the device technical reference manual listed in 节11.3.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
7.3 Pin Diagram –RKP Package (Top View)
RF_P
RF_N
1
2
3
4
5
6
7
8
9
30 DIO_17
29 DIO_16
28 DIO_15
27 RESET_N
26 VDDS_DCDC
25 DCDC_SW
24 DIO_14
23 DIO_13
22 DIO_12
21 DIO_11
NC
NC
TX_10DBM_P
TX_10DBM_N
RX_TX
X32K_Q1
X32K_Q2
DIO_5 10
图7-2. RKP (5-mm × 5-mm) Pinout, 0.4-mm Pitch (Top View)
The following I/O pins marked in 图7-2 in bold have high-drive capabilities:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 18, JTAG_TMSC
• Pin 20, DIO_10
• Pin 21, DIO_11
The following I/O pins marked in 图7-2 in italics have analog capabilities:
• Pin 28, DIO_15
• Pin 29, DIO_16
• Pin 30, DIO_17
• Pin 31, DIO_18
• Pin 32, DIO_19
• Pin 33, DIO_20
• Pin 34, DIO_21
• Pin 35, DIO_22
7.4 Signal Descriptions –RKP Package
表7-2. Signal Descriptions –RKP Package
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
25
DCDC_SW
DCOUPL
DIO_5
Power
Power
Digital
Digital
Output from internal DC/DC converter(1)
—
—
17
For decoupling of internal 1.27 V regulated digital-supply (2)
10
I/O
I/O
GPIO, high-drive capability
DIO_6
11
GPIO, high-drive capability
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
表7-2. Signal Descriptions –RKP Package (continued)
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
12
14
15
20
21
22
23
24
28
29
30
31
32
33
34
35
DIO_7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
GND
GPIO, high-drive capability
DIO_8
GPIO
DIO_9
GPIO
DIO_10
DIO_11
GPIO, JTAG_TDO, high-drive capability
GPIO, JTAG_TDI, high-drive capability
GPIO
DIO_12
DIO_13
DIO_14
DIO_15
DIO_16
DIO_17
DIO_18
DIO_19
DIO_20
DIO_21
DIO_22
EGP
GPIO
GPIO
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
GPIO, analog capability
Ground –exposed ground pad(3)
JTAG TMSC, high-drive capability
JTAG TCKC
—
18
19
27
—
I/O
I
JTAG_TSMC
JTAG_TCKC
RESET_N
Digital
Digital
Digital
I
Reset, active low. No internal pullup resistor
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RF_P
RF_N
1
2
RF
RF
—
—
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RX_TX
7
5
6
RF
RF
RF
Optional bias pin for the RF LNA
Positive high-power TX signal
Negative high-power TX signal
—
—
—
TX_20DBM_P
TX_20DBM_N
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (4) (6)
VDDR
37
40
Power
Power
—
—
Internal supply, must be powered from the internal DC/DC
converter or the internal LDO(2) (5) (6)
VDDR_RF
VDDS
36
13
16
26
38
39
8
Power
Power
Power
Power
Analog
Analog
Analog
Analog
1.8-V to 3.8-V main chip supply(1)
1.8-V to 3.8-V DIO supply(1)
—
—
—
—
—
—
—
—
VDDS2
VDDS3
1.8-V to 3.8-V DIO supply(1)
VDDS_DCDC
X48M_N
X48M_P
X32K_Q1
X32K_Q2
1.8-V to 3.8-V DC/DC converter supply
48-MHz crystal oscillator pin 1
48-MHz crystal oscillator pin 2
32-kHz crystal oscillator pin 1
32-kHz crystal oscillator pin 2
9
(1) For more details, see the device technical reference manual listed in 节11.3.
(2) Do not supply external circuitry from this pin.
(3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO.
(5) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
(6) Output from internal DC/DC and LDO is trimmed to 1.68 V.
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
7.5 Connections for Unused Pins and Modules
表7-3. Connections for Unused Pins –RGZ Package
PREFERRED
PRACTICE(1)
FUNCTION
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE(1)
10–12
14–21
26–32
36–43
GPIO
DIO_n
NC or GND
NC
X32K_Q1
X32K_Q2
NC
8
9
32.768-kHz crystal
No Connects
NC or GND
NC
NC
NC
NC
NC
3–4
33
DCDC_SW
VDDS_DCDC
DC/DC converter(2)
34
VDDS
VDDS
(1) NC = No connect
(2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
表7-4. Connection for Unused Pins and Modules –RKP Package
ACCEPTABLE
PRACTICE
FUNCTION
SIGNAL NAME
PIN NUMBER
PREFERRED PRACTICE
10-12
14-15
20-24
28-35
GPIO
DIO_n
NC or GND
NC
X32K_Q1
X32K_Q2
NC
3
4
32.768-kHz crystal
No Connects
NC or GND
NC
NC
NC
NC
NC
3–4
25
DCDC_SW
VDDS_DCDC
DC/DC converter
26
VDDS
VDDS
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX UNIT
VDDS(3) (6) Supply voltage
4.1
V
V
V
Voltage on any digital pin(4) (5)
VDDS + 0.3, max 4.1
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
Voltage scaling enabled
VDDR + 0.3, max 2.25
VDDS
1.49
Vin
Voltage on ADC input
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
V
VDDS / 2.9
5
Input level, RF pins (RF_P and RF_N)
Storage temperature
dBm
°C
Tstg
150
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) All voltage values are with respect to ground, unless otherwise noted.
(3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS.
(4) Including analog capable DIOs.
(5) Injection current is not supported on any GPIO pin
(6) Connect VDDR to the external PA bias voltage for +10dBm and VDDS to the external PA bias voltage for +14dBm to +20dBm
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged device model (CDM), per JESD22-C101(2)
All pins
All pins
VESD
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
105
115
3.8
UNIT
°C
Operating ambient temperature(1) (2)
–40
Operating junction temperature(1) (2)
°C
–40
Operating supply voltage (VDDS)
Rising supply voltage slew rate
Falling supply voltage slew rate(3)
1.8
0
V
100
20
mV/µs
mV/µs
0
(1) Operation at or near maximum operating temperature for extended durations will result in lifetime reduction.
(2) For thermal resistance characteristics refer to 节8.8.
(3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
8.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VDDS Power-on-Reset (POR) threshold
VDDS Brown-out Detector (BOD)
MIN
TYP
1.1 - 1.55
1.77
MAX
UNIT
V
V
V
V
Rising threshold
Rising threshold
Falling threshold
VDDS Brown-out Detector (BOD), before initial boot (1)
VDDS Brown-out Detector (BOD)
1.70
1.75
(1) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.5 Power Consumption - Power Modes
When measured on the CC26x1-P3EM-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Core Current Consumption
Reset. RESET_N pin asserted or VDDS below power-on-reset
threshold
150
100
0.8
Reset and
Shutdown
nA
Shutdown. No clocks running, no retention
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
µA
µA
µA
µA
µA
mA
Standby
without cache
retention
RTC running, CPU, 32KB RAM and (partial) register retention
XOSC_LF
0.9
2.4
Icore
RTC running, CPU, 32KB RAM and (partial) register retention.
RCOSC_LF
Standby
with cache retention
RTC running, CPU, 32KB RAM and (partial) register retention.
XOSC_LF
2.6
Supply Systems and RAM powered
RCOSC_HF
Idle
650
2.91
MCU running CoreMark at 48 MHz
RCOSC_HF
Active
Peripheral Current Consumption
Peripheral power
domain
Delta current with domain enabled
56.0
5.0
Serial power domain Delta current with domain enabled
Delta current with power domain enabled,
clock enabled, RF core idle
RF Core
µDMA
144
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle(1)
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
Delta current with clock enabled, module is idle
68.6
102
Timers
Iperi
µA
I2C
12.1
30.8
71.7
147
I2S
SSI
UART
CRYPTO (AES)
TRNG
28.1
27.1
(1) Only one GPTimer running
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.6 Power Consumption - Radio Modes
When measured on the CC26x1-P3EM-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled
unless otherwise noted.
High-power PA connected to VDDS unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Radio receive current
2440 MHz
6.4
mA
0 dBm output power setting
2440 MHz
7.1
9.5
mA
mA
mA
Radio transmit current
2.4 GHz PA (Bluetooth Low Energy)
+5 dBm output power setting
2440 MHz
Radio transmit current
High-power PA
+20 dBm output power setting(1)
2440 MHz. VDDS = 3.3 V
101
Radio transmit current
High-power PA, 10 dBm
configuration(2)
+10 dBm output power setting
2440 MHz VDDR = 1.67 V
22
mA
(1) +20 dBm is only available on the RGZ (7x7) package
(2) Measured on evaluation board as described in https://www.ti.com/lit/pdf/swra636.
8.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Flash sector size
8
KB
Supported flash erase cycles before failure, full bank(1) (5)
Supported flash erase cycles before failure, single sector(2)
30
60
k Cycles
k Cycles
Maximum number of write operations per row before sector
erase(3)
Write
Operations
83
Flash retention
105 °C
11.4
Years
mA
ms
Flash sector erase current
Average delta current
Zero cycles
9.7
10
Flash sector erase time(4)
30k cycles
4000
ms
Flash write current
Flash write time(4)
Average delta current, 4 bytes at a time
4 bytes at a time
5.3
mA
µs
21.6
(1) A full bank erase is counted as a single erase cycle on each sector.
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum
number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.
8.8 Thermal Resistance Characteristics
PACKAGE
RGZ
(VQFN)
RKP
(VQFN)
THERMAL METRIC(1)
UNIT
48 PINS
25.0
14.5
8.7
40 PINS
30.9
20.2
10.3
0.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
°C/W(2)
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
8.6
10.3
2.1
ψJB
RθJC(bot)
2.1
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.9 RF Frequency Bands
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
Frequency bands
2360
2500
MHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.10 Bluetooth Low Energy - Receive (RX)
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
125 kbps (LE Coded)
Receiver sensitivity
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential mode. BER = 10–3
dBm
dBm
dBm
kHz
–104
–104
Single ended mode. Measured on CC26x1-
Receiver sensitivity
P3EM-5XS24, at the SMA connector, BER = 10–3
Receiver saturation
Differential mode. BER = 10–3
>5
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
> (–300 / 300)
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
Data rate error tolerance
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
Selectivity, ±2 MHz(1)
Selectivity, ±3 MHz(1)
Selectivity, ±4 MHz(1)
Selectivity, ±6 MHz(1)
Selectivity, ±7 MHz
ppm
ppm
dB
> (–320 / 240)
> (–125 / 125)
–1.5
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
Wanted signal at –79 dBm, modulated interferer in
channel, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±1
8 / 4.5(2)
44 / 39(2)
46 / 44(2)
44 / 46(2)
48 / 44(2)
51 / 45(2)
39
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±2
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±3
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ±4
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ≥±6
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at ≥±7
dB
MHz, BER = 10–3
Wanted signal at –79 dBm, modulated interferer at
Selectivity, Image frequency(1)
dB
image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co- channel –
1 MHz. Wanted signal at –79 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
Selectivity, Image frequency ±1
MHz(1)
4.5 / 44 (2)
dB
500 kbps (LE Coded)
Receiver sensitivity
Differential mode. BER = 10–3
dBm
dBm
dBm
kHz
–100
–100
Single ended mode. Measured on CC26x1-
Receiver sensitivity
P3EM-5XS24, at the SMA connector, BER = 10–3
Receiver saturation
Differential mode. BER = 10–3
> 5
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
> (–300 / 300)
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
Data rate error tolerance
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
Selectivity, ±2 MHz(1)
Selectivity, ±3 MHz(1)
Selectivity, ±4 MHz(1)
Selectivity, ±6 MHz(1)
ppm
ppm
dB
> (–450 / 450)
> (–175 / 175)
–3.5
Difference between incoming data rate and the internally
generated data rate (255-byte packets)
Wanted signal at –72 dBm, modulated interferer in
channel, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±1
8 / 4(2)
dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±2
44 / 37(2)
46 / 46(2)
45 / 47(2)
46 / 45(2)
dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±3
dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ±4
dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at ≥±6
dB
MHz, BER = 10–3
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.10 Bluetooth Low Energy - Receive (RX) (continued)
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Wanted signal at –72 dBm, modulated interferer at ≥±7
Selectivity, ±7 MHz
49 / 45(2)
dB
MHz, BER = 10–3
Wanted signal at –72 dBm, modulated interferer at
Selectivity, Image frequency(1)
37
dB
dB
image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co- channel –
1 MHz. Wanted signal at –72 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
Selectivity, Image frequency ±1
MHz(1)
4 / 46(2)
1 Mbps (LE 1M)
Receiver sensitivity
Differential mode. BER = 10–3
dBm
dBm
dBm
kHz
–97
–97
Single ended mode. Measured on CC26x1-
Receiver sensitivity
P3EM-5XS24, at the SMA connector, BER = 10–3
Receiver saturation
Differential mode. BER = 10–3
> 5
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
> (–350 / 350)
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±1 MHz(1)
ppm
dB
dB
dB
dB
dB
dB
dB
> (–750 / 750)
–6
Wanted signal at –67 dBm, modulated interferer in
channel, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±1
7 / 4(2)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
Selectivity, ±2 MHz(1)
40 / 33(2)
36 / 41(2)
37 / 45(2)
40
MHz,BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±3
Selectivity, ±3 MHz(1)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(1)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ≥±5
Selectivity, ±5 MHz or more(1)
Selectivity, image frequency(1)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at
33
image frequency, BER = 10–3
Note that Image frequency + 1 MHz is the Co- channel –
1 MHz. Wanted signal at –67 dBm, modulated interferer
at ±1 MHz from image frequency, BER = 10–3
Selectivity, image frequency
±1 MHz(1)
4 / 41(2)
dB
Out-of-band blocking(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
dBm
dBm
dBm
–10
–18
–12
–2
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2405 and 2408 MHz respectively, at the given power
level
Intermodulation
dBm
–42
Spurious emissions,
30 to 1000 MHz
dBm
dBm
Measurement in a 50-Ωsingle-ended load.
Measurement in a 50-Ωsingle-ended load.
< –59
< –47
Spurious emissions,
1 to 12.75 GHz
RSSI dynamic range
RSSI accuracy
70
±4
dB
dB
2 Mbps (LE 2M)
Differential mode. Measured at SMA connector, BER =
10–3
Receiver sensitivity
Receiver sensitivity
Receiver saturation
dBm
dBm
dBm
–92
–92
> 5
Single ended mode. Measured on CC26x1-
P3EM-5XS24, at the SMA connector, BER = 10–3
Differential mode. Measured at SMA connector, BER =
10–3
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.10 Bluetooth Low Energy - Receive (RX) (continued)
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Difference between the incoming carrier frequency and
the internally generated carrier frequency
Frequency error tolerance
kHz
> (–500 / 500)
Difference between incoming data rate and the internally
generated data rate (37-byte packets)
Data rate error tolerance
Co-channel rejection(1)
Selectivity, ±2 MHz(1)
ppm
dB
dB
dB
dB
dB
> (–700 / 750)
–7
Wanted signal at –67 dBm, modulated interferer in
channel,BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±2
MHz, Image frequency is at –2 MHz, BER = 10–3
8 / 4(2)
Wanted signal at –67 dBm, modulated interferer at ±4
Selectivity, ±4 MHz(1)
36 / 31(2)
37 / 36(2)
4
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at ±6
Selectivity, ±6 MHz(1)
MHz, BER = 10–3
Wanted signal at –67 dBm, modulated interferer at
Selectivity, image frequency(1)
image frequency, BER = 10–3
Note that Image frequency + 2 MHz is the Co-channel.
Wanted signal at –67 dBm, modulated interferer at ±2
MHz from image frequency, BER = 10–3
Selectivity, image frequency
±2 MHz(1)
–7 / 36(2)
dB
Out-of-band blocking(3)
Out-of-band blocking
Out-of-band blocking
Out-of-band blocking
30 MHz to 2000 MHz
2003 MHz to 2399 MHz
2484 MHz to 2997 MHz
3000 MHz to 12.75 GHz
dBm
dBm
dBm
dBm
–16
–21
–15
–12
Wanted signal at 2402 MHz, –64 dBm. Two interferers
at 2408 and 2414 MHz respectively, at the given power
level
Intermodulation
dBm
–38
(1) Numbers given as I/C dB
(2) X / Y, where X is +N MHz and Y is –N MHz
(3) Excluding one exception at Fwanted / 2, per Bluetooth Specification
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.11 Bluetooth Low Energy - Transmit (TX)
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Max output power,
high power PA
20
6
dBm
dB
Differential mode, delivered to a single-ended 50 Ωload through a balun
Differential mode, delivered to a single-ended 50 Ωload through a balun
Output power
programmable range
high power PA
Max output power,
high power PA, 10
dBm configuration(3)
10.5
9
dBm
dBm
Differential mode, delivered to a single-ended 50 Ωload through a balun
Max output power,
high power PA, 10
dBm configuration(3)
Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50 Ω
load through a balun
Output power
programmable range
high power PA, 10
dBm configuration(3)
5
dB
Differential mode, delivered to a single-ended 50 Ωload through a balun
Differential mode, delivered to a single-ended 50 Ωload through a balun
Max output power,
regular PA
5
3
dBm
dBm
Max output power,
regular PA
Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50 Ω
load through a balun
Output power
programmable range,
regular PA
26
dB
Differential mode, delivered to a single-ended 50 Ωload through a balun
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands
< -36
< -55
-37
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Spurious emissions,
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
high-power PA(1)
+20 dBm setting
-35
Harmonics,
high-power PA(2)
Third harmonic
-42
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
< -36
< -54
< -55
-41
Spurious emissions,
high-power PA, 10
dBm configuration(1)
(3)
+10 dBm setting(3)
Harmonics,
< -42
high-power PA, 10
dBm configuration(3)
Third harmonic
< -42
dBm
f < 1 GHz, outside restricted bands
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
dBm
dBm
dBm
dBm
dBm
dBm
< –36
< –54
< –55
< –42
< –42
< –42
Spurious emissions,
regular PA
+5 dBm setting
Harmonics,
regular PA
Third harmonic
(1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at the upper Bluetooth Low Energy channel(s).
(2) To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. The CC2651P3 LaunchPad
reference design should also be reviewed as the filter provides higher attenuation of harmonics compared to the CC26x1-P3EM-XD24-
PA24 reference design.
(3) Measured on evaluation board as described in www.ti.com/lit/pdf/swra636.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
General Parameters
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receiver sensitivity
Receiver sensitivity
Receiver saturation
Adjacent channel rejection
Differential mode PER = 1%
dBm
dBm
dBm
dB
–100
-99
Single-Ended mode. Measured on CC26x1-P3EM-5XS24 at
the SMA connector. PER = 1%
PER = 1%
> 5
Wanted signal at –82 dBm, modulated interferer at ±5 MHz,
PER = 1%
36
Wanted signal at –82 dBm, modulated interferer at ±10
MHz, PER = 1%
Alternate channel rejection
57
59
dB
dB
Wanted signal at –82 dBm, undesired signal is IEEE
802.15.4 modulated channel, stepped through all channels
2405 to 2480 MHz, PER = 1%
Channel rejection, ±15 MHz or more
Blocking and desensitization,
5 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
57
63
63
66
60
60
63
65
dB
dB
Blocking and desensitization,
10 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
Blocking and desensitization,
20 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Blocking and desensitization,
50 MHz from upper band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–5 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–10 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–20 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Blocking and desensitization,
–50 MHz from lower band edge
Wanted signal at –97 dBm (3 dB above the sensitivity
level), CW jammer, PER = 1%
dB
Spurious emissions, 30 MHz to 1000
MHz
Measurement in a 50-Ω single-ended load(1)
Measurement in a 50-Ω single-ended load(1)
–66
–53
dBm
dBm
ppm
ppm
Spurious emissions, 1 GHz to 12.75
GHz
Difference between the incoming carrier frequency and the
internally generated carrier frequency
Frequency error tolerance
Symbol rate error tolerance
> 350
> 1000
Difference between incoming symbol rate and the internally
generated symbol rate
RSSI dynamic range
RSSI accuracy
95
±4
dB
dB
(1) Suitable for systems targeting compliance with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is
measured at a dedicated antenna connection. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
General Parameters
Max output power, high
power PA
20
6
dBm
dB
Differential mode, delivered to a single-ended 50-Ωload through a balun
Differential mode, delivered to a single-ended 50-Ωload through a balun
Output power
programmable range,
high power PA
Max output power, high
power PA, 10 dBm
configuration(4)
10.5
9
dBm
dBm
Differential mode, delivered to a single-ended 50-Ωload through a balun
Max output power, high
power PA, 10 dBm
configuration(4)
Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50-
Ωload through a balun
Output power
programmable range,
high power PA, 10 dBm
configuration(4)
5
dB
Differential mode, delivered to a single-ended 50-Ωload through a balun
Max output power,
regular PA
5
dBm
dB
Differential mode, delivered to a single-ended 50-Ωload through a balun
Differential mode, delivered to a single-ended 50-Ωload through a balun
Output power
programmable range,
regular PA
26
Spurious emissions and harmonics
f < 1 GHz, outside restricted
< -39
dBm
bands
Spurious emissions,
high-power PA(2)
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
< -49
-40
dBm
dBm
dBm
dBm
+20 dBm setting
-35
Harmonics,
high-power PA(3)
Third harmonic
-42
f < 1 GHz, outside restricted
bands
< -36
dBm
Spurious emissions,
high-power PA, 10 dBm
configuration(2) (4)
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
< -47
< -55
-42
dBm
dBm
dBm
dBm
+10 dBm setting(4)
Harmonics,
< -42
high-power PA, 10 dBm
configuration(4)
Third harmonic
< -42
< -36
dBm
dBm
f < 1 GHz, outside restricted
bands
Spurious emissions,
regular PA (1)
f < 1 GHz, restricted bands ETSI
f < 1 GHz, restricted bands FCC
f > 1 GHz, including harmonics
Second harmonic
< -47
< -55
dBm
dBm
dBm
dBm
dBm
+5 dBm setting
< –42
< -42
Harmonics,
regular PA
Third harmonic
< -42
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector magnitude,
+20 dBm setting
2
2
2
%
%
%
high power PA
Error vector magnitude,
high power PA, 10 dBm
+10 dBm setting
+5 dBm setting
configuration(4)
Error vector magnitude
Regular PA
(1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at 2480 MHz.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
(2) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than
100% duty cycle may be used when operating at the upper 802.15.4 channel(s).
(3) To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. The CC2651P3 LaunchPad
reference design should also be reviewed as the filter provides higher attenuation of harmonics compared to the CC26x1-
P3EM-7XD24-PA24 reference design.
(4) Measured on evaluation board as described in https://www.ti.com/lit/pdf/swra636.
8.14 Timing and Switching Characteristics
8.14.1 Reset Timing
PARAMETER
MIN
TYP
MAX
UNIT
RESET_N low duration
1
µs
8.14.2 Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not
include software overhead.
PARAMETER
TEST CONDITIONS
MIN
TYP
850 - 4000
850 - 4000
160
MAX
UNIT
MCU, Reset to Active(1)
µs
µs
µs
µs
µs
MCU, Shutdown to Active(1)
MCU, Standby to Active
MCU, Active to Standby
MCU, Idle to Active
36
14
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has
been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value.
8.14.3 Clock Specifications
8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
MAX
UNIT
Crystal frequency
48
MHz
Equivalent series resistance
6 pF < CL ≤9 pF
ESR
ESR
20
60
80
Ω
Equivalent series resistance
5 pF < CL ≤ 6 pF
Ω
Motional inductance, relates to the load capacitance that is used for the crystal (CL
in Farads)(5)
2
LM
CL
< 3 × 10–25 / CL
H
Crystal load capacitance(4)
Start-up time(2)
5
7(3)
9
pF
µs
200
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device.
(2) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
(3) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG).
(4) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with
certain regulations. See the device errata for further details.
(5) The crystal manufacturer's specification must satisfy this requirement for proper operation.
8.14.3.2 48 MHz RC Oscillator (RCOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
MHz
%
Frequency
48
Uncalibrated frequency accuracy
Calibrated frequency accuracy(1)
Start-up time
±1
±0.25
5
%
µs
(1) Accuracy relative to the calibration source (XOSC_HF)
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.14.3.3 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
32.768
30
MAX
UNIT
kHz
kΩ
Crystal frequency
ESR
CL
Equivalent series resistance
Crystal load capacitance
100
12
6
7(1)
pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be
used.
8.14.3.4 32 kHz RC Oscillator (RCOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Calibrated frequency
Calibrated
32.8
kHz
RTC
Calibrated periodically against XOSC_HF(2)
±600(3)
50
ppm
variation(1)
Temperature coefficient.
ppm/°C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time
Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This
functionality is available through the TI-provided Power driver.
(2) TI driver software calibrates the RTC every time XOSC_HF is enabled.
(3) Some device's variation can exceed 1000 ppm. Further calibration will not improve variation.
8.14.4 Synchronous Serial Interface (SSI) Characteristics
8.14.4.1 Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PARAMETER
MIN
TYP
MAX
UNIT
NO.
S1
tclk_per
tclk_high
tclk_low
SSIClk cycle time
12
65024
System Clocks (2)
tclk_per
S2(1)
S3(1)
SSIClk high time
SSIClk low time
0.5
0.5
tclk_per
(1) Refer to SSI timing diagrams 图8-1, 图8-2, and 图8-3.
(2) When using the TI-provided Power driver, the SSI system clock is always 48 MHz.
S1
S2
SSIClk
S3
SSIFss
SSITx
MSB
LSB
SSIRx
4 to 16 bits
图8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
S2
SSIClk
S3
S1
SSIFss
MSB
LSB
SSITx
SSIRx
8-bit control
0
MSB
LSB
4 to 16 bits output data
图8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
S1
S2
SSIClk
(SPO = 0)
S3
SSIClk
(SPO = 1)
SSITx
(Master)
MSB
LSB
SSIRx
(Slave)
MSB
LSB
SSIFss
图8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
8.14.5 UART
8.14.5.1 UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
UART rate
3
MBaud
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.15 Peripheral Characteristics
8.15.1 ADC
8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
Input voltage range
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0
VDDS
12
Bits
ksps
LSB
LSB
LSB
LSB
Sample Rate
200
Offset
Internal 4.3 V equivalent reference(2)
–0.24
7.14
>–1
±4
Gain error
Internal 4.3 V equivalent reference(2)
DNL(4)
INL
Differential nonlinearity
Integral nonlinearity
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone, DC/DC enabled
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
ENOB
Effective number of bits
Bits
11.1
Internal reference, voltage scaling disabled,
11.3
11.6
14-bit mode, 200 kSamples/s, 300 Hz input tone (5)
Internal reference, voltage scaling disabled,
15-bit mode, 200 kSamples/s, 300 Hz input tone (5)
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
–65
–70
–72
THD
Total harmonic distortion
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
dB
dB
Internal reference, voltage scaling disabled,
32 samples average, 200 kSamples/s, 300 Hz input tone
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
60
63
Signal-to-noise
and
distortion ratio
SINAD,
SNDR
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
68
Internal 4.3 V equivalent reference(2), 200 kSamples/s,
9.6 kHz input tone
70
73
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
SFDR
Spurious-free dynamic range
dB
Internal reference, voltage scaling disabled,
32 samples average (software), 200 kSamples/s, 300 Hz input
tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
Internal 4.3 V equivalent reference(2)
VDDS as reference
50
0.39
0.56
Clock Cycles
Current consumption
Current consumption
mA
mA
Equivalent fixed internal reference (input voltage scaling
enabled). For best accuracy, the ADC conversion should be
initiated through the TI-RTOS API in order to include the gain/
offset compensation factors stored in FCFG1
Reference voltage
4.3(2) (3)
V
Fixed internal reference (input voltage scaling disabled). For
best accuracy, the ADC conversion should be initiated through
the TI-RTOS API in order to include the gain/offset
compensation factors stored in FCFG1. This value is derived
from the scaled value (4.3 V) as follows:
Reference voltage
1.48
V
Vref = 4.3 V × 1408 / 4095
Reference voltage
Reference voltage
VDDS as reference, input voltage scaling enabled
VDDS as reference, input voltage scaling disabled
VDDS
V
V
VDDS /
2.82(3)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance depends on sampling frequency and sampling
time
Input impedance
>1
MΩ
(1) Using IEEE Std 1241-2010 for terminology and test methods
(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V
(3) Applied voltage must be within Absolute Maximum Ratings at all times
(4) No missing codes
(5) ADC_output = Σ(4n samples ) >> n, n = desired extra bits
8.15.2 DAC
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
General Parameters
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
8
Bits
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
1.8
2.0
3.8
3.8
External Load(4), any VREF, pre-charge OFF, DAC charge-pump
OFF
VDDS
Supply voltage
V
Any load, VREF = DCOUPL, pre-charge ON
Buffer ON (recommended for external load)
Buffer OFF (internal load)
2.6
16
16
3.8
250
FDAC
Clock frequency
kHz
1000
VREF = VDDS, buffer OFF, internal load
VREF = VDDS, buffer ON, external capacitive load = 20 pF(3)
13
13.8
20
Voltage output settling time
1 / FDAC
External capacitive load
External resistive load
Short circuit current
200
400
pF
MΩ
µA
10
VDDS = 3.8 V, DAC charge-pump OFF
VDDS = 3.0 V, DAC charge-pump ON
VDDS = 3.0 V, DAC charge-pump OFF
VDDS = 2.0 V, DAC charge-pump ON
VDDS = 2.0 V, DAC charge-pump OFF
VDDS = 1.8 V, DAC charge-pump ON
VDDS = 1.8 V, DAC charge-pump OFF
50.8
51.7
53.2
48.7
70.2
46.3
88.9
Max output impedance Vref =
VDDS, buffer ON, CLK 250
kHz
ZMAX
kΩ
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
FDAC = 250 kHz
Differential nonlinearity
Differential nonlinearity
±1
DNL
LSB(1)
VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked
Comparator
±1.2
FDAC = 16 kHz
VREF = VDDS = 3.8 V
±0.64
±0.81
±1.27
±3.43
±2.88
±2.37
VREF = VDDS= 3.0 V
Offset error(2)
Load = Continuous Time
Comparator
VREF = VDDS = 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.78
±0.77
±3.46
±3.44
±4.70
±4.11
±1.53
±1.71
±2.10
±6.00
±3.85
±5.84
±2.92
±3.06
±3.91
±7.84
±4.06
±6.94
0.03
MAX
UNIT
VREF = VDDS= 3.8 V
VREF = VDDS = 3.0 V
VREF = VDDS= 1.8 V
Offset error(2)
Load = Low Power Clocked
Comparator
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V
VREF = VDDS = 3.0 V
Max code output voltage
variation(2)
Load = Continuous Time
Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF =VDDS= 3.0 V
Max code output voltage
variation(2)
Load = Low Power Clocked
Comparator
VREF = VDDS= 1.8 V
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
3.62
0.02
2.86
0.01
Output voltage range(2)
Load = Continuous Time
Comparator
1.71
V
0.01
1.21
1.27
2.46
0.01
VREF = ADCREF, code 255
1.41
VREF = VDDS = 3.8 V, code 1
VREF = VDDS= 3.8 V, code 255
VREF = VDDS= 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS = 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
0.03
3.61
0.02
2.85
0.01
Output voltage range(2)
Load = Low Power Clocked
Comparator
1.71
V
0.01
1.21
1.27
2.46
0.01
VREF = ADCREF, code 255
1.41
External Load (Keysight 34401A Multimeter)
VREF = VDDS, FDAC = 250 kHz
±1
±1
±1
±1
INL
Integral nonlinearity
VREF = DCOUPL, FDAC = 250 kHz
VREF = ADCREF, FDAC = 250 kHz
VREF = VDDS, FDAC = 250 kHz
LSB(1)
LSB(1)
DNL
Differential nonlinearity
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
±0.20
±0.25
±0.45
±1.55
±1.30
±1.10
±0.60
±0.55
±0.60
±3.45
±2.10
±1.90
0.03
MAX
UNIT
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS = 1.8 V
Offset error
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS= 3.8 V
VREF = VDDS= 3.0 V
VREF = VDDS= 1.8 V
Max code output voltage
variation
LSB(1)
VREF = DCOUPL, pre-charge ON
VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS = 3.0 V, code 1
VREF = VDDS= 3.0 V, code 255
VREF = VDDS= 1.8 V, code 1
VREF = VDDS = 1.8 V, code 255
VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
3.61
0.02
2.85
0.02
Output voltage range
Load = Low Power Clocked
Comparator
1.71
V
0.02
1.20
1.27
2.46
0.02
VREF = ADCREF, code 255
1.42
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.15.3 Temperature and Battery Monitor
8.15.3.1 Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
°C
Resolution
Accuracy
Accuracy
2
-40 °C to 0 °C
0 °C to 105 °C
±4.0
±2.5
3.9
°C
°C
Supply voltage coefficient(1)
°C/V
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
8.15.3.2 Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
V
Resolution
Range
25
1.8
3.8
Integral nonlinearity (max)
Accuracy
23
22.5
-32
-1
mV
mV
mV
%
VDDS = 3.0 V
Offset error
Gain error
8.15.4 Comparator
8.15.4.1 Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input voltage range(1)
0
VDDS
Offset
Measured at VDDS / 2
Step from –10 mV to 10 mV
Internal reference
±5
0.78
9.2
mV
µs
Decision time
Current consumption
µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.15.5 GPIO
8.15.5.1 GPIO DC Characteristics
PARAMETER
TA = 25 °C, VDDS = 1.8 V
TEST CONDITIONS
MIN
TYP
MAX UNIT
GPIO VOH at 8 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
1.56
0.24
1.59
0.21
73
V
V
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
V
GPIO VOL at 4 mA load
IOCURR = 1
V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
µA
µA
V
GPIO pulldown current
19
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.08
0.73
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
0.35
V
TA = 25 °C, VDDS = 3.0 V
GPIO VOH at 8 mA load
GPIO VOL at 8 mA load
GPIO VOH at 4 mA load
GPIO VOL at 4 mA load
IOCURR = 2, high-drive GPIOs only
IOCURR = 2, high-drive GPIOs only
IOCURR = 1
2.59
0.42
2.63
0.40
V
V
V
V
IOCURR = 1
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
MAX UNIT
8.15.5.1 GPIO DC Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
TA = 25 °C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
282
110
µA
µA
V
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
IH = 1, transition voltage for input read as 0 →1
IH = 1, transition voltage for input read as 1 →0
GPIO low-to-high input transition, with hysteresis
GPIO high-to-low input transition, with hysteresis
1.97
1.55
V
IH = 1, difference between 0 →1
and 1 →0 points
GPIO input hysteresis
TA = 25 °C
0.42
V
Lowest GPIO input voltage reliably interpreted as a
High
VIH
0.8*VDDS
V
Highest GPIO input voltage reliably interpreted as a
Low
VIL
0.2*VDDS
V
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.16 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See
Recommended Operating Conditions, 节 8.3, for device limits. Values exceeding these limits are for reference
only.
8.16.1 MCU Current
图8-4. Active Mode (MCU) Current vs. Supply
图8-5. Standby Mode (MCU) Current vs.
Voltage (VDDS)
Temperature
8.16.2 RX Current
图8-7. RX Current vs. Supply Voltage (VDDS) (BLE
图8-6. RX Current vs. Temperature (BLE 1 Mbps,
1 Mbps, 2.44 GHz)
2.44 GHz)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.16.3 TX Current
TX Current vs. Temperature
TX Current vs. Temperature
BLE 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V
Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm
25
24
23
22
21
20
19
18
17
130
125
120
115
110
105
100
95
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
90
85
80
75
70
65
60
55
50
45
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [C]
40
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110
Temperature [°C]
D020
图8-8. TX Current vs. Temperature (BLE 1 Mbps,
图8-9. TX Current vs. Temperature (BLE 1 Mbps,
2.44 GHz)
2.44 GHz, VDDS = 3.3 V)
TX Current vs. VDDS
TX Current vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA
Bluetooth Low Energy 1 Mbps 2.44GHz, + 10 dBm PA
45
40
35
30
25
20
15
10
33
+10 dBm
+9 dBm
+8 dBm
30
+7 dBm
+6 dBm
27
24
21
18
15
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
图8-11. TX Current vs. Supply Voltage (VDDS)
Temperature [°C]
(BLE 1 Mbps, 2.44 GHz)
图8-10. TX Current vs. Temperature (250 kbps,
2.44 GHz, +10 dBm PA)
TX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz, +20 dBm PA
TX Current vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA
120
50
116
112
108
104
100
96
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
+10 dBm
+9 dBm
45
+ 8dBm
+7 dBm
+6 dBm
40
35
30
25
20
15
10
92
88
84
80
76
72
68
64
60
56
52
48
44
40
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
Voltage [V]
D025
Voltage [V]
图8-12. TX Current vs. Supply Voltage (VDDS)
图8-13. TX Current vs. Supply Voltage (VDDS) (250
(BLE 1 Mbps, 2.44 GHz, +20 dBm PA)
kbps, 2.44 GHz, +10 dBm PA)
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
表8-1. Typical TX Current and Output Power, regular PA
CC2651P3 at 2.4 GHz, VDDS = 3.0 V (Measured on CC2651-P3EM-7XD24-PA24)
txPower
0x701F
0x3A17
0x3A64
0x325F
0x2C5C
0x2659
0x1697
0x1693
0x1292
0xCD3
0xAD1
0xACF
0x6CD
0x6CA
0x4C8
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
5
4
5.5
4.5
12.5
11.9
11.2
10.8
10.5
10.2
9.4
3
3.1
2
2.0
1
1.3
0
0.4
-3
-5
-6
-9
-10
-12
-15
-18
-20
-2.8
-4.8
-5.4
-9.0
-10.4
-12.0
-13.7
-16.8
-19.3
8.9
8.8
8.4
8.2
8.1
7.9
7.7
7.6
表8-2. Typical TX Current and Output Power, high power PA, 10 dBm mode
CC2651P3 at 2.4 GHz, VDDS = 3.0 V (Measured on CC261-P3EM-5XS24-PA24_10dBm)
txPower
0x14395A
0x142F55
0x62F35
0x63930
0x6292B
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
10
9
10.1
9.0
7.8
6.9
5.9
23.6
22.1
21.1
20.1
19.1
8
7
6
表8-3. Typical TX Current and Output Power, high power PA, 20 dBm mode
CC2651P3 at 2.4 GHz, VDDS = 3.3 V (Measured on CC2651-P3EM-7XD24-PA24)
txPower
0x3F75F5
0x3F61E2
0x3047E0
0x1B4FE5
0x1B39DE
0x1B2FDA
0x1B27D6
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
20
19
18
17
16
15
14
20.0
19.4
19.0
18.1
17.3
16.7
15.9
100.1
91.1
86.4
78.3
71.8
67.1
61.8
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.16.4 RX Performance
Sensitivity vs. Frequency
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps)
Sensitivity vs. Frequency
BLE 1 Mbps, 2.44 GHz
-95
-96
-92
-93
-97
-94
-95
-98
-96
-99
-97
-100
-101
-102
-103
-104
-105
-98
-99
-100
-101
-102
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
2.4
2.408
2.416
2.424
2.432
2.44
2.448
2.456
2.464
2.472
2.48
Frequency [GHz]
Frequency [GHz]
D028
D029
图8-14. Sensitivity vs. Frequency (BLE 1 Mbps,
图8-15. Sensitivity vs. Frequency (250 kbps, 2.44
2.44 GHz)
GHz)
Sensitivity vs. Temperature
BLE 1 Mbps, 2.44 GHz
Sensitivity vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-92
-93
-95
-96
-94
-97
-98
-95
-99
-96
-100
-101
-102
-103
-104
-105
-97
-98
-99
-100
-101
-102
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
Temperature [°C]
D032
D031
图8-17. Sensitivity vs. Temperature (250 kbps, 2.44
图8-16. Sensitivity vs. Temperature (BLE 1 Mbps,
GHz)
2.44 GHz)
Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz
Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz, DCDC Off
-92
-93
-92
-93
-94
-94
-95
-95
-96
-96
-97
-97
-98
-98
-99
-99
-100
-101
-102
-100
-101
-102
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Voltage [V]
D034
D035
图8-18. Sensitivity vs. Supply Voltage (VDDS) (BLE 图8-19. Sensitivity vs. Supply Voltage (VDDS) (BLE
1 Mbps, 2.44 GHz) 1 Mbps, 2.44 GHz, DCDC Off)
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
Sensitivity vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D036
图8-20. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.16.5 TX Performance
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, 0 dBm
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, +5 dBm
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
0.8
0.6
0.4
0.2
0
4.8
4.6
4.4
4.2
4
-0.2
-0.4
-0.6
-0.8
-1
3.8
3.6
3.4
3.2
3
-1.2
-1.4
-1.6
-1.8
-2
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
Temperature [°C]
D042
D041
图8-22. Output Power vs. Temperature (BLE 1
图8-21. Output Power vs. Temperature (BLE 1
Mbps, 2.44 GHz, +5 dBm)
Mbps, 2.44 GHz)
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V
Output Power vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA
26
14
+20 dBm
+19 dBm
+10 dBm
+9 dBm
13
24
22
20
18
16
14
12
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
+8 dBm
+7 dBm
+6 dBm
12
11
10
9
8
7
6
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D043
Temperature [°C]
图8-23. Output Power vs. Temperature (BLE 1
图8-24. Output Power vs. Temperature (2.44 GHz,
Mbps, 2.44 GHz, +20 dBm PA)
+10 dBm PA)
Output Power vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
Output power vs. VDDS
BLE 1 Mbps, 2.44 GHz, +5 dBm
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
0.8
0.6
0.4
0.2
0
5.8
5.6
5.4
5.2
5
-0.2
-0.4
-0.6
-0.8
-1
4.8
4.6
4.4
4.2
4
-1.2
-1.4
-1.6
-1.8
-2
3.8
3.6
3.4
3.2
3
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
Voltage [V]
D046
D048
图8-25. Output Power vs. Supply Voltage (VDDS) 图8-26. Output Power vs. Supply Voltage (VDDS)
(BLE 1 Mbps, 2.44 GHz) (BLE 1 Mbps, 2.44 GHz, +5 dBm)
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
Output power vs. VDDS
BLE 1 Mbps, 2.44 GHz, +20 dBm PA
Output Power vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA
22
20
18
16
14
12
10
14
+20 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
+10 dBm
+9 dBm
+8dBm
13.5
13
12.5
12
+7 dBm
+6 dBm
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D050
Voltage [V]
图8-27. Output Power vs. Supply Voltage (VDDS)
图8-28. Output Power vs. Supply Voltage (VDDS)
(BLE 1 Mbps, 2.44 GHz, +20 dBm PA)
(2.44 GHz, +10 dBm PA)
Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, 0 dBm
Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, +5 dBm
2
1.8
1.6
1.4
1.2
1
7
6.8
6.6
6.4
6.2
6
0.8
0.6
0.4
0.2
0
5.8
5.6
5.4
5.2
5
-0.2
-0.4
-0.6
-0.8
-1
4.8
4.6
4.4
4.2
4
-1.2
-1.4
-1.6
-1.8
-2
3.8
3.6
3.4
3.2
3
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
Frequency [GHz]
D058
D059
图8-29. Output Power vs. Frequency (BLE 1 Mbps, 图8-30. Output Power vs. Frequency (BLE 1 Mbps,
2.44 GHz)
2.44 GHz, +5 dBm)
Output Power vs. Frequency
BLE 1 Mbps, +20 dBm PA, VDDS = 3.3 V
Output Power vs. Frequency
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), +10 dBm PA
25
24
23
22
21
20
19
18
17
16
15
14
13
14
13
12
11
10
9
+20 dBm
+10 dBm
+9 dBm
+ 8dBm
+7 dBm
+6 dBm
+19 dBm
+18 dBm
+17 dBm
+16 dBm
+15 dBm
+14 dBm
8
7
6
5
2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
2405
2415
2425
2435
2445
2455
2465
2475 2480
Frequency [GHz]
D060
Frequency [MHz]
图8-31. Output Power vs. Frequency (BLE 1 Mbps,
图8-32. Output Power vs. Frequency (250 kbps,
2.44 GHz, +20 dBm PA)
+10 dBm PA)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
8.16.6 ADC Performance
ENOB vs. Input Frequency
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference,
Fin = Fs / 10
11.4
11.1
10.8
10.5
10.2
9.9
Internal Reference, No Averaging
Internal Unscaled Reference, 14-bit Mode
10.2
10.15
10.1
10.05
10
9.95
9.9
9.85
9.8
9.6
1
2
3
4
5
6
7 8 10
20
30 40 50 70 100
200
0.2 0.3
0.5 0.7
1
2
3
4
5
6 7 8 10
20
30 40 50 70 100
Frequency [kHz]
Frequency [kHz]
D062
D061
图8-34. ENOB vs. Sampling Frequency
图8-33. ENOB vs. Input Frequency
INL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference,
200 kSamples/s
1.5
1
2.5
2
0.5
0
1.5
1
-0.5
-1
0.5
0
-1.5
-0.5
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
0
400
800
1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
ADC Code
D064
D065
图8-35. INL vs. ADC Code
图8-36. DNL vs. ADC Code
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference,
200 kSamples/s
ADC Accuracy vs. Temperature
Vin = 1 V, Internal reference,
200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Temperature [°C]
Voltage [V]
D066
D067
图8-37. ADC Accuracy vs. Temperature
图8-38. ADC Accuracy vs. Supply Voltage (VDDS)
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9 Detailed Description
9.1 Overview
节4 shows the core modules of the CC2651P3 device.
9.2 System CPU
The CC2651P3 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4 system CPU, which runs the
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
• ARMv7-M architecture optimized for small-footprint embedded applications
• Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
• Fast code execution permits increased sleep mode time
• Deterministic, high-performance interrupt handling for time-critical applications
• Single-cycle multiply instruction and hardware divide
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
• Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
• Optimized for single-cycle flash memory access
• Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
• Ultra-low-power consumption with integrated sleep modes
• 48 MHz operation
• 1.25 DMIPS per MHz
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that
interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and
assembles the information bits in a given packet structure. The RF core offers a high level, command-based API
to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not
programmable by customers and is interfaced through the TI-provided RF driver that is included with the
SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main
CPU, which reduces power and leaves more resources for the user application. Several signals are also
available to control external circuitry such as RF switches or range extenders autonomously.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is
either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with
the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards
even with over-the-air (OTA) updates while still using the same silicon.
9.3.1 Bluetooth 5.2 Low Energy
The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-sped 2-Mbps physical layer and
the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or
through a high-level Bluetooth API.
The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times
the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers
significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.
Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application needs,
which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2
Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not
previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster
responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates.
9.3.2 802.15.4 (Zigbee and 6LoWPAN)
Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2
Mchips per second Offset-QPSK with DSSS 1:8), used in Zigbee and 6LoWPAN protocols. TI provides royalty-
free protocol stacks for Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution.
Copyright © 2022 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-
system programmable and erasable. The last flash memory sector must contain a Customer Configuration
section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is
done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is a single 32-KB block and can be used for both storage of
data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and
included in Standby mode power consumption numbers.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way
nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU.
The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area
(CCFG).
The ROM contains a serial (SPI and UART) bootloader that can be used for initial programming of the device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.5 Cryptography
The CC2651P3 device comes with a wide set of cryptography-related hardware accelerators, reducing code
footprint and execution time for cryptographic operations. It also has the benefit of being lower power and
improves availability and responsiveness of the system because the cryptography operations run in a
background hardware thread.
The hardware accelerator modules are:
• True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the
purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is
built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit.
• Advanced Encryption Standard (AES) with 128 bit key lengths
Together with the hardware accelerator module, a large selection of open-source cryptography libraries provided
with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily
built on top of the platform. The TI provided cryptography drivers are:
• Key Agreement Schemes
– Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE)
• Signature Generation
– Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA)
• Curve Support
– Short Weierstrass form (full hardware support), such as:
• NIST-P256
– Montgomery form (hardware support for multiplication), such as:
• Curve25519
• Hash
– SHA256
• MACs
– HMAC with SHA256
– AES CBC-MAC
• Block ciphers
– AESECB
– AESCBC
– AESCTR
• Authenticated Encryption
– AESCCM
• Random number generation
– True Random Number Generator
– AES CTR DRBG
Copyright © 2022 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.6 Timers
A large selection of timers are available as part of the CC2651P3 device. These timers are:
• Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF)
This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for
frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with
frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this.
When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be
accessed through the kernel APIs such as the Clock module. By default, the RTC halts when a debugger
halts the device.
• General Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48
MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting,
pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of
the timer are connected to the device event fabric, which allows the timers to interact with signals such as
GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
• Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is
typically used as the timing base in wireless network communication using the 32-bit timing word as the
network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device
radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running
when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in
the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the
source of SCLK_HF.
• Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is
typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the
system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock
rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and
when a debugger halts the device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.7 Serial Peripherals and I/O
The SSI is a synchronous serial interface that is compatible with SPI, MICROWIRE, and TI's synchronous serial
interfaces. The SSI support both SPI master and slave up to 4 MHz. The SSI module support configurable phase
and polarity.
The UART implement universal asynchronous receiver and transmitter functions. It support flexible baud-rate
generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation
microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface
can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals
to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a
programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge
(configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs
have high-drive capabilities, which are marked in bold in 节 7. All digital peripherals can be connected to any
digital pin on the device.
For more information, see the CC13x1x3, CC26x1x3 SimpleLink™ Wireless MCU Technical Reference Manual.
9.8 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2651P3 device. The battery and
temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and
respond to changes in environmental conditions as needed. The module contains window comparators to
interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can
also be used to wake up the device from Standby mode through the Always-On (AON) event fabric.
9.9 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload
data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available
bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA
controller has dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list):
• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits
• Ping-pong mode for continuous streaming of data
9.10 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.
The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
Copyright © 2022 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.11 Power Management
To minimize power consumption, the CC2651P3 supports a number of power modes and power management
features (see 表9-1).
表9-1. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
MODE
ACTIVE
Active
On
IDLE
Off
STANDBY
Off
SHUTDOWN
CPU
Off
Off
Off
Off
No
No
Off
Off
Off
Off
No
No
Flash
Available
On
Off
SRAM
On
Retention
Duty Cycled
Partial
Full
Supply System
Register and CPU retention
SRAM retention
On
On
Full
Full
Full
Full
48 MHz high-speed clock
(SCLK_HF)
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off
Off
Off
Off
Off
32 kHz low-speed clock
(SCLK_LF)
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Peripherals
Available
Available
Available
On
Available
Available
Available
On
Off
Available
Available
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Wake-up on RTC
Wake-up on pin edge
Wake-up on reset pin
Brownout detector (BOD)
Power-on reset (POR)
Watchdog timer (WDT)
Available
On
On
On
Duty Cycled
On
Off
On
On
Off
Available
Available
Paused
Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation
of the processor and all of the peripherals that are currently enabled. The system clock can be any available
clock source (see 表9-1).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked
and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event or RTC event is
required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured
when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are
latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with
the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from
shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in
this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in
this mode is the latched I/O state and the flash memory contents.
备注
The power, RF and clock management for the CC2651P3 device require specific configuration and
handling by software for optimized performance. This configuration and handling is implemented in the
TI-provided drivers that are part of the CC2651P3 software development kit (SDK). Therefore, TI
highly recommends using this software framework for all application development on the device. The
complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in
source code.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
9.12 Clock Systems
The CC2651P3 device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the
internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation
requires an external 48 MHz crystal.
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used for the RTC and to synchronize
the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC
Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other
devices, thereby reducing the overall system cost.
9.13 Network Processor
Depending on the product configuration, the CC2651P3 device can function as a wireless network processor
(WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as
a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case,
the application must be written according to the application framework supplied with the wireless protocol stack.
Copyright © 2022 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
10 Application, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware
Configuration and PCB Design Considerations Application Report.
For optimum RF performance, especially when using the high-power PA, it is important to accurately follow the
reference design with respect to component values and layout. Failure to do so may lead to reduced RF
performance due to balun mismatch. The amplitude- and phase balance through the balun must be <1 dB and
<6 degrees, respectively.
PCB stack-up is also critical for proper operation. The CC2651P3 EVMs and characterization boards use a
finished thickness between the top layer (RF signals) and layer 2 (ground plane) of 175 µm. It is very important
to use the same substrate thickness, or slightly thicker, in an end product implementing the CC2651P3 device.
10.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2651P3
device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator
components, as well as ground connections for all of these.
CC26x1-P3EM-5XS24-
PA24_10dBm Design
Files
The CC26x1PEM-5XS24-PA24_10dBm reference design provides schematic, layout
and production files for the characterization board used for deriving the performance
number found in this document. This design is optimized for operating the high power
PA at 10 dBm output power and is using a single-ended front-end configuration with
external LNA bias for RX.
CC26x1-P3EM-7XD24-
PA24 Design Files
The CC26x1-P3EM-7XD24-PA24 reference design provides schematic, layout and
production files for the characterization board used for deriving the performance
number found in this document. This design is configured for 20 dBm operation on the
high output power PA.
LP-CC2651P3 Design
Files
The CC2651P3 LaunchPad Design Files contain detailed schematics and layouts to
build application specific boards using the CC2651P3 device.
Sub-1 GHz and 2.4 GHz
Antenna Kit for LaunchPad™
Development Kit and
SensorTag
The antenna kit allows real-life testing to identify the optimal antenna for your
application. The antenna kit includes 16 antennas for frequencies from 169 MHz
to 2.4 GHz, including:
• PCB antennas
• Helical antennas
• Chip antennas
• Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU
LaunchPad Development Kits and SensorTags.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed as follows.
11.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-
code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, XCC2651P3 is
in preview; therefore, an X prefix/identification is assigned).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, RGZ).
For orderable part numbers of CC2651P3 devices in the RGZ (7-mm x 7-mm) package type, see the Package
Option Addendum of this document, the Device Information in 节 3, the TI website (www.ti.com), or contact your
TI sales representative.
CC2651
P
3
1
T
0
RGZ R
PREFIX
X = Experimental device
Blank = Qualified devie
R = Large Reel
PACKAGE
RGZ = 48-pin VQFN (Very Thin Quad Flatpack No-Lead)
RKP = 40-pin VQFN (Very Thin Quad Flatpack No-Lead)
DEVICE
SimpleLink™ Ultra-Low-Power
Wireless MCU
PRODUCT REVISION
CONFIGURATION
R = Regular
P = +20 dBm PA included
TEMPERATURE
T = 105 C Ambient
FLASH SIZE
SRAM SIZE
3 = 352 kB
1 = 32kB
图11-1. Device Nomenclature
Copyright © 2022 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
11.2 Tools and Software
The CC2651P3 device is supported by a variety of software and hardware development tools.
Development Kit
CC2651P3
LaunchPad™
Development Kit
The CC2651P3 LaunchPad™ Development Kit enables development of high-performance
wireless applications that benefit from low-power operation. The kit features the
CC2651P3 SimpleLink Wireless MCU, which allows you to quickly evaluate and
prototype 2.4-GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee and
Thread, plus combinations of these. The kit works with the LaunchPad ecosystem, easily
enabling additional functionality like sensors, display and more.
Software
SimpleLink™
CC13XX-
CC26XX SDK
The SimpleLink CC13xx and CC26xx Software Development Kit (SDK) provides a complete
package for the development of wireless applications on the CC13XX / CC26XX family of
devices. The SDK includes a comprehensive software package for the CC2651P3 device,
including the following protocol stacks:
• Bluetooth Low Energy 4 and 5.2
• Thread (based on OpenThread)
• Zigbee 3.0
• Wi-SUN®
• TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and
2.4 GHz
• Proprietary RF - a large set of building blocks for building proprietary RF software
• Multiprotocol support - concurrent operation between stacks using the Dynamic
Multiprotocol Manager (DMM)
The SimpleLink CC13XX-CC26XX SDK is part of TI’s SimpleLink MCU platform, offering a
single development environment that delivers flexible hardware, software and tool options for
customers developing wired and wireless applications. For more information about the
SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
Development Tools
Code Composer
Studio™ Integrated
Development
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and
many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to
get started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse® software framework with advanced embedded debug capabilities from TI resulting
in a compelling feature-rich development environment for embedded developers.
Environment (IDE)
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™
software (application energy usage profiling). A real-time object viewer plugin is available
for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS
debuggers included on a LaunchPad Development Kit.
Code Composer
Studio™ Cloud
IDE
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and
build CCS and Energia™ projects. After you have successfully built your project, you can
download and run on your connected LaunchPad. Basic debugging, including features like
setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded
Workbench® for
Arm®
IAR Embedded Workbench® is a set of development tools for building and debugging
embedded system applications using assembler, C and C++. It provides a completely
integrated development environment that includes a project manager, editor, and build
tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support,
including XDS110, IAR I-jet™ and Segger J-Link™. A real-time object viewer plugin is
available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on
most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRF™ Studio
SmartRF™ Studio is a Windows® application that can be used to evaluate and configure
SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of
RF systems to easily evaluate the radio at an early stage in the design process. It is
especially useful for generation of configuration register values and for practical testing and
debugging of the RF system. SmartRF Studio can be used either as a standalone
application or together with applicable evaluation boards or debug probes for the RF
device. Features of the SmartRF Studio include:
• Link tests - send and receive packets between nodes
• Antenna and radiation tests - set the radio in continuous wave TX and RX states
• Export radio configuration code for use with the TI SimpleLink SDK RF driver
• Custom GPIO configuration for signaling and control of external switches
CCS UniFlash
CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs.
UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free
of charge.
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
11.2.1 SimpleLink™ Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired
and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible
hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software
development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
11.3 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate
to the device product folder on ti.com/product/CC2651P3. In the upper right corner, click on Alert me to register
and receive a weekly digest of any product information that has changed. For change details, review the revision
history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as
follows.
TI Resource Explorer
TI Resource Explorer
Software examples, libraries, executables, and documentation are available for your
device and development board.
Errata
CC2651P3 Silicon
Errata
The silicon errata describes the known exceptions to the functional specifications for
each silicon revision of the device and description on how to recognize a device
revision.
Application Reports
All application reports for the CC2651P3 device are found on the device product folder at: ti.com/product/
CC2651P3/#tech-docs.
Technical Reference Manual (TRM)
CC13x1x, CC26x1x SimpleLink™
Wireless MCU TRM
The TRM provides a detailed description of all modules and
peripherals available in the device family.
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
SimpleLink™, LaunchPad™, Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas
Instruments.
I-jet™ is a trademark of IAR Systems AB.
J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation.
Zigbee® is a registered trademark of Zigbee Alliance Inc.
Bluetooth® is a registered trademark of Bluetooth SIG Inc.
Arm Thumb® is a registered trademark of Arm Limited (or its subsidiaries).
Wi-SUN® is a registered trademark of Wi-SUN Alliance Inc.
Eclipse® is a registered trademark of Eclipse Foundation.
IAR Embedded Workbench® is a registered trademark of IAR Systems AB.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
Windows® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: CC2651P3
CC2651P3
ZHCSQD6 –MARCH 2022
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: CC2651P3
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC2651P31T0RGZR
CC2651P31T0RKPR
ACTIVE
VQFN
VQFN
RGZ
48
40
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
CC2651
P31
Samples
Samples
ACTIVE
RKP
NIPDAU
CC2651
P31
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2651P31T0RGZR
CC2651P31T0RKPR
VQFN
VQFN
RGZ
RKP
48
40
2500
3000
330.0
330.0
16.4
12.4
7.3
5.3
7.3
5.3
1.1
1.1
12.0
8.0
16.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC2651P31T0RGZR
CC2651P31T0RKPR
VQFN
VQFN
RGZ
RKP
48
40
2500
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RKP 40
5 x 5, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229305/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RKP0040B
PLASTIC QUAD FLATPACK- NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
3.6
3.4
(0.1) TYP
11
20
36X 0.4
10
21
41
SYMM
4X
3.6
0.25
0.15
30
40X
1
0.1
C A B
C
PIN1 ID
(OPTIONAL)
40
31
0.05
SYMM
0.5
0.3
40X
4219083/A 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RKP0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (4.8)
3.5)
SYMM
(
40X (0.6)
40X (0.2)
40
31
1
30
36X (0.4)
SYMM
2X
(4.8)
2X (0.6)
2X (0.9)
21
10
(R 0.05) TYP
(Ø 0.2) VIA
11
20
TYP
2X (0.9283)
2X (0.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
SOLDERMASK
EXPOSED
OPENING
METAL
EXPOSED METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219083/A 03/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RKP0040B
PLASTIC QUAD FLATPACK- NO LEAD
2X (4.8)
SYMM
9X
1)
(
40X (0.6)
40X (0.2)
40
31
1
30
36X (0.4)
SYMM
2X
(4.8)
2X
(1.2)
21
10
(R 0.05) TYP
11
20
2X (1.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
74% PRINTED COVERAGE BY AREA
SCALE: 15X
4219083/A 03/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明