CC3220MOD [TI]
SimpleLink™ 32 位 Arm Cortex-M4 Wi-Fi CERTIFIED™ 无线模块;
| 型号： | CC3220MOD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SimpleLink™ 32 位 Arm Cortex-M4 Wi-Fi CERTIFIED™ 无线模块 无线 无线模块 |
| 文件： | 总95页 (文件大小：3848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC3220MOD, CC3220MODA
ZHCSGZ7E –MARCH 2017 –REVISED MAY 2021
CC3220MODx 和CC3220MODAx SimpleLink™ Wi-Fi® CERTIFIED™
无线MCU 模块
• 802.11b/g/n 基站
• 802.11b/g/n 接入点支持多达4 个基站
• Wi-Fi Direct® 客户端和组所有者
• WPA2™ 个人版和企业版安全性：WEP、
WPA™、WPA2 PSK 和WPA2 企业版
(802.1x)、WPA3™ 个人版和企业版
1 特性
• CC3220MODx 无线MCU 模块系列，包含
SimpleLink™ Wi-Fi® 单芯片无线MCU -
CC3220MODS 和CC3220MODAS 模块包含
CC3220SM2ARGK 无线MCU；CC3220MODSF
和CC3220MODASF 模块包含
• IPv4 和IPv6 TCP 与IP 堆栈
CC3220SF12ARGK 无线MCU。完全集成的工业
温度级绿色模块，包括所有必需的时钟、SPI 闪存
和无源器件
• 业界通用BSD 套接字应用编程接口(API)：
– 16 个同步TCP 或UDP 套接字
– 6 个同步TLS 和SSL 套接字
• IP 寻址：具有重复地址检测(DAD) 的
StaticIP、LLA、DHCPv4、DHCPv6
• SimpleLink™ 技术连接管理器，可实现自主
快速的Wi-Fi 连接
• CC3220MODAx 模块包含一体化天线，可轻松集成
到主机系统中
• CC3220MODx 和CC3220MODAx SimpleLink™
Wi-Fi® 无线MCU 片上系统(SoC) 包含支持两种独
立执行环境的单芯片：
• 可通过SmartConfig™ 技术、AP 模式和
– 用户应用专用的Arm® Cortex®-M4 MCU
– 用以运行所有Wi-Fi 和互联网逻辑层的网络处理
器MCU
WPS2 选项灵活配置Wi-Fi
• RESTful API 支持（使用内部HTTP 服务
器）
• 在专用网络处理器上运行的嵌入式网络应用
• 获得FCC、IC、CE、MIC 和SRRC 认证
• Wi-Fi Alliance 成员可以申请Wi-Fi CERTIFIED™ 模
块的证书转让
• 1.27mm 间距QFM 封装，实现轻松组装和低成本
PCB 设计
• 广泛的安全特性：
– 硬件特性：
• 独立执行环境
• 器件身份
• 用于实现高级快速安全性的硬件加密
引擎，其中包括：AES、DES、
3DES、SHA2、MD5、CRC 和校验和
– 初始安全编程：
• 调试安全性
• JTAG 和调试端口处于锁定状态
– 个人和企业Wi-Fi 安全性
– 安全套接字
• 应用MCU 子系统：
– Arm® Cortex®-M4 内核，运行频率80MHz
– 嵌入式存储器：
• CC3220MODS 和CC3220MODAx 型号包含
256KB RAM
• CC3220MODSF 和CC3220MODASF 是基
于闪存的MCU，集成1MB 闪存和256KB
RAM
• 采用ROM 的外设驱动器
– McASP 支持两个I2S 通道
– SD
（SSLv3、TLS1.0、TLS1.1、TLS1.2）
• 网络安全性
– HTTPS 服务器
– SPI
– I2C
– 受信任的根证书目录
– TI 信任根公钥
– UART
– 8 位同步图像接口
• SW IP 保护：
– 安全密钥存储
– 4 个具有16 位PWM
模式的通用计时器(GPT)
– 1 个看门狗计时器模块
– 4 通道、12 位模数转换器(ADC)
– 调试接口：JTAG、cJTAG 和SWD
• Wi-Fi 网络处理器子系统：
– 文件系统安全性
– 软件篡改检测
– 克隆保护
– 安全启动：启动期间验证运行时二进制的
完整性和真实性
• 在专用网络处理器上运行的嵌入式网络应
用：
– Wi-Fi® Internet-on-a chip™ 专用Arm® MCU 可
将Wi-Fi 和互联网协议完全从应用MCU 中转移
– Wi-Fi® 模式：
– 具有动态用户回调的HTTP 和HTTPS 网
络服务器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWRS206
CC3220MOD, CC3220MODA
ZHCSGZ7E –MARCH 2017 –REVISED MAY 2021
www.ti.com.cn
– mDNS、DNS-SD 和DHCP 服务器
– Ping
2 应用
• 物联网(IoT)
• 楼宇自动化
• 恢复机制：可恢复到出厂默认设置或恢复到
完整出厂映像
• 低功耗摄像头
• 恒温器
• 访问控制和电子锁(E-Lock)
• 资产跟踪和实时定位系统(RTLS) 标签
• 云连接
• 互联网网关
• 设备
• 安防系统
• 智能能源
– Wi-Fi TX 功率：
• 1 DSSS 时为17.0dBm
• 54 OFDM 时为13.5dBm
– Wi-Fi RX 灵敏度：
• 1 DSSS 时为–95.0dBm
• 54 OFDM 时为–73.5dBm
– 应用吞吐量：
• UDP：16Mbps
• TCP：13Mbps
• 电源管理子系统：
– 具有宽电源电压范围的
• 工业控制
• 智能插座和仪表计量
• 无线音频
• IP 网络传感器节点
• 医疗设备
集成式直流/直流转换器
• VBAT：2.3V 至3.6V
– 高级低功耗模式：
• 关断：1µA
• 休眠：5µA
• 低功耗深度睡眠(LPDS)：135µA（测试对象
为具有256KB RAM 容量的CC3220MODS
和CC3220MODSF）
• RX 流量（MCU 处于活动模式）：54 OFDM
时为59mA（测试对象为CC3220MODS；
CC3220MODSF 和CC3220MODASF 会额
外消耗
15mA）
• TX 流量（MCU 处于活动模式）：在54
OFDM、最大功耗时为223mA（测试对象为
CC3220MODS；CC3220MODSF 和
CC3220MODASF 会额外消耗
15mA）
• 空闲连接（MCU 处于LPDS 状态）：DTIM
= 1 时为710µA（测试对象为具有256KB
RAM 容量的CC3220MODS 和
CC3220MODSF）
• 其他集成元件：
– 40.0MHz 晶体
– 32.768kHz 晶体(RTC)
– 32 兆位SPI 串行闪存
– 射频滤波器和无源器件
• 尺寸兼容的QFM 封装：
– CC3220MODx：1.27mm 间距、
63 引脚、20.5mm × 17.5mm
– CC3220MODAx：1.27mm 间距、
63 引脚、20.5mm × 25.0mm
• 工作温度：
– 环境温度范围：–40°C 至+85°C
• 模块支持SimpleLink 开发人员生态系统
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3 说明
使用此完全可编程的无线微控制器(MCU) 模块开始您的设计，它经过FCC、IC、CE、MIC 和SRRC 认证，且具
有内置Wi-Fi 连接。德州仪器(TI)™ 的SimpleLink™ CC3220MODx 和CC3220MODAx 模块系列专为物联网而设
计，是集成了两个物理隔离片上MCU 的无线模块。
• 应用处理器Arm® Cortex®-M4 MCU 具有用户专用的256KB RAM（CC3220SF 型号上具有1MB XIP 闪
存）。
• 一个网络处理器MCU，可运行所有Wi-Fi® 和互联网逻辑层。此基于ROM 的子系统包含802.11b/g/n 无线
电、基带和具有强大加密引擎的MAC，采用256 位加密，可实现快速安全的互联网连接。
CC3220MODx 和 CC3220MODAx 无线 MCU 系列属于 TI 第二代 Internet-on-a chip™ 系列解决方案。这一代引
进了可进一步简化互联网连接的新特性和功能。新功能包括：
• IPv6
• 增强的Wi-Fi 配置
• 优化的低功耗管理
• 增强的文件系统安全
• Wi-Fi AP 可连接多达4 个基站
• 可同时打开更多的BSD 套接字—多达16 个BSD 套接字（其中6 个支持安全型HTTPS）
• 支持HTTPS
• 支持RESTful API
• 非对称密钥加密库
CC3220MODx 和CC3220MODAx 无线MCU 系列支持以下模式：基站、AP 和Wi-Fi Direct®。CC3220MODx 和
CC3220MODAx 模块还支持 WPA2 和 WPA3 个人版和企业版安全性。该子系统包含嵌入式 TCP/IP 和 TLS/SSL
堆栈、HTTP 服务器和多个互联网协议。该模块支持多种 Wi-Fi 配置方法，包括基于 AP 模式的 HTTP、
SmartConfig™ 技术和WPS2.0。
电源管理子系统包括支持宽电源电压范围的集成式直流/直流转换器。此子系统支持低功耗深度睡眠、RTC 休眠
（仅消耗5µA）和关断模式（仅消耗
1µA）等低功耗模式，有助于延长电池寿命。
该模块包含多种外设，如快速并行摄像头接口、I2S、SD、UART、SPI、I2C 和4 通道ADC。
SimpleLink CC3220MODx 和 CC3220MODAx 模块系列有 4 个不同的模块型号： CC3220MODS 、
CC3220MODSF、CC3220MODA 和CC3220MODASF。
• CC3220MODS 和CC3220MODAS 模块包含用于处理代码和数据的应用专用型嵌入式RAM (256KB)。此外，
CC3220MODAS 还包含一体式天线。
• CC3220MODSF 和CC3220MODASF 模块包含用于处理代码和数据的应用专用型串行闪存(1MB) 和RAM
(256KB)。此外，CC3220MODASF 还包含一体式天线。
这 4 个模块集成有 40MHz 晶体、32.768kHz RTC 时钟、32Mb SPI 串行闪存、射频滤波器和无源器件。这些模
块还具有其他安全功能，例如经过加密和身份验证的文件系统、用户 IP 加密和身份验证、安全引导（闪存引导时
对应用映像进行身份验证和完整性验证）等。
CC3220MODx 和 CC3220MODAx 器件是 SimpleLink™ MCU 平台的一部分，包含 Wi-Fi、低功耗蓝牙®、低于
1GHz 和主机MCU。它们都共用配有单核软件开发套件(SDK) 和丰富工具集的通用、易用型开发环境。一次性集
成SimpleLink 平台后，用户可以将产品组合中器件的任何组合添加至您的设计中。SimpleLink 平台的最终目标是
确保设计要求变更时，完全重复使用代码。
CC3220MODx 和 CC3220MODAx 模块系列是完整的平台解决方案，其中包括软件、示例应用、工具、用户和编
程指南、参考设计以及 E2E™ 在线社区。该模块系列还是 SimpleLink™ MCU 产品系列的一部分，并且支持
SimpleLink™ 开发人员生态系统。如需了解更多相关信息，请访问www.ti.com.cn/simplelink/cn。
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器件信息(1)
封装
封装尺寸（标称值）
器件型号
CC3220MODSM2MOBR
CC3220MODSF12MOBR
CC3220MODASM2MONR
CC3220MODASF12MONR
QFM (63)
QFM (63)
QFM (63)
QFM (63)
20.50mm × 17.50mm
20.50mm × 17.50mm
25.50mm × 20.50mm
25.50mm × 20.50mm
(1) 有关详细信息，请参阅节13。
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4 功能方框图
图4-1 显示了CC3220MODx 模块的功能方框图。
CC3x20
40 MHz
RF_ANT1
32.768 kHz
BGN
UART
SPI
WRF
F
nReset
2.3 V to 3.6 V
VBAT
PM
32-Mbit
SFlash
External SPI
Programming
User GPIOs
图4-1. CC3220MODx 功能方框图
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图4-2 显示了CC3220MODAx 模块的功能方框图。
CC3x20
40 MHz
RF_ANT1
32.768 kHz
BGN
UART
SPI
WRF
F
nReset
2.3 V to 3.6 V
VBAT
PM
32-Mbit
SFlash
External SPI
Programming
User GPIOs
Copyright © 2017, Texas Instruments Incorporated
图4-2. CC3220MODAx 功能方框图
有关3200MOD 模块引脚多路复用的详细信息，请参阅CC3200 SimpleLink™ Wi-Fi® 无线和物联网解决方案，单芯片无线MCU 数据
表。
图4-3. CC3200MOD 模块功能方框图
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图4-4 显示了CC3220x 硬件概述。
CC32xx œ Single-Chip Wireless MCU
1-MB Flash (optional)
256-KB RAM
ROM
ARM
Cortex-M4
80 MHz
1x SPI
2x UART
1 I2C
1x I2S/PCM
1x SD/MMC
DMA
Timers
GPIOs
8-bit Camera
4x ADC
Network Processor
Power
Management
Application
Protocols
Wi-Fi Driver
TCP/IP Stack
Oscillators
DC-DC
RTC
RAM
ROM
(ARM Cortex)
Synthesizer
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图4-4. CC3220x 硬件概述
图4-5 显示了CC3220x 嵌入式软件的概述。
Applications MCU
Customer Application
BSD
NetApp
Wi-Fi
Socket
Peripherals
Driver
SimpleLink Driver APIs
Host Interface
Network Applications
TCP/IP Stack
WLAN Security
and
Management
WLAN MAC and PHY
Network Processor
图4-5. CC3220x 嵌入式软件概述
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Table of Contents
9 Detailed Description......................................................50
9.1 Overview...................................................................50
9.2 Arm® Cortex®-M4 处理器内核子系统........................50
9.3 Wi-Fi® Network Processor Subsystem..................... 50
9.4 Security.....................................................................53
9.5 Power-Management Subsystem...............................55
9.6 Low-Power Operating Mode..................................... 55
9.7 Memory.....................................................................58
9.8 Restoring Factory Default Configuration...................60
9.9 Boot Modes...............................................................60
9.10 Device Certification and Qualification..................... 61
9.11 Module Markings.....................................................63
9.12 End Product Labeling..............................................65
9.13 Manual Information to the End User....................... 65
10 Applications, Implementation, and Layout............... 66
10.1 Typical Application.................................................. 67
10.2 Device Connection and Layout Fundamentals....... 70
10.3 PCB Layout Guidelines...........................................70
11 Environmental Requirements and Specifications....76
11.1 PCB Bending...........................................................76
11.2 Handling Environment.............................................76
11.3 Storage Condition................................................... 76
11.4 Baking Conditions................................................... 76
11.5 Soldering and Reflow Condition..............................77
12 Device and Documentation Support..........................78
12.1 Development Tools and Software........................... 78
12.2 Firmware Updates...................................................78
12.3 Device Nomenclature..............................................79
12.4 Documentation Support.......................................... 80
12.5 Trademarks.............................................................82
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 3
4 功能方框图.........................................................................5
5 Revision History.............................................................. 8
6 Device Comparison.........................................................9
6.1 Related Products...................................................... 10
7 Terminal Configuration and Functions........................11
7.1 CC3220MODx and CC3220MODAx Pin Diagram.... 11
7.2 Pin Attributes.............................................................13
7.3 Connections for Unused Pins................................... 14
7.4 Pin Attributes and Pin Multiplexing........................... 16
7.5 Drive Strength and Reset States for Analog-
Digital Multiplexed Pins............................................... 27
7.6 Pad State After Application of Power to Chip, but
Before Reset Release................................................. 27
8 Specifications................................................................ 28
8.1 Absolute Maximum Ratings...................................... 28
8.2 ESD Ratings............................................................. 28
8.3 Recommended Operating Conditions.......................28
8.4 Current Consumption (CC3220MODS and
CC3220MODAS).........................................................29
8.5 Current Consumption (CC3220MODSF and
CC3220MODASF).......................................................30
8.6 TX Power and IBAT Versus TX Power Level
Settings....................................................................... 31
8.7 Brownout and Blackout Conditions...........................33
8.8 Electrical Characteristics...........................................34
8.9 CC3220MODAx Antenna Characteristics.................36
8.10 WLAN Receiver Characteristics..............................36
8.11 WLAN Transmitter Characteristics..........................36
8.12 Reset Requirement.................................................36
8.13 Thermal Resistance Characteristics for MOB
Information.................................................................... 83
13.1 Mechanical, Land, and Solder Paste Drawings ..... 83
13.2 Package Option Addendum....................................83
and MON Packages.................................................... 37
8.14 Timing and Switching Characteristics..................... 37
5 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from September 22, 2020 to May 13, 2021 (from Revision D (September 2020) to
Revision E (May 2021))
Page
• 节1 新增了WPA3 个人版和企业版.................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 节3 新增了WPA3 个人版和企业版.................................................................................................................... 3
• Added WPA3 personal and enterprise to 表6-1 ................................................................................................9
• Added WPA3 personal and enterprise to 节9.3 ..............................................................................................50
• Added WPA3 Personal and WPA3 Enterprise to 节9.3.1 ............................................................................... 51
• Added WPA3 personal and enterprise to 表9-1 ..............................................................................................51
• Added CC3220MODA reel information in 节13.2 ........................................................................................... 83
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6 Device Comparison
表6-1 shows the features supported across different CC3x20 modules.
表6-1. Device Features Comparison
DEVICE
FEATURE
CC3120MOD
CC3120
No
CC3220MODS
CC3220S
No
CC3220MODSF
CC3220SF
No
CC3220MODAS
CC3220S
Yes
CC3220MODASF
CC3220SF
Yes
On-board chip
On-board ANT
sFlash
32-Mbit
32-Mbit
32-Mbit
32-Mbit
32-Mbit
FCC, IC, CE, MIC,
SRRC
FCC, IC, CE, MIC,
SRRC
FCC, IC, CE, MIC,
SRRC
Regulatory certifications
FCC, IC, CE, MIC, SRRC
FCC, IC, CE, MIC, SRRC
Wi-Fi Alliance®
Certification
Yes
Yes
Yes
Yes
Yes
Input voltage
Package
2.3 V to 3.6 V
2.3 V to 3.6 V
2.3 V to 3.6 V
2.3 V to 3.6 V
25.0 mm × 20.5 mm QFM
2.3 V to 3.6 V
25.0 mm × 20.5 mm QFM
17.5 mm × 20.5 mm
QFM
17.5 mm × 20.5 mm
QFM
17.5 mm × 20.5 mm
QFM
Operating temperature
range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Wi-Fi Network
Processor
Wireless
Microcontroller
Classification
Wireless Microcontroller
Wireless Microcontroller
Wireless Microcontroller
Standard
802.11 b/g/n
2.4 GHz
IPv4, IPv6
16
802.11 b/g/n
2.4 GHz
IPv4, IPv6
16
802.11 b/g/n
2.4 GHz
IPv4, IPv6
16
802.11 b/g/n
2.4 GHz
IPv4, IPv6
16
802.11 b/g/n
2.4 GHz
IPv4, IPv6
16
Frequency
TCP/IP Stack
Sockets
Arm® Cortex®-M4 at 80 Arm® Cortex®-M4 at
Arm® Cortex®-M4 at 80
MHz
Arm® Cortex®-M4 at 80
MHz
Integrated MCU
–
MHz
80 MHz
ON-CHIP APPLICATION MEMORY
256KB
RAM
256KB
256KB
256KB
1MB
–
–
Flash
1MB
–
–
PERIPHERALS AND INTERFACES
Universal Asynchronous
Receiver/Transmitter
(UART)
1
2
2
2
2
Serial Port Interface (SPI)
1
1
1
1
1
Multichannel Audio Serial
Port (McASP)- I2S or
PCM
2-ch
2-ch
2-ch
2-ch
–
Inter-Integrated Circuit
(I2C)
1
1
1
1
–
–
Analog-to-digital converter
(ADC)
4-ch, 12-bit
4-ch, 12-bit
4-ch, 12-bit
4-ch, 12-bit
Parallel interface (8-bit PI)
General-purpose timers
1
4
1
4
1
4
1
4
–
–
Multimedia card (MMC /
SD)
1
1
1
1
–
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表6-1. Device Features Comparison (continued)
DEVICE
FEATURE
CC3120MOD
CC3220MODS
CC3220MODSF
CC3220MODAS
CC3220MODASF
SECURITY FEATURES
WEP, WPS, WPA /
WPA2 PSK WPA2
(802.1x), WPA3
personal and
WEP, WPS, WPA /
WPA2 PSK WPA2
(802.1x), WPA3
personal and
WEP, WPS, WPA /
WPA2 PSK WPA2
(802.1x), WPA3 personal
and enterprise
WEP, WPS, WPA / WPA2
PSK WPA2 (802.1x),
WPA3 personal and
enterprise
WEP, WPS, WPA / WPA2
PSK WPA2 (802.1x), WPA3
personal and enterprise
Wi-Fi level of security
enterprise
enterprise
Secure sockets (SSL v3
or TLS 1.0 /1.1/ 1.2)
6
6
6
6
6
Unique Device Identity Unique Device Identity
Unique Device Identity
Unique Device Identity
Trusted Root-Certificate
Catalog
TI Root-of-Trust Public
key
Unique Device Identity
Trusted Root-Certificate
Catalog
Trusted Root-
Trusted Root-Certificate Trusted Root-
Additional networking
security
Certificate Catalog
Catalog
Certificate Catalog
TI Root-of-Trust Public
key
TI Root-of-Trust Public TI Root-of-Trust Public
TI Root-of-Trust Public key
key
key
Hardware Crypto
Engines
Hardware Crypto
Engines
Hardware Crypto
Engines
Hardware acceleration
Secure boot
Hardware Crypto Engines
Yes
Hardware Crypto Engines
Yes
Yes
Yes
–
–
File system security
Secure key storage
Software tamper
detection
Cloning protection
Initial secure
File system security
Secure key storage
Software tamper
detection
Cloning protection
Initial secure
File system security
Secure key storage
Software tamper
detection
File system security
Secure key storage
Software tamper detection
Cloning protection
Initial secure programming Initial secure
programming
Enhanced Application
Level Security
Cloning protection
programming
programming
6.1 Related Products
For information about other devices in this family of products or related products see the links below.
The SimpleLink™ MCU offers a single development environment that delivers flexible hardware, software and
Portfolio
tool options for customers developing wired and wireless applications. With 100
percent code reuse across host MCUs, Wi-Fi®, Bluetooth® low energy, Sub-1GHz
devices and more, choose the MCU or connectivity standard that fits your design. A
one-time investment with the SimpleLink software development kit (SDK) allows you to
reuse often, opening the door to create unlimited applications.
Companion Products
Review products that are frequently purchased or used in conjunction with this
product.
SimpleLink™ Wi-Fi®
Family
The SimpleLink Wi-Fi Family offers several Internet-on-a chip solutions, which address
the need of battery operated, security enabled products. Texas instruments offers a
single chip wireless microcontroller and a wireless network processor which can be
paired with any MCU, to allow developers to design new wi-fi products, or upgrade
existing products with wi-fi capabilities.
BoosterPack™ Plug-In BoosterPack™ Plug-In Modules extend the functionality of TI LaunchPad Kit.
Modules
Application specific BoosterPack Plug in modules allow you to explore a broad range
of applications, including capacitive touch, wireless sensing, LED Lighting control, and
more. Stack multiple BoosterPack modules onto a single LaunchPad kit to further
enhance the functionality of your design.
Reference Designs for TI Designs Reference Design Library is a robust reference design library spanning
CC3200 and CC3220 analog, embedded processor and connectivity. Created by TI experts to help you jump
Modules
start your system design, all TI Designs include schematic or block diagrams, BOMs
and design files to speed your time to market. Search and download designs at ti.com/
tidesigns.
SimpleLink™ Wi-Fi®
CC3220 SDK
The SimpleLink Wi-Fi CC3220 SDK contains drivers for the CC3220 programmable
MCU, sample applications, and documentation required to start development with
CC3220 solutions.
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7 Terminal Configuration and Functions
7.1 CC3220MODx and CC3220MODAx Pin Diagram
图7-1 shows the pin diagram for the CC3220MODx module.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GND
NC
16
15
14
13
12
11
10
9
GND
FLASH_SPI_CLK
GND
FLASH_SPI_nCS_IN
FLASH_SPI_MISO
JTAG_TDI
RF_BG
GND
NC
CC3220MODx
GPIO22
SOP0
nRESET
GPIO13
GPIO12
VBAT_RESET
8
GPIO17
GPIO16
63
62
61
VBAT1
GND
7
6
GPIO15
GPIO14
60
55
59
56
58
57
NC
5
VBAT2
NC
4
GPIO11
GPIO10
GND
3
GPIO30
GND
2
1
49
54
51
50
48
47
46
45
44
GND
53
52
图7-1 shows the approximate location of pins on the module. For the actual mechanical diagram, see 节13.
图7-1. CC3220MODx Pin Diagram Bottom View
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图7-2 shows the pin diagram for the CC3220MODAx module.
17
18
19
20
21
22
23
24
25
26
27
28
GND
16
15
14
13
12
11
10
9
GND
29 NC
FLASH_SPI_CLK
30
31
GND
FLASH_SPI_nCS_IN
FLASH_SPI_MISO
JTAG_TDI
RF_BG
32 GND
CC3220MODAx
NC
33
GPIO22
SOP0
34
35
36
37
38
39
40
41
42
43
GPIO13
nRESET
GPIO12
8
VBAT_RESET
GPIO17
GPIO16
63
62
61
7
VBAT1
GND
6
GPIO15
GPIO14
60
55
59
56
58
57
NC
5
4
VBAT2
NC
GPIO11
GPIO10
GND
3
2
GPIO30
GND
1
49
54
51
50
48
47
46
45
44
GND
53
52
图7-2. CC3220MODAx Pin Diagram Bottom View
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7.2 Pin Attributes
节7.2.1 lists the pin descriptions of the CC3220MODx and CC3220MODAx module.
7.2.1 Module Pin Attributes
MODULE PIN
NAME
CC3220 DEVICE
PIN NO.
TYPE(1)
MODULE PIN DESCRIPTION
NO.
1
GND
Ground
Ground
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
–
–
1
2
GND
3
GPIO10
4
GPIO11
2
5
GPIO14
5
6
GPIO15
6
7
GPIO16
7
8
GPIO17
8
9
GPIO12
3
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
30
31
32
34
GPIO13
4
GPIO22
15
16
JTAG_TDI
FLASH_SPI_MISO
FLASH_SPI_nCS_IN
FLASH_SPI_CLK
GND
JTAG TDI input. Leave unconnected if not used on product(2)
External Serial Flash Programming: SPI data in
External Serial Flash Programming: SPI chip select (active low)
External Serial Flash Programming: SPI clock
Ground
–
–
–
–
–
17
18
19
20
I
I
–
O
FLASH_SPI_MOSI
JTAG_TDO
GPIO28
External Serial Flash Programming: SPI data out
JTAG TDO output. Leave unconnected if not used on product(1)
GPIO(2)
JTAG TCK input. Leave unconnected if not used on product.(2)
JTAG TMS input. Leave unconnected if not used on product.(2)
See 节9.9.1 for SOP[2:0] configuration modes.
See 节9.9.1 for SOP[2:0] configuration modes.
Antenna selection control(2)
I/O
I/O
I/O
I/O
JTAG_TCK
JTAG_TMS
SOP2
21
34
29
30
–
SOP1
–
I/O
I/O
ANT_SEL1
ANT_SEL2
GND
Antenna selection control(2)
Ground
–
–
–
–
–
31
GND
Ground
GND
Ground
–
RF_BG
I/O
2.4-GHz RF input/output
GND
Ground
–
–
–
SOP0
35
See 节9.9.1 for SOP[2:0] configuration modes.
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MODULE PIN
CC3220 DEVICE
PIN NO.
TYPE(1)
MODULE PIN DESCRIPTION
NO.
NAME
35
nRESET
I
32
There is an internal, 100 kΩ, pull-up resistor option from the
nRESET pin to VBAT_RESET. Note: VBAT_RESET is not
connected to VBAT1 or VBAT2 within the module. The following
connection schemes are recommended:
•
Connect nRESET to a switch, external controller, or host,
only if nRESET will be in a defined state under all operating
conditions. Leave VBAT_RESET unconnected to save
power.
36
VBAT_RESET
37
–
•
If nRESET cannot be in a defined state under all operating
conditions, connect VBAT_RESET to the main module
power supply (VBAT1 and VBAT2). Due to the internal pull-
up resistor a leakage current of 3.3 V / 100 kΩis expected.
Power supply for the module, must be connected to battery (2.3
V to 3.6 V)
37
38
40
VBAT1
GND
Power
39
Ground
–
Power
I/O
–
10, 44, 54
53
Power supply for the module, must be connected to battery (2.3
V to 3.6 V)
GPIO(2)
VBAT2
42
43
44
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
GPIO30
GND
Ground
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
GPIO(2)
–
–
50
55
57
58
59
60
61
62
63
64
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO(2)
GPIO(2)
GPIO(2)
Thermal ground
Thermal ground
Thermal ground
Thermal ground
Thermal ground
Thermal ground
Thermal ground
Thermal ground
Thermal ground
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GND
GND
GND
GND
GND
GND
GND
GND
(1) I = input; O = output; I/O = bidirectional
(2) For pin multiplexing details, see 表7-3.
7.3 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. 表 7-1 and 表 7-2 list the NC pins on the CC3220MODx
and CC3220MODAx modules, respectively.
表7-1. Connections for Unused Pins
DEFAULT
FUNCTION
STATE AT RESET AND
HIBERNATE
PIN
I/O TYPE
DESCRIPTION
Reserved. Do not connect.
20
NC
WLAN analog
–
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PIN
表7-1. Connections for Unused Pins (continued)
DEFAULT
FUNCTION
STATE AT RESET AND
HIBERNATE
I/O TYPE
DESCRIPTION
Reserved. Do not connect.
29
33
39
41
45
NC
NC
NC
NC
NC
WLAN analog
WLAN analog
WLAN analog
WLAN analog
WLAN analog
–
–
–
–
–
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
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表7-2. CC3220MODAx Connections for Unused Pins
DEFAULT
FUNCTION
STATE AT RESET AND
HIBERNATE
PIN
I/O TYPE
DESCRIPTION
Reserved. Do not connect.
20
29
31
33
39
41
45
NC
NC
NC
NC
NC
NC
NC
WLAN analog
WLAN analog
WLAN analog
WLAN analog
WLAN analog
WLAN analog
WLAN analog
–
–
–
–
–
–
–
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
Reserved. Do not connect.
7.4 Pin Attributes and Pin Multiplexing
The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in
the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of
hardware configuration (at module reset) and register control.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does
not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. 表
7-3 describes the general pin attributes and presents an overview of pin multiplexing. All pin multiplexing options
are configurable using the pin MUX registers. The following special considerations apply:
• All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each pin.
• All I/Os support 10-μA pullup and pulldown resistors.
• By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
• All digital I/Os are non fail-safe.
Note
If an external device drives a positive voltage to the signal pads and the CC3220MODx or
CC3220MODAx modules are not powered, DC is drawn from the other device. If the drive strength of
the external device is adequate, an unintentional wakeup and boot of the CC3220MODx or
CC3220MODAx modules can occur. To prevent current draw, TI recommends any one of the following
conditions:
• All devices interfaced to CC3220MODx and CC3220MODAx modules must be powered from the
same power rail as the chip.
• Use level shifters between the device and any external devices fed from other independent rails.
• The nRESET pin of the CC3220MODx and CC3220MODAx modules must be held low until the
VBAT supply to the module is driven and stable.
• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the
TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.
表7-3. Pin Attributes and Pin Multiplexing
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
1
2
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
Hi-Z,
Pull,
Drive
0
1
3
GPIO10
GPIO
I/O
I/O
Hi-Z,
(open Pull,
drain) Drive
I2C_SCL
I2C clock
GPIO_PA
D_
CONFIG_1
0
(0x4402
E0C8)
Pulse-width
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
GT_PWM06 modulated
O/P
O
3
GPIO10
I/O
No
No
No
Hi-Z
UART TX
UART1_TX
7
6
O
O
1
0
data
SDCARD_CL
SD card clock
K
Hi-Z,
Pull,
Drive
Timer capture
12
0
GT_CCP01
port
I
Hi-Z,
Pull,
Drive
GPIO11
GPIO
I/O
I/O
Hi-Z,
(open Pull,
drain) Drive
1
I2C_SDA
I2C data
Pulse-width
Hi-Z,
3
GT_PWM07 modulated
O/P
O
Pull,
Drive
Free clock to
pXCLK
GPIO_PA
D_
CONFIG_1
1
(0x4402
E0CC)
4
parallel
O
0
(XVCLK)
Hi-Z,
Pull,
camera
4
GPIO11
I/O
Yes
No
No
Hi-Z
I/O
Hi-Z,
Drive
SDCARD_C SD card
6
(open Pull,
drain) Drive
MD
command line
Hi-Z,
Pull,
Drive
UART RX
data
7
UART1_RX
I
I
Hi-Z,
Pull,
Drive
Timer capture
port
12
13
GT_CCP02
MCAFSX
Hi-Z,
Pull,
Drive
I2S audio port
frame sync
O
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
Hib(2)
p
0
GPIO14
GPIO
I/O
I/O
(open
drain)
5
I2C_SCL
I2C clock
GPIO_PA
D_
CONFIG_1
4
(0x4402
E0D8)
General SPI
clock
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
7
4
GSPI_CLK
I/O
I
5
GPIO14
I/O
No
No
No
Hi-Z
Parallel
camera data
bit 4
pDATA8
(CAM_D4)
Timer capture
port
12
0
GT_CCP05
GPIO15
I
GPIO
I/O
I/O
(open
drain)
5
7
4
I2C_SDA
I2C data
GPIO_PA
D_
CONFIG_1
5
(0x4402
E0DC)
General SPI
MISO
GSPI_MISO
I/O
I
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
6
GPIO15
I/O
No
No
No
Hi-Z
Parallel
camera data
bit 5
pDATA9
(CAM_D5)
Timer capture
port
13
8
GT_CCP06
I
SDCARD_
DATA0
SD card data
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
0
GPIO16
GPIO
I/O
I/O
Hi-Z,
Pull,
Drive
GPIO_PA
D_
Hi-Z,
Hi-Z,
Pull,
Drive
General SPI
MOSI
7
GSPI_MOSI
CONFIG_1
6
7
GPIO16
I/O
No
No
No
Pull,
Drive
Hi-Z
(0x4402
E0E0)
Parallel
camera data
bit 6
Hi-Z,
Pull,
Drive
pDATA10
(CAM_D6)
4
5
I
UART1 TX
data
UART1_TX
GT_CCP07
O
I
1
Hi-Z,
Pull,
Drive
Timer capture
port
13
8
SDCARD_CL
K
SD card clock
O
Zero
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
0
5
GPIO17
GPIO
I/O
I
UART1 RX
data
UART1_RX
GPIO_PA
D_
CONFIG_1
7
(0x4402
E0E4)
General SPI
chip select
7
4
8
0
GSPI_CS
I/O
I
Hi-Z, Hi-Z,
8
GPIO17
I/O
Yes
No
No
Pull,
Pull,
Hi-Z
Parallel
camera data
bit 7
Drive Drive
pDATA11
(CAM_D7)
SDCARD_ SD card
I/O
I/O
CMD
command line
Hi-Z,
Pull,
GPIO12
GPIO
Drive
Hi-Z,
Pull,
Drive
I2S audio port
clock output
3
4
McACLK
O
GPIO_PA
D_
CONFIG_1
2
(0x4402
E0D0)
Parallel
camera
vertical sync
Hi-Z,
Pull,
Drive
pVS
(VSYNC)
I
Hi-Z,
Pull,
Drive
9
GPIO12
I/O
No
No
No
Hi-Z
I/O
Hi-Z,
5
7
I2C_SCL
I2C clock
(open Pull,
drain) Drive
UART0 TX
data
UART0_TX
O
1
Hi-Z,
Pull,
Drive
Timer capture
port
12
0
GT_CCP03
GPIO13
I
GPIO
I/O
I/O
(open
drain)
5
I2C_SDA
I2C data
GPIO_PA
D_
CONFIG_1
3
(0x4402
E0D4)
Parallel
camera
horizontal
sync
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
pHS
(HSYNC)
10
GPIO13
I/O
Yes
No
No
4
7
I
I
Hi-Z
UART0 RX
data
UART0_RX
Timer capture
port
12
0
GT_CCP04
GPIO22
I
GPIO_PA
D_
CONFIG_2
2
(0x4402
E0F8)
GPIO
I/O
O
I2S audio port
frame sync
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
7
McAFSX
11
GPIO22
I/O
No
No
No
Hi-Z
Timer capture
port
5
GT_CCP04
I
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
Hib(2)
p
JTAG TDI.
Reset default
pinout.
Hi-Z,
Pull,
Drive
1
TDI
I
GPIO_PA
D_
with CONFIG_2
Muxed
0
2
GPIO23
GPIO
I/O
O
Hi-Z,
Pull,
Drive
JTAG_T
DI
12
I/O
No
No
Hi-Z
UART1 TX
data
JTAG
TDI
3
UART1_TX
1
(0x4402
E0FC)
I/O
Hi-Z,
9
I2C_SCL
I2C clock
(open Pull,
drain) Drive
FLASH_
SPI_
MISO
Data from SPI
serial Flash
(fixed default)
FLASH_SPI_
MISO
13
14
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hi-Z
1
Hi-Z
Hi-Z
Hi-Z
Chip select to
FLASH_SPI_ SPI serial
FLASH_
SPI_
nCS_IN
Hi-Z,
Pull,
Drive
N/A
nCS_IN
Flash (fixed
default)
FLASH_
SPI_CL
K
Clock to SPI
serial Flash
(fixed default)
Hi-Z, Hi-Z,
Pull, Pull,
Drive(3) Drive
FLASH_SPI_
CLK
15
16
17
N/A
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hi-Z
N/A
Hi-Z
GND
GND
GND
N/A N/A
Hi-Z, Hi-Z,
FLASH_
SPI_
MOSI
Data to SPI
serial Flash
(fixed default)
FLASH_SPI_
MOSI
Pull,
Pull,
Drive(3) Drive
JTAG TDO.
Reset default
pinout.
1
0
5
TDO
O
I/O
O
GPIO24
PWM0
GPIO
Drive
n
Pulse-width
modulated
O/P
GPIO_PA
D_
CONFIG_
24
(0x4402
E100)
high
in
Muxed
with
JTAG
TDO
Hi-Z,
JTAG_T
DO
UART1 RX
data
SWD;
Pull,
18
I/O
Yes
No
2
9
UART1_RX
I2C_SDA
I
Hi-Z
drive
Drive
n low
in 4-
wire
I/O
(open
drain)
I2C data
JTAG
Timer capture
port
4
6
GT_CCP06
McAFSX
I
I2S audio port
frame sync
O
GPIO_PA
D_
CONFIG_
40
(0x4402
E140)
Hi-Z, Hi-Z,
19
20
GPIO28
NC
I/O
No
No
No
0
GPIO28
NC
GPIO
I/O
Pull,
Pull,
Hi-Z
N/A
Drive Drive
WLAN
analog
N/A
N/A
N/A
N/A
N/A
Reserved
N/A
N/A
N/A
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
JTAG/SWD
TCK.
Reset default
pinout.
GPIO_PA
D_
CONFIG_
28
(0x4402
E110)
Muxed
with
JTAG/
SWD-
TCK
1
8
1
TCK
I
Hi-Z, Hi-Z,
JTAG_T
CK
21
22
I/O
I/O
No
No
No
No
Pull,
Pull,
Hi-Z
Hi-Z
Drive Drive
Pulse-width
GT_PWM03 modulated
O/P
O
GPIO_PA
D_
CONFIG_
29
JTAG/SWD
TMS.
Reset default
pinout.
Muxed
with
JTAG/
SWD-
TMSC
TMS
Hi-Z, Hi-Z,
JTAG_T
MS
I/O
Pull,
Pull,
Drive Drive
(0x4402
E114)
0
0
GPIO29
GPIO25
GPIO
Hi-Z,
Pull,
Drive
GPIO
O
O
O
Pulse-width
Hi-Z,
Pull,
Drive
9
2
GT_PWM02 modulated
O/P
GPIO_PA
D_
CONFIG_
25
(0x4402
E104)
Hi-Z,
Drive
Pull,
n
I2S audio port
frame sync
McAFSX
23(4)
SOP2
O only
No
No
No
Hi-Z
Drive
Low
Enable to
optional
external 40-
MHz TCXO
See(5) TCXO_EN
O
0
Hi-Z,
Pull,
Drive
Sense-on-
power 2
See(6)
N/A
SOP2
SOP1
I
Config
sense
Sense-on-
power 1
24
SOP1
N/A
No
N/A
N/A
No
N/A
N/A
N/A
N/A
N/A
User
config
not
GPIO_PA
D_
CONFIG_2
6
(0x4402
E108)
Antenna
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
ANT_SE
L1
25(7)
O only
O only
0
0
ANTSEL1(3) selection
control
O
O
Hi-Z
requir
ed
(8)
User
config
not
GPIO_PA
D_
CONFIG_2
7
(0x4402
E10C)
Antenna
ANTSEL2(3) selection
control
Hi-Z, Hi-Z,
Pull,
Drive Drive
ANT_SE
L2
26(7)
No
No
Pull,
Hi-Z
requir
ed
(8)
27
28
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WLAN
analog
29
30
NC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NC
Reserved
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
Hib(2)
p
CC3220MOD
x:
N/A RF BG band N/A
CC3220MOD
WLAN
analog
31
RF_BG
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Ax: NC
32
33
GND
NC
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
NC
GND
WLAN
analog
Reserved
Config
sense
Sense-on-
power 0
34
SOP0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SOP0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Master chip
reset. Active
low.
Global
reset
35 nRESET
nRESET
VBAT to
nRESET
pullup resistor
VBAT_
36
Global
reset
VBAT_RESE
T
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
RESET
Analog
DC/DC input
(connected to
chip input
supply
Supply
input
37
VBAT1
VBAT1
[VBAT])
38
39
GND
NC
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
NC
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WLAN
analog
Reserved
Supply
input
Analog input
supply VBAT
40
41
VBAT2
NC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VBAT2
NC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WLAN
analog
Reserved
GPIO
Hi-Z,
Pull,
Drive
0
9
2
GPIO30
UART0_TX
McACLK
I/O
O
UART0 TX
data
1
Hi-Z,
Pull,
Drive
I2S audio port
clock
User
config
not
GPIO_PA
D_
CONFIG_3
0
(0x4402
E118)
O
Hi-Z,
Pull,
Drive
42
GPIO30
I/O
No
No
Hi-Z
Hi-Z,
Pull,
Drive
requir
I2S audio port
frame sync
3
4
McAFSX
O
I
ed
(8)
Hi-Z,
Pull,
Drive
Timer capture
port
GT_CCP05
Hi-Z,
Pull,
Drive
General SPI
MISO
7
GSPI_MISO
GND
I/O
43
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
N/A
N/A
N/A
N/A
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
Source g Mux
Hi-Z, Hi-Z,
0
12
6
GPIO0
GPIO
I/O
I
Pull,
Drive Drive
Pull,
Hi-Z
UART0 Clear-
Hi-Z,
Pull,
Drive
UART0_CTS to-Send input
(active low)
I2S audio port
data 1
(RX/TX)
Hi-Z,
Pull,
Drive
McAXR1
GT_CCP00
GSPI_CS
I/O
I
Hi-Z,
Pull,
Drive
Timer capture
port
7
User
config
not
requir
GPIO_PA
D_
CONFIG_0
(0x4402
E0A0)
Hi-Z,
44
GPIO0
I/O
No
No
General SPI
chip select
9
I/O
Pull, Hi-Z,
Drive Pull,
Drive
ed
Hi-Z
(8)
UART1
Request-to-
Send (active
low)
10
3
UART1_RTS
UART0_RTS
O
O
1
UART0
Request-to-
Send (active
low)
1
I2S audio port
data 0
(RX/TX)
Hi-Z,
Pull,
Drive
4
N/A
0
McAXR0
NC
I/O
N/A
I/O
O
WLAN
analog
45
NC
N/A
N/A
N/A
N/A
Reserved
GPIO
N/A
N/A
N/A
Hi-Z,
Pull,
Drive
GPIO1
UART0 TX
data
3
UART0_TX
1
GPIO_PA
D_
CONFIG_1
(0x4402
E0A4)
Pixel clock
from parallel
camera
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
pCLK
(PIXCLK)
46
GPIO1
I/O
No
No
No
4
I
Hi-Z
sensor
UART1 TX
data
6
7
UART1_TX
GT_CCP01
O
I
1
Hi-Z,
Pull,
Drive
Timer capture
port
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
Hib(2)
p
ADC channel
Hi-Z,
Pull,
Drive
See(5) ADC_CH0 0 input (1.5-V
max)
I
Hi-Z,
Pull,
Drive
0
3
6
7
GPIO2
GPIO
I/O
Analog
input
(up to
1.8 V)/
digital
I/O
GPIO_PA
D_
CONFIG_2
(0x4402
E0A8)
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
UART0 RX
data
47(10) GPIO2
Yes
See(9)
No
UART0_RX
UART1_RX
GT_CCP02
I
I
I
I
Hi-Z
Hi-Z,
Pull,
Drive
UART1 RX
data
Hi-Z,
Pull,
Drive
Timer capture
port
ADC channel
Hi-Z,
Pull,
Drive
See(5) ADC_CH1 1 input (1.5-V
max)
Analog
input
(up to
1.8 V)/
digital
I/O
Hi-Z,
Pull,
Drive
GPIO_PA
D_
CONFIG_3
(0x4402
E0AC)
0
6
4
GPIO3
GPIO
I/O
O
I
Hi-Z,
Pull,
Drive
48(10) GPIO3
No
See(9)
No
Hi-Z
UART1 TX
data
UART1_TX
1
Parallel
camera data
bit 3
Hi-Z,
Pull,
Drive
pDATA7
(CAM_D3)
ADC channel
Hi-Z,
Pull,
Drive
See(5) ADC_CH2 2 input (1.5-V
max)
I
I/O
I
Hi-Z,
Pull,
Drive
Analog
input
(up to
1.8 V)/
digital
I/O
GPIO_PA
D_
Yes CONFIG_4
(0x4402
0
6
4
GPIO4
GPIO
Hi-Z,
Pull,
Drive
49(10) GPIO4
Yes
See(9)
Hi-Z
Hi-Z,
Pull,
Drive
UART1 RX
data
UART1_RX
E0B0)
Parallel
camera data
bit 2
Hi-Z,
Pull,
Drive
pDATA6
(CAM_D2)
I
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表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
Hib(2)
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
p
ADC channel
i-Z,
Pull,
Drive
See(5) ADC_CH3 3 input (1.5 V
max)
I
Hi-Z,
Pull,
Drive
0
4
6
7
0
GPIO5
GPIO
I/O
I
GPIO_PA
D_
CONFIG_5
(0x4402
E0B4)
Analog
Parallel
camera data
bit 1
Hi-Z, Hi-Z,
Pull,
Drive Drive
pDATA5
(CAM_D1)
50(10) GPIO5 input up
to 1.5 V
No
See(9)
No
Pull,
Hi-Z
I2S audio port
data 1 (RX,
TX)
Hi-Z,
Pull,
Drive
McAXR1
GT_CCP05
GPIO6
I/O
I
Hi-Z,
Pull,
Drive
Timer capture
port
Hi-Z,
Pull,
GPIO
I/O
Drive
UART0
Request-to-
Send (active
low)
5
UART0_RTS
O
1
Parallel
camera data
bit 0
Hi-Z,
Pull,
Drive
GPIO_PA
D_
CONFIG_6
(0x4402
E0B8)
pDATA4
(CAM_D0)
4
3
I
I
Hi-Z,
Pull,
Drive
51
GPIO6
I/O
No
No
No
Hi-Z
UART1 Clear
UART1_CTS to send
(active low)
Hi-Z,
Pull,
Drive
UART0 Clear
UART0_CTS to send
Hi-Z,
Pull,
6
I
(active low)
Drive
Hi-Z,
Pull,
Drive
Timer capture
port
7
GT_CCP06
GPIO7
I
Hi-Z,
Pull,
Drive
0
GPIO
I/O
O
Hi-Z,
Pull,
Drive
I2S audio port
clock
13
McACLK
GPIO_PA
D_
CONFIG_7
(0x4402
E0BC)
UART1
Hi-Z,
Pull,
Drive
Request to
send (active
low)
52
GPIO7
I/O
No
No
No
3
UART1_RTS
O
1
Hi-Z
UART0
Request to
send (active
low)
10
11
UART0_RTS
UART0_TX
O
O
1
1
UART0 TX
data
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www.ti.com.cn
表7-3. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Dig.
Select Confi
as g.
Wakeu Addl. With
Analo JTAG
Source g Mux
Pin
Mux
Dig. Pin
Mux
Config.
Reg.
Signa
l
Description Direct
ion
Muxed
Pkg.
Pin
Pin
Alias
Signal
LPD
S(1)
nRESET =
0
Use
Confi Signal Name
g.
Mode
Value
Hib(2)
p
0
GPIO8
GPIO
I/O
I
Interrupt from
SDCARD_IR SD card
GPIO_PA
D_
CONFIG_8
(0x4402
E0C0)
6
Q
(future
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
support)
53
GPIO8
I/O
No
No
No
Hi-Z
I2S audio port
frame sync
7
McAFSX
O
Timer capture
port
12
0
GT_CCP06
GPIO9
I
GPIO
I/O
Pulse-width
3
GT_PWM05 modulated
O/P
O
GPIO_PA
D_
CONFIG_9
(0x4402
E0C4)
Hi-Z, Hi-Z,
Pull, Pull,
Drive Drive
SDCARD_
SD card data
DATA0
54
GPIO9
I/O
No
No
No
6
7
I/O
I/O
I
Hi-Z
I2S audio port
McAXR0
data (RX, TX)
Timer capture
12
GT_CCP00
port
55
56
57
58
59
60
61
62
63
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
表 7-4 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time
power up and reset (nRESET pulled low).
表7-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
MAXIMUM
STATE AFTER CONFIGURATION OF EFFECTIVE
BOARD LEVEL
CONFIGURATION AND USE
DEFAULT STATE AT FIRST
POWER UP OR FORCED RESET
PIN
ANALOG SWITCHES (ACTIVE,
LPDS, and HIB POWER MODES)
DRIVE
STRENGTH
(mA)
Connected to the enable pin of the
RF switch (ANT_SEL1). Other use
is not recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
25
26
4
4
Connected to the enable pin of the
RF switch (ANT_SEL2). Other use
is not recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
44
42
47
48
49
50
Generic I/O
Generic I/O
4
4
4
4
4
4
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
7.6 Pad State After Application of Power to Chip, but Before Reset Release
When a stable power is applied to the CC3220MODx or CC3220MODAx module for the first time or when supply
voltage is restored to the proper value following a prior period with supply voltage below 1.5 V, the level of the
digital pads are undefined in the period starting from the release of nRESET and until the DIG_DCDC of the
CC3220x chip powers up. This period is less than approximately 10 ms. During this period, pads can be
internally pulled weakly in either direction. If a certain set of pins are required to have a definite value during this
pre-reset period, an appropriate pullup or pulldown must be used at the board level. The recommended value of
these external pullup or pulldown resistors is 2.7 kΩ.
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8 Specifications
8.1 Absolute Maximum Ratings
All measurements are referenced at the module pins unless otherwise indicated. All specifications are over process and
voltage unless otherwise indicated.
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
–0.5
–0.5
–40
–40
MAX
UNIT
V
VBAT
3.8
Digital I/O
VBAT + 0.5
V
RF pin
2.1
2.1
85
V
Analog pins
V
Operating temperature (TA)
°C
°C
°C
Storage temperature (Tstg
)
85
Junction temperature (Tj)(3)
120
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Junction temperature is for the CC3220x device that is contained within the module.
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1)
±2000
VESD
Electrostatic discharge
V
Charged device model (CDM),
All pins
±500
per JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(2) (1)(3)
MIN
2.3
TYP
3.3
25
MAX
3.6
85
UNIT
VBAT
V
°C
Operating temperature
Ambient thermal slew
–40
–20
20
°C/minute
(1) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the
transmission.
(2) To ensure WLAN performance, the ripple on the power supply must be less than ±300 mV. The ripple should not cause the supply to
fall below the brownout voltage.
(3) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
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8.4 Current Consumption (CC3220MODS and CC3220MODAS)
TA = 25 °C, VBAT = 3.6 V
PARAMETER
TEST CONDITIONS(1) (2)
MIN
TYP MAX UNIT
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
272
190
248
182
1 DSSS
TX
6 OFDM
NWP ACTIVE
MCU ACTIVE
223
160
59
mA
54 OFDM
1 DSSS
RX(6)
54 OFDM
59
NWP idle connected(3)
15.3
269
187
245
179
220
157
56
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP ACTIVE
MCU SLEEP
mA
1 DSSS
RX(6)
NWP idle connected(3)
54 OFDM
56
12.2
266
184
242
176
217
154
53
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP active
mA
MCU LPDS
1 DSSS
RX(6)
54 OFDM
53
NWP LPDS(4)
135
710
5
µA
µA
NWP idle connected(3)
MCU hibernate
MCU shutdown
NWP hibernate
µA
NWP shutdown
1
VBAT = 3.6 V
VBAT = 3.3 V
VBAT= 2.3 V
420
450
620
Peak calibration current (5)
mA
(1) TX power level = 0 implies maximum power (see 图8-1, 图8-2, and 图8-3). TX power level = 4 implies output power backed off
approximately 4 dB.
(2) CC3220MODx and CC3220MODAx are constant, power-source systems. The active current numbers scale based on the VBAT voltage
supplied.
(3) DTIM = 1
(4) The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3220MODx and CC3220MODAx modules can be
configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases
LPDS current by 4 μA.
(5) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is
performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.
There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further
details, see CC3x20 SimpleLink™ Wi-Fi® and Internet of Things Network Processor Programmer's Guide.
(6) The RX current is measured with a 1-Mbps throughput rate.
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8.5 Current Consumption (CC3220MODSF and CC3220MODASF)
TA = 25 °C, VBAT = 3.6 V
PARAMETER
TEST CONDITIONS(1) (2)
MIN
TYP MAX UNIT
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
286
202
255
192
1 DSSS
TX
6 OFDM
NWP ACTIVE
MCU ACTIVE
232
174
74
mA
54 OFDM
1 DSSS
RX(3)
54 OFDM
74
NWP idle connected(4)
25.2
282
198
251
188
228
170
70
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP ACTIVE
MCU SLEEP
mA
1 DSSS
RX(3)
NWP idle connected(4)
54 OFDM
70
21.2
266
184
242
176
217
154
53
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP active
mA
MCU LPDS
1 DSSS
RX(3)
54 OFDM
53
NWP LPDS(5)
135
710
5
µA
µA
NWP idle connected(4)
MCU hibernate
MCU shutdown
NWP hibernate
µA
NWP shutdown
1
VBAT= 3.6 V
VBAT= 3.3 V
VBAT= 2.3 V
420
450
620
Peak calibration current (5)
mA
(1) TX power level = 0 implies maximum power (see 图8-1, 图8-2, and 图8-3). TX power level = 4 implies output power backed off
approximately 4 dB.
(2) CC3220MODx and CC3220MODAx are constant, power-source systems. The active current numbers scale based on the VBAT voltage
supplied.
(3) The RX current is measured with a 1-Mbps throughput rate.
(4) DTIM = 1
(5) The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3220MODx and CC3220MODAx modules can be
configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases
LPDS current by 4 μA.
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8.6 TX Power and IBAT Versus TX Power Level Settings
图 8-1, 图 8-2, and 图 8-3 show TX Power and IBAT versus TX power level settings for the CC3220MODS
module at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3220MODSF module, the
IBAT current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX
power level will remain the same.
In 图 8-1, the area enclosed in the circle represents a significant reduction in current during transition from TX
power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using
TX power level 4 to reduce the current.
1 DSSS
19.00
17.00
280.00
264.40
249.00
233.30
218.00
202.00
186.70
171.00
Color by
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
17.00
280.00
264.40
249.00
233.30
218.00
202.00
186.70
171.00
Color by
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
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54 OFDM
19.00
17.00
280.00
264.40
249.00
233.30
218.00
202.00
186.70
171.00
Color by
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
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8.7 Brownout and Blackout Conditions
The module enters a brownout condition whenever the input voltage dips below VBROWNOUT (see 图 8-4 and 图
8-5). This condition must be considered during design of the power supply routing, especially if operating from a
battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to
networking) can cause a drop in the supply voltage, potentially triggering a brownout. The resistance includes
the internal resistance of the battery, contact resistance of the battery holder (four contacts for a 2× AA battery),
and the wiring and PCB routing resistance.
Note
When the module is in HIBERNATE state, brownout is not detected. Only blackout is in effect during
HIBERNATE state.
图8-4. Brownout and Blackout Levels (1 of 2)
图8-5. Brownout and Blackout Levels (2 of 2)
In the brownout condition, all sections of the device shut down within the module except for the Hibernate block
(including the 32-kHz RTC clock), which remains on. The current in this state can reach approximately 400 µA.
The blackout condition is equivalent to a hardware reset event in which all states within the module are lost.
Vbrownout = 2.1 V and Vblackout = 1.67 V
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表8-1 lists the brownout and blackout voltage levels.
表8-1. Brownout and Blackout Voltage Levels
CONDITION
Vbrownout
VOLTAGE LEVEL
UNIT
V
2.1
Vblackout
1.67
V
8.8 Electrical Characteristics
TA = 25°C, VBAT = 3.3 V
PARAMETER
TEST CONDITIONS(1)
MIN
NOM
MAX
UNIT
GPIO Pins Except 25, 26, 42, and 44 (25°C)
CIN
VIH
VIL
IIH
Pin capacitance
4
pF
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
0.65 × VDD
VDD + 0.5 V
0.35 × VDD
V
–0.5
5
5
nA
nA
IIL
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤VDD < 3.6 V
VDD × 0.8
VDD × 0.7
VDD × 0.7
VDD × 0.75
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤VDD < 3.6 V
VOH
High-level output voltage
V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤VDD < 3.6 V
VDD × 0.2
VDD × 0.2
VDD × 0.2
VDD × 0.25
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤VDD < 3.6 V
VOL
Low-level output voltage
V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤VDD < 2.4 V
2-mA drive
2
4
6
2
4
6
High-level
source current
IOH
4-mA drive
6-mA drive
2-mA drive
4-mA drive
6-mA drive
mA
mA
Low-level
sink current
IOL
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TA = 25°C, VBAT = 3.3 V
PARAMETER
TEST CONDITIONS(1)
MIN
NOM
MAX
UNIT
GPIO Pins 25, 26, 42, and 44 (25°C)
CIN
VIH
VIL
IIH
Pin capacitance
7
pF
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
0.65 × VDD
VDD + 0.5 V
0.35 × VDD
V
–0.5
50
50
nA
nA
IIL
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤VDD < 3.6 V
VDD × 0.8
VDD × 0.7
VDD × 0.7
VDD × 0.75
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤VDD < 3.6 V
VOH
High-level output voltage
V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤VDD < 3.6 V
VDD × 0.2
VDD × 0.2
VDD × 0.2
VDD × 0.25
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤VDD < 3.6 V
VOL
Low-level output voltage
V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.3 V ≤VDD < 2.4 V
2-mA drive
1.5
2.5
3.5
1.5
2.5
3.5
High-level
source current,
VOH = 2.4
IOH
4-mA drive
6-mA drive
2-mA drive
4-mA drive
6-mA drive
mA
Low-level
sink current
IOL
mA
V
VIL
nRESET(2)
0.6
Pin Internal Pullup and Pulldown (25°C)
Pullup current
IOH
5
5
10
µA
µA
(VDD = 3.0 V)
Pulldown current
IOL
(VDD = 3.0 V)
(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
(2) The nRESET pin must be held below 0.6 V for the device to register a reset.
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8.9 CC3220MODAx Antenna Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Polarization
Peak Gain
Efficiency
Linear
2450 MHz
2450 MHz
2.5
dBi
70%
8.10 WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.3 V to 3.6 V. Parameters measured at module pin on channel 6 (2437 MHz).
PARAMETER
RATE
MIN
TYP
–95.0
–93.0
–87.0
–89.5
–89.0
–85.5
–79.5
–73.5
–69.5
–3.0
MAX
UNIT
1 DSSS
2 DSSS
11 CCK
6 OFDM
9 OFDM
18 OFDM
36 OFDM
54 OFDM
Sensitivity
(8% PER for 11b rates, 10% PER for 11g or 11n rates)
dBm
(10% PER)(1)
MCS7 (mixed mode)
802.11b
Maximum input level
(10% PER)
dBm
802.11g
–9.0
(1) Sensitivity is 1-dB worse on channel 13 (2472 MHz).
8.11 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.3 V to 3.6 V. Parameters measured at module pin on channel 6 (2437 MHz) (1) (2)
.
PARAMETER
RATE
MIN
TYP
17.0
17.0
17.3
16.3
16.3
16
MAX
UNIT
dBm
ppm
1 DSSS
2 DSSS
11 CCK
6 OFDM
9 OFDM
18 OFDM
36 OFDM
54 OFDM
Max RMS Output Power measured at 1 dB
from IEEE spectral mask or EVM
15
13.5
12
MCS7 (mixed mode)
Transmit center frequency accuracy
20
–20
(1) The edge channels (2412 MHz and 2462 MHz) have reduced TX power to meet FCC emission limits.
(2) Power of 802.11b rates is reduced to meet ETSI requirements.
8.12 Reset Requirement
PARAMETER
Operation mode level
MIN
TYP
MAX UNIT
VIH
VIL
0.65 × VBAT
0.6
V
V
Shutdown mode level(1)
0
5
Minimum time for nReset low for resetting the module
Rise and fall times
ms
µs
Tr and Tf
20
(1) The nRESET pin must be held below 0.6 V for the module to register a reset.
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8.13 Thermal Resistance Characteristics for MOB and MON Packages
NAME
RΘJC
RΘJB
RΘJA
PsiJT
DESCRIPTION
°C/W(1) (2)
11.4
AIR FLOW (m/s)(3)
Junction-to-case
0.00
0.00
0.00
0.00
0.00
Junction-to-board
Junction-to-free air
Junction-to-package top
Junction-to-board
8.0
18.7
5.3
PsiJB
7.7
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70°C is assumed.
(3) m/s = meters per second.
8.14 Timing and Switching Characteristics
8.14.1 Power-Up Sequencing
For proper start-up of the CC3220MODx and CC3220MODAx modules, perform the recommended power-up
sequencing as follows:
1. Tie VBAT1 (pin 37) and VBAT2 (pin 40) together on the board.
2. Hold the nRESET pin low while the supplies are ramping up.
图8-6 shows the reset timing diagram for the first-time power-up and reset removal.
T1
T2
T3
T4
VBAT
nRESET
APP CODE
EXECUTION
POWER
APP CODE
LOAD
RESET
HW INIT
FW INIT
STATE
OFF
32-kHz
RTC CLK
图8-6. First-Time Power-Up and Reset Removal Timing Diagram
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表8-2 lists the timing requirements for the first-time power-up and reset removal.
表8-2. First-Time Power-Up and Reset Removal Timing Requirements
ITEM
NAME
DESCRIPTION
MIN
TYP
3
MAX UNIT
Depends on application board power supply, decoupling capacitor,
and so on
T1 Supply settling time
T2 Hardware wake-up time
T3 Initialization time
ms
ms
s
25
Internal 32-kHz crystal settling plus firmware initialization time plus
radio calibration
1.35
App code load time for
CC3220MODS and
CC3220MODAS
CC3220MODS and CC3220MODAS
CC3220MODSF and CC3220MODASF
Image size (KB) × 1.7 ms
Image size (KB) × 0.06 ms
T4
App code load time for
CC3220MODSF and
CC3220MODASF
8.14.2 Power-Down Sequencing
For proper power down of the CC3220MODx and CC3220MODAx module, ensure that the nRESET (pin 35) and
nHIB (pin 4) pins have remained in a known state for a minimum of 200 ms before removing power from the
module.
8.14.3 Device Reset
When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must
ensure the reset is properly applied: A negative reset pulse (on pin 35) of at least 200-mS duration.
8.14.4 Wake Up From Hibernate Timing
表8-3 lists the software hibernate timing requirements.
Note
The internal 32.768-kHz crystal is kept enabled by default when the module goes to hibernate.
表8-3. Software Hibernate Timing Requirements
ITEM
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
THIB_MIN
Minimum hibernate time
10
ms
Hardware wakeup time plus
firmware initialization time
(1)
Twake_from_hib
50 (2)
ms
App code load time for
CC3220MODS and
CC3220MODAS
CC3220MODS and CC3220MODAS
Image size (KB) × 1.7 ms
Image size (KB) × 0.06 ms
T_APP_CODE_LOAD
App code load time for
CC3220MODSF and
CC3220MODASF
CC3220MODSF and
CC3220MODASF
(1) Twake_from_hib can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting
Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.
(2) Wake-up time can extend to 75 ms if a patch is downloaded from the serial Flash.
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图8-7 shows the timing diagram for wake up from the hibernate state.
Application software requests
entry to hibernate moade
Twake_from_hib
TAPP_CODE_LOAD
THIB_MIN
VBAT
nRESET
APP CODE
LOAD
ACTIVE
Hibernate
HW WAKEUP
FW INIT
EXECUTION
STATE
32-kHz
RTC CLK
图8-7. Wake Up From Hibernate Timing Diagram
8.14.5 Peripherals Timing
This section describes the peripherals that are supported by the CC3220MODx and CC3220MODAx modules,
as follows:
• SPI
• I2S
• GPIOs
• I2C
• IEEE 1149.1 JTAG
• ADC
• Camera parallel port
• External Flash
• UART
• SD Host
• Timers
8.14.5.1 SPI
8.14.5.1.1 SPI Master
The CC3220MODx and CC3220MODAx microcontroller includes one SPI module, which can be configured as a
master or slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase; a
programmable timing control between chip select and external clock generation; and a programmable delay
before the first SPI word is transmitted. Slave mode does not include a dead cycle between two successive
words.
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图8-8 shows the timing diagram for the SPI master.
T2
CLK
T6
T7
MISO
MOSI
T9
T8
图8-8. SPI Master Timing Diagram
表8-4 lists the timing parameters for the SPI master.
表8-4. SPI Master Timing Parameters
ITEM
NAME
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
F(1)
Tclk
D(1)
Clock frequency
20
(1)
T2
Clock period
50
45%
1
Duty cycle
55%
(1)
T6
T7
T8
T9
tIS
RX data setup time
RX data hold time
TX data output delay
TX data hold time
ns
ns
ns
ns
(1)
tIH
2
(1)
(1)
tOD
tOH
8.5
8
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.1.2 SPI Slave
图8-9 shows the timing diagram for the SPI slave.
T2
CLK
T6
T7
MISO
MOSI
T9
T8
图8-9. SPI Slave Timing Diagram
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表8-5 lists the timing parameters for the SPI slave.
表8-5. SPI Slave Timing Parameters
ITEM
NAME
DESCRIPTION
Clock frequency @ VBAT = 3.3 V
Clock frequency @ VBAT ≤2.3 V
Clock period
MIN
MAX
20
UNIT
MHz
ns
F(1)
12
(1)
T2
Tclk
D(1)
50
45%
4
Duty cycle
55%
(1)
T6
T7
T8
T9
tIS
RX data setup time
ns
ns
ns
ns
(1)
tIH
RX data hold time
4
(1)
(1)
tOD
tOH
TX data output delay
TX data hold time
20
24
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
8.14.5.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.14.5.2.1 I2S Transmit Mode
图8-10 shows the timing diagram for the I2S transmit mode.
T2
T1
T3
McACLKX
T4
T4
McAFSX
McAXR0/1
图8-10. I2S Transmit Mode Timing Diagram
表8-6 lists the timing parameters for the I2S transmit mode.
表8-6. I2S Transmit Mode Timing Parameters
ITEM
T1
NAME
DESCRIPTION
MIN
MAX
9.216
1/2 fclk
1/2 fclk
22
UNIT
MHz
ns
(1)
fclk
Clock frequency
T2
tLP (1)
Clock low period
(1)
T3
tHT
Clock high period
ns
(1)
T4
tOH
TX data hold time
ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.2.2 I2S Receive Mode
图8-11 shows the timing diagram for the I2S receive mode.
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T2
T1
T3
McACLKX
T5
T4
McAFSX
McAXR0/1
图8-11. I2S Receive Mode Timing Diagram
表8-7 lists the timing parameters for the I2S receive mode.
表8-7. I2S Receive Mode Timing Parameters
DESCRIPTION
ITEM
T1
NAME
MIN
MAX
9.216
1/2 fclk
1/2 fclk
0
UNIT
MHz
ns
(1)
fclk
Clock frequency
T2
tLP (1)
Clock low period
(1)
T3
tHT
Clock high period
ns
(1)
T4
tOH
RX data hold time
ns
(1)
T5
tOS
RX data setup time
15
ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.5.3 GPIOs
All digital pins of the module can be used as general-purpose input/output (GPIO) pins. The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown
strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
图8-12 shows the GPIO timing diagram.
VDD
80%
20%
tGPIOF
tGPIOR
SWAS031-067
图8-12. GPIO Timing Diagram
表8-8 lists the GPIO output transition times for VBAT = 2.3 V.
表8-8. GPIO Output Transition Times (VBAT = 2.3 V)(1) (2)
Tr
Tf
DRIVE
STRENGTH (mA)
DRIVE STRENGTH
CONTROL BITS
UNIT
ns
MIN
NOM
MAX
MIN
NOM
MAX
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
2
4
6
11.7
13.9
15.6
6.4
16.3
11.5
13.9
11.6
4.7
16.7
13.7
5.5
18.0
7.4
9.9
3.8
13.6
5.8
ns
ns
(1) VBAT = 2.3 V, T = 25°C, total pin load = 30 pF
(2) The transition data applies to the pins other than the multiplexed analog-digital pins 25, 26, 42, and 44.
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表8-9 lists the GPIO output transition times for VBAT = 3.3 V.
表8-9. GPIO Output Transition Times (VBAT = 3.3 V)(1) (2)
Tr
Tf
DRIVE
STRENGTH (mA)
DRIVE STRENGTH
CONTROL BITS
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
2
4
6
8.0
9.3
7.1
3.5
10.7
8.2
9.5
5.2
2.6
11.0
5.8
ns
ns
ns
6.6
3.2
7.6
3.7
4.7
2.3
2.9
(1) VBAT = 3.3 V, T = 25°C, total pin load = 30 pF
(2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52 and 53.
8.14.5.3.1 GPIO Input Transition Time Parameters
表8-10 lists the input transition time parameters.
表8-10. GPIO Input Transition Time Parameters
MIN
MAX
UNIT
tr
tf
1
1
3
3
ns
ns
Input transition time (tr, tf), 10% to 90%
8.14.5.4 I2C
The CC3220MODx and CC3220MODAx MCUs include one I2C module operating with standard (100 kbps) or
fast (400 kbps) transmission speeds.
图8-13 shows the I2C timing diagram.
T2
T6
T5
I2CSCL
I2CSDA
T1
T7
T4
T8
T3
T9
图8-13. I2C Timing Diagram
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表8-11 lists the I2C timing parameters.
表8-11. I2C Timing Parameters(3)
ITEM
T2
NAME
DESCRIPTION
MIN
MAX
UNIT
System clock
ns
tLP
Clock low period
See (1)
T3
tSRT
tDH
tSFT
tHT
SCL/SDA rise time
Data hold time
See (2)
T4
NA
3
T5
SCL/SDA fall time
Clock high time
ns
T6
See (1)
tLP/2
36
System clock
System clock
System clock
System clock
T7
tDS
Data setup time
T8
tSCSR
tSCS
Start condition setup time
Stop condition setup time
T9
24
(1) This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
(2) Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
(3) All timing is with 6-mA drive and 20-pF load.
8.14.5.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary
scan architecture for digital integrated circuits and provides a standardized serial interface to control the
associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
图8-14 shows the JTAG timing diagram.
T2
T3
T4
TCK
TMS
TDI
T7
TMS Input Valid
T9 T10
TDI Input Valid
T8
T8
TMS Input Valid
T7
T9
T10
TDI Input Valid
T1
T11
TDO Output Valid
TDO
TDO Output Valid
图8-14. JTAG Timing Diagram
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表8-12 lists the JTAG timing parameters.
表8-12. JTAG Timing Parameters
ITEM
T1
NAME
DESCRIPTION
MIN
MAX
15
UNIT
MHz
ns
fTCK
tTCK
tCL
Clock frequency
Clock period
T2
1 / fTCK
tTCK / 2
tTCK / 2
T3
Clock low period
Clock high period
TMS setup time
TMS hold time
TDI setup time
TDI hold time
ns
T4
tCH
ns
T7
tTMS_SU
tTMS_HO
tTDI_SU
tTDI_HO
tTDO_HO
1
16
1
ns
T8
ns
T9
ns
T10
T11
16
ns
TDO hold time
15
ns
8.14.5.6 ADC
表 8-13 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the
ADC and for application-specific examples.
Repeats Every 16 µs
Internal Ch
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
EXT CHANNEL 1
INTERNAL CHANNEL
INTERNAL CHANNEL
图8-15. ADC Clock Timing Diagram
图8-15 shows the ADC clock timing diagram.
表8-13. ADC Electrical Specifications
TEST CONDITIONS /
ASSUMPTIONS
PARAMETER
Nbits
DESCRIPTION
Number of bits
MIN
TYP
MAX
UNIT
12
Bits
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
INL
Integral nonlinearity
2.5
LSB
–2.5
Worst-case deviation of any step
from ideal
DNL
Differential nonlinearity
4
1.4
LSB
V
–1
Input range
0
Driving source
impedance
100
Ω
Successive approximation input
clock rate
FCLK
Clock rate
10
12
MHz
pF
Input capacitance
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表8-13. ADC Electrical Specifications (continued)
TEST CONDITIONS /
ASSUMPTIONS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
ADC Pin 57
2.15
0.7
ADC Pin 58
ADC Pin 59
ADC Pin 60
Input impedance
kΩ
2.12
1.17
4
Number of channels
Fsample
Sampling rate of each pin
62.5
KSPS
kHz
F_input_max
Maximum input signal frequency
31
Input frequency DC to 300 Hz
and 1.4 Vpp sine wave input
SINAD
Signal-to-noise and distortion
Active supply current
55
60
dB
Average for analog-to-digital
during conversion without
reference current
I_active
1.5
mA
Total for analog-to-digital when
not active (this must be the SoC
level test)
Power-down supply current for
core supply
I_PD
1
µA
Absolute offset error
Gain error
FCLK = 10 MHz
±2
±2%
mV
Vref
ADC reference voltage
1.467
V
8.14.5.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
图8-16 shows the timing diagram for the camera parallel port.
T3
T2
T4
pCLK
T6
T7
pVS, pHS
pDATA
图8-16. Camera Parallel Port Timing Diagram
表8-14 lists the timing parameters for the camera parallel port.
表8-14. Camera Parallel Port Timing Parameters
ITEM
NAME
DESCRIPTION
MIN
MAX
2
UNIT
MHz
ns
pCLK
Tclk
tLP
Clock frequency
T2
T3
T4
T6
T7
Clock period
1/pCLK
Tclk/2
Tclk/2
2
Clock low period
Clock high period
RX data setup time
RX data hold time
ns
tHT
ns
tIS
ns
tIH
2
ns
8.14.5.8 UART
The CC3220MODx and CC3220MODAx modules include two UARTs with the following features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
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• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Generation and detection of line-breaks
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Generation and detection of even, odd, stick, or no-parity bits
– Generation of 1 or 2 stop-bits
• RTS and CTS hardware flow support
• Standard FIFO-level and End-of-Transmission interrupts
• Efficient transfers using µDMA:
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
• System clock is used to generate the baud clock.
8.14.5.9 External Flash Interface
The CC3220MODx and CC3220MODAx modules include the Macronix™ 32-Mbit serial Flash. The serial Flash
can be programmed directly using the external Flash interface (pins 13, 14, 15, and 17). Note that during normal
operation, the external Flash interface should remain unconnected.
For timing details of the 32-Mbit Macronix serial Flash, see the MX25R3235F data sheet.
8.14.5.10 SD Host
The CC3220MODx and CC3220MODAx modules provide an interface between a local host (LH), such as an
MCU and an SD memory card, and handles SD transactions with minimal LH intervention.
The SD host does the following:
• Provides SD card access in 1-bit mode
• Deals with SD protocol at the transmission level
• Handles data packing
• Adds cyclic redundancy checks (CRC)
• Start and end bit
• Checks for syntactical correctness
The application interface sends every SD command and either polls for the status of the adapter or waits for an
interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-
of-operation. The controller can be configured to generate DMA requests and work with minimum CPU
intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI recommends that
developers use peripheral library APIs to control and operate the block. This section emphasizes understanding
the SD host APIs provided in the peripheral library of the CC3220x Software Development Kit (SDK).
The SD Host features are as follows:
• Full compliance with SD command and response sets, as defined in the SD memory card
– Specifications, v2.0
– Includes high-capacity (size >2 GB) cards HC SD
• Flexible architecture, allowing support for new command structure.
• 1-bit transfer mode specifications for SD cards
• Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
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– Each buffer is 32-bits wide by 128-words deep
• 32-bit-wide access bus to maximize bus throughput
• Single interrupt line for multiple interrupt source events
• Two slave DMA channels (1 for TX, 1 for RX)
• Programmable clock generation
• Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
• Supports configurable busy and response timeout
• Support for a wide range of card clock frequency with odd and even clock ratio
• Maximum frequency supported is 24 MHz
8.14.5.11 Timers
Programmable timers can be used to count or time external events that drive the timer input pins. The general-
purpose timer module (GPTM) of the CC3220MODx and CC3220MODAx contains 16- or 32-bit GPTM blocks.
Each 16- or 32-bit GPTM block provides two 16-bit timers or counters (referred to as Timer A and Timer B) that
can be configured to operate independently as timers or event counters, or they can be concatenated to operate
as one 32-bit timer. Timers can also be used to trigger µDMA transfers.
The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:
• Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
• Counts up or counts down
• Sixteen 16- or 32-bit capture compare pins (CCP)
• User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt
service routine
• Efficient transfers using micro direct memory access controller (µDMA):
– Dedicated channel for each timer
– Burst request generated on timer interrupt
• Runs from system clock (80 MHz)
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9 Detailed Description
9.1 Overview
The CC3220MODx and CC3220MODAx are Wi-Fi® internet-on-a chip modules that consists of an Arm®
Cortex®-M4 processor with a rich set of peripherals for diverse application requirements, a Wi-Fi network
processor, and power-management subsystems.
9.2 Arm® Cortex®-M4 处理器内核子系统
高性能 Arm® Cortex®-M4 处理器是一个低成本平台，可满足减少存储器和引脚数以及降低功耗的需求，同时提供
出色的计算性能和系统中断响应能力。
• Cortex®-M4 内核的低延迟中断处理具有以下特性：
– 32 位Arm® Thumb® 指令集针对嵌入式应用进行了优化
– 处理程序和线程模式
– 在进入和退出期间处理器状态自动保存和恢复，实现低延迟中断处理
– 支持ARMv6 未对齐的访问
• 嵌套矢量中断控制器(NVIC) 与处理器内核紧密集成，可实现低延迟中断处理。NVIC 包含以下特性：
– 可配置的优先级位（从3 到8）
– 动态重设中断优先级
– 优先级分组，支持选择优先中断级别和非优先中断级别
– 支持尾链和中断延迟到达，执行背对背中断处理时，两次中断之间无状态保存和恢复开销
– 中断到达时自动保存处理器状态，中断退出时恢复，无指令开销
– 唤醒中断控制器(WIC) 提供超低功耗睡眠模式支持
• 总线接口：
– 先进的高性能总线(AHB-Lite) 接口：系统总线接口
– 对存储器和部分外设的位段支持，包含原子位段写入和读取操作
• 低成本调试解决方案的特性：
– 对系统中所有存储器和寄存器进行调试访问，包括对存储器映射器件的访问，内核暂停时对内部内核寄存器
的访问和在SYSRESETn 置位时对调试控制寄存器的访问
– 串行线调试端口(SW-DP) 或串行线JTAG 调试端口(SWJ-DP) 调试访问
– 闪存补丁和断点(FPB) 单元，可实施断点和代码补丁
9.3 Wi-Fi® Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated Arm® MCU to completely offload the host MCU
along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN
and Internet connections with 256-bit encryption. The CC3220MODx and CC3220MODAx modules support
station, AP, and Wi-Fi Direct® modes. The module also supports WPA2 personal and enterprise security, WPS
2.0, WPA3 personal and enterprise security. The Wi-Fi network processor includes an embedded IPv6, IPv4
TCP/IP stack.
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9.3.1 WLAN
The WLAN features are as follows:
• 802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP, Wi-
Fi Direct® client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels 1 to 13.
Note
802.11n is supported only in Wi-Fi station, Wi-Fi Direct, and P2P client modes.
• Autocalibrated radio with a single-ended 50-Ωinterface enables easy connection to the antenna without
requiring expertise in radio circuit design.
• Advanced connection manager with multiple user-configurable profiles stored in serial-Flash allows automatic
fast connection to an access point without user or host intervention.
• Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal and WPA3
Enterprise.
• Smart provisioning options deeply integrated within the module providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the provisioning
decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3220MODx or CC3220MODAx-
enabled module to the home wireless network, removing dependency on the I/O capabilities of the host
MCU; thus, it is usable by deeply embedded applications
• 802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
9.3.2 Network Stack
The Network Stack features are as follows:
• Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,
microprocessor, or ASIC
Note
Not all BSD APIs are supported.
• Support of 16 simultaneous TCP, UDP, or RAW sockets
• Support of 6 simultaneous SSL\TLS sockets
• Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
• Built-in network application and utilities:
– HTTP/HTTPS
• Web page content stored on serial Flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks
– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized
server. After connecting to the access point, the CC3220MODx and CC3220MODAx modules provide
critical information, such as device name, IP, vendor, and port number.
– DHCP server
– Ping
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表9-1 describes the NWP features.
表9-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
1 to 13
Wi-Fi channels
Wi-Fi security
Wi-Fi provisioning
IP protocols
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IPv4/IPv6
IP addressing
Cross layer
Static IP, LLA, DHCPv4, DHCPv6 with DAD
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
HTTP/HTTPS web server
Network applications and
utilities
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Trusted root-certificate catalog
TI root-of-trust public key
Secure key storage
File system security
Software tamper detection
Security
Cloning protection
Secure boot
Validate the integrity and authenticity of the run-time binary during boot
Initial secure programming
Debug security
JTAG and debug
Power management
Other
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Transceiver
Programmable RX filters with event-trigger mechanism
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9.4 Security
The SimpleLink™ Wi-Fi® CC3220MODx and CC3220MODAx internet-on-a chip modules enhance the security
capabilities available for development of IoT devices, while completely offloading these activities from the MCU
to the networking subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
• Personal and enterprise Wi-Fi security
– Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP
– Enterprise standards
• EAP Fast
• EAP PEAPv0/1
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TLS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2
• Secure sockets
– Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2
– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS
and SSL connections
– Ciphers suites
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
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– Runtime socket upgrade to secure socket –STARTTLS
• Secure HTTP server (HTTPS)
• Trusted root-certificate catalog –Verifies that the CA used by the application is trusted and known secure
content delivery
• TI root-of-trust public key –Hardware-based mechanism that allows authenticating TI as the genuine origin
of a given content using asymmetric keys
• Secure content delivery –Allows encrypted file transfer to the system using asymmetric keys created by the
device
Code and Data Security:
• Network passwords and certificates are encrypted and signed.
• Cloning protection –Application and data files are encrypted by a unique key per device.
• Access control –Access to application and data files only by using a token provided in file creation time. If
an unauthorized access is detected, a tamper protection lockdown mechanism takes effect.
• Encrypted and Authenticated file system
• Secured boot –Authentication of the application image on every boot
• Code and data encryption –User application and data files are encrypted in sFlash.
• Code and data authentication –User Application and data files are authenticated with a public key
certificate.
• Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data
buffer
• Recovery mechanism
Device Security:
• Separate execution environments –Application processor and network processor run on separate Arm®
cores
• Initial secure programming –Allows for keeping the content confidential on the production line
• Debug security
– JTAG lock
– Debug ports lock
• True random number generator
图 9-1 shows the high-level structure of the CC3220S and CC3220SF devices that are contained within the
CC3220MODS and CC3220MODSF modules, respectively. The application image, user data, and network
information files (passwords, certificates) are encrypted using a device-specific key.
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CC3220S and CC3220SF
Network Processor + MCU
Network Processor
MCU
Peripherals
SPI and I2C
GPIO
ARM Cortex-M4
Internet
HTTPS
Wi-Fi
MAC
Internet
256KB RAM /
UART
1MB Flash (CC3220SF)
PWM
ADC
TLS/SSL
TCP/IP
Baseband
Radio
OEM
Application
•
Serial Flash
OEM
Data Files
Network information
Application
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图9-1. CC3220S and CC3220SF High-Level Structure
9.5 Power-Management Subsystem
The CC3220MODx and CC3220MODAx power-management subsystems contain DC/DC converters to
accommodate the differing voltage or current requirements of the system.
The CC3220MODx and CC3220MODAx are fully integrated module-based WLAN radio solution used on an
embedded system with a wide-voltage supply range. The internal power management, including DC/DC
converters and LDOs, generates all of the voltages required for the module to operate from a wide variety of
input sources. For maximum flexibility, the module can operate in the modes described in the following sections.
9.5.1 VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the module can be directly connected to two AA alkaline batteries. All
other voltages required to operate the module are generated internally by the DC/DC converters. This scheme is
the most common mode for the module because it supports wide-voltage operation from 2.3 to 3.6 V.
9.6 Low-Power Operating Mode
From a power-management perspective, the CC3220MODx and CC3220MODAx module comprise the following
two independent subsystems:
• Arm® Cortex®-M4 application processor subsystem
• Networking subsystem
Each subsystem operates in one of several power states.
The Arm® Cortex®-M4 application processor runs the user application loaded from an external serial Flash, or
internal Flash (in CC3220MODSF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link
layer functions.
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The user program controls the power state of the application processor subsystem and can be in one of the five
modes described in 表9-2.
表9-2. User Program Modes
APPLICATION PROCESSOR
DESCRIPTION
(MCU) MODE(1)
MCU active mode
MCU executing code at 80-MHz state rate
The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode
offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity
from any GPIO line or peripheral.
MCU sleep mode
State information is lost and only certain MCU-specific register configurations are retained. The MCU
can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)
Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory
retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU
can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the
wake-up source.
MCU LPDS mode
The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly
powered by the input supply is retained. The RTC keeps running and the MCU supports wakeup from an
external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms
plus the time to load the application from serial Flash, which varies according to code size. In this mode,
the MCU can be configured to wake up using the RTC timer or external event on a GPIO .
MCU hibernate mode
MCU shutdown mode
The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in
this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the
nRESET line is changed (low to shut down, high to turn on).
(1) Modes are listed in order of power consumption, with highest power modes listed first.
The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network
activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
表9-3).
表9-3. Networking Subsystem Modes
NETWORK PROCESSOR MODE
DESCRIPTION
Network active mode
(processing layer 3, 2, and 1)
Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)
Transmitting or receiving MAC management frames; IP processing not required.
Network active listen mode
Network connected Idle
Special power optimized active mode for receiving beacon frames (no other frames supported)
A composite mode that implements 802.11 infrastructure power save operation. The CC3220MODx
and CC3220MODAx NWPs automatically goes into LPDS mode between beacons and then wakes
to active listen mode to receive a beacon and determine if there is pending traffic at the AP. If not,
the NWP returns to LPDS mode and the cycle repeats.
Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid
wake up.
Network LPDS mode
Network disabled
The network is disabled
The operation of the application and network processor ensures that the module remains in the lowest power
mode most of the time to preserve battery life.
The following examples show the use of the power modes in applications:
• A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but
sends and receives little data spends most of the time in connected idle, which is a composite of receiving a
beacon frame and waiting for the next beacon.
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• A product that is not continuously connected to the network but instead wakes up periodically (for example,
every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to
transmit data.
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9.7 Memory
9.7.1 Internal Memory
The CC3220x device within the CC3220MODx and CC3220MODAx modules includes on-chip SRAM to which
application programs are downloaded and executed. The application developer must share the SRAM for code
and data. The micro direct memory access (μDMA) controller can transfer data to and from SRAM and various
peripherals. The CC3220x device ROM holds the rich set of peripheral drivers, which saves SRAM space. For
more information on drivers, see the CC3220x API list.
9.7.1.1 SRAM
The CC3220MODx and CC3220MODAx family provides 256KB of on-chip SRAM. Internal RAM is capable of
selective retention during LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.
Use the μDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of memory
based on need. Retaining the memory during low-power mode provides a faster wakeup. The application
developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API
guide.
9.7.1.2 ROM
The internal zero-wait-state ROM of the CC3220MODx and CC3220MODAx module is at address 0x0000 0000
of the device memory and is programmed with the following components:
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial Flash memory is empty). The DriverLib
software library of the CC3220MODx and CC3220MODAx controls on-chip peripherals with a bootloader
capability. The library performs peripheral initialization and control functions, with a choice of polled or interrupt-
driven peripheral support. The DriverLib APIs in ROM can be called by applications to reduce Flash memory
requirements and free the Flash memory to be used for other purposes.
9.7.1.3 Flash Memory
The CC3220SF device within the CC3220MODSF and CC3220MODASF modules comes with an on-chip Flash
memory of 1MB that allows application code to execute in place while freeing SRAM exclusively for read-write
data. The Flash memory is used for code and constant data sections and is directly attached to the ICODE/
DCODE bus of the Arm® Cortex®-M4 core. A 128-bit-wide instruction prefetch buffer allows maintenance of
maximum performance for linear code or loops that fit inside the buffer.
The Flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can be
performed at word (32-bit) level.
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9.7.1.4 Memory Map
表 9-4 describes the various MCU peripherals and how they are mapped to the processor memory. For more
information on peripherals, see the API document.
表9-4. Memory Map
START ADDRESS
0x0000 0000
0x0100 0000
0x2000 0000
0x2200 0000
0x4000 0000
0x4000 4000
0x4000 5000
0x4000 6000
0x4000 7000
0x4000 C000
0x4000 D000
0x4002 0000
0x4002 4000
0x4002 0800
0x4003 0000
0x4003 1000
0x4003 2000
0x4003 3000
0x400F7000
0x400F E000
0x400F F000
0x4200 0000
0x4401 0000
0x4401 8000
0x4401 C000
0x4402 0000
0x4402 1000
0x4402 5000
0x4402 6000
0x4402 D000
0x4402 E000
0x4402 F000
END ADDRESS
0x0007 FFFF
0x010F FFFF
0x2003 FFFF
0x23FF FFFF
0x4000 0FFF
0x4000 4FFF
0x4000 5FFF
0x4000 6FFF
0x4000 7FFF
0x4000 CFFF
0x4000 DFFF
0x4000 07FF
0x4002 4FFF
0x4002 0FFF
0x4003 0FFF
0x4003 1FFF
0x4003 2FFF
0x4003 3FFF
0x400F 7FFF
0x400F EFFF
0x400F FFFF
0x43FF FFFF
0x4401 0FFF
0x4401 8FFF
0x4401 DFFF
0x4402 0FFF
0x4402 1FFF
0x4402 5FFF
0x4402 6FFF
0x4402 DFFF
0x4402 EFFF
0x4402 FFFF
DESCRIPTION
On-chip ROM (bootloader + DriverLib)
On-chip Flash (for user application code)
Bit-banded on-chip SRAM
Bit-band alias of 0x2000 0000 to 0x200F FFFF
Watchdog timer A0
COMMENT
CC3220SF device only
GPIO port A0
GPIO port A1
GPIO port A2
GPIO port A3
UART A0
UART A1
I2C A0 (master)
GPIO group 4
I2C A0 (slave)
General-purpose timer A0
General-purpose timer A1
General-purpose timer A2
General-purpose timer A3
Configuration registers
System control
µDMA
Bit band alias of 0x4000 0000 to 0x400F FFFF
SDIO master
Camera Interface
McASP
SSPI
Used for external serial Flash
Used by application processor
GSPI
MCU reset clock manager
MCU configuration space
Global power, reset, and clock manager (GPRCM)
MCU shared configuration
Hibernate configuration
Crypto range (includes apertures for all crypto-related
blocks as follows)(1)
0x4403 0000
0x4403 FFFF
0x4403 0000
0x4403 5000
0x4403 7000
0x4403 9000
0xE000 0000
0xE000 1000
0xE000 2000
0xE000 E000
0x4403 0FFF
0x4403 5FFF
0x4403 7FFF
0x4403 9FFF
0xE000 0FFF
0xE000 1FFF
0xE000 2FFF
0xE000 EFFF
DTHE registers and TCP checksum(1)
MD5/SHA(1)
AES(1)
DES(1)
Instrumentation trace Macrocell™
Data watchpoint and trace (DWT)
Flash patch and breakpoint (FPB)
NVIC
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表9-4. Memory Map (continued)
DESCRIPTION
START ADDRESS
0xE004 0000
END ADDRESS
0xE004 0FFF
0xE004 1FFF
0xE00F FFFF
COMMENT
Trace port interface unit (TPIU)
Reserved for embedded trace macrocell (ETM)
Reserved
0xE004 1000
0xE004 2000
(1) Additional memory is available in the CC3220SF device (not available in CC3200R device).
9.8 Restoring Factory Default Configuration
The module has an internal recovery mechanism that rolls back the file system to its predefined factory image or
restoring the factory default parameters of the device. The factory image is kept in a separate sector on the
sFLASH in a secure manner and cannot be accessed from the host processor. The following restore modes are
supported:
• None—no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters
The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and
toggling the nRESET pin from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.
9.9 Boot Modes
9.9.1 Boot Mode List
The CC3220MODx and CC3220MODAx module implements a sense-on-power (SoP) scheme to determine the
device operation mode.
SoP values are sensed from the module pin during power up. This encoding determines the boot flow. Before
the device is taken out of reset, the SoP values are copied to a register and used to determine the device
operation mode while powering up. These values determine the boot flow as well as the default mapping for
some of the pins (JTAG, SWD, UART0). 表9-5 lists the pull configurations.
All CC3220MODx and CC3220MODAx modules contain internal pull down resistors on the SOP[2:0] lines. The
application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP values
from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The SOP0
and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.
表9-5. CC3220MODx and CC3220MODAx Functional Configurations
NAME
SOP[2]
SOP[1]
SOP[0]
SoP MODE
COMMENT
Factory, lab Flash, and SRAM loads
through the UART. The device waits
indefinitely for the UART to load code.
The SOP bits then must be toggled to
configure the device in functional mode.
Also puts JTAG in 4-wire mode.
UARTLOAD
Pullup
Pulldown
Pulldown LDfrUART
Functional development mode. In this
mode, 2-pin SWD is available to the
developer. TMS and TCK are available
for debugger connection.
FUNCTIONAL_2WJ
FUNCTIONAL_4WJ
Pulldown Pulldown
Pulldown Pulldown
Pullup
Fn2WJ
Functional development mode. In this
mode, 4-pin JTAG is available to the
developer. TDI, TMS, TCK, and TDO are
available for debugger connection. The
default configuration for CC3220MODx
and CC3220MODAx modules.
Pulldown Fn4WJ
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表9-5. CC3220MODx and CC3220MODAx Functional Configurations (continued)
NAME
SOP[2]
SOP[1]
SOP[0]
SoP MODE
COMMENT
Supports Flash and SRAM load through
UART and functional mode. The MCU
bootloader tries to detect a UART break
on UART receive line. If the break signal
is present, the device enters the
UARTLOAD mode, otherwise, the device
enters the functional mode. TDI, TMS,
TCK, and TDO are available for debugger
connection.
UARTLOAD_FUNCTIONAL_4WJ
RET_FACTORY_IMAGE
Pulldown Pullup
Pulldown Pullup
Pulldown LDfrUART_FnWJ
When module reset is toggled, the MCU
bootloader kickstarts the procedure to
restore factory default images.
Pullup
RetFactDef
9.10 Device Certification and Qualification
The CC3220MODx and CC3220MODAx modules from TI are certified for FCC, IC, ETSI/CE, Japan MIC, and
SRRC. Moreover, the module is also Wi-Fi CERTIFIED™ with the ability to request a certificate transfer for Wi-Fi
alliance members. TI customers that build products based on the CC3220MODx or CC3220MODAx from TI can
save in testing cost and time per product family.
表9-6. CC3220MODx and CC3200MODAx List of Certifications
Regulatory Body
FCC (USA)
Specification
ID (IF APPLICABLE)
Part 15C + MPE FCC RF Exposure
RSS-102 (MPE) and RSS-247 (Wi-Fi)
EN300328 v2.1.1 (2.4GHz Wi-Fi)
EN62311:2008 (MPE)
Z64-CC3220MOD
IC (Canada)
451I-CC3220MOD
—
—
—
—
ETSI/CE (Europe)
EN301489-1 v2.1.1 (General EMC)
EN301489-17 v3.1.1 (EMC)
EN60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
—
MIC (Japan)
Article 49-20 of ORRE
201-170386
CC3220MODSM2MOB: 2017DJ2948(M)
CC3220MODSF12MOB: 2017DJ2944(M)
CC3220MODASM2MON: 2017DJ3095
CC3220MODASF12MON: 2017DJ3121
SRRC (China)
EN300328 v1.7.1
9.10.1 FCC Certification and Statement
FCC RF Radiation Exposure Statement:
CAUTION
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled
environment. End users must follow the specific operating instructions for satisfying RF exposure
limits. This transmitter must not be co-located or operating with any other antenna or transmitter.
The CC3220MODx and CC3220MODAx modules from TI are certified for the FCC as a single-modular
transmitter. The modules are FCC-certified radio modules that carries a modular grant.
You are cautioned that changes or modifications not expressly approved by the party responsible for compliance
could void the user’s authority to operate the equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
• This device may not cause harmful interference.
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• This device must accept any interference received, including interference that may cause undesired
operation of the device.
9.10.2 Industry Canada (IC) Certification and Statement
CAUTION
IC RF Radiation Exposure Statement:
To comply with IC RF exposure requirements, this device and its antenna must not be co-located or
operating in conjunction with any other antenna or transmitter.
Pour se conformer aux exigences de conformité RF canadienne l'exposition, cet appareil et son
antenne ne doivent pas étre co-localisés ou fonctionnant en conjonction avec une autre antenne ou
transmetteur.
The CC3220MODx and CC3220MODAx modules from TI are certified for IC as a single-modular transmitter. The
CC3220MODx and CC3220MODAx modules from TI meet IC modular approval and labeling requirements. The
IC follows the same testing and rules as the FCC regarding certified modules in authorized equipment.
This device complies with Industry Canada licence-exempt RSS standards.
Operation is subject to the following two conditions:
• This device may not cause interference.
• This device must accept any interference, including interference that may cause undesired operation of the
device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de
licence.
L'exploitation est autorisée aux deux conditions suivantes:
• L'appareil ne doit pas produire de brouillage
• L'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est
susceptible d'en compromettre le fonctionnement.
9.10.3 ETSI/CE Certification
The CC3220MODx and CC3220MODAx modules from TI are CE certified with certifications to the appropriate
EU radio and EMC directives summarized in the Declaration of Conformity and evidenced by the CE mark. The
modules are tested against the new Radio Equipment Directive (RE-D). See the full text of the EU Declaration of
Conformity for the CC3220MODSM2MOB, CC3220MODSF12MOB, CC3220MODASM2MON, and
CC3220MODASF12MON devices.
9.10.4 MIC Certification
The CC3220MODx and CC3220MODAx modules from TI are MIC certified against article 49-20 and the relevant
articles of the Ordinance Regulating Radio Equipment.
Operation is subject to the following condition:
• The host system does not contain a wireless wide area network (WWAN) device.
9.10.5 SRRC Certification and Statement
The CC3220MODx modules from TI comply with the rules and regulations of the SRRC for a limited modular
approval (LMA).
Operation is subject to the following condition:
• The host system does not contain a WWAN device.
In addition, the host system using an approved LMA radio requires the following:
• New CMIIT ID
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• Required radiated related testing only
• The host system’s new SRRC certificate contains the CMIIT ID information of the LMA.
• The host system must be affixed with the new MIIT ID (not the CMIIT ID of the LMA) following the SRRC
labeling requirements.
Note
When an LMA radio is embedded into a host system, it does not mean the host system complies with
SRRC rules and regulations. The manufacturer of the host system is responsible for ensuring that the
combined system complies with SRRC rules and regulations.
The CC3220MODAx modules from TI comply with the rules and regulations of the SRRC for a full modular
approval (FMA).
Operation is subject to the following condition:
• The host system does not contain a WWAN device.
In addition, the host system using an approved FMA radio requires the following:
• The host system does not require a new SRRC certificate for the combined system.
• The host system must be affixed with the MIIT ID of the FMA following the SRRC labeling requirements.
9.11 Module Markings
图9-2 and 图9-3 show the markings for the SimpleLink™ CC3220MODx modules.1
M/N: CC3220MODSM2MOB
LTC: YMLLLLP SSSS
XXXXXXXXXX-VVSS
M/N: CC3220MODSF12MOB
LTC: YMLLLLP SSSS
XXXXXXXXXX-VVSS
FCC ID: Z64-CC3220MOD
IC: 451I-CC3220MOD
CMIIT ID:2017DJ2948(M)
FCC ID: Z64-CC3220MOD
IC: 451I-CC3220MOD
CMIIT ID:2017DJ2944(M)
R
201-170386
R 201-170386
图9-2. CC3220MODS Module Marking
图9-3. CC3220MODSF Module Marking
1
Drawings are representative. Content or placement may vary from what is illustrated.
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图9-4 and 图9-5 show the markings for the SimpleLink™ CC3220MODAx modules.
M/N: CC3220MODASM2MON
LTC: YMLLLLP SSSS
M/N: CC3220MODASF12MON
LTC: YMLLLLPSSSS
XXXXXXXXXX-VVSS
XXXXXXXXXX-VVSS
FCC ID: Z64-CC3220MOD
IC: 451I-CC3220MOD
CMIIT ID:2017DJ3095
FCC ID: Z64-CC3220MOD
IC: 451I-CC3220MOD
CMIIT ID:2017DJ3121
R
201-170386
R 201-170386
图9-4. CC3220MODAS Module Marking
图9-5. CC3220MODASF Module Marking
表9-7 lists the CC3220MODx and CC3220MODAx module markings.
表9-7. Module Descriptions
MARKING
DESCRIPTION
CC3220MODSM2MOB
CC3220MODSF12MOB
CC3220MODASM2MON
CC3220MODASF12MON
Model
LTC (lot trace code):
•
•
•
•
•
Y = Year
M = Month
YMLLLLP SSSS
LLLL = Assembly lot code
P = Reserved for internal use
SSSS = Serial number
XXXXXXXXXX-VVSS
Z64-CC3220MOD
451I-CC3220MOD
2017DJ2946(M)
2017DJ2944(M)
2017DJ3095
TI internal use only
FCC ID: single modular FCC grant ID
IC: single modular IC grant ID
CMIIT: limited modular SRRC grant ID
CMIIT: limited modular SRRC grant ID
CMIIT: full modular SRRC grant ID
CMIIT: full modular SRRC grant ID
2017DJ3121
MIC compliance mark
MIC ID: modular MIC grant ID
CE compliance mark
R 201-170386
CE
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9.12 End Product Labeling
These modules are designed to comply with the FCC single modular FCC grant, FCC ID: Z64-CC3220MOD.
The host system using this module must display a visible label indicating the following text:
Contains FCC ID: Z64-CC3220MOD
These modules are designed to comply with the IC single modular FCC grant, IC: 451I-CC3220MOD. The host
system using this module must display a visible label indicating the following text:
Contains IC: 451I-CC3220MOD
This module is designed to comply with the JP statement, 201-170386. The host system using this module must
display a visible label indicating the following text:
Contains transmitter module with certificate number: 201-170386
9.13 Manual Information to the End User
The OEM integrator must be aware not to provide information to the end user regarding how to install or remove
this RF module in the user’s manual of the end product which integrates this module.
The end user manual must include all required regulatory information and warnings as shown in this manual.
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10 Applications, Implementation, and Layout
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
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10.1 Typical Application
图10-1 shows the typical application schematic using the CC3220MODx module.
Note that the CC3220MODx and CC3220MODAx modules share the same reference schematic. The difference between the two references is the
antenna and its matching circuitry. Pin 31 is not accessible to the designer in the CC3220MODAx module, because it contains an integral antenna. See
the full reference schematics for CC3220MODx and CC3220MODAx.
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Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
VCC
VCC
C3
0.1µF
C6
100µF
C7
100µF
GND
C4
0.1µF
U7
GPIO_0
44
46
47
48
49
50
51
52
53
54
3
37
40
GND
GND
VBAT1
P50_GPIO_00
P55_GPIO_01
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
GPIO_08
GPIO_09
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_22
GPIO_28
GPIO_30
VBAT2
P57_GPIO_02
At a minimum, pull thes pins out
P58_GPIO_03
GND
to test points to aid in debug:
P59_GPIO_04
Pin 48: CC_WL_RS232_TX
P60_GPIO_05
Pin 49: CC_WL_RS232_RX
P61_GPIO_06
36
35
SEE TABLE 4-1 FOR
VBAT_RESET and nRESET
CONNECTION OPTIONS
Matching circuit shown below is for
VBAT_RESET
RESET
Pin 50: CC_WL_UART_TX
P62_GPIO_07
the antenna. The module is matched
internally to 50 Ω. Final solution
may require antenna matching
optimization with a pi-network
E1
Pin 52: CC_NPW_UART_TX
P63_GPIO_08
P64_GPIO_09
P01_GPIO_10
P02_GPIO_11
P03_GPIO_12
P04_GPIO_13
P05_GPIO_14
P06_GPIO_15
P07_GPIO_16
P08_GPIO_17
P15_GPIO_22
P18_GPIO_28
P53_GPIO_30
JTAG_TDI
4
12
18
21
22
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS
JTAG /
DEBUG
9
JTAG_TDO
JTAG_TCK
JTAG_TMS
L1
10
5
6
3.3nH
7
C2
1pF
GNDGND
8
11
19
42
31
RF_BG
VCC
25
26
ANT_SEL1
ANT_SEL2
P29_GPIO_26
P30_GPIO_27
R1
270
GND
1
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SOP[2:0] USED FOR
FACTORY RESTORE
16
27
28
30
32
38
43
55
56
57
58
59
60
61
62
63
34
24
23
1
3
5
2
4
6
SOP0
SOP1
SOP2
J1
15
14
17
13
SFL_CLK
SFL_nCS
SFL_MOSI
SFL_MISO
FLASH_SPI_CLK
FLASH_SPI_CS_IN
FLASH_SPI_MOSI
FLASH_SPI_MISO
EXTERNAL
PROGRAMMING
20
29
33
39
41
45
NC
NC
NC
NC
NC
NC
CC3220MODSF12MOBR
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GND
For the board files and BOM, see the LAUNCHXL-CC3220MODSF.
图10-1. CC3220MODx Typical Application Schematic
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表10-1 provides the bill of materials for a typical application using the CC3220MODx module in 图10-1.
Note that the CC3220MODx and CC3220MODAx modules share the same reference BOM. The difference between the two references is the antenna
and its matching circuitry. Pin 31 is not accessible to the designer in the CC3220MODAx module, because it contains an integral antenna. See the full
reference schematics for CC3220MODx and CC3220MODAx.
表10-1. Bill of Materials
PART
REFERENCE
QTY
VALUE
1 pF
MANUFACTURER
PART NUMBER
DESCRIPTION
Capacitor, ceramic, 1 pF,
1
3
C2(1)
Murata
GRM1555C1H1R0BA01D
GRM155R61A104KA01D
50 V, ±10%, C0G/NP0, 0402
Capacitor, ceramic, 0.1 μF,
10 V, ±10%, X5R, 0402
C3, C4, C5
0.1 µF
Murata
Capacitor, ceramic, 100 μF,
10 V, ±20%, X5R,
AEC-Q200 Grade 3, 1210
2
1
1
C6, C7
E1(1)
100 µF
2.45-GHz Ant
3.3 nH
Murata
Taiyo Yuden
Murata
LMK325ABJ107MMHT
AH316M245001-T
Antenna Bluetooth WLAN ZigBee® WIMAX
Inductor, multilayer,
air core, 3.3 nH,
L1(1)
LQG15HS3N3S02D
0.3 A, 0.17 Ω, SMD
RES, 270, 5%,
0.063 W, 0402
1
1
R1
U1
270
Vishay-Dale
CRCW0402270RJNED
SimpleLink™ Wi-Fi® and Internet-of-Things
Module Solution, a Single-Chip Wireless
MCU, MOB0063A (SIP MODULE-63)
CC3220MODSF
Texas Instruments
CC3220MODSF12MOBR
(1) For CC3220MODAx: C2, L1, and E1 are not present.
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10.2 Device Connection and Layout Fundamentals
10.2.1 Power Supply Decoupling and Bulk Capacitors
Depending upon routing resistors and battery type, TI recommends adding two 100-µF ceramic capacitors to
help provide the peak current drawn by the CC3220MODx and CC3220MODAx modules.
Note
The module enters a brown-out condition whenever the input voltage dips below VBROWN (see 图 8-4
and 图8-5). This condition must be considered during design of the power supply routing specifically if
operating from a battery. For more details on brown-out consideration, see 节8.7.
10.2.2 Reset
The module features an internal RC circuit to reset the device during power ON. The nRESET pin must be held
below 0.6 V for at least 5 ms for the device to successfully reset.
10.2.3 Unused Pins
All unused pins can be left unconnected without any concern to leakage current.
10.3 PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3220MODx and
CC3220MODAx modules. The integrator of the CC3220MODx and CC3220MODAx modules must comply with
the PCB layout recommendations described in the following subsections to minimize the risk with regulatory
certifications for the FCC, IC, CE, MIC, and SRRC. Moreover, TI recommends customers follow the guidelines
described in this section to achieve similar performance to that obtained with the TI reference design.
10.3.1 General Layout Recommendations
Ensure that the following general layout recommendations are followed:
• Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
• Do not run signal traces underneath the module on a layer where the module is mounted.
10.3.2 CC3220MODx RF Layout Recommendations
The RF section of this wireless module gets top priority in terms of layout. It is very important for the RF section
to be laid out correctly to ensure optimum performance from the module. A poor layout can cause low-output
power, EVM degradation, sensitivity degradation, and mask violations.
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图10-2 shows the RF placement and routing of the CC3220MODx module with external antenna.
图10-2. RF Section Layout
Follow these RF layout recommendations for the CC320MODx device:
• RF traces must have 50-Ωimpedance.
• RF trace bends must be made with gradual curves, and 90° bends must be avoided.
• RF traces must not have sharp corners.
• There must be no traces or ground under the antenna section.
• RF traces must have via stitching on the ground plane beside the RF trace on both sides.
• RF traces must be as short as possible. The antenna, RF traces, and the module must be on the edge of the
PCB product in consideration of the product enclosure material and proximity.
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For optimal RF performance, ensure the copper cut out on the top layer under the RF-BG pin (pin 31) is as
shown in 图10-3.
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图10-3. Top Layer Copper Pullback on RF Pads
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10.3.2.1 Antenna Placement and Routing
The antenna is the element used to convert the guided waves on the PCB traces to the free space
electromagnetic radiation. The placement and layout of the antenna are the keys to increased range and data
rates. 表10-2 provides a summary of the recommended antennas to use with the CC3220MODx module.
表10-2. Antenna Guidelines
SR NO.
GUIDELINES
1
Place the antenna on an edge or corner of the PCB.
Ensure that no signals are routed across the antenna elements on all the layers of the
PCB.
2
3
Most antennas, including the chip antenna used on the LaunchPad™, require ground
clearance on all the layers of the PCB. Ensure that the ground is cleared on inner layers
as well.
Ensure that there is provision to place matching components for the antenna. These
must be tuned for best return loss when the complete board is assembled. Any plastics
or casing must also be mounted while tuning the antenna because this can impact the
impedance.
4
5
Ensure that the antenna impedance is 50 Ωbecause the module is rated to work only
with a 50-Ωsystem.
In case of printed antenna, ensure that the simulation is performed with the solder mask
in consideration.
6
7
Ensure that the antenna has a near omnidirectional pattern.
The feed point of the antenna is required to be grounded. This is only for the antenna
type used on the CC3220MODx Launchpad. See the specific antenna data sheets for
the recommendations.
8
9
To use the FCC certification of the module, refer to the CC3120 and CC3220 Radio
Certifications wiki page on CC3220MODx Radio certification
表 10-3 lists the recommended antennas to use with the CC3220MODx module. Other antennas may be
available for use with the CC3220MODx modules. See the CC3120 and CC3220 Radio Certifications wiki page.
表10-3. Recommended Components
CHOICE
PART NUMBER
MANUFACTURER
NOTES
Can be placed on edge of the PCB and uses much
less PCB space
1
AH316M245001-T
Taiyo Yuden
10.3.2.2 Transmission Line Considerations
The RF signal from the module is routed to the antenna using a Coplanar Waveguide with ground (CPW-G)
structure. CPW-G structure offers the maximum amount of isolation and the best possible shielding to the RF
lines. In addition to the ground on the L1 layer, placing GND vias along the line also provides additional
shielding.
图10-4 shows a cross section of the coplanar waveguide with the critical dimensions.
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图10-4. Coplanar Waveguide (Cross Section)
图10-5 shows the top view of the coplanar waveguide with GND and via stitching.
S
W
图10-5. CPW With GND and Via Stitching (Top View)
The recommended values for the PCB are provided for 2-layer boards in 表10-4 and 4-layer boards in 表10-5.
表10-4. Recommended PCB Values for 2-Layer
Board (L1 to L2 = 42.1 mils)
PARAMETER
VALUE
24.5
6.5
UNIT
mils
mils
mils
W
S
H
42.1
4.8
Er (FR-4 substrate)
表10-5. Recommended PCB Values for 4-Layer
Board (L1 to L2 = 16 mils)
PARAMETER
VALUE
UNITS
mils
W
S
21
10
mils
H
16
mils
Er (FR-4 substrate)
4.5
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10.3.3 CC3220MODAx RF Layout Recommendations
Use the following guidelines to lay out the CC3220MODAx module with integral antenna, as shown in 图10-6.
• The module must have an overhang of 1 mm from the PCB edge.
• The module must have a 6-mm clearance on all layers (no copper) to the left and right of the module
placement.
• There must be at least one ground-reference plane under the module on the main PCB.
• For additional Layout recommendations, see the CC3220MODASx SimpleLink™ Wi-Fi® and IoT Solution
With MCU LaunchPad™ Hardware User's Guide.
6 mm
6 mm
1 mm
6 mm
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图10-6. CC3220MODAx Layout Guidelines
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11 Environmental Requirements and Specifications
11.1 PCB Bending
The PCB bending specification will maintain planeness at a thickness of less than 0.1 mm.
11.2 Handling Environment
11.2.1 Terminals
The product is mounted with motherboard through land-grid array (LGA). To prevent poor soldering, do not make
skin contact with the LGA portion.
11.2.2 Falling
The mounted components will be damaged if the product falls or is dropped. Such damage may cause the
product to malfunction.
11.3 Storage Condition
11.3.1 Moisture Barrier Bag Before Opened
A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH. The
calculated shelf life for the dry-packed product will be 12 months from the date the bag is sealed.
11.3.2 Moisture Barrier Bag Open
Humidity indicator cards must be blue, < 30%.
11.4 Baking Conditions
Products require baking before mounting if:
• Humidity indicator cards read > 30%
• Temp < 30°C, humidity < 70% RH, over 96 hours
Baking condition: 90°C, 12 to 24 hours
Baking times: 1 time
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11.5 Soldering and Reflow Condition
• Heating method: Conventional convection or IR convection
• Temperature measurement: Thermocouple d = 0.1 mm to 0.2 mm CA (K) or CC (T) at soldering portion or
equivalent method
• Solder paste composition: Sn/3.0 Ag/0.5 Cu
• Allowable reflow soldering times: 2 times based on the reflow soldering profile
(see 图11-1)
• Temperature profile: Reflow soldering will be done according to the temperature profile (see
图11-1)
• Peak temperature: 245°C
图11-1. Temperature Profile for Evaluation of Solder Heat Resistance of a Component (at Solder Joint)
Note
TI does not recommend the use of conformal coating or similar material on the SimpleLink™ module.
This coating can lead to localized stress on the solder connections inside the module and impact the
module reliability. Use caution during the module assembly process to the final PCB to avoid the
presence of foreign material inside the module.
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12 Device and Documentation Support
TI offers and extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed in this section.
12.1 Development Tools and Software
For the most up to date list of Development Tools and Software, visit the CC3220MOD tools and software page.
Or, click on the Alert me button in the top-right corner of the page, to stay informed of updates related to the
CC3220MOD.
SimpleLink™ Wi-Fi®
Starter Pro
The SimpleLink™ Wi-Fi® Starter Pro mobile App is a new mobile application for
SimpleLink provisioning. It goes along with the embedded provisioning library and
example that runs on the device side. The new provisioning release is TI
recommendation for Wi-Fi provisioning using SimpleLink Wi-Fi products. It
implements advanced AP mode provisioning along with feedback and fallback
options to ensure successful process has been accomplished. Customers can use
both embedded library and the mobile library for integration to their end products.
SimpleLink™ CC3220 Wi- The SimpleLink™ Wi-Fi® CC3220 SDK contains drivers for the CC3220
Fi® Software Development programmable MCU, 30+ sample applications, and documentation needed to use
Kit (SDK)
the solution. It also contains the flash programmer, a command line tool for flashing
software, configuring network and software parameters (SSID, access point
channel, network profile, and so on), system files, and user files (certificates, web
pages, and so on). This SDK can be used with TI’s SimpleLink Wi-Fi CC3220
LaunchPads.
SimpleLink™ Wi-Fi® Radio The SimpleLink™ Wi-Fi® Radio Testing Tool is a Windows-based software tool for
Testing Tool
RF evaluation and testing of SimpleLink Wi-Fi CC3120 and CC3220 designs
during development and certification. The tool enables low-level radio testing
capabilities by manually setting the radio into transmit or receive modes. Usage of
the tool requires familiarity and knowledge of radio circuit theory and radio test
methods.
Uniflash Standalone Flash CCS Uniflash is a standalone tool used to program on-chip flash memory on TI
Tool for TI Microcontrollers MCUs and on-board flash memory for Sitara processors. Uniflash has a GUI,
(MCU), Sitara Processors command line, and scripting interface. CCS Uniflash is available free of charge.
and SimpleLink™ Devices
12.2 Firmware Updates
TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,
TI recommends users have the latest service pack in their module for production.
To stay informed, sign up for updates using the SDK Alert me button in the top-right corner of the product page,
or visit http://www.ti.com/cc3220sdk.
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12.3 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3220MODx and CC3220MODAx and support tools (see 图12-1).
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, CC3220MODx and CC3220MODAx). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
P
Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
X
CC 3220 MOD
X
XXXX XXX
R
PACKAGING
R = tape/reel
T = small reel
PREFIX
X = preproduction device
no prefix = production device
PACKAGE DESIGNATOR
MOB = LGA package
MON = LGA package
DEVICE FAMILY
CC = wireless connectivity
SERIES NUMBER
3 = Wi-Fi Centric
SM2 = S module
SF12 = SF module
A = integral antenna
No prefix = no antenna
MODULE
MOD = module
图12-1. CC3220MODx and CC3220MODAx Module Nomenclature
For orderable part numbers of the CC3220MODx and CC3220MODAx devices in the QFM package type, see ,
see ti.com, or contact your TI sales representative.
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12.4 Documentation Support
To receive notification of documentation updates — including silicon errata — go to the CC3220MOD product
folder on ti.com. In the upper-right corner, click on Alert me to receive a weekly digest of any product information
that has changed. For change details, check the revision history of any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is as
follows.
Application Reports
Transfer of TI's Wi-Fi® Alliance
This document explains how to employ the Wi-Fi Alliance® (WFA)
Certifications to Products Based on derivative certification transfer policy to transfer a WFA certification,
SimpleLink™
SimpleLink™ CC3x20 Wi-Fi®
already obtained by Texas Instruments, to a system you have developed.
The SimpleLink Wi-Fi CC3120 and CC3220 Internet-on-a chip™ family of
Internet-on-a chip™ Solution Built- devices from Texas Instruments offers a wide range of built-in security
In Security Features
features to help developers address a variety of security needs, which is
achieved without any processing burden on the main microcontroller
(MCU). This document describes these security-related features and
provides recommendations for leveraging each in the context of practical
system implementation.
Using Serial Flash on SimpleLink™ This application note is divided into two parts. The first part provides
CC3x20 Wi-Fi® and Internet-of-
Things Devices
important guidelines and best- practice design techniques to consider
when choosing and embedding a serial flash paired with the CC3120 and
CC3220 (CC3x20) devices. The second part describes the file system,
along with guidelines and considerations for system designers working
with the CC3x20 devices.
SimpleLink™ CC3x20 Wi-Fi® and This document describes the OTA library for the SimpleLink™ Wi-Fi®
Internet-of-Things Over-the-Air
Update
CC3x20 family of devices from Texas Instruments and explains how to
prepare a new cloud-ready update to be downloaded by the OTA library.
SimpleLink™ CC3x20 Wi-Fi®
Internet-on-a chip™ Solution
Device Provisioning
This guide describes the provisioning process, which provides the
SimpleLink Wi-Fi device with the information (network name, password,
and so forth) needed to connect to a wireless network.
SimpleLink™ CC3x20 Wi-Fi®
Internet-on-a chip™ Networking
Sub-System Power Management
This application report describes the best practices for power management
and extended battery life for embedded low-power Wi-Fi devices such as
the SimpleLink Wi-Fi Internet-on-a chip™ solution from Texas Instruments.
More Literature
RemoTI Manifest
CC3220MODx SimpleLink™ Wi-Fi® and Internet-of-Things Hardware Design Files
CC3220MODAx SimpleLink™ Wi-Fi® and Internet-of-Things Hardware Design Files
CC3120, CC3220 SimpleLink™ Wi-Fi® and Internet-of-Things Design Checklist
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User's Guides
Simplelink™ CC3x20 Wi-
Fi® Embedded
Programming
This application note describes in details additional options that leverage all the
features UniFlash has to offer, but without the necessary connected PC. This
option is referred to as Embedded Programming. To achieve embedded
programming, bootloader protocol implemented over UART is described in detail.
UniFlash SimpleLink™
This document describes the installation, operation, and usage of the SimpleLink
CC3x20 Wi-Fi® and IoC™ ImageCreator tool as part of the UniFlash.
Solution ImageCreator and
Pro
SimpleLink™ CC3x20 Wi- This document provides software (SW) programmers with all of the required
Fi® and Internet-of-Things knowledge for working with the networking subsystem of the SimpleLink Wi-Fi
Network Processor
devices. This guide provides basic guidelines for writing robust, optimized
networking host applications, and describes the capabilities of the networking
subsystem. The guide contains some example code snapshots, to give users an
idea of how to work with the host driver. More comprehensive code examples can
be found in the formal software development kit (SDK). This guide does not
provide a detailed description of the host driver APIs.
SimpleLink™ CC3220 Wi- This application demonstrates the out-of-box (OOB) experience with the CC3220
Fi® Out-of-Box Application LaunchPad™ Development Kit from Texas Instruments.
This guide describes TI’s SimpleLink™ Wi-Fi® provisioning solution for mobile
applications, specifically on the use of the Android®™ and iOS® building blocks for
UI requirements, networking, and provisioning APIs required for building the
mobile application.
SimpleLink™ CC3x20 Wi-
Fi® Provisioning for Mobile
Applications
SimpleLink™ CC3220 Wi- This quick start guide details the out-of-box experience for the CC3220
Fi® Out-of-Box Quick Start LaunchPad™ Development Kit from Texas Instruments.
Guide
SimpleLink™ CC3220 Wi- This manual describes the modules and peripherals of the SimpleLink CC32xx
Fi® and Internet-of-Things wireless MCU. Each description presents the module or peripheral in a general
TRM
sense. Not all features and functions of all modules or peripherals may be present
on all devices. Pin functions, internal signal connections, and operational
parameters differ from device to device. The user should consult the device-
specific data sheet for these details.
SimpleLink™ CC3x20 Wi- The Radio Tool serves as a control panel for direct access to the radio, and can be
Fi® and Internet-on-a chip™ used for both the radio frequency (RF) evaluation and for certification purposes.
Solution Radio Tool
This guide describes how to have the tool work seamlessly on Texas Instruments
™ evaluation platforms such as the BoosterPack™ plus FTDI emulation board for
CC3120 devices, and the LaunchPad™ for CC3220 devices.
SimpleLink™ CC3220 Wi- This guide is intended to assist users in the initial setup and demonstration of
Fi® and Internet-of-Things running their first sample application for the CC3220, CC3220S, CC3220SF,
Solution, a Single-Chip
Wireless MCU
CC3220MODx, and CC3220MODAx SimpleLink™ Wi-Fi® and Internet-of-Things
Solution, a Single-Chip Wireless MCU from Texas Instruments™. The guide
explains how to install the software development kit (SDK) and various other tools
required to get started with the first application.
SimpleLink™ CC3220MOD The CC3220MOD SimpleLink LaunchPad™ Development Kit
Wi-Fi® LaunchPad™ (LAUNCHCC3220MODASF) is a low-cost evaluation platform for Arm®Cortex®-
Development Kit Hardware M4-based MCUs. The LaunchPad design highlights the CC3220MOD Internet-on-
a chip™ solution and Wi-Fi capabilities. The CC3220MOD LaunchPad also
features temperature and accelerometer sensors, programmable user buttons,
three LEDs for custom applications, and onboard emulation for debugging. The
stackable headers of the CC3220MOD LaunchPad XL interface demonstrate how
easy it is to expand the functionality of the LaunchPad when interfacing with other
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peripherals on many existing BoosterPack™ Plug-in Module add-on boards, such
as graphical displays, audio codecs, antenna selection, environmental sensing,
and more.
SimpleLink™ CC3220 Wi- This document introduces the user to the environment setup for the CC3220x
Fi® and Internet of Things device, along with some reference examples from the software development kit
(SDK). This document explains both the platform and the framework available to
enable further application development.
12.5 Trademarks
SimpleLink™, Internet-on-a chip™, SmartConfig™, 德州仪器(TI)™, E2E™, BoosterPack™, LaunchPad™, and are
trademarks of Texas Instruments.
Wi-Fi CERTIFIED™, WPA2™, WPA™, and WPA3™ are trademarks of Wi-Fi Alliance.
Macronix™ is a trademark of Macronix International Co..
Macrocell™ is a trademark of Kappa Global Inc.
Wi-Fi® and Wi-Fi Direct® are registered trademarks of Wi-Fi Alliance.
Arm®, Cortex®, and Thumb® are registered trademarks of Arm Limited.
蓝牙® is a registered trademark of Bluetooth SIG, Inc.
ZigBee® is a registered trademark of ZigBee Alliance.
Android® is a registered trademark of Google, Inc.
iOS® is a registered trademark of Apple.
所有商标均为其各自所有者的财产。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document.
13.1 Mechanical, Land, and Solder Paste Drawings
Note
The total height of the module is 2.45 mm.
The weight of the CC3220MODx module is 0.00175 kg ±3%.
The weight of the CC3220MODAx module is 0.00206 kg ±3%
Note
1. All dimensions are in mm.
2. Solder mask should be the same or 5% larger than the dimension of the pad
3. Solder paste must be the same as the pin for all peripheral pads. For ground pins, make the
solder paste 20% smaller than the pad.
13.2 Package Option Addendum
The CC3220MOD is only offered in a 750-unit reel. The CC3220MODA is only offered in a 600-unit reel.
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13.2.1 Packaging Information
Package
Type
Package
Qty
Lead/Ball
Finish
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Drawing
Pins
63
Eco Plan (2)
MSL, Peak Temp (3) Op Temp (°C)
Device Marking(4) (5)
Green (RoHS
and no Sb/Br)
CC3220MODSM2MOBR
CC3220MODSF12MOBR
CC3220MODASM2MONR
CC3220MODASF12MONR
QFM
QFM
QFM
QFM
MOB
MOB
MON
MON
750
750
600
600
Ni, AU
Ni, AU
Ni, AU
Ni, AU
3, 250°C
3, 250°C
3, 250°C
3, 250°C
CC3220MODSM2MOB
CC3220MODSF12MOB
CC3220MODASM2MON
CC3220MODASF12MON
–40 to 85
–40 to 85
–40 to 85
–40 to 85
Green (RoHS
and no Sb/Br)
63
Green (RoHS
and no Sb/Br)
63
Green (RoHS
and no Sb/Br)
63
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%
by weight in homogeneous material)
space
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain
information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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13.2.2 Tape and Reel Information
Surface resistance
Vendor No.
Spec
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13.2.2.1 CC3220MODx Tape Specifications
25
1000
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13.2.2.2 CC3220MODAx Tape Specifications
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
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这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OUTLINE
MOB0063A
QFM - 2.4 mm max height
SCALE 0.650
QUAD FLAT MODULE
17.75
17.25
B
A
PIN 1 INDEX
AREA
20.75
20.25
2X (0.45)
2X (0.38)
C
2.40
2.03
0.1
0.88
0.72
2X 12.7
20X 1.27
(0.3) TYP
30X 1.27
17
27
16
15
28
29
(0.32)
PADS 1,16,28 & 43
(0.3)
TYP
9X
0.05
2
1.5
60
57
56
63
2X
19.05
59
62
61
6X 3
55
58
54X 0.81 0.08
2
1
42
0.15
0.05
C A B
C
44 43
54
PIN 1 ID
(45 X1)
1.5
6X 3
4221462/D 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
MOB0063A
QFM - 2.4 mm max height
QUAD FLAT MODULE
PKG
SEE DETAIL
54X ( 0.81)
54
44
1
2
43
42
(
8.1)
9X ( 2)
0.05 MIN TYP
58
(45 X 1)
(
0.2) TYP
VIA
61
62
55
56
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
9X
59
PKG
6X (3)
(1.5)
2X (19.1)
63
57
(0.65)
TYP
60
(1.5)
(0.65)
TYP
6X (3)
(1.27) TYP
15
16
29
28
17
27
(R0.05)
ALL PADS
2X (16.1)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:6X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SIGNAL PADS DETAIL
4221462/D 06/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
MOB0063A
QFM - 2.4 mm max height
QUAD FLAT MODULE
PKG
54X ( 0.81)
54
44
1
2
43
(R0.05)
TYP
42
SOLDER MASK
EDGE, TYP
SOLDER MASK EDGE
SEE DETAILS
58
55
61
62
59
56
57
PKG
(3) TYP
2X (19.1)
(1.5) TYP
63
60
(1.5) TYP
(3) TYP
(1.27) TYP
15
16
29
28
17
27
2X (16.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PADS PRINTED SOLDER COVERAGE BY AREA
PAD 55: 77.5 %, PADS 56 - 63: 79%
SCALE:6X
(1.54)
(0.55) TYP
(0.55) TYP
(0.55) TYP
(0.45)
(
0.89) TYP
2X ( 0.89)
(0.55 TYP)
METAL
TYP
(R0.05) TYP
(R0.05)
TYP
PADS 56 - 63 DETAIL
PAD 55 DETAIL
SCALE:10X
SCALE:10X
4221462/D 06/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
MON0063A
QFM - 2.4 mm max height
SCALE 0.600
QUAD FLAT MODULE
25.25
24.75
B
A
PIN 1 ID
20.75
20.25
19.61 0.1
PICK & PLACE
NOZZLE AREA
16.74 0.1
2.40
2.03
C
SEATING PLANE
0.08 C
0.88
0.72
2X 12.7
PKG
20X 1.27
30X 1.27
17
27
28
16
15
29
9X
0.05
2
1.5
60
2X
63
57
19.05
PADS 1-16
& 28-43
PKG
56
55
19.038
PADS 17-27
& 44-54
59
62
61
6X 3
58
PIN 1 ID
(45 X1)
2
1
42
54
44
43
(0.326) TYP
54X 0.81 0.08
6X 3
11.769
2.224
0.15
0.05
C A B
C
4.321
4223415/D 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
MON0063A
QFM - 2.4 mm max height
QUAD FLAT MODULE
SEE DETAIL
PATTERN
PKG
54X ( 0.81)
44
54
1
2
43
42
(
8.1)
9X ( 2)
(
0.2) TYP
0.05 MIN TYP
58
VIA
(45 X 1)
61
55
56
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
9X
59
62
(19.048)
PKG
6X (3)
(20.5)
(1.5)
63
57
(0.65)
TYP
60
(1.5)
(0.65)
TYP
6X (3)
(1.27) TYP
15
16
29
28
17
27
(R0.05)
ALL PADS
(8.05)
(3.724)
(25)
(4.326)
NO TRACES, VIAS, GND PLANE
OR SILK SCREEN SHOULD BE
LOCATED WITHIN THIS AREA
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:5X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SIGNAL PADS DETAIL
4223415/D 11/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
MON0063A
QFM - 2.4 mm max height
QUAD FLAT MODULE
PATTERN
PKG
54X ( 0.81)
54
44
1
2
43
42
SOLDER MASK
EDGE, TYP
SOLDER MASK EDGE
SEE DETAILS
58
61
62
55
56
59
(3) TYP
(19.048)
PKG
57
63
(1.5) TYP
60
(1.5) TYP
(3) TYP
(1.27) TYP
29
28
15
16
17
27
(R0.05)
TYP
(8.05)
(3.724)
(16.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PADS PRINTED SOLDER COVERAGE BY AREA
PAD 55: 77.5 %, PADS 56 - 63: 79%
SCALE:6X
(1.54)
(0.55) TYP
(0.55) TYP
(0.55) TYP
(0.45)
2X ( 0.89)
(
0.89) TYP
(0.55 TYP)
EXPOSED METAL
TYP
(R0.05) TYP
(R0.05)
TYP
PAD 55 DETAIL
PADS 56 - 63 DETAIL
SCALE:10X
SCALE:10X
4223415/D 11/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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