CC3220SF [TI]
具有 1MB 闪存和 256kB RAM 的 SimpleLink™ 32 位 Arm Cortex-M4 Wi-Fi® 无线 MCU;
| 型号： | CC3220SF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1MB 闪存和 256kB RAM 的 SimpleLink™ 32 位 Arm Cortex-M4 Wi-Fi® 无线 MCU 无线 闪存 |
| 文件： | 总92页 (文件大小：3445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CC3220R, CC3220S, CC3220SF
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
CC3220R、CC3220S 和 CC3220SF SimpleLink™ Wi-Fi®
单芯片无线 MCU 解决方案
– RESTful API 允许使用内部 HTTP 服务器
– 广泛的安全功能：
1 特性
•
双核架构：
•
硬件特性：
– 用户专用的应用 MCU 子系统
– 高度集成的 Wi-Fi 网络处理器
丰富的物联网安全功能：
– 增强的物联网网络安全性
– 非对称密钥和唯一器件身份
– 软件知识产权保护和安全存储 (CC3220S/
CC3220SF)
– 独立执行环境
– 器件标识
•
– 针对高级快速安全性的硬件加密引擎，
其中包括 AES、DES、3DES、SHA2、
MD5、CRC 和校验和
– 初始安全编程
•
•
调试安全性
JTAG 和调试端口处于锁定状态
•
•
•
•
高级低功耗模式，适用于电池供电应用
内置电源管理子系统
– 个人和企业 Wi-Fi 安全性
– 安全套接字（SSLv3、TLS1.0、
TLS1.1、TLS1.2）
工业温度：–40°C 至 85°C
芯片级 Wi-Fi Alliance® Wi-Fi CERTIFIED™
•
•
网络安全性：
扩展特性列表：
– 个人和企业 Wi-Fi 安全性
– 安全套接字（SSLv3、TLS1.0、
TLS1.1、TLS1.2）
•
应用微控制器子系统：
– 运行频率为 80 MHz 的 Arm® Cortex®-M4 内核
– 嵌入式存储器：
– HTTPS 服务器
•
•
•
256KB RAM
可选的 1MB 可执行文件闪存
外部串行闪存
– 受信任的根证书目录
– TI 信任根公钥
软件知识产权保护：
– 安全密钥存储
– 外设：
•
•
•
•
•
McASP 支持两个 I2S 通道
– 文件系统安全
SD、SPI、I2C、UART
8 位同步成像仪接口
4 通道 12 位 ADC
– 软件篡改检测
– 克隆保护
– 安全启动：启动期间验证运行时二进制的
完整性和真实性
4 个具有 16 位 PWM 模式的通用计时器
(GPT)
– 在专用网络处理器上运行的嵌入式网络应用：
•
•
•
看门狗计时器
多达 27 个 GPIO 引脚
调试接口：JTAG、cJTAG、SWD
•
具有动态用户回调的 HTTP/HTTPS Web 服
务器
•
•
mDNS、DNS-SD、DHCP 服务器
•
Wi-Fi 网络处理器 (NWP) 子系统：
– Wi-Fi 模式：
Ping
– 恢复机制 — 可恢复为出厂默认设置或恢复为完
整出厂映像
– Wi-Fi TX 功率：
•
•
•
802.11b/g/n 基站
802.11b/g 接入点 (AP) 支持多达 4 个基站
Wi-Fi Direct® 客户端和组所有者
•
•
1 DSSS 时为 18.0dBm
– WPA2 个人版和企业版安全性：WEP、WPA™/
54 OFDM 时为 14.5dBm
WPA2™ PSK、WPA2 企业版 (802.1x)、WPA3
– Wi-Fi RX 灵敏度：
™
个人版、WPA3™ 企业版
•
•
1 DSSS 时为 -96dBm
– IPv4 和 IPv6 TCP/IP 堆栈
– 行业标准 BSD 套接字应用编程接口 (API)：
54 OFDM 时为 -74.5dBm
– 应用吞吐量：
•
•
16 个同步 TCP 或 UDP 套接字
6 个同步 TLS 和 SSL 套接字
•
•
•
UDP：16Mbps
TCP：13Mbps
峰值：72Mbps
– IP 寻址：具有重复地址检测 (DAD) 的静态 IP、
LLA、DHCPv4、DHCPv6
•
电源管理子系统：
– 适用于自主和快速 Wi-Fi 连接的 SimpleLink 连
接管理器
– 集成式直流/直流转换器支持宽电源电压范围：
•
•
VBAT 宽电压模式：2.1 V 至 3.6 V
VIO 始终与 VBAT 关联
– 可通过 SmartConfig™ 技术、AP 模式和 WPS2
选项灵活配置 Wi-Fi
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWAS035
CC3220R, CC3220S, CC3220SF
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
www.ti.com.cn
•
预稳压 1.85V 模式
•
RGK 封装
– 高级低功耗模式:
– 64 引脚 9mm × 9mm 极薄四方扁平无引线
(VQFN) 封装，0.5mm 间距
工作温度
– 环境温度范围：–40°C 至 +85°C
器件支持 SimpleLink™ MCU 平台开发人员生态系
统
•
•
•
关断：1µA
休眠：4.5µA
低功耗深度睡眠 (LPDS)：135µA（测量对象
为具有 256KB RAM 容量的 CC3220R、
CC3220S 和 CC3220SF）
RX 流量（MCU 处于活动模式）：54 OFDM
时为 59mA （测量对象为 CC3220R 和
CC3220S；CC3220SF 会额外消耗 10mA）
TX 流量（MCU 处于活动模式）：54 OFDM
时为 223mA（测量对象为 CC3220R
和 CC3220S；CC3220SF 会额外消耗
15mA），最大功率
空闲连接（MCU 处于 LPDS 状态）：DTIM
= 1 时为 710µA（测量对象为具有 256KB
RAM 容量的 CC3220R 和 CC3220S）
•
•
•
•
2 应用
•
对于物联网应用，例如：
– 楼宇和住宅自动化：
•
•
•
HVAC 系统和恒温器
视频监控、可视门铃和低功耗摄像头
楼宇安全系统和电子锁
•
– 电器
– 资产跟踪
– 工厂自动化
– 医疗和保健
– 电网基础设施
•
时钟源：
– 具有内部振荡器的 40.0MHz 晶体
– 32.768kHz 晶体或外部 RTC
3 说明
SoC 无线 MCU CC3220x 器件提供三种型号：CC3220R、CC3220S 和 C3220SF。
•
•
CC3220R 具有 256KB RAM、物联网网络安全功能和器件身份/密钥。
CC3220S 基于 CC3220R 和 MCU 级安全性（例如文件系统加密、用户 IP [MCU 镜像] 加密、安全启动和调试
安全性）构建。
•
CC3220SF 基于 CC3220S 构建，除了 256KB RAM 以外，还集成了一个用户专用的 1MB 可执行闪存。
使用 Wi-Fi CERTIFIED™ 无线微控制器开始您的物联网 (IoT) 设计。SimpleLink™ Wi-Fi® CC3220x 器件系列是一
个片上系统 (SoC) 解决方案，将两个处理器集成在一个芯片上：
•
•
应用处理器是一个 Arm® Cortex®-M4 MCU，具有用户专用的 256KB RAM 和可选的 1MB 串行闪存。
网络处理器 MCU 可运行所有 Wi-Fi® 和互联网逻辑层。这个基于 ROM 的子系统包含 802.11b/g/n 无线电、基
带和具有强大加密引擎的 MAC。
这些器件引入了可进一步简化物联网连接的新特性和新功能。主要新特性包括：
•
•
•
•
•
•
•
•
•
优化的低功耗管理
增强的网络安全性
器件身份和非对称密钥
增强的文件系统安全性（只有 CC3220S 和 CC3220SF 变体提供此支持）
IPv6 TCP/IP 堆栈
支持 4 个基站的接入点模式
可同时打开多达 16 个 BSD 套接字，其中 6 个支持安全型
HTTPS）
支持 RESTful API
CC3220x 器件系列是 SimpleLink™ MCU 平台的一部分，该平台是一个通用、简单易用的开发环境，基于一个
单核软件开发套件 (SDK)、丰富的工具集、参考设计和 E2E™ 社区而构建，支持 Wi-Fi®、低功耗 Bluetooth®、
Sub-1GHz 器件和主机 MCU。如需了解更多相关信息，请访问 SimpleLink™ MCU 平台。
器件信息
器件型号 (1)
CC3220RM2ARGKR/T
CC3220SM2ARGKR/T
封装
封装尺寸（标称值）
9.00mm x 9.00mm
9.00mm x 9.00mm
VQFN (64)
VQFN (64)
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器件信息 (continued)
器件型号 (1)
CC3220SF12ARGKR/T
封装
封装尺寸（标称值）
VQFN (64)
9.00mm x 9.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
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4 功能方框图
图 4-1 显示了 CC3220x SimpleLink Wi-Fi 解决方案的功能方框图。
图 4-1. 功能模块图
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图 4-2 概要显示了 CC3220x 的硬件。
CC32xx œ Single-Chip Wireless MCU
1MB flash (optional)
256KB RAM
ROM
Arm® Cortex®-M4
Processor
80 MHz
1× SPI
2× UART
1× I2C
1× I2S/PCM
1× SD/MMC
8-bit Camera
4× ADC
DMA
Timers
GPIOs
Network Processor
Power
Management
Application
Protocols
Wi-Fi® Driver
TCP/IP Stack
Oscillators
DC/DC
RTC
(Arm® Cortex®
Processor)
RAM
ROM
Synthesizer
图 4-2. CC3220x 硬件概述
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图 4-3 概要显示了 CC3220x 的嵌入式软件。
Customer Application
NetApp
BSD Socket
Wi-Fi®
SimpleLink™ Driver APIs
Host Interface
Network Apps
WLAN Security
and
Management
TCP/IP Stack
WLAN MAC and PHY
图 4-3. CC3220x 嵌入式软件概述
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Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 2
3 说明................................................................................... 2
4 功能方框图.........................................................................4
5 Revision History.............................................................. 7
6 Device Comparison.........................................................8
6.1 Related Products........................................................ 9
7 Terminal Configuration and Functions........................10
7.1 Pin Diagram.............................................................. 10
7.2 Pin Attributes and Pin Multiplexing............................11
7.3 Signal Descriptions................................................... 19
7.4 Pin Multiplexing.........................................................24
7.5 Drive Strength and Reset States for Analog and
Digital Multiplexed Pins............................................... 26
7.6 Pad State After Application of Power to Chip But
Before Reset Release................................................. 26
7.7 Connections for Unused Pins................................... 27
8 Specifications................................................................ 28
8.1 Absolute Maximum Ratings...................................... 28
8.2 ESD Ratings............................................................. 28
8.3 Power-On Hours (POH)............................................28
8.4 Recommended Operating Conditions.......................29
8.5 Current Consumption Summary (CC3220R,
8.11 WLAN Transmitter Characteristics..........................37
8.12 WLAN Filter Requirements..................................... 38
8.13 Thermal Resistance Characteristics....................... 38
8.14 Timing and Switching Characteristics..................... 38
9 Detailed Description......................................................56
9.1 Arm® Cortex®-M4 Processor Core Subsystem.........56
9.2 Wi-Fi Network Processor Subsystem....................... 57
9.3 Security.....................................................................59
9.4 Power-Management Subsystem...............................61
9.5 Low-Power Operating Mode..................................... 62
9.6 Memory.....................................................................64
9.7 Restoring Factory Default Configuration...................67
9.8 Boot Modes...............................................................67
10 Applications, Implementation, and Layout............... 68
10.1 Application Information........................................... 68
10.2 PCB Layout Guidelines...........................................73
11 Device and Documentation Support..........................76
11.1 Development Tools and Software........................... 76
11.2 Firmware Updates...................................................77
11.3 Device Nomenclature..............................................77
11.4 Documentation Support.......................................... 78
11.5 支持资源..................................................................80
11.6 Trademarks............................................................. 80
11.7 Electrostatic Discharge Caution..............................80
11.8 Export Control Notice..............................................80
11.9 术语表..................................................................... 81
12 Mechanical, Packaging, and Orderable
CC3220S) ...................................................................29
8.6 Current Consumption Summary (CC3220SF).......... 31
8.7 TX Power and IBAT versus TX Power Level
Settings....................................................................... 32
8.8 Brownout and Blackout Conditions...........................34
8.9 Electrical Characteristics (3.3 V, 25°C)..................... 35
8.10 WLAN Receiver Characteristics..............................37
Information.................................................................... 82
12.1 Packaging Information............................................ 82
5 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from November 29, 2018 to May 13, 2021 (from Revision B (November 2018) to
Revision C (May 2021))
Page
•
•
•
•
•
更新和格式和组织，以反映最新 TI 标准.........................................................................................................0
节 1 新增了 WPA3 个人版和 WPA3 企业版........................................................................................................ 1
Added WPA3 personal and enterprise to 节 9.2 ..............................................................................................57
Added WPA3 personal and enterprise to 节 9.2.1 ...........................................................................................57
Added WPA3 personal and enterprise to 表 9-1 ..............................................................................................57
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6 Device Comparison
表 6-1 shows the features supported across different CC3220 devices.
表 6-1. Device Features Comparison
DEVICE
FEATURE
CC3220R
CC3220S
CC3220SF
On-Chip Application Memory
RAM
256KB
–
256KB
256KB
1MB
Flash
–
Security Features
File system security
File system security
Secure key storage
Software tamper detection
Cloning protection
Secure key storage
Software tamper detection
Cloning protection
Enhanced Application Level
Security
–
Initial secure programming
Initial secure programming
Hardware Acceleration
Additional Networking Security
Secure Boot
Hardware Crypto Engines
Unique Device Identity
Trusted Root-Certificate Catalog Trusted Root-Certificate Catalog Trusted Root-Certificate Catalog
TI Root-of-Trust Public key
Hardware Crypto Engines
Hardware Crypto Engines
Unique Device Identity
Unique Device Identity
TI Root-of-Trust Public key
TI Root-of-Trust Public key
No
Yes
Yes
Additional Features
802.11 b/g/n
Standard
TCP/IP Stack
Package
IPv4, IPv6
9 mm × 9 mm VQFN
16
Sockets
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6.1 Related Products
For information about other devices in this family of products or related products, see the following links:
SimpleLink™ MCU
Portfolio
This portfolio offers a single development environment that delivers flexible hardware,
software and tool options for customers developing wired and wireless applications.
With 100 percent code reuse across host MCUs, Wi-Fi™, Bluetooth® low energy,
Sub-1 GHz devices and more, choose the MCU or connectivity standard that fits your
design. A one-time investment with the SimpleLink software development kit (SDK)
allows you to reuse often, opening the door to create unlimited applications.
SimpleLink™ Wi-Fi®
Family
This device platform offers several Internet-on-a chip™ solutions, which address the
need of battery operated, security enabled products. Texas instruments offers a single
chip wireless microcontroller and a wireless network processor which can be paired
with any MCU, to allow developers to design new wi-fi products, or upgrade existing
products with wi-fi capabilities.
BoosterPack™ Plug-In The BoosterPack Plug-in modules extend the functionality of TI LaunchPad
Modules
Development Kit. Application-specific BoosterPack Plug-in modules allow you to
explore a broad range of applications, including capacitive touch, wireless sensing,
LED Lighting control, and more. Stack multiple BoosterPack modules onto a single
LaunchPad kit to further enhance the functionality of your design.
Reference Designs for TI Designs Reference Design Library is a robust reference design library spanning
CC3200 and CC3220
Devices
analog, embedded processor and connectivity. Created by TI experts to help you
jump start your system design, all TI Designs include schematic or block diagrams,
BOMs and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
SimpleLink™ Wi-Fi®
CC3220 SDK
This SDK contains drivers for the CC3220 programmable MCU, sample applications,
and documentation required to start development with CC3220 solutions.
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7 Terminal Configuration and Functions
7.1 Pin Diagram
图 7-1 shows pin assignments for the 64-pin VQFN package.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
nRESET
RF_BG
VDD_RAM
GPIO0
RTC_XTAL_P
ANTSEL2
RTC_XTAL_N
GPIO30
ANTSEL1
NC
VIN_IO2
NC
GPIO1
NC
VDD_DIG2
LDO_IN2
VDD_PLL
WLAN_XTAL_P
WLAN_XTAL_N
SOP2
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
TMS
TCK
GPIO28
TDO
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
NC = No internal connection
图 7-1. VQFN 64-Pin Assignments Top View
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7.2 Pin Attributes and Pin Multiplexing
The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in
the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of
hardware configuration (at device reset) and register control.
Note
TI highly recommends using Pin Mux Tool to obtain the desired pinout.
The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does
not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.
节 7.2.1 and 表 7-1 list the pin descriptions and attributes. 节 7.3.1 lists the signal descriptions. 表 7-2 presents
an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers.
The following special considerations apply:
•
•
•
•
•
All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.
All I/Os support 10-µA pullup and pulldown resistors.
The VIO and VBAT supply must be tied together at all times.
By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
All digital I/Os are nonfail-safe.
Note
If an external device drives a positive voltage to the signal pads and the CC3220x device is not
powered, DC is drawn from the other device. If the drive strength of the external device is adequate,
an unintentional wakeup and boot of the CC3220x device can occur. To prevent current draw, TI
recommends any one of the following conditions:
•
All devices interfaced to the CC3220x device must be powered from the same power rail as the
chip.
•
•
Use level shifters between the device and any external devices fed from other independent rails.
The nRESET pin of the CC3220x device must be held low until the VBAT supply to the device is
driven and stable.
•
All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the
TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.
7.2.1 Pin Descriptions
PINS
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
TYPE
DESCRIPTION
NO.
NAME
1
2
3
4
5
6
7
8
9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
I/O
I/O
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
Internal digital core voltage
No
Yes
No
No
No
No
No
No
No
No
No
N/A
No
No
No
No
No
No
No
No
N/A
I/O
I/O
Yes
No
I/O
I/O
No
I/O
No
I/O
Yes
N/A
VDD_DIG1
Power
I/O power supply (same as
battery voltage)
10
11
VIN_IO1
Power
O
N/A
N/A
N/A
N/A
N/A
N/A
FLASH_SPI_CLK
Serial flash interface: SPI clock
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PINS
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
TYPE
DESCRIPTION
NO.
12
NAME
Serial flash interface: SPI data
out
FLASH_SPI_DOUT
FLASH_SPI_DIN
FLASH_SPI_CS
GPIO22
O
I
N/A
N/A
N/A
No
N/A
N/A
N/A
No
N/A
N/A
N/A
No
13
14
15
16
Serial flash interface: SPI data in
Serial flash interface: SPI chip
select
O
I/O
I/O
General-purpose input or output
JTAG interface: data input
Muxed with
JTAG TDI
TDI
No
No
Muxed with
JTAG TDO
17
18
TDO
I/O
I/O
JTAG interface: data output
Yes
No
No
No
GPIO28
General-purpose input or output
No
Muxed with
JTAG/
SWD-TCK
19
TCK
TMS
I/O
I/O
JTAG/SWD interface: clock
No
No
No
No
Muxed with
JTAG/
SWD-TMSC
JTAG/SWD interface: mode
select or SWDIO
20
21(2)
22
SOP2
I
Configuration sense-on-power 2
No
No
No
40-MHz crystal. Pulldown if
external TCXO is used.
WLAN_XTAL_N
Analog
N/A
N/A
N/A
40-MHz crystal or TCXO clock
input
23
24
25
WLAN_XTAL_P
VDD_PLL
Analog
Power
Power
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Internal analog voltage
Internal analog RF supply from
analog DC/DC output
LDO_IN2
26
27
28
NC
NC
NC
—
—
—
No connect
Reserved
Reserved
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
User configuration
not required (3)
29(1)
ANTSEL1
O
Antenna selection control
No
No
User configuration
not required (3)
30(1)
31
ANTSEL2
RF_BG
O
RF
I
Antenna selection control
No
N/A
N/A
No
N/A
N/A
RF BG band: 2.4-GHz TX, RX
N/A
N/A
Master chip reset input. Active
low input.
32
nRESET
Internal RF power amplifier (PA)
input from PA DC/DC output
33
VDD_PA_IN
Power
N/A
N/A
N/A
34
35
SOP1
SOP0
I
I
Configuration sense-on-power 1
Configuration sense-on-power 0
N/A
N/A
N/A
N/A
N/A
N/A
Internal Analog RF supply from
analog DC/DC output
36
37
38
LDO_IN1
Power
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Analog DC/DC supply input
(same as battery voltage [VBAT])
VIN_DCDC_ANA
DCDC_ANA_SW
Internal Analog DC/DC converter
switching node
Power
Power
PA DC/DC converter input
supply (same as battery voltage
[VBAT])
39
VIN_DCDC_PA
N/A
N/A
N/A
Internal PA DC/DC converter
+ve switching node
40
41
DCDC_PA_SW_P
DCDC_PA_SW_N
Power
Power
N/A
N/A
N/A
N/A
N/A
N/A
Internal PA DC/DC converter
–ve switching node
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NO.
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
PINS
NAME
SELECT AS
WAKEUP
SOURCE
CONFIGURE
ADDITIONAL
ANALOG MUX
MUXED
WITH JTAG
TYPE
DESCRIPTION
Internal PA buck DC/DC
converter output
42
43
DCDC_PA_OUT
DCDC_DIG_SW
Power
Power
N/A
N/A
N/A
N/A
N/A
N/A
Internal Digital DC/DC converter
switching node
Digital DC/DC converter supply
input (same as battery voltage
[VBAT])
44
VIN_DCDC_DIG
Power
I/O
N/A
No
N/A
N/A
No
Analog2 DC/DC converter
+ve switching node
User configuration
not required (3)
45(4)
DCDC_ANA2_SW_P
Internal Analog2 DC/DC
converter –ve switching node
46
47
DCDC_ANA2_SW_N
VDD_ANA2
Power
Power
N/A
N/A
N/A
N/A
N/A
N/A
Internal Analog2 DC/DC output
Internal Analog1 power supply
fed by analog2 DC/DC converter
output
48
VDD_ANA1
Power
N/A
N/A
N/A
49
50
VDD_RAM
GPIO0
Power
I/O
Internal SRAM LDO output
N/A
No
N/A
N/A
No
User configuration
not required (3)
General-purpose input or output
32.768-kHz XTAL_P or external
CMOS level clock input
51
RTC_XTAL_P
RTC_XTAL_N
GPIO30
Analog
Analog
I/O
N/A
N/A
No
N/A
N/A
No
User configuration
not required (3) (7)
52(5)
53
32.768-kHz XTAL_N
User configuration
not required (3)
General-purpose input or output
No
54
55
56
VIN_IO2
GPIO1
Power
I/O
device supply voltage (VBAT
)
N/A
No
N/A
No
N/A
No
General-purpose input or output
internal digital core voltage
VDD_DIG2
Power
N/A
N/A
N/A
Analog input (up to 1.5-V ) or
general-purpose input or output
57(6)
58(6)
59(6)
60(6)
GPIO2
GPIO3
GPIO4
GPIO5
I/O
I/O
I/O
I/O
Yes
No
See (8)
See (8)
See (8)
See (8)
No
No
No
No
Analog input (up to 1.5-V ) or
general-purpose input or output
Analog input (up to 1.5-V ) or
general-purpose input or output
Yes
No
Analog input (up to 1.5 V) or
general-purpose input or output
61
62
63
64
GPIO6
GPIO7
GPIO8
GPIO9
I/O
I/O
I/O
I/O
General-purpose input or output
General-purpose input or output
General-purpose input or output
General-purpose input or output
No
No
No
No
No
No
No
No
No
No
No
No
Thermal pad and electrical
ground
GND_TAB
—
N/A
N/A
N/A
(1) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device
between two antennas. These pins must not be used for other functionalities.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(3) Device firmware automatically enables the digital path during ROM boot.
(4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the
CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to
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automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
(6) This pin is shared by the ADC inputs and digital I/O pad cells.
(7) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.
(8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always
connected and must be made Hi-Z before enabling the ADC switch.
表 7-1. Pin Attributes
PAD STATES
Hib(4)
PIN
NO.
SIGNAL
TYPE(2)
PIN MUX
SIGNAL
SIGNAL NAME(1)
LPDS(3)
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
nRESET = 0
ENCODING
DIRECTION
GPIO10 (PN)
I2C_SCL
0
1
I/O
I/O (open drain)
GT_PWM06
UART1_TX
SDCARD_CLK
GT_CCP01
GPIO11 (PN)
I2C_SDA
3
O
Hi-Z, Pull,
Drive
1
2
3
I/O
I/O
I/O
Hi-Z
7
O
6
O
0
12
0
I
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
0
I/O
1
I/O (open drain)
GT_PWM07
pXCLK (XVCLK)
SDCARD_CMD
UART1_RX
GT_CCP02
McAFSX
3
O
4
O
Hi-Z, Pull,
Drive
Hi-Z
6
I/O (open drain)
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
7
I
12
13
0
I
O
GPIO12 (PN)
McACLK
I/O
3
O
pVS (VSYNC)
I2C_SCL
4
I
Hi-Z, Pull,
Drive
Hi-Z
5
I/O (open drain)
UART0_TX
GT_CCP03
GPIO13 (PN)
I2C_SDA
7
O
12
0
I
Hi-Z, Pull, Drive
I/O
5
I/O (open drain)
Hi-Z, Pull,
Drive
4
5
pHS (HSYNC)
UART0_RX
GT_CCP04
GPIO14 (PN)
I2C_SCL
I/O
I/O
4
I
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z
Hi-Z
7
I
12
0
I
I/O
5
I/O (open drain)
Hi-Z, Pull,
Drive
GSPI_CLK
7
I/O
pDATA8 (CAM_D4)
GT_CCP05
GPIO15 (PN)
I2C_SDA
4
I
12
0
I
I/O
5
I/O (open drain)
GSPI_MISO
pDATA9 (CAM_D5)
GT_CCP06
SDCARD_DATA0
7
I/O
Hi-Z, Pull,
Drive
6
I/O
Hi-Z, Pull, Drive
Hi-Z
4
I
I
13
8
I/O
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PIN
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
表 7-1. Pin Attributes (continued)
PAD STATES
SIGNAL
TYPE(2)
PIN MUX
ENCODING
SIGNAL
DIRECTION
SIGNAL NAME(1)
LPDS(3)
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
Hib(4)
nRESET = 0
NO.
GPIO16 (PN)
GSPI_MOSI
0
7
I/O
I/O
I
pDATA10 (CAM_D6)
UART1_TX
4
Hi-Z, Pull,
Drive
7
I/O
I/O
Hi-Z
5
O
GT_CCP07
13
8
I
Hi-Z, Pull, Drive
0
SDCARD_CLK
GPIO17 (PN)
UART1_RX
O
0
I/O
I
5
Hi-Z, Pull,
Drive
8
GSPI_CS
7
I/O
I
Hi-Z, Pull, Drive
Hi-Z
pDATA11 (CAM_D7)
SDCARD_CMD
VDD_DIG1 (PN)
VIN_IO1
4
8
I/O
N/A
N/A
9
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
10
Hi-Z, Pull,
Drive(5)
Hi-Z, Pull,
Drive
11
12
13
14
FLASH_SPI_CLK
FLASH_SPI_DOUT
FLASH_SPI_DIN
FLASH_SPI_CS
O
O
I
N/A
N/A
N/A
N/A
O
O
I
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z, Pull,
Drive(5)
Hi-Z, Pull,
Drive
Hi-Z, Pull,
Drive(5)
Hi-Z
Hi-Z, Pull,
Drive
O
O
1
GPIO22 (PN)
McAFSX
I/O
O
I
0
7
5
1
0
2
9
1
0
5
2
9
4
6
I/O
Hi-Z, Pull,
Drive
15
16
O
Hi-Z, Pull, Drive
Hi-Z
Hi-Z
GT_CCP04
TDI (PN)
I
I
Hi-Z, Pull, Drive
GPIO23
I/O
Hi-Z, Pull,
Drive
I/O
UART1_TX
I2C_SCL
TDO (PN)
GPIO24
O
1
I/O (open drain)
Hi-Z, Pull, Drive
O
I/O
Driven high
in SWD;
driven low in
4-wire JTAG
PWM0
O
17
UART1_RX
I2C_SDA
GT_CCP06
McAFSX
I/O
I
Hi-Z, Pull, Drive
Hi-Z
I/O (open drain)
I
O
Hi-Z, Pull,
Drive
18
19
GPIO28
I/O
I/O
0
I/O
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z
Hi-Z
TCK (PN)
GT_PWM03
TMS (PN)
GPIO29
1
8
1
0
I
Hi-Z, Pull,
Drive
O
Hi-Z, Pull,
Drive
20
I/O
I/O
Hi-Z, Pull, Drive
Hi-Z
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nRESET = 0
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
表 7-1. Pin Attributes (continued)
PAD STATES
Hib(4)
PIN
NO.
SIGNAL
TYPE(2)
PIN MUX
ENCODING
SIGNAL
DIRECTION
SIGNAL NAME(1)
LPDS(3)
GPIO25
0
9
O
O
O
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
GT_PWM02
McAFSX
2
21(6)
O
Driven low
Hi-Z
N/A
TCXO_EN
O
I
0
Hi-Z, Pull, Drive
N/A
(see (8)
)
)
)
N/A
SOP2 (PN)
(see (9)
N/A
22
WLAN_XTAL_N
—
N/A
N/A
N/A
(see (8)
23
24
25
26
27
28
WLAN_XTAL_P
VDD_PLL
LDO_IN2
NC
—
—
—
—
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NC
NC
Hi-Z, Pull,
Drive
29(10) ANTSEL1
30(10) ANTSEL2
O
O
0
0
O
O
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z
Hi-Z
Hi-Z, Pull,
Drive
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RF_BG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
nRESET
VDD_PA_IN
SOP1
SOP0
LDO_IN1
VIN_DCDC_ANA
DCDC_ANA_SW
VIN_DCDC_PA
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
DCDC_DIG_SW
VIN_DCDC_DIG
GPIO31
UART0_RX
McAFSX
9
12
O
I/O
Hi-Z
Hi-Z
Hi-Z
UART1_RX
McAXR0
2
I
45(7)
6
I/O
I/O
GSPI_CLK
7
DCDC_ANA2_SW_P
(PN)
N/A
—
N/A
N/A
N/A
N/A
(see (8)
)
46
47
48
49
DCDC_ANA2_SW_N
VDD_ANA2
—
—
—
—
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VDD_ANA1
VDD_RAM
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PIN
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
表 7-1. Pin Attributes (continued)
PAD STATES
SIGNAL
TYPE(2)
PIN MUX
ENCODING
SIGNAL
DIRECTION
SIGNAL NAME(1)
LPDS(3)
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
Hib(4)
nRESET = 0
NO.
GPIO0 (PN)
UART0_CTS
McAXR1
0
12
6
I/O
I
I/O
I
GT_CCP00
GSPI_CS
7
Hi-Z, Pull,
Drive
50
I/O
Hi-Z
9
I/O
O
UART1_RTS
UART0_RTS
McAXR0
10
3
O
1
4
I/O
N/A
N/A
O
Hi-Z, Pull, Drive
N/A
51
RTC_XTAL_P
RTC_XTAL_N (PN)
GPIO32
—
O
N/A
N/A
0
N/A
N/A
N/A
McACLK
2
O
Hi-Z, Pull, Drive
Hi-Z, Pull,
Drive
52(11)
Hi-Z
McAXR0
4
O
UART0_RTS
GSPI_MOSI
GPIO30 (PN)
UART0_TX
McACLK
6
O
1
8
O
Hi-Z, Pull, Drive
Hi-Z, Pull, Drive
1
0
I/O
O
9
2
O
Hi-Z, Pull,
Drive
53
I/O
Hi-Z
McAFSX
3
O
Hi-Z, Pull, Drive
GT_CCP05
GSPI_MISO
VIN_IO2
4
I
7
I/O
N/A
I/O
O
54
55
56
—
I/O
—
N/A
0
N/A
N/A
N/A
Hi-Z
N/A
GPIO1 (PN)
UART0_TX
pCLK (PIXCLK)
UART1_TX
GT_CCP01
VDD_DIG2
Hi-Z, Pull, Drive
3
1
Hi-Z, Pull,
Drive
4
I
Hi-Z, Pull, Drive
6
O
1
Hi-Z, Pull, Drive
N/A
7
I
N/A
N/A
N/A
N/A
ADC_CH0
I
(see (8)
)
Analog input
(up to 1.5 V)
or digital I/O
GPIO2 (PN)
UART0_RX
UART1_RX
GT_CCP02
0
3
6
7
I/O
Hi-Z, Pull,
Drive
57(12)
Hi-Z, Pull, Drive
Hi-Z
I
I
I
N/A
ADC_CH1
I
(see (8)
)
Hi-Z, Pull, Drive
Analog input
(up to 1.5 V)
or digital I/O
Hi-Z, Pull,
Drive
58(12)
Hi-Z
Hi-Z
GPIO3 (PN)
0
6
4
I/O
O
I
UART1_TX
1
pDATA7 (CAM_D3)
Hi-Z, Pull, Drive
N/A
ADC_CH2
I
(see (8)
)
Analog input
(up to 1.5 V)
or digital I/O
Hi-Z, Pull,
Drive
59(12)
Hi-Z, Pull, Drive
GPIO4 (PN)
0
6
4
I/O
UART1_RX
I
I
pDATA6 (CAM_D2)
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nRESET = 0
Hi-Z
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
表 7-1. Pin Attributes (continued)
PAD STATES
Hib(4)
PIN
NO.
SIGNAL
TYPE(2)
PIN MUX
ENCODING
SIGNAL
DIRECTION
SIGNAL NAME(1)
LPDS(3)
N/A
ADC_CH3
I
(see (8)
)
Analog input
(up to 1.5 V)
or digital I/O
GPIO5 (PN)
pDATA5 (CAM_D1)
McAXR1
0
4
I/O
I
Hi-Z, Pull,
Drive
60(12)
Hi-Z, Pull, Drive
6
I/O
I
GT_CCP05
GPIO6 (PN)
UART0_RTS
pDATA4 (CAM_D0)
UART1_CTS
UART0_CTS
GT_CCP06
GPIO7 (PN)
McACLKX
7
0
I/O
O
I
Hi-Z, Pull, Drive
1
5
4
Hi-Z, Pull,
Drive
61
I/O
Hi-Z
3
I
Hi-Z, Pull, Drive
6
I
7
I
0
I/O
O
O
O
O
I/O
I
Hi-Z, Pull, Drive
1
13
3
Hi-Z, Pull,
Drive
62
63
64
UART1_RTS
UART0_RTS
UART0_TX
I/O
I/O
Hi-Z
Hi-Z
10
11
0
GPIO8 (PN)
SDCARD_IRQ
McAFSX
6
Hi-Z, Pull,
Drive
Hi-Z, Pull, Drive
7
O
I
GT_CCP06
GPIO9 (PN)
GT_PWM05
SDCARD_DATA0
McAXR0
12
0
I/O
O
I/O
I/O
I
3
Hi-Z, Pull,
Drive
I/O
—
6
Hi-Z, Pull, Drive
N/A
Hi-Z
N/A
7
GT_CCP00
12
N/A
GND_TAB
N/A
N/A
(1) Signals names with (PN) denote the default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin
configuration), according to the need.
(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak
pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(7) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF
device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.
(8) For details on proper use, see 节 7.5.
(9) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.
For this reason, the pin must be output only when used for digital functions.
(10) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device
between two antennas. These pins must not be used for other functionalities.
(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level
configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some
applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,
the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to
automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent
false detection, TI recommends using pin 52 for output-only functions.
(12) This pin is shared by the ADC inputs and digital I/O pad cells.
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Note
The ADC inputs are tolerant up to 1.8 V (see 节 8.14.6.6.1 for more details about the usable range of
the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent
accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital
I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter
disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For
more information about drive strength and reset states for analog-digital multiplexed pins, see 节 7.5.
7.3 Signal Descriptions
7.3.1 Signal Descriptions
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
FUNCTION
SIGNAL NAME
ADC_CH0
DESCRIPTION
57
58
59
60
29
30
21
22
23
I/O
I/O
I/O
I/O
O
I
I
ADC channel 0 input (maximum of 1.5 V)
ADC channel 1 input (maximum of 1.5 V)
ADC channel 2 input (maximum of 1.5 V)
ADC channel 3 input (maximum of 1.5 V)
Antenna selection control 1
ADC_CH1
ADC
ADC_CH2
I
ADC_CH3
I
ANTSEL1
O
O
O
—
—
Antenna
selection
ANTSEL2
O
Antenna selection control 2
TCX0_EN
O
Enable to optional external 40-MHz TCXO
40-MHz crystal; pull down if external TCXO is used
40-MHz crystal or TCXO clock input
WLAN_XTAL_N
WLAN_XTAL_P
—
—
Clock
Connect 32.768-kHz crystal or force external CMOS
level clock
RTC_XTAL_P
RTC_XTAL_N
51
52
—
—
—
—
Connect 32.768-kHz crystal or connect 100-kΩ resistor
to supply voltage
TDI
16
17
19
20
1
I/O
I/O
I/O
I/O
I
O
I
JTAG TDI. Reset default pinout.
TDO
TCK
TMS
JTAG TDO. Reset default pinout.
JTAG/SWD TCK. Reset default pinout.
JTAG/SWD TMS. Reset default pinout.
JTAG / SWD
I/O
3
I2C_SCL
I2C_SDA
I/O
I/O
I/O (open drain) I2C clock data
5
16
2
I2C
4
I/O (open drain) I2C data
6
17
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PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
FUNCTION
SIGNAL NAME
GT_PWM06
DESCRIPTION
Pulse-width modulated O/P
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
GT_CCP01
GT_PWM07
GT_CCP02
GT_CCP03
Timer capture port
2
O
I
Pulse-width modulated O/P
2
3
I
4
I
GT_CCP04
GT_CCP05
15
5
I
I
Timer capture port
6
I
17
61
63
7
I
GT_CCP06
I
Timers
I
GT_CCP07
PWM0
I
17
19
21
50
64
53
55
57
60
64
O
O
O
I
GT_PWM03
GT_PWM02
Pulse-width modulated output
I/O
I/O
I/O
I/O
I/O
I
GT_CCP00
I
GT_CCP05
GT_CCP01
GT_CCP02
GT_CCP05
GT_PWM05
I
Timer capture port
I
I
I
I/O
O
Pulse-width modulated output
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FUNCTION
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PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
SIGNAL NAME
GPIO10
DESCRIPTION
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO22
GPIO23
GPIO24
GPIO28
GPIO29
GPIO25
GPIO31
GPIO0
2
3
4
5
6
7
General-purpose input or output
8
15
16
17
18
20
21
45
50
52
53
55
57
58
59
60
61
62
63
64
2
GPIO
General-purpose output only
General-purpose input or output
General-purpose output only
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GPIO32
GPIO30
GPIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO2
GPIO3
GPIO4
General-purpose input or output
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
15
17
21
45
53
63
3
McAFSX
I/O
O
I2S audio port frame sync
I/O
O
O
O
McASP
McACLK
McAXR1
52
53
50
60
45
50
I2S audio port clock output
I2S or PCM
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I2S audio port data 1 (RX and TX)
I2S audio port data 0 (RX and TX)
I/O
I/O
I2S audio port data (only output mode is supported on
pin 52)
McAXR0
52
O
O
64
62
I/O
I/O
I/O
O
I2S audio port data (RX and TX)
I2S audio port clock
McACLKX
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PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
FUNCTION
SIGNAL NAME
DESCRIPTION
1
7
SDCARD_CLK
I/O
O
SD card clock data
2
I/O
I/O
I/O (open drain)
I/O
SDCARD_CMD
SD card command line
SD card data
Multimedia card
(MMC or SD)
8
6
SDCARD_DATA0
I/O
I/O
64
63
2
SDCARD_IRQ
pXCLK (XVCLK)
pVS (VSYNC)
pHS (HSYNC)
pDATA8 (CAM_D4)
pDATA9 (CAM_D5)
pDATA10 (CAM_D6)
pDATA11 (CAM_D7)
pCLK (PIXCLK)
pDATA7 (CAM_D3)
pDATA6 (CAM_D2)
pDATA5 (CAM_D1)
pDATA4 (CAM_D0)
VDD_DIG1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I
Interrupt from SD card (future support)
Free clock to parallel camera
Parallel camera vertical sync
Parallel camera horizontal sync
Parallel camera data bit 4
3
4
I
5
I
6
I
Parallel camera data bit 5
7
I
Parallel camera data bit 6
Parallel interface
(8-bit π)
8
I
Parallel camera data bit 7
55
58
59
60
61
9
I
Pixel clock from parallel camera sensor
Parallel camera data bit 3
I
I
Parallel camera data bit 2
I
Parallel camera data bit 1
I/O
—
I
Parallel camera data bit 0
—
—
—
—
—
—
Internal digital core voltage
VIN_IO1
10
24
25
33
36
—
Device supply voltage (VBAT
Internal analog voltage
)
VDD_PLL
—
LDO_IN2
—
Internal analog RF supply from analog DC/DC output
Internal PA supply voltage from PA DC/DC output
Internal analog RF supply from analog DC/DC output
VDD_PA_IN
—
LDO_IN1
—
Analog DC/DC input (connected to device input supply
[VBAT])
VIN_DCDC_ANA
DCDC_ANA_SW
VIN_DCDC_PA
37
38
39
—
—
—
—
—
—
Internal analog DC/DC switching node
PA DC/DC input (connected to device input supply
[VBAT])
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
DCDC_DIG_SW
40
41
42
43
—
—
—
—
—
—
—
—
Internal PA DC/DC switching node
Power
Internal PA buck converter output
Internal digital DC/DC switching node
Digital DC/DC input (connected to device input supply
[VBAT])
VIN_DCDC_DIG
44
—
—
DCDC_ANA2_SW_P
DCDC_ANA2_SW_N
VDD_ANA2
45
46
47
48
49
54
56
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Analog to DC/DC converter +ve switching node
Internal analog to DC/DC converter –ve switching node
Internal analog to DC/DC output
VDD_ANA1
Internal analog supply fed by ANA2 DC/DC output
Internal SRAM LDO output
VDD_RAM
VIN_IO2
Device supply voltage (VBAT
Internal digital core voltage
)
VDD_DIG2
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FUNCTION
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
SIGNAL NAME
DESCRIPTION
5
45
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
GSPI_CLK
General SPI clock
GSPI_MISO
GSPI_CS
General SPI MISO
General SPI chip select
General SPI MOSI
53
8
SPI
50
7
GSPI_MOSI
52
11
12
13
14
1
FLASH_SPI_CLK
FLASH_SPI_DOUT
FLASH_SPI_DIN
FLASH_SPI_CS
O
Clock to SPI serial flash (fixed default)
Data to SPI serial flash (fixed default)
Data from SPI serial flash (fixed default)
Device select to SPI serial flash (fixed default)
O
FLASH SPI
I
O
O
O
O
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
7
UART1_TX
16
55
58
2
UART1 TX data
8
I
17
45
57
59
50
62
61
3
I
UART1_RX
UART1 RX data
I
I
I
O
O
I
UART1_RTS
UART1_CTS
UART1 request-to-send (active low)
UART1 clear-to-send (active low)
UART
O
O
O
O
I
53
55
62
4
UART0_TX
UART0 TX data
UART0_RX
45
57
50
61
50
52
61
62
21(1)
34
35
32
I
UART0 RX data
I
I
UART0_CTS
UART0 clear-to-send input (active low)
I
O
O
O
O
I
UART0_RTS
SOP2
UART0 request-to-send (active low)
I/O
I/O
O
Sense-on-power 2
Sense-on-Power SOP1
SOP0
—
—
—
—
Configuration sense-on-power 1
Configuration sense-on-power 0
Global master device reset (active low)
—
Reset
nRESET
—
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PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
FUNCTION
RF
SIGNAL NAME
RF_BG
DESCRIPTION
31
—
—
WLAN analog RF 802.11 b/g bands
(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
7.4 Pin Multiplexing
表 7-2. Pin Multiplexing
ANALO
G OR
REGIST
ER
ADDRE
SS
SPECIA
L
FUNCTI
ON
DIGITAL FUNCTION (XXX FIELD ENCODING)(1)
REGISTER NAME
PIN
JTAG
0
1
2
3
4
5
6
7
8
9
10
11
12
13
SDCA
RD_C
LK
0x4402 GPIO_PAD_CONFI
E0C8 G_10
I2C_S
CL
GT_PW
M06
UART1_
TX
GT_CC
P01
1
2
—
GPIO10
—
—
—
—
—
—
—
—
pXCL
K
(XVCL
K)
SDCA
RD_C
MD
0x4402 GPIO_PAD_CONFI
E0CC G_11
I2C_S
DA
GT_PW
M07
UART1_
RX
GT_CC MCAFS
P02
—
GPIO11
—
—
—
—
—
—
X
pVS
0x4402 GPIO_PAD_CONFI
E0D0 G_12
I2C_SC
L
UART0_
TX
GT_CC
P03
3
4
—
—
GPIO12
GPIO13
—
—
—
—
McACLK (VSYN
C)
—
—
—
—
—
—
—
—
—
—
—
—
pHS
(HSYN
C)
0x4402 GPIO_PAD_CONFI
E0D4 G_13
I2C_SD
A
UART0_
RX
GT_CC
P04
—
—
pDATA
8
(CAM_
D4)
0x4402 GPIO_PAD_CONFI
E0D8 G_14
I2C_SC
L
GSPI_C
LK
GT_CC
P05
5
6
7
8
—
—
—
GPIO14
GPIO15
GPIO16
GPIO17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
pDATA
9
(CAM_
D5)
SDCA
RD_D
ATA0
0x4402 GPIO_PAD_CONFI
E0DC G_15
I2C_SD
A
GSPI_
MISO
GT_CC
P06
—
—
—
—
—
—
pDATA
10
(CAM_
D6)
SDCA
RD_C
LK
0x4402 GPIO_PAD_CONFI
E0E0 G_16
UART1
_TX
GSPI_
MOSI
GT_CC
P07
pDATA
11
(CAM_
D7)
SDCA
RD_C
MD
0x4402 GPIO_PAD_CONFI
E0E4 G_17
UART1
_RX
GSPI_C
S
—
—
—
—
—
—
—
0x4402 GPIO_PAD_CONFI
E0F8 G_22
GT_CC
P04
McAFS
X
15
16
GPIO22
GPIO23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Muxed
with
JTAG
0x4402 GPIO_PAD_CONFI
E0FC G_23
UART1
_TX
I2C_S
CL
TDI
—
—
Muxed
with
JTAG
TDO
0x4402 GPIO_PAD_CONFI
E100 G_24
UART1
_RX
GT_C
CP06
McAF
SX
I2C_S
DA
17
18
GPIO24
GPIO28
TDO
—
—
—
PWM0
—
—
—
—
—
—
—
—
—
—
—
—
—
0x4402 GPIO_PAD_CONFI
E140 G_40
—
—
—
—
—
—
—
—
—
Muxed
with
JTAG or
SWD
GT_
PWM0
3
0x4402 GPIO_PAD_CONFI
E110 G_28
19
—
TCK
—
—
—
—
—
—
—
and TCK
Muxed
with
0x4402 GPIO_PAD_CONFI
E114 G_29
JTAG or
SWD
and
20
GPIO29
GPIO25
TMS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMSC
GT_
PWM0
2
0x4402 GPIO_PAD_CONFI
E104 G_25
McAFS
X
21(2)
—
0x4402 GPIO_PAD_CONFI
E108 G_26
ANTSEL1
29
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
0x4402 GPIO_PAD_CONFI
E10C G_27
ANTSEL2
(3)
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表 7-2. Pin Multiplexing (continued)
ANALO
G OR
SPECIA
L
REGIST
ER
ADDRE
SS
DIGITAL FUNCTION (XXX FIELD ENCODING)(1)
REGISTER NAME
PIN
FUNCTI
ON
JTAG
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0x4402 GPIO_PAD_CONFI
UART1
_RX
McAX GSPI_C
R0 LK
UART0
_RX
McAFS
X
45
50
—
GPIO31
—
—
—
—
—
—
—
—
—
—
E11C
G_31
UART1
_
RTS
UART0
_
CTS
0x4402 GPIO_PAD_CONFI
E0A0 G_0
UART0_ McAX
RTS
McAX GT_CC
GSPI_
CS
—
GPIO0
—
—
—
—
R0
R1
P00
UART
0 _
RTS
0x4402 GPIO_PAD_CONFI
E120 G_32
McACL
K
McAX
R0
GSPI_
MOSI
52
53
55
57
—
-—
—
GPIO32
GPIO30
GPIO1
GPIO2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x4402 GPIO_PAD_CONFI
E118 G_30
McACL
K
GT_C
CP05
GSPI_
MISO
UART0
_TX
McAFSX
—
—
—
—
pCLK
(PIXC
LK)
0x4402 GPIO_PAD_CONFI
E0A4 G_1
UART0_
TX
UART GT_CC
1_TX P01
—
—
—
—
0x4402 GPIO_PAD_CONFI
E0A8 G_2
UART0_
RX
UART GT_CC
1_RX
—
—
P02
—
pDATA
7
(CAM_
D3)
0x4402 GPIO_PAD_CONFI
E0AC G_3
UART
1_TX
58
59
60
61
—
—
—
—
GPIO3
GPIO4
GPIO5
GPIO6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
pDATA
6
(CAM_
D2)
0x4402 GPIO_PAD_CONFI
E0B0 G_4
UART
1_RX
—
pDATA
5
(CAM_
D1)
0x4402 GPIO_PAD_CONFI
E0B4 G_5
McAX GT_CC
R1
P05
pDATA
4
(CAM_
D0)
UART0 UART
0x4402 GPIO_PAD_CONFI
E0B8 G_6
UART1_
CTS
GT_CC
P06
_
RTS
0_
CTS
—
—
UART0
_
RTS
0x4402 GPIO_PAD_CONFI
E0BC G_7
UART1_
RTS
UART
0_TX
McACL
KX
62
63
64
—
—
GPIO7
GPIO8
GPIO9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDCA
RD_
IRQ
0x4402 GPIO_PAD_CONFI
E0C0 G_8
McAFS
X
GT_CC
P06
—
—
—
—
—
—
—
SDCA
RD_
DATA0
0x4402 GPIO_PAD_CONFI
E0C4 G_9
GT_PW
M05
McAXR
0
GT_CC
P00
-—
(1) Pin mux encodings with (RD) denote the default encoding after reset release.
(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
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7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
表 7-3 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time
power up and reset (nRESET pulled low).
表 7-3. Drive Strength and Reset States for Analog and Digital Multiplexed Pins
STATE AFTER
CONFIGURATION OF
ANALOG SWITCHES
(ACTIVE, LPDS, AND HIB
POWER MODES)
MAXIMUM
EFFECTIVE
DRIVE
STRENGTH
(mA)
DEFAULT STATE AT FIRST
POWER UP OR FORCED
RESET
BOARD-LEVEL CONFIGURATION AND
USE
Pin
Connected to the enable pin of the
RF switch (ANTSEL1). Other use is not
recommended.
Analog is isolated. The digital I/O Determined by the I/O state, as
cell is also isolated. are other digital I/Os.
29
30
4
4
Connected to the enable pin of the
RF switch (ANTSEL2). Other use is not
recommended.
Analog is isolated. The digital I/O Determined by the I/O state, as
cell is also isolated. are other digital I/Os.
VDD_ANA2 (pin 47) must be shorted to the
input supply rail. Otherwise, the pin is driven
by the ANA2 DC/DC.
Analog is isolated. The digital I/O Determined by the I/O state, as
cell is also isolated. are other digital I/Os.
45
50
52
4
4
4
Analog is isolated. The digital I/O Determined by the I/O state, as
cell is also isolated. are other digital I/Os.
Generic I/O
The pin must have an external pullup of 100
kΩ to the supply rail and must be used in
output signals only.
Analog is isolated. The digital I/O Determined by the I/O state, as
cell is also isolated. are other digital I/Os.
Analog is isolated. The digital I/O Determined by the I/O state, as
53
57
58
59
60
Generic I/O
4
4
4
4
4
cell is also isolated.
are other digital I/Os.
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
Analog signal (1.8-V absolute, 1.46-V full
scale)
ADC is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as
are other digital I/Os.
7.6 Pad State After Application of Power to Chip But Before Reset Release
When a stable power is applied to the CC3220x chip for the first time or when supply voltage is restored to the
proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined
in the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than
approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set
of pins is required to have a definite value during this prereset period, an appropriate pullup or pulldown resistor
must be used at the board level. The recommended value of this external pull is 2.7 kΩ.
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7.7 Connections for Unused Pins
All unused pins must be left as no connect (NC) pins. 表 7-4 provides a list of NC pins.
表 7-4. Connections for Unused Pins
STATE AT RESET
PIN
DEFAULT FUNCTION
I/O TYPE
DESCRIPTION
AND HIBERNATE
WLAN analog
WLAN analog
WLAN analog
26
27
28
NC
NC
NC
—
—
—
Unused; leave unconnected.
Unused; leave unconnected.
Unused; leave unconnected.
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8 Specifications
All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over
process and voltage, unless otherwise indicated.
8.1 Absolute Maximum Ratings
All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process, voltage,
and operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VBAT and VIO
Pins: 37, 39, 44
Pins: 10, 54
–0.5
3.8
V
VBAT and VIO should be
tied together
VIO – VBAT (differential)
V
Digital inputs
–0.5
–0.5
–0.5
–40
–55
VIO + 0.5
2.1
V
V
RF pins
Analog pins, crystal
Operating temperature, TA
Storage temperature, Tstg
Pins: 22, 23, 51, 52
2.1
V
85
°C
°C
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
8.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
VESD
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Power-On Hours (POH)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's
standard terms and conditions for TI semiconductor products.
POWER-ON HOURS [POH]
OPERATING CONDITION
(hours)
TA up to 85°C(1)
87,600
(1) The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device
can be in any other state.
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8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
TYP
MAX
UNIT
Direct battery connection(3)
2.1(6)
3.3
3.6
VBAT, VIO
(shorted to VBAT
Pins: 10, 37, 39,
44, 54
V
Preregulated 1.85 V(4) (5)
)
Ambient thermal slew
–20
20 °C/minute
(1) Operating temperature is limited by crystal frequency variation.
(2) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect
feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the
transmission.
(3) To ensure WLAN performance, ripple on the supply must be less than ±300 mV.
(4) To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).
(5) TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.
(6) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1
V, and care must be taken when operating at the minimum specified voltage.
8.5 Current Consumption Summary (CC3220R, CC3220S)
TA = 25°C, VBAT = 3.6 V
PARAMETER
TEST CONDITIONS(1) (5)
TX power level = 0
MIN
TYP
272
190
248
182
223
160
59
MAX UNIT
1 DSSS
6 OFDM
54 OFDM
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX
RX
NWP ACTIVE
MCU ACTIVE
mA
1 DSSS
54 OFDM
59
NWP idle connected(3)
15.3
269
187
245
179
220
157
56
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP ACTIVE
MCU SLEEP
mA
1 DSSS
RX
NWP idle connected(3)
54 OFDM
56
12.2
266
184
242
176
217
154
53
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP ACTIVE
mA
MCU LPDS
1 DSSS
RX
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP LPDS(2)
135
710
µA
µA
NWP idle connected(3)
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TA = 25°C, VBAT = 3.6 V
PARAMETER
TEST CONDITIONS(1) (5)
MIN
TYP
1
MAX UNIT
MCU SHUTDOWN MCU shutdown
µA
µA
MCU HIBERNATE
MCU hibernate
4.5
420
450
670
700
VBAT = 3.6 V
VBAT = 3.3 V
VBAT = 2.1 V
VBAT = 1.85 V
Peak calibration current(4)
mA
(1) TX power level = 0 implies maximum power (see 图 8-1, 图 8-2, and 图 8-3). TX power level = 4 implies output power backed off
approximately 4 dB.
(2) LPDS current does not include the external serial Flash. The LPDS number of reported is with retention of 256KB of MCU SRAM.
The CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
(3) DTIM = 1
(4) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is
performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.
There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further
details, see CC3120, CC3220 SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide.
(5) The CC3220x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied.
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8.6 Current Consumption Summary (CC3220SF)
TA = 25°C, VBAT = 3.6 V
PARAMETER
TEST CONDITIONS(1) (5)
MIN
TYP MAX UNIT
TX power level = maximum
TX power level = maximum – 4
TX power level = maximum
TX power level = maximum – 4
TX power level = maximum
TX power level = maximum – 4
286
202
255
192
1 DSSS
6 OFDM
54 OFDM
TX
RX
NWP ACTIVE
MCU ACTIVE
232
174
74
mA
1 DSSS
54 OFDM
74
NWP idle connected(3)
25.2
282
198
251
188
228
170
70
TX power level = maximum
TX power level = maximum – 4
TX power level = maximum
TX power level = maximum – 4
TX power level = maximum
TX power level = maximum – 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP ACTIVE
MCU SLEEP
mA
1 DSSS
RX
NWP idle connected(3)
54 OFDM
70
21.2
266
184
242
176
217
154
53
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
TX power level = 0
TX power level = 4
1 DSSS
6 OFDM
54 OFDM
TX
NWP active
mA
MCU LPDS
1 DSSS
RX
54 OFDM
53
120 µA at 64KB
135 µA at 256KB
NWP LPDS(2)
135
710
1
NWP idle connected(3)
MCU shutdown
µA
MCU
SHUTDOWN
MCU
HIBERNATE
MCU hibernate
4.5
VBAT = 3.6 V
420
450
670
700
VBAT = 3.3 V
VBAT = 2.1 V
VBAT = 1.85 V
Peak calibration current(4)
mA
(1) TX power level = 0 implies maximum power (see 图 8-1, 图 8-2, and 图 8-3). TX power level = 4 implies output power backed off
approximately 4 dB.
(2) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The
CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU
retained SRAM increases LPDS current by 4 µA.
(3) DTIM = 1
(4) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,
typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be
controlled by a configuration file in the serial Flash..
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8.7 TX Power and IBAT versus TX Power Level Settings
图 8-1, 图 8-2, and 图 8-3 show TX Power and IBAT versus TX power level settings for the CC3220R and
CC3220S devices at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3220SF device,
the IBAT current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX
power level will remain the same.
In 图 8-1, the area enclosed in the circle represents a significant reduction in current during transition from TX
power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using
TX power level 4 to reduce the current.
1 DSSS
19.00
17.00
280.00
264.40
249.00
233.30
218.00
202.00
186.70
171.00
Color by
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图 8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)
6 OFDM
19.00
17.00
280.00
264.40
249.00
233.30
218.00
202.00
186.70
171.00
Color by
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图 8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)
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54 OFDM
19.00
17.00
280.00
Color by
264.40
249.00
233.30
218.00
202.00
186.70
171.00
TX Power (dBm)
15.00
13.00
IBAT (VBAT @ 3.6 V)
11.00
9.00
7.00
5.00
3.00
1.00
155.60
140.00
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TX power level setting
图 8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)
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8.8 Brownout and Blackout Conditions
The device enters a brownout condition when the input voltage drops below Vbrownout (see 图 8-4 and 图 8-5).
This condition must be considered during design of the power supply routing, especially when operating from a
battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to
networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The resistance
includes the internal resistance of the battery, the contact resistance of the battery holder (four contacts for 2×
AA batteries), and the wiring and PCB routing resistance.
Note
When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during
HIBERNATE state.
图 8-4. Brownout and Blackout Levels (1 of 2)
图 8-5. Brownout and Blackout Levels (2 of 2)
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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the
Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout
condition is equivalent to a hardware reset event in which all states within the device are lost.
表 8-1 lists the brownout and blackout voltage levels.
表 8-1. Brownout and Blackout Voltage Levels
CONDITION
VOLTAGE LEVEL
UNIT
V
Vbrownout
Vblackout
2.1
1.67
V
8.9 Electrical Characteristics (3.3 V, 25°C)
GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
Pin capacitance
TEST CONDITIONS
MIN
NOM
MAX
UNIT
pF
V
CIN
VIH
VIL
IIH
4
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
0.65 × VDD
–0.5
VDD + 0.5 V
0.35 × VDD
V
5
5
nA
nA
IIL
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.8
VDD × 0.7
VDD × 0.7
VDD × 0.75
VDD × 0.7
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VOH
High-level output voltage
V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.4 V ≤ VDD < 3.6 V
VDD × 0.2
VDD × 0.2
VDD × 0.2
VDD × 0.25
VDD × 0.35
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
IL = 6 mA; configured I/O drive
strength = 6 mA;
2.4 V ≤ VDD < 3.6 V
VOL
Low-level output voltage
V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
2-mA drive
2
4
6
2
4
6
High-level
source current
IOH
4-mA drive
6-mA drive
2-mA drive
4-mA drive
6-mA drive
mA
mA
Low-level
sink current
IOL
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UNIT
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GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
GPIO Pins 29, 30, 50, 52, and 53 (25°C)(1)
CIN
VIH
VIL
IIH
Pin capacitance
7
pF
V
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
0.65 × VDD
–0.5
VDD + 0.5 V
0.35 × VDD
V
50
50
nA
nA
IIL
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD × 0.8
VDD × 0.7
VDD × 0.7
VDD × 0.75
VDD × 0.7
2.4 V ≤ VDD < 3.6 V
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
IL = 6 mA; configured I/O drive
strength = 6 mA;
VOH
High-level output voltage
V
2.4 V ≤ VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD × 0.2
VDD × 0.2
VDD × 0.2
VDD × 0.25
VDD × 0.35
2.4 V ≤ VDD < 3.6 V
IL = 4 mA; configured I/O drive
strength = 4 mA;
2.4 V ≤ VDD < 3.6 V
IL = 6 mA; configured I/O drive
strength = 6 mA;
VOL
Low-level output voltage
V
2.4 V ≤ VDD < 3.6 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
2.1 V ≤ VDD < 2.4 V
IL = 2 mA; configured I/O drive
strength = 2 mA;
VDD = 1.85 V
2-mA drive
1.5
2.5
3.5
1.5
2.5
3.5
High-level
IOH
source current, 4-mA drive
mA
VOH = 2.4
6-mA drive
2-mA drive
Low-level
sink current
IOL
4-mA drive
mA
V
6-mA drive
nRESET(2)
VIL
0.6
Pin Internal Pullup and Pulldown (25°C)(1)
Pullup current, VOH = 2.4
(VDD = 3.0 V)
IOH
5
5
10
µA
µA
Pulldown current, VOL = 0.4
(VDD = 3.0 V)
IOL
(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk
of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength
setting is 6 mA.
(2) The nRESET pin must be held below 0.6 V for the device to register a reset.
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8.10 WLAN Receiver Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).
PARAMETER
TEST CONDITIONS (Mbps)
MIN
TYP(1)
–96.0
–94.0
–88.0
–90.5
–90.0
–86.5
–80.5
–74.5
–71.5
–70.5
–4.0
MAX
UNIT
1 DSSS
2 DSSS
11 CCK
6 OFDM
Sensitivity
9 OFDM
(8% PER for 11b rates, 10% PER for 11g/11n
dBm
rates) (10% PER)(3)
18 OFDM
36 OFDM
54 OFDM
MCS7 (GF)(2)
MCS7 (MM)(2)
802.11b
Maximum input level
(10% PER)
dBm
802.11g
–10.0
(1) In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower.
(2) Sensitivity for mixed mode is 1-dB worse.
(3) Sensitivity is 1-dB worse on channel 13 (2472 MHz).
8.11 WLAN Transmitter Characteristics
TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).(1) (2) (3)
PARAMETER
TEST CONDITIONS(3)
MIN
TYP
18.0
18.0
18.3
17.3
17.3
17.0
16.0
14.5
13.0
MAX
UNIT
dBm
ppm
1 DSSS
2 DSSS
11 CCK
6 OFDM
Maximum RMS output power measured at 1
dB from IEEE spectral mask or EVM
9 OFDM
18 OFDM
36 OFDM
54 OFDM
MCS7 (MM)
Transmit center frequency accuracy
–25
25
(1) The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.
(2) Power of 802.11b rates are reduced to meet ETSI requirements.
(3) In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.
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8.12 WLAN Filter Requirements
The device requires an external band-pass filter to meet the various emission standards, including FCC. 节
8.12.1 presents the attenuation requirements for the band-pass filter. TI recommends using the same filter used
in the reference design to ease the process of certification.
8.12.1 WLAN Filter Requirements
PARAMETER
FREQUENCY (MHz)
2412 to 2484
2412 to 2484
800 to 830
MIN
TYP
MAX
UNIT
dB
Return loss
Insertion loss(1)
10
1
45
25
48
50
25
25
35
45
25
50
1.5
dB
30
20
30
45
20
20
20
35
20
1600 to 1670
3200 to 3300
4000 to 4150
4800 to 5000
5600 to 5800
6400 to 6600
7200 to 7500
7500 to 10000
2412 to 2484
Bandpass
Attenuation
dB
Reference impendence
Filter type
Ω
(1) Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation
requirements.
8.13 Thermal Resistance Characteristics
8.13.1 Thermal Resistance Characteristics for RGK Package
AIR FLOW
PARAMETER
0 lfm (C/W)
150 lfm (C/W)
250 lfm (C/W)
500 lfm (C/W)
θja
Ψjt
Ψjb
θjc
23
0.2
2.3
6.3
2.4
14.6
0.2
12.4
0.3
10.8
0.1
2.3
2.2
2.4
θjb
8.14 Timing and Switching Characteristics
8.14.1 Power Supply Sequencing
For proper operation of the CC3220x device, perform the recommended power-up sequencing as follows:
1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board.
2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K
||, 1 µF, RC = 100 ms).
3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).
For timing diagrams, see 节 8.14.3.
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8.14.2 Device Reset
When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow
one of the two alternatives to ensure the reset is properly applied:
•
•
A negative reset pulse (on pin 32) of at least 200-ms duration
If the above cannot be guaranteed, a pull-down resistor of 2 MΩ should be connected to pin 52
(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.
To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset. It is
preferable to use software reset instead of an external trigger when a reset is required.
8.14.3 Reset Timing
8.14.3.1 nRESET (32-kHz Crystal)
图 8-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.
T1
T2
T3
T4
VBAT
VIO
nRESET
APP CODE
LOAD
APP CODE
EXECUTION
POWER
OFF
RESET
HW INIT
FW INIT
STATE
32-kHz
RTC CLK
T1 should be ≥200 ms without a pulldown resistor on the XTAL_N pin or T1 should be ≥100 µs if there is 2-MΩ pulldown resistor on the
XTAL_N pin.
图 8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)
节 8.14.3.2 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset removal.
8.14.3.2 First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)
ITEM
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
ms
ms
s
Depends on application board
power supply, decoupling capacitor,
and so on
T1
T2
T3
Supply settling time
3
Hardware wake-up time
25
Time taken by ROM
firmware to initialize
hardware
Includes 32.768-kHz XOSC settling
time
1.1
CC3220R
CC3220S
Image size (KB) × 0.75 ms
Image size (KB) × 1.7 ms
App code load time for
CC3220R and CC3220S
T4
App code integrity check
time for CC3220SF
CC3220SF
Image size (KB) × 0.06 ms
8.14.3.3 nRESET (External 32-kHz)
图 8-7 shows the reset timing diagram for the external 32-kHz first-time power-up and reset removal.
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T1
T2
T3
T4
VBAT
VIO
nRESET
APP CODE
EXECUTION
POWER
STATE
OFF
APP CODE
LOAD
RESET
HW INIT
FW INIT
32-kHz
RTC CLK
图 8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz)
节 8.14.3.3.1 describes the timing requirements for the external 32-kHz clock first-time power-up and reset
removal.
8.14.3.3.1 First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz)
ITEM
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
ms
Depends on application board power
supply, decoupling capacitor, and so
on
T1
T2
Supply settling time
Hardware wake-up time
3
25
5
ms
CC3220R
CC3220S
CC3220SF
CC3220R
CC3220S
Time taken by ROM
firmware to initialize
hardware
T3
T4
10.3
17.3
ms
Image size (KB) × 0.75 ms
Image size (KB) × 1.7 ms
App code load time for
CC3220R and CC3220S
App code integrity check
time for CC3220SF
CC3220SF
Image size (KB) × 0.06 ms
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8.14.4 Wakeup From HIBERNATE Mode
图 8-8 shows the timing diagram for wakeup from HIBERNATE mode.
Application software requests
entry to HIBERNATE mode
THIB_MIN
T2
T3
T4
VBAT
VIO
nRESET
STATE
APP CODE
EXECUTION
LOAD
ACTIVE
HIBERNATE
HW WAKEUP
FW INIT
32-kHz
RTC CLK
图 8-8. Wakeup From HIBERNATE Timing Diagram
Note
The 32.768-kHz crystal is kept enabled by default when the chip goes into HIBERNATE mode .
8.14.5 Clock Specifications
The CC3220x device requires two separate clocks for its operation:
•
•
A slow clock running at 32.768 kHz is used for the RTC.
A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.
The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated
TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system
and to reduce overall cost.
8.14.5.1 Slow Clock Using Internal Oscillator
The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock
frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P
(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.
图 8-9 shows the crystal connections for the slow clock.
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51
RTC_XTAL_P
10 pF
GND
32.768 kHz
52
RTC_XTAL_N
10 pF
GND
Copyright © 2017, Texas Instruments Incorporated
图 8-9. RTC Crystal Connections
节 8.14.5.1.1 lists the RTC crystal requirements.
8.14.5.1.1 RTC Crystal Requirements
CHARACTERISTICS
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
ppm
kΩ
32.768
Frequency accuracy
Crystal ESR
Initial plus temperature plus aging
32.768 kHz
±150
70
8.14.5.2 Slow Clock Using an External Clock
When an RTC oscillator is present in the system, the CC3220x device can accept this clock directly as an
input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a
CMOS-level clock compatible with VIO fed to the device.
图 8-10 shows the external RTC input connection.
32.768 kHz
RTC_XTAL_P
Host system
VIO
100 KΩ
RTC_XTAL_N
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图 8-10. External RTC Input
节 8.14.5.2.1 lists the external RTC digital clock requirements.
8.14.5.2.1 External RTC Digital Clock Requirements
CHARACTERISTICS
Frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32768
Hz
Frequency accuracy
(Initial plus temperature plus aging)
±150
ppm
ns
tr, tf
Input transition time tr, tf (10% to 90%)
100
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CHARACTERISTICS
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TEST CONDITIONS
MIN
TYP
MAX
80%
UNIT
Frequency input duty cycle
20%
50%
Vih
Vil
0.65 × VIO
VIO
V
Slow clock input voltage limits
Square wave, DC coupled
0
1
0.35 × VIO
Vpeak
MΩ
pF
Input impedance
5
8.14.5.3 Fast Clock (Fref) Using an External Crystal
The CC3220x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The
crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading
capacitors.
图 8-11 shows the crystal connections for the fast clock.
23
WLAN_XTAL_P
6.2 pF
GND
40 MHz
22
WLAN_XTAL_N
6.2 pF
GND
SWAS031-030
A. The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for
information on frequency tuning.
图 8-11. Fast Clock Crystal Connections
节 8.14.5.3.1 lists the WLAN fast-clock crystal requirements.
8.14.5.3.1 WLAN Fast-Clock Crystal Requirements
CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ppm
Ω
Frequency
40
Frequency accuracy
Crystal ESR
Initial plus temperature plus aging
40 MHz
±25
60
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8.14.5.4 Fast Clock (Fref) Using an External Oscillator
The CC3220x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the
clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external
TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the
system.
If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the
LDO improves noise on the TCXO power supply.
图 8-12 shows the connection.
Vcc
XO (40 MHz)
EN
CC3220x
TCXO_EN
82 pF
WLAN_XTAL_P
WLAN_XTAL_N
OUT
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图 8-12. External TCXO Input
节 8.14.5.4.1 lists the external Fref clock requirements.
8.14.5.4.1 External Fref Clock Requirements (–40°C to +85°C)
CHARACTERISTICS
Frequency
TEST CONDITIONS
MIN
TYP
MAX UNIT
40.00
MHz
Frequency accuracy (Initial plus temperature plus
aging)
±25 ppm
55%
Frequency input duty cycle
Clock voltage limits
45%
0.7
50%
Sine or clipped sine wave, AC
coupled
Vpp
1.2
Vpp
at 1 kHz
–125
Phase noise at 40 MHz
at 10 kHz
at 100 kHz
–138.5 dBc/Hz
–143
kΩ
Resistance
Input impedance
12
Capacitance
7
pF
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8.14.6 Peripherals Timing
This section describes the peripherals that are supported by the CC3220x device:
•
•
•
•
•
•
•
•
•
•
SPI
I2S
GPIOs
I2C
IEEE 1149.1 JTAG
ADC
Camera parallel port
UART
SD Host
Timers
8.14.6.1 SPI
8.14.6.1.1 SPI Master
The CC3220x microcontroller includes one SPI module, which can be configured as a master or slave device.
The SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing
control between chip select and external clock generation; and a programmable delay before the first SPI word is
transmitted. Slave mode does not include a dead cycle between two successive words.
图 8-13 shows the timing diagram for the SPI master.
T2
CLK
T6
T7
MISO
MOSI
T9
T8
图 8-13. SPI Master Timing Diagram
节 8.14.6.1.1.1 lists the timing parameters for the SPI master.
8.14.6.1.1.1 SPI Master Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
F(1)
Tclk
D(1)
Clock frequency
Clock period
20
MHz
ns
(1)
T2
50
45%
1
Duty cycle
55%
(1)
T6
T7
T8
T9
tIS
RX data setup time
RX data hold time
TX data output delay
TX data hold time
ns
ns
ns
ns
(1)
tIH
2
(1)
(1)
tOD
tOH
8.5
8
(1) Timing parameter assumes a maximum load of 20 pF.
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8.14.6.1.2 SPI Slave
图 8-14 shows the timing diagram for the SPI slave.
T2
CLK
T6
T7
MISO
MOSI
T9
T8
图 8-14. SPI Slave Timing Diagram
节 8.14.6.1.2.1 lists the timing parameters for the SPI slave.
8.14.6.1.2.1 SPI Slave Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
Clock frequency at VBAT = 3.3 V
20
12
F(1)
MHz
ns
Clock frequency at VBAT ≤ 2.1 V
Clock period
(1)
T2
Tclk
D(1)
50
45%
4
Duty cycle
55%
(1)
T6
T7
T8
T9
tIS
RX data setup time
RX data hold time
TX data output delay
TX data hold time
ns
ns
ns
ns
(1)
tIH
4
(1)
(1)
tOD
tOH
20
24
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
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8.14.6.2 I2S
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit
and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A
fractional divider is available for bit-clock generation.
8.14.6.2.1 I2S Transmit Mode
图 8-15 shows the timing diagram for the I2S transmit mode.
T2
T1
T3
McACLKX
T4
T4
McAFSX
McAXR0/1
图 8-15. I2S Transmit Mode Timing Diagram
节 8.14.6.2.1.1 lists the timing parameters for the I2S transmit mode.
8.14.6.2.1.1 I2S Transmit Mode Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
(1)
T1
T2
T3
T4
fclk
Clock frequency
Clock low period
Clock high period
TX data hold time
9.216
1/2 fclk
1/2 fclk
22
MHz
ns
tLP (1)
(1)
tHT
ns
(1)
tOH
ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.6.2.2 I2S Receive Mode
图 8-16 shows the timing diagram for the I2S receive mode.
T2
T1
T3
McACLKX
T5
T4
McAFSX
McAXR0/1
图 8-16. I2S Receive Mode Timing Diagram
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节 8.14.6.2.2.1 lists the timing parameters for the I2S receive mode.
8.14.6.2.2.1 I2S Receive Mode Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
(1)
T1
T2
T3
T4
T5
fclk
Clock frequency
Clock low period
Clock high period
RX data hold time
RX data setup time
9.216
1/2 fclk
1/2 fclk
0
MHz
ns
tLP (1)
(1)
tHT
ns
(1)
tOH
ns
(1)
tOS
15
ns
(1) Timing parameter assumes a maximum load of 20 pF.
8.14.6.3 GPIOs
All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module
consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24
programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown
strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.
图 8-17 shows the GPIO timing diagram.
VDD
80%
20%
tGPIOF
tGPIOR
SWAS031-067
图 8-17. GPIO Timing Diagram
8.14.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
节 8.14.6.3.1.1 lists the GPIO output transition times for Vsupply = 3.3 V.
8.14.6.3.1.1 GPIO Output Transition Times (Vsupply = 3.3 V)(1) (2)
tr
tf
DRIVE
STRENGTH (mA)
DRIVE STRENGTH
CONTROL BITS
UNIT
ns
MIN
NOM
MAX
MIN
NOM
MAX
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
2
4
6
8.0
9.3
10.7
8.2
9.5
5.2
2.6
11.0
6.6
3.2
7.1
3.5
7.6
3.7
4.7
2.3
5.8
2.9
ns
ns
(1) Vsupply = 3.3 V, T = 25°C, total pin load = 30 pF
(2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.
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8.14.6.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.85 V)
节 8.14.6.3.2.1 lists the GPIO output transition times for Vsupply = 1.8 V.
8.14.6.3.2.1 GPIO Output Transition Times (Vsupply = 1.85 V)(1) (2)
tr
tf
DRIVE
STRENGTH (mA)
DRIVE STRENGTH
CONTROL BITS
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
2MA_EN=1
4MA_EN=0
2MA_EN=0
4MA_EN=1
2MA_EN=1
4MA_EN=1
2
4
6
11.7
13.9
16.3
11.5
13.9
16.7
ns
ns
ns
13.7
5.5
15.6
6.4
18.0
7.4
9.9
3.8
11.6
4.7
13.6
5.8
(1) Vsupply = 1.8 V, T = 25°C, total pin load = 30 pF
(2) The transition data applies to the pins other than the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.
8.14.6.3.3 GPIO Input Transition Time Parameters
节 8.14.6.3.3.1 lists the input transition time parameters.
8.14.6.3.3.1 GPIO Input Transition Time Parameters'
MIN
MAX
UNIT
tr
tf
1
1
3
3
ns
ns
Input transition time (tr, tf), 10% to 90%
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8.14.6.4 I2C
The CC3220x microcontroller includes one I2C module operating with standard (100 kbps) or fast
(400 kbps) transmission speeds.
图 8-18 shows the I2C timing diagram.
T2
T6
T5
I2CSCL
I2CSDA
T1
T7
T4
T8
T3
T9
图 8-18. I2C Timing Diagram
节 8.14.6.4.1 lists the I2C timing parameters.
8.14.6.4.1 I2C Timing Parameters(3)
PARAMETER
NUMBER
MIN
MAX
UNIT
T2
T3
T4
T5
T6
T7
T8
T9
tLP
Clock low period
See (1)
System clock
ns
tSRT
tDH
tSFT
tHT
SCL/SDA rise time
Data hold time
See (2)
NA
3
SCL/SDA fall time
Clock high time
ns
See (1)
tLP/2
36
System clock
System clock
System clock
System clock
tDS
Data setup time
tSCSR
tSCS
Start condition setup time
Stop condition setup time
24
(1) This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal
value programmed in this register.
(2) Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
(3) All timing is with 6-mA drive and 20-pF load.
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8.14.6.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control
the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.
图 8-19 shows the JTAG timing diagram.
T2
T3
T4
TCK
TMS
TDI
T7
TMS Input Valid
T9 T10
TDI Input Valid
T8
T8
TMS Input Valid
T7
T9
T10
TDI Input Valid
T1
T11
TDO Output Valid
TDO
TDO Output Valid
图 8-19. JTAG Timing Diagram
节 8.14.6.5.1 lists the JTAG timing parameters.
8.14.6.5.1 JTAG Timing Parameters
PARAMETER
NUMBER
MIN
MAX
UNIT
T1
T2
fTCK
Clock frequency
Clock period
15
1 / fTCK
tTCK / 2
tTCK / 2
MHz
ns
tTCK
T3
tCL
Clock low period
Clock high period
TMS setup time
TMS hold time
TDI setup time
TDI hold time
ns
T4
tCH
ns
T7
tTMS_SU
tTMS_HO
tTDI_SU
tTDI_HO
tTDO_HO
1
16
1
ns
T8
ns
T9
ns
T10
T11
16
ns
TDO hold time
15
ns
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8.14.6.6 ADC
图 8-20 shows the ADC clock timing diagram.
Repeats Every 16 µs
Internal Ch
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
EXT CHANNEL 1
INTERNAL CHANNEL
INTERNAL CHANNEL
图 8-20. ADC Clock Timing Diagram
节 8.14.6.6.1 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using
the ADC and for application-specific examples.
8.14.6.6.1 ADC Electrical Specifications
TEST CONDITIONS AND
PARAMETER
Nbits
DESCRIPTION
Number of bits
MIN
TYP
MAX
UNIT
ASSUMPTIONS
12
Bits
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
INL
Integral nonlinearity
–2.5
2.5
LSB
Worst-case deviation of any step
from ideal
DNL
Differential nonlinearity
–1
0
4
1.4
LSB
V
Input range
Driving source
impedance
100
Ω
Successive approximation input
clock rate
FCLK
Clock rate
10
MHz
pF
Input capacitance
12
2.15
0.7
ADC Pin 57
ADC Pin 58
ADC Pin 59
ADC Pin 60
Input impedance
kΩ
2.12
1.17
4
Number of channels
Fsample
Sampling rate of each pin
62.5
KSPS
kHz
F_input_max
Maximum input signal frequency
31
Input frequency DC to 300 Hz
and 1.4 Vpp sine wave input
SINAD
Signal-to-noise and distortion
Active supply current
55
60
dB
Average for analog-to-digital
during conversion without
reference current
I_active
1.5
mA
Total for analog-to-digital when
not active (this must be the SoC
level test)
Power-down supply current for
core supply
I_PD
1
µA
Absolute offset error
Gain error
FCLK = 10 MHz
±2
mV
±2%
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PARAMETER
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TEST CONDITIONS AND
ASSUMPTIONS
DESCRIPTION
MIN
TYP
MAX
UNIT
Vref
ADC reference voltage
1.467
V
8.14.6.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a
FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
图 8-21 shows the timing diagram for the camera parallel port.
T3
T2
T4
pCLK
T6
T7
pVS, pHS
pDATA
图 8-21. Camera Parallel Port Timing Diagram
节 8.14.6.7.1 lists the timing parameters for the camera parallel port.
8.14.6.7.1 Camera Parallel Port Timing Parameters
PARAMETER NUMBER
MIN
MAX
2
UNIT
MHz
ns
pCLK
Tclk
tLP
Clock frequency
Clock period
T2
T3
T4
T6
T7
1/pCLK
Tclk/2
Tclk/2
2
Clock low period
Clock high period
RX data setup time
RX data hold time
Duty cycle
ns
tHT
tIS
ns
ns
tIH
2
ns
D
45%
55%
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8.14.6.8 UART
The CC3220x device includes two UARTs with the following features:
•
•
•
Programmable baud-rate generator allowing speeds up to 3 Mbps
Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered
interface
•
•
•
•
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Generation and detection of line-breaks
Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Generation and detection of even, odd, stick, or no-parity bits
– Generation of 1 or 2 stop-bits
•
•
•
RTS and CTS hardware flow support
Standard FIFO-level and end-of-transmission interrupts
Efficient transfers using µDMA:
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO
level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed
FIFO level
•
System clock is used to generate the baud clock.
8.14.6.9 SD Host
CC3220x provides an interface between a local host (LH), such as an MCU and an SD memory card, and
handles SD transactions with minimal LH intervention.
The SD host does the following:
•
•
•
•
•
•
Provides SD card access in 1-bit mode
Deals with SD protocol at the transmission level
Handles data packing
Adds cyclic redundancy checks (CRC)
Start and end bit
Checks for syntactical correctness
The application interface sends every SD command and either polls for the status of the adapter or waits for
an interrupt request. The result is then sent back to the application interface in case of exceptions or to warn
of end-of-operation. The controller can be configured to generate DMA requests and work with minimum CPU
intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI recommends that
developers use peripheral library APIs to control and operate the block. This section emphasizes understanding
the SD host APIs provided in the peripheral library of the CC3220x Software Development Kit (SDK).
The SD Host features are as follows:
•
Full compliance with SD command and response sets, as defined in the SD memory card
– Specifications, v2.0
– Includes high-capacity (size >2 GB) cards HC SD
Flexible architecture, allowing support for new command structure.
1-bit transfer mode specifications for SD cards
•
•
•
Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
– Each buffer is 32-bits wide by 128-words deep
32-bit-wide access bus to maximize bus throughput
Single interrupt line for multiple interrupt source events
Two slave DMA channels (1 for TX, 1 for RX)
•
•
•
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•
•
•
•
•
Programmable clock generation
Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
Supports configurable busy and response timeout
Support for a wide range of card clock frequency with odd and even clock ratio
Maximum frequency supported is 24 MHz
8.14.6.10 Timers
Programmable timers can be used to count or time external events that drive the timer input pins. The CC3220x
general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block
provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate
independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers
can also be used to trigger µDMA transfers.
The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:
•
Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
Counts up or counts down
Sixteen 16- or 32-bit capture compare pins (CCP)
User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt
service routine
•
•
•
•
•
Efficient transfers using micro direct memory access controller (µDMA):
– Dedicated channel for each timer
– Burst request generated on timer interrupt
•
Runs from system clock (80 MHz)
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9 Detailed Description
The CC3220x wireless MCU family has a rich set of peripherals for diverse application requirements. This
section briefly highlights the internal details of the CC3220x devices and offers suggestions for application
configurations.
9.1 Arm® Cortex®-M4 Processor Core Subsystem
The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal
memory implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
•
•
The Cortex-M4 core has low-latency interrupt processing with the following features:
– A 32-bit Arm® Thumb® instruction set optimized for embedded applications
– Handler and thread modes
– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit
– Support for ARMv6 unaligned accesses
Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency
interrupt processing. The NVIC includes the following features:
– Bits of priority configurable from 3 to 8
– Dynamic reprioritization of interrupts
– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels
– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts
– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction
overhead
– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
Bus interfaces:
– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations
Low-cost debug solution featuring:
•
•
– Debug access to all memory and registers in the system, including access to memory-mapped devices,
access to internal core registers when the core is halted, and access to debug control registers even while
SYSRESETn is asserted
– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
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9.2 Wi-Fi Network Processor Subsystem
The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU
along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN
and Internet connections with 256-bit encryption. The CC3220x devices support station, AP, and Wi-Fi Direct
modes. The device also supports WPA2 personal and enterprise security, WPS 2.0, WPA3 personal and
enterprise. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack.
9.2.1 WLAN
The WLAN features are as follows:
•
802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,
Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels 1 to 13.
Note
802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client modes.
•
•
•
Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna without
requiring expertise in radio circuit design.
Advanced connection manager with multiple user-configurable profiles stored in serial Flash allows automatic
fast connection to an access point without user or host intervention.
Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security
accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal, and WPA3
Enterprise.
•
Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end
solution. With elaborate events notification to the host, enabling the application to control the provisioning
decision flow. The wide variety of Wi-Fi provisioning methods include:
– Access Point using HTTPS
– SmartConfig Technology: a 1-step, 1-time process to connect a CC3220-enabled device to the home
wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is usable by
deeply embedded applications
•
802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without
adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working
channel, rate, and transmitted power. The receiver mode works with the filtering options.
9.2.2 Network Stack
The Network Stack features are as follows:
•
Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet connectivity with
any MCU, microprocessor, or ASIC
Note
Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
•
•
•
Support of 16 simultaneous TCP, UDP, or RAW sockets
Support of 6 simultaneous SSL\TLS sockets
Built-in network protocols:
– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration
– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND
– DNS client for easy connection to the local network and the Internet
Built-in network application and utilities:
•
– HTTP/HTTPS
•
•
•
Web page content stored on serial Flash
RESTful APIs for setting and configuring application content
Dynamic user callbacks
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– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized
server. After connecting to the access point, the CC3220x device provides critical information, such as
device name, IP, vendor, and port number.
– DHCP server
– Ping
表 9-1 describes the NWP features.
表 9-1. NWP Features
Feature
Description
802.11b/g/n station
Wi-Fi standards
802.11b/g AP supporting up to four stations
Wi-Fi Direct client and group owner
1 to 13
Wi-Fi channels
Wi-Fi security
Wi-Fi provisioning
IP protocols
WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise
SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server
IPv4/IPv6
IP addressing
Cross layer
Static IP, LLA, DHCPv4, DHCPv6 with DAD
ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP
UDP, TCP
Transport
SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2
RAW
Ping
HTTP/HTTPS web server
Network applications and
utilities
mDNS
DNS-SD
DHCP server
Host interface
UART/SPI
Device identity
Trusted root-certificate catalog
TI root-of-trust public key
The CC3220S and CC3220SF variants also support:
•
•
•
•
•
•
•
•
•
Secure key storage
File system security
Security
Software tamper detection
Cloning protection
Secure boot
Validate the integrity and authenticity of the run-time binary during boot
Initial secure programming
Debug security
JTAG and debug
Power management
Other
Enhanced power policy management uses 802.11 power save and deep-sleep power modes
Transceiver
Programmable RX filters with event-trigger mechanism
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9.3 Security
The SimpleLink™ Wi-Fi® CC3220x Internet-on-a-Chip device enhances the security capabilities available for
development of IoT devices, while completely offloading these activities from the MCU to the networking
subsystem. The security capabilities include the following key features:
Wi-Fi and Internet Security:
•
Personal and enterprise Wi-Fi security
– Personal standards
•
•
•
AES (WPA2-PSK)
TKIP (WPA-PSK)
WEP
– Enterprise standards
•
•
•
•
•
•
•
EAP Fast
EAP PEAPv0/1
EAP PEAPv0 TLS
EAP PEAPv1 TLS EAP LS
EAP TLS
EAP TTLS TLS
EAP TTLS MSCHAPv2
•
Secure sockets
– Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2
– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS
and SSL connections
– Ciphers suites
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA
SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5
SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA
SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA
SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256
SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA
SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256
SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384
SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256
SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384
SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256
– Server authentication
– Client authentication
– Domain name verification
– Runtime socket upgrade to secure socket – STARTTLS
Secure HTTP server (HTTPS)
Trusted root-certificate catalog—Verifies that the CA used by the application is trusted and known secure
content delivery
•
•
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•
•
TI root-of-trust public key—Hardware-based mechanism that allows authenticating TI as the genuine origin of
a given content using asymmetric keys
Secure content delivery—Allows encrypted file transfer to the system using asymmetric keys created by the
device
Code and Data Security:
•
•
•
Network passwords and certificates are encrypted and signed.
Cloning protection—Application and data files are encrypted by a unique key per device.
Access control—Access to application and data files only by using a token provided in file creation time. If an
unauthorized access is detected, a tamper protection lockdown mechanism takes effect.
Encrypted and Authenticated file system (not supported in CC3220R)
Secured boot—Authentication of the application image on every boot
Code and data encryption (not supported in CC3220R)—User application and data files are encrypted in
serial flash.
•
•
•
•
•
•
Code and data authentication (not supported in CC3220R)—User Application and data files are authenticated
with a public key certificate.
Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data
buffer.
Recovery mechanism
Device Security:
•
•
Separate execution environments—Application processor and network processor run on separate Arm cores
Initial secure programming (not supported in CC3220R)—Allows for keeping the content confidential on the
production line
•
Debug security (not supported in CC3220R)
– JTAG lock
– Debug ports lock
•
True random number generator
图 9-1 shows the high-level structure of the CC3220R device. The network information files (passwords and
certificates) are encrypted using a device-specific key.
CC3220R
Network Processor + MCU
MCU
Arm® Cortex®-M4
Processor
Network Processor
Peripherals
SPI and I2C
GPIO
Wi-Fi®
Internet
256KB RAM
Internet
UART
HTTPS
TLS/SSL
TCP/IP
MAC
Baseband
Radio
PWM
ADC
OEM
Application
•
Serial Flash
OEM
Application
Data Files
Network Information
图 9-1. CC3220R High-Level Structure
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图 9-2 shows the high-level structure of the CC3220S and CC3220SF devices. The application image, user data,
and network information files (passwords, certificates) are encrypted using a device-specific key.
CC3220S and CC3220SF
Network Processor + MCU
MCU
Network Processor
Peripherals
SPI and I2C
GPIO
Arm® Cortex®-M4
Processor
Wi-Fi®
Internet
HTTPS
Internet
256KB RAM /
1MB Flash (CC3220SF)
UART
MAC
Baseband
Radio
PWM
ADC
TLS/SSL
TCP/IP
OEM
Application
•
Serial Flash
OEM
Application
Data Files
Network Information
图 9-2. CC3220S and CC3220SF High-Level Structure
9.4 Power-Management Subsystem
The CC3220x power-management subsystem contains DC/DC converters to accommodate the different voltage
or current requirements of the system.
•
Digital DC/DC (Pin 44)
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
ANA1 DC/DC (Pin 37)
•
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the ANA1 DC/DC converter is bypassed.
PA DC/DC (Pin 39)
– Input: VBAT wide voltage (2.1 to 3.6 V)
– In preregulated 1.85-V mode, the PA DC/DC converter is bypassed.
ANA2 DC/DC (Pin 47)
•
•
– Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
The CC3220x device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage
supply range. The internal power management, including DC/DC converters and LDOs, generates all of the
voltages required for the device to operate from a wide variety of input sources. For maximum flexibility, the
device can operate in the modes described in 节 9.4.1 and 节 9.4.2.
9.4.1 VBAT Wide-Voltage Connection
In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V
supply. All other voltages required to operate the device are generated internally by the DC/DC converters. This
scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common mode for the device.
9.4.2 Preregulated 1.85-V Connection
The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at pins 10, 25, 33, 36,
37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. This mode
provides the lowest BOM count version in which inductors used for PA DC/DC and ANA1 DC/DC (2.2 and 1 µH)
and a capacitor (22 µF) can be avoided.
In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following characteristics:
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•
•
Load current capacity ≥900 mA
Line and load regulation with <2% ripple with 500-mA step current and settling time of < 4 µs with the load
step
Note
The regulator must be placed as close as possible to the device so that the IR drop to the device is
very low.
9.5 Low-Power Operating Mode
From a power-management perspective, the CC3220x device comprises the following two independent
subsystems:
•
•
Arm Cortex-M4 application processor subsystem
Networking subsystem
Each subsystem operates in one of several power states.
The Cortex-M4 application processor runs the user application loaded from an external serial Flash, or internal
Flash (in CC3220SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer
functions.
The user program controls the power state of the application processor subsystem and can be in one of the five
modes described in 表 9-2.
表 9-2. User Program Modes
APPLICATION PROCESSOR
DESCRIPTION
(MCU) MODE(1)
MCU active mode
MCU executing code at 80-MHz state rate
The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode
offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity
from any GPIO line or peripheral.
MCU sleep mode
State information is lost and only certain MCU-specific register configurations are retained. The MCU
can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)
Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory
retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU
can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the
wake-up source.
MCU LPDS mode
The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly
powered by the input supply is retained. The RTC keeps running and the MCU supports wakeup from
an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms
plus the time to load the application from serial Flash, which varies according to code size. In this mode,
the MCU can be configured to wake up using the RTC timer or external event on a GPIO.
MCU hibernate mode
MCU shutdown mode
The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in
this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the
nRESET line is changed (low to shut down, high to turn on).
(1) Modes are listed in order of power consumption, with highest power modes listed first.
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The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network
activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
表 9-3).
表 9-3. Networking Subsystem Modes
NETWORK PROCESSOR MODE
DESCRIPTION
Network active mode
(processing layer 3, 2, and 1)
Transmitting or receiving IP protocol packets
Network active mode
(processing layer 2 and 1)
Transmitting or receiving MAC management frames; IP processing not required.
Network active listen mode
Network connected Idle
Special power optimized active mode for receiving beacon frames (no other frames supported)
A composite mode that implements 802.11 infrastructure power save operation. The CC3220x NWP
automatically goes into LPDS mode between beacons and then wakes to active listen mode to
receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS
mode and the cycle repeats.
Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid
wake up.
Network LPDS mode
Network disabled
The network is disabled
The operation of the application and network processor ensures that the device remains in the lowest power
mode most of the time to preserve battery life.
The following examples show the use of the power modes in applications:
•
A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but
sends and receives little data spends most of the time in connected idle, which is a composite of receiving a
beacon frame and waiting for the next beacon.
•
A product that is not continuously connected to the network but instead wakes up periodically (for example,
every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to
transmit data.
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9.6 Memory
9.6.1 External Memory Requirements
The CC3220x device maintains a proprietary file system on the serial flash. The CC3220x file system stores
the MCU binary, service pack file, system files, configuration files, certificate files, web page files, and user files.
By using a format command through the API, users can provide the total size allocated for the file system.
The starting address of the file system cannot be set and is always at the beginning of the serial flash. The
applications microcontroller must access the serial flash memory area allocated to the file system directly
through the CC3220x file system. The applications microcontroller must not access the serial flash memory area
directly.
The file system manages the allocation of serial flash blocks for stored files according to download order,
which means that the location of a specific file is not fixed in all systems. Files are stored on serial flash using
human-readable filenames rather than file IDs. The file system API works using plain text, and file encryption
and decryption is invisible to the user. Encrypted files can be accessed only through the file system.
All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB blocks and
thus use a minimum of 4KB of Flash space. Fail-safe files require twice the original size and use a minimum of
8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size is 1MB.
表 9-4 lists the minimum required memory consumption under the following assumptions:
•
•
•
System files in use consume 64 blocks (256KB).
Vendor files are not taken into account.
MCU code is taken as the maximal possible size for the CC3220 with fail-safe enabled to account for future
updates, such as through OTA.
•
•
Gang image:
– Storage for the gang image is rounded up to 32 blocks (meaning 128KB resolution).
– Gang image size depends on the actual content size of all components. Additionally, the image should
be 128KB aligned so unaligned memory is considered lost. Service pack, system files, and the 128KB
aligned memory are assumed to occupy 256KB.
All calculations consider that the restore-to-default is enabled.
表 9-4. Recommended Flash Size
ITEM
CC3220R and CC3220S [KB]
CC3220SF [KB]
20
File system allocation table
System and configuration files(1)
Service Pack(1)
20
256
256
264
264
MCU Code(1)
512
2048
Gang image size
256 + MCU
1308 + MCU
16MBit
16MBit
256 + MCU
2844 + MCU
32MBit
Total
Minimal Flash size(2)
Recommended Flash size(2)
32MBit
(1) Including fail-safe.
(2) For maximum MCU size.
Note
The maximum supported serial flash size is 32MB (256Mb). See the Using Serial Flash on CC3120/
CC3220 SimpleLink™ Wi-Fi® and Internet-of-Things Devices application report.
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9.6.2 Internal Memory
The CC3220x device includes on-chip SRAM to which application programs are downloaded and executed.
The application developer must share the SRAM for code and data. The micro direct memory access (μDMA)
controller can transfer data to and from SRAM and various peripherals. The CC3220x ROM holds the rich set of
peripheral drivers, which saves SRAM space. For more information on drivers, see the CC3220x API list.
9.6.2.1 SRAM
The CC3220x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention during
LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.
Use the µDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of memory
based on need. Retaining the memory during low-power mode provides a faster wakeup. The application
developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API
guide.
9.6.2.2 ROM
The internal zero-wait-state ROM of the CC3220x device is at address 0x0000 0000 of the device memory and
is programmed with the following components:
•
•
Bootloader
Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial Flash memory is empty). The CC3220x
DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The
DriverLib APIs in ROM can be called by applications to reduce Flash memory requirements and free the Flash
memory for other purposes.
9.6.2.3 Flash Memory
The CC3220SF device comes with an on-chip Flash memory of 1MB that allows application code to execute in
place while freeing SRAM exclusively for read-write data. The Flash memory is used for code and constant data
sections and is directly attached to the ICODE/DCODE bus of the Cortex-M4 core. A 128-bit-wide instruction
prefetch buffer allows maintenance of maximum performance for linear code or loops that fit inside the buffer.
The Flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can be
performed at word (32-bit) level.
9.6.2.4 Memory Map
表 9-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more
information on peripherals, see the API document.
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表 9-5. Memory Map
START ADDRESS
0x0000 0000
0x0100 0000
0x2000 0000
0x2200 0000
0x4000 0000
0x4000 4000
0x4000 5000
0x4000 6000
0x4000 7000
0x4000 C000
0x4000 D000
0x4002 0000
0x4002 4000
0x4002 0800
0x4003 0000
0x4003 1000
0x4003 2000
0x4003 3000
0x400F7000
0x400F E000
0x400F F000
0x4200 0000
0x4401 0000
0x4401 8000
0x4401 C000
0x4402 0000
0x4402 1000
0x4402 5000
0x4402 6000
0x4402 D000
0x4402 E000
0x4402 F000
END ADDRESS
0x0007 FFFF
0x010F FFFF
0x2003 FFFF
0x23FF FFFF
0x4000 0FFF
0x4000 4FFF
0x4000 5FFF
0x4000 6FFF
0x4000 7FFF
0x4000 CFFF
0x4000 DFFF
0x4000 07FF
0x4002 4FFF
0x4002 0FFF
0x4003 0FFF
0x4003 1FFF
0x4003 2FFF
0x4003 3FFF
0x400F 7FFF
0x400F EFFF
0x400F FFFF
0x43FF FFFF
0x4401 0FFF
0x4401 8FFF
0x4401 DFFF
0x4402 1FFF
0x4402 2FFF
0x4402 5FFF
0x4402 6FFF
0x4402 DFFF
0x4402 EFFF
0x4402 FFFF
DESCRIPTION
COMMENT
On-chip ROM (bootloader + DriverLib)
On-chip Flash (for user application code)
Bit-banded on-chip SRAM
Bit-band alias of 0x2000 0000 to 0x200F FFFF
Watchdog timer A0
CC3220SF device only
GPIO port A0
GPIO port A1
GPIO port A2
GPIO port A3
UART A0
UART A1
I2C A0 (master)
GPIO group 4
I2C A0 (slave)
General-purpose timer A0
General-purpose timer A1
General-purpose timer A2
General-purpose timer A3
Configuration registers
System control
µDMA
Bit band alias of 0x4000 0000 to 0x400F FFFF
SDIO master
Camera Interface
McASP
SSPI
Used for external serial Flash
Used by application processor
GSPI
MCU reset clock manager
MCU configuration space
Global power, reset, and clock manager (GPRCM)
MCU shared configuration
Hibernate configuration
Crypto range (includes apertures for all crypto-related
blocks as follows)
0x4403 0000
0x4403 FFFF
0x4403 0000
0x4403 5000
0x4403 7000
0x4403 9000
0xE000 0000
0xE000 1000
0xE000 2000
0xE000 E000
0xE004 0000
0xE004 1000
0xE004 2000
0x4403 0FFF
0x4403 5FFF
0x4403 7FFF
0x4403 9FFF
0xE000 0FFF
0xE000 1FFF
0xE000 2FFF
0xE000 EFFF
0xE004 0FFF
0xE004 1FFF
0xE00F FFFF
DTHE registers and TCP checksum
MD5/SHA
AES
DES
Instrumentation trace Macrocell™
Data watchpoint and trace (DWT)
Flash patch and breakpoint (FPB)
NVIC
Trace port interface unit (TPIU)
Reserved for embedded trace macrocell (ETM)
Reserved
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9.7 Restoring Factory Default Configuration
The device has an internal recovery mechanism that allows rolling back the file system to its predefined factory
image or restoring the factory default parameters of the device. The factory image is kept in a separate sector
on the serial flash in a secure manner and cannot be accessed from the host processor. The following restore
modes are supported:
•
•
•
None—no factory restore settings
Enable restore of factory default parameters
Enable restore of factory image and factory default parameters
The restore process is performed by calling SW APIs, or by pulling or forcing SOP[2:0] = 110 pins and toggling
the nRESET pin from low to high.
The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The
restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.
9.8 Boot Modes
9.8.1 Boot Mode List
The CC3220x device implements a sense-on-power (SoP) scheme to determine the device operation mode.
SoP values are sensed from the device pin during power up. This encoding determines the boot flow. Before the
device is taken out of reset, the SoP values are copied to a register and used to determine the device operation
mode while powering up. These values determine the boot flow as well as the default mapping for some of the
pins (JTAG, SWD, UART0). 表 9-6 lists the pull configurations.
表 9-6. CC3220x Functional Configurations
NAME
SOP[2]
SOP[1]
SOP[0]
SoP MODE
COMMENT
Factory, lab Flash, and SRAM loads
through the UART. The device waits
indefinitely for the UART to load code.
The SOP bits then must be toggled to
configure the device in functional mode.
Also puts JTAG in 4-wire mode.
UARTLOAD
Pullup
Pulldown
Pulldown LDfrUART
Functional development mode. In this
mode, 2-pin SWD is available to the
developer. TMS and TCK are available
for debugger connection.
FUNCTIONAL_2WJ
FUNCTIONAL_4WJ
Pulldown Pulldown
Pulldown Pulldown
Pullup
Fn2WJ
Functional development mode. In this
mode, 4-pin JTAG is available to the
developer. TDI, TMS, TCK, and TDO are
available for debugger connection.
Pulldown Fn4WJ
Supports Flash and SRAM load through
UART and functional mode. The MCU
bootloader tries to detect a UART break
on UART receive line. If the break
UARTLOAD_FUNCTIONAL_4WJ
RET_FACTORY_IMAGE
Pulldown Pullup
Pulldown Pullup
Pulldown LDfrUART_Fn4WJ signal is present, the device enters the
UARTLOAD mode, otherwise, the device
enters the functional mode. TDI, TMS,
TCK, and TDO are available for debugger
connection.
When device reset is toggled, the MCU
Pullup
RetFactDef
bootloader kickstarts the procedure to
restore factory default images.
The recommended values of pull resistors are 100 kΩ for SOP0 and SOP1 and 2.7 kΩ for SOP2. The
application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP
values from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The
SOP0 and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.
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10 Applications, Implementation, and Layout
Note
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
10.1.1 Typical Application —CC3220x Wide-Voltage Mode
图 10-1 shows the schematic for an application using the CC3220x device in the wide-voltage mode of
operation. For a full operation reference design, refer to CC3220 SimpleLink™ and Internet of Things Hardware
Design Files.
Note
For complete reference schematics and BOM, see the CC3220x product page.
表 10-1 lists the bill of materials for an application using the CC3220x device in wide-voltage mode.
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VBAT_CC
VBAT_CC
VBAT_CC
R1
10k
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
VBAT_CC
Antenna match. Pi
C2
1µF
network might be
required depending on
type of antenna.
E1
C3
C4
C5
C6
C7
0.1µF
4.7µF
4.7µF
C2
100µF
C3
100µF
4.7µF
0.1µF
L1
GND
FL1
IN
1
3
OUT
GND
GND
GND
GND
GND
3.3nH
2
4
GND
GND
GND
GND
C9
0.5pF GND GND
GND
VBAT_CC
GND
U2
VCC
U1
VIN_IO1
8
L2
10
54
44
39
37
38
48
32
31
1
6
5
2
3
7
RESET
RF_BG
CS
SCLK
SI/SIO0
R2
100k
C8
0.1µF
2.2uH
VIN_IO2
C10
SO/SIO1
WP/SIO2
RESET/SIO3
C11
0.1µF
VIN_DCDC_DIG
VIN_DCDC_PA
VIN_DCDC_ANA
DCDC_ANA_SW
VDD_ANA1
10µF
GND
4
GND
14
13
12
11
FLASH_SPI_CS
FLASH_SPI_DIN
L3
GND
GND
1uH
FLASH_SPI_DOUT
FLASH_SPI_CLK
GND
C12
0.1µF
C13
0.1µF
50
55
57
58
59
60
61
62
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
CC_GPIO_00
CC_GPIO_01
CC_GPIO_02
CC_GPIO_03
CC_GPIO_04
CC_GPIO_05
CC_GPIO_06
CC_GPIO_07
36
25
LDO_IN1
LDO_IN2
GND
GND
40
41
42
33
43
TP1
TP1
TP1
TP1
TP1
C16
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
VDD_PA_IN
CC_nReset
C14
22µF
C15
22µF
FLASH PROGRAMMING
INTERFACE
1µF
CC_GPIO_01
CC_GPIO_02
SOP0
63
64
1
L4
GPIO8
GPIO9
CC_GPIO_08
CC_GPIO_09
CC_GPIO_10
CC_GPIO_11
CC_GPIO_12
CC_GPIO_13
CC_GPIO_14
CC_GPIO_15
Add provision on the board to isolate
GPIO_01 and GPIO_02 while programming
GND
GND
GND
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
2.2uH
C19
2
3
DCDC_DIG_SW
SOP2
C17
4
VBAT_CC
9
56
5
VDD_DIG1
VDD_DIG2
10µF
C18
0.1µF
6
0.1µF
PIN 45, 46, and 47:
Refer to the BOM in the following table for
notes on device-dependent configurations.
45
46
47
49
24
7
DCDC_ANA2_SW_P
DCDC_ANA2_SW_N
VDD_ANA2
GPIO16
GPIO17
GPIO22
GPIO28
GPIO30
CC_GPIO_16
CC_GPIO_17
CC_GPIO_22
CC_GPIO_28
CC_GPIO_30
8
R8
0
15
18
53
L5
GND
GND
10uH
VDD_RAM
51
52
RTC_XTAL_P
RTC_XTAL_N
VDD_PLL
C20
10µF
27
28
26
Y1
32.768kHz
NC
NC
NC
C21
0.1µF
23
22
WLAN_XTAL_P
WLAN_XTAL_N
C22
0.1µF
2
1
35
34
21
SOP0
SOP1
SOP2
GND
C23
10pF
C24
10pF
30
29
65
ANTSEL2
ANTSEL1
GND_TAB
GND
GND
19
20
16
17
TCK
TMS
TDI
C25
6.2pF
TDO
C26
6.2pF
GND
GND
Y2
40 MHz
CC3220SF12RGK
GND
VBAT_CC
GND
GND
CC_JTAG_TDO
CC_JTAG_TDI
CC_JTAG_TMS
CC_JTAG_TCK
R7
270
JTAG
GND
J1
2
1
3
5
4
6
R4
100k
R5
100k
R6
2.7k
R3
100k
GND
GND
图 10-1. CC3220x Wide-Voltage Mode Application Circuit
表 10-1. Bill of Materials for CC3220x in Wide-Voltage Mode
QUANTI
TY
MANUFACTUR
DESIGNATOR
C1
VALUE
PART NUMBER
DESCRIPTION
ER
1
1 µF
MuRata
GRM155R61A105KE15 Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402
D
10
C2, C6, C10, C12, 0.1 µF
C13, C14, C19,
TDK
C1005X5R1A104K050B Capacitor, Ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402
A
C20, C22, C23
3
2
1
3
C3, C4, C5
C7, C8
4.7 µF
100 µF
0.5 pF
10 µF
TDK
C1005X5R0J475M050B Capacitor, Ceramic, 4.7 µF, 6.3 V, ±20%, X5R,
C
0402
Taiyo Yuden
MuRata
MuRata
LMK325ABJ107MMHT
Capacitor, Ceramic, 100 µF, 10 V, ±20%, X5R,
AEC-Q200 Grade 3, 1210
C9
GRM1555C1HR50BA01 Capacitor, Ceramic, 0.5 pF, 50 V, ±20%, C0G/NP0,
0402
D
C11, C18, C21
GRM188R60J106ME47 Capacitor, Ceramic, 10 µF, 6.3 V, ±20%, X5R, 0603
D
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表 10-1. Bill of Materials for CC3220x in Wide-Voltage Mode (continued)
QUANTI
TY
MANUFACTUR
ER
DESIGNATOR
VALUE
PART NUMBER
DESCRIPTION
1
C15
1 µF
TDK
C1005X5R1A105K050B Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402
B
2
2
2
1
C16, C17
C24, C25
C26, C27
E1
22 µF
10 pF
6.2 pF
TDK
C1608X5R0G226M080A Capacitor, Ceramic, 22 µF, 4 V, ±20%, X5R, 0603
A
MuRata
MuRata
Taiyo Yuden
GRM1555C1H100JA01 Capacitor, Ceramic, 10 pF, 50 V, ±5%, C0G/NP0,
D
0402
GRM1555C1H6R2CA01 Capacitor, Ceramic, 6.2 pF, 50 V, ±5%, C0G/NP0,
D
0402
2.45-
AH316M245001-T
ANT Bluetooth W-LAN Zigbee® WiMAX™, SMD
GHz
Antenna
1
1
2
1
1
FL1
L1
1.02 dB TDK
DEA202450BT-1294C1- Multilayer Chip Band Pass Filter For 2.4 GHz W-
H
LAN/Bluetooth, SMD
3.3 nH
2.2 µH
1 µH
MuRata
LQG15HS3N3S02D
Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17
ohm, SMD
L2, L4
L3
MuRata
LQM2HPN2R2MG0L
LQM2HPN1R0MG0L
CBC2518T100M
Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08
ohm, SMD
MuRata
Inductor, Multilayer, Ferrite, 1 µH, 1.6 A, 0.055 ohm,
SMD
L5(1)
10 µH
Taiyo Yuden
Inductor, Wirewound, Ceramic, 10 µH, 0.48 A, 0.36
ohm, SMD
1
4
1
1
1
1
R1
10 k
100 k
2.7 k
270
0
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
Panasonic
CRCW040210K0JNED Resistor, 10 k, 5%, 0.063 W, 0402
CRCW0402100KJNED Resistor, 100 k, 5%, 0.063 W, 0402
CRCW04022K70JNED Resistor, 2.7 k, 5%, 0.063 W, 0402
CRCW0402270RJNED Resistor, 270, 5%, 0.063 W, 0402
R2, R3, R4, R5
R6
R7
R8(2)
ERJ-2GE0R00X
Resistor, 0, 5% 0.063W, 0402
U1
MX25R Macronix
International Co.,
MX25R3235FM1IL0
Ultra-Low Power, 32-Mbit [x 1/x 2/x 4] CMOS
MXSMIO
LTD
(Serial Multi I/O) Flash Memory, SOP-8
1
1
1
U2
Y1
Y2
CC3220 Texas
CC3220SF12RGK
SimpleLink™ Wi-Fi® and internet-of-things Solution,
a Single-Chip Wireless MCU, RGK0064B
Instruments
Crystal
Crystal
Abracon
Corportation
ABS07-32.768KHZ-9-T Crystal, 32.768 KHz, 9PF, SMD
Epson
Q24FA20H0039600 Crystal, 40 MHz, 8pF, SMD
(1) For CC3220SF device, L5 is populated. For CC3220R and CC3220S devices, L5 is not populated.
(2) For CC3220SF device, R8 is not populated. For CC3220R and CC3220S devices if R8 is populated, Pin 47 can be used as GPIO_31.
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10.1.2 Typical Application Schematic—CC3220x Preregulated, 1.85-V Mode
图 10-2 shows the typical application schematic using the CC3220x in preregulated, 1.85-V mode of operation.
For addition information on this mode of operation please contact your TI representative.
1.85V
1.85V
1.85V
Optional:
R1
10k
Consider adding extra decoupling
capacitors if the battery cannot source
the peak currents.
1.85V
Antenna match. Pi
network might be
required depending on
type of antenna.
C1
1µF
E1
C2
C3
4.7µF
C4
C5
C6
0.1µF
4.7µF
C7
100µF
C8
100µF
4.7µF
0.1µF
L1
GND
FL1
IN
1
3
OUT
GND
GND
GND
GND
GND
3.3nH
2
4
GND
GND
GND
GND
C9
0.5pF GND GND
GND
1.85V
GND
U1
VCC
1.85V
8
U2
VIN_IO1
10
54
44
39
37
38
48
32
31
1
6
5
2
3
7
RESET
RF_BG
CS
SCLK
SI/SIO0
R2
100k
C10
0.1µF
VIN_IO2
SO/SIO1
WP/SIO2
RESET/SIO3
C11
0.1µF
VIN_DCDC_DIG
VIN_DCDC_PA
VIN_DCDC_ANA
DCDC_ANA_SW
VDD_ANA1
GND
4
GND
14
13
12
11
FLASH_SPI_CS
FLASH_SPI_DIN
GND
FLASH_SPI_DOUT
FLASH_SPI_CLK
GND
C12
0.1µF
C13
0.1µF
50
55
57
58
59
60
61
62
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
CC_GPIO_00
CC_GPIO_01
CC_GPIO_02
CC_GPIO_03
CC_GPIO_04
CC_GPIO_05
CC_GPIO_06
CC_GPIO_07
36
25
LDO_IN1
LDO_IN2
GND
GND
C14
1µF
C15
22µF
40
41
42
33
43
TP1
TP2
TP3
TP4
TP5
DCDC_PA_SW_P
DCDC_PA_SW_N
DCDC_PA_OUT
VDD_PA_IN
CC_nReset
CC_GPIO_01
CC_GPIO_02
SOP0
FLASH PROGRAMMING
INTERFACE
GND
GND
63
64
1
L2
GPIO8
GPIO9
CC_GPIO_08
CC_GPIO_09
CC_GPIO_10
CC_GPIO_11
CC_GPIO_12
CC_GPIO_13
CC_GPIO_14
CC_GPIO_15
Add provision on the board to isolate
GPIO_01 and GPIO_02 while programming
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
2.2uH
2
3
DCDC_DIG_SW
SOP2
C16
10µF
4
1.85V
9
56
5
VDD_DIG1
VDD_DIG2
C17
0.1µF
6
C18
0.1µF
PIN 45, 46, and 47:
Refer to the BOM in the following table for
notes on device-dependent configurations.
45
46
47
49
24
7
DCDC_ANA2_SW_P
DCDC_ANA2_SW_N
VDD_ANA2
GPIO16
GPIO17
GPIO22
GPIO28
GPIO30
CC_GPIO_16
CC_GPIO_17
CC_GPIO_22
CC_GPIO_28
CC_GPIO_30
8
15
18
53
GND
GND
L3
10uH
VDD_RAM
51
52
RTC_XTAL_P
RTC_XTAL_N
VDD_PLL
27
28
26
Y1
32.768kHz
NC
NC
NC
C19
10µF
C20
0.1µF
C21
0.1µF
23
22
WLAN_XTAL_P
WLAN_XTAL_N
2
1
35
34
21
SOP0
SOP1
SOP2
C22
10pF
C23
10pF
30
29
65
ANTSEL2
ANTSEL1
GND_TAB
GND
GND
GND
19
20
16
17
TCK
TMS
TDI
C24
6.2pF
TDO
C25
6.2pF
GND
GND
Y2
40 MHz
1.85V
CC3220SF12RGK
GND
GND
R7
270
GND
J1
2
4
6
1
3
5
CC_JTAG_TDO
CC_JTAG_TDI
CC_JTAG_TMS
CC_JTAG_TCK
GND
JTAG
R3
100k
R4
100k
R5
2.7k
R6
100k
GND
GND
图 10-2. CC3220x Preregulated 1.85-V Mode Application Circuit
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表 10-2 lists the bill of materials for an application using the CC3120R device in preregulated 1.85-V mode.
表 10-2. Bill of Materials for CC3220x Preregulated, 1.85-V Mode
QUANTI
TY
MANUFACTURE
R
DESIGNATOR
VALUE
PART NUMBER
DESCRIPTION
GRM155R61A105KE1 Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402
5D
1
C1
1 µF
MuRata
TDK
C2, C6, C10, C11,
C12, C13, C17,
C18, C20, C21
Capacitor, Ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402
C1005X5R1A104K050
BA
10
0.1 µF
C1005X5R0J475M050 Capacitor, Ceramic, 4.7 µF, 6.3 V, ±20%, X5R, 0402
BC
3
2
1
1
1
2
2
2
C3, C4, C5
C7, C8
C9
4.7 µF
100 µF
0.5 pF
1 µF
TDK
Capacitor, Ceramic, 100 µF, 10 V, ± 20%, X5R,
LMK325ABJ107MMHT
Taiyo Yuden
MuRata
TDK
AEC-Q200 Grade 3, 1210
GRM1555C1HR50BA Capacitor, Ceramic, 0.5 pF, 50 V, ±20%, C0G/NP0,
01D
0402
C1005X5R1A105K050 Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402
BB
C14
C1608X5R0G226M08 Capacitor, Ceramic, 22 µF, 4 V, ±20%, X5R, 0603
0AA
C15
22 µF
10 µF
10 pF
6.2 pF
TDK
GRM188R60J106ME4 Capacitor, Ceramic, 10 µF, 6.3 V, ±20%, X5R, 0603
7D
C16, C19
C22, C23
C24, C25
MuRata
MuRata
GRM1555C1H100JA0 Capacitor, Ceramic, 10 pF, 50 V, ±5%, C0G/NP0,
1D
0402
GRM1555C1H6R2CA Capacitor, Ceramic, 6.2 pF, 50 V, ±5%, C0G/NP0,
MuRata
01D
0402
Macronix
Ultra-low power, 32-Mbit [x 1/x 2/x 4] CMOS
MXSMIO
(Serial Multi I/O) Flash Memory, SOP-8
1
1
U1
E1
MX25R International Co. MX25R3235FM1IL0
LTD
2.45-
GHz
ANT Bluetooth W-LAN Zigbee® WiMAX™, SMD
Taiyo Yuden
AH316M245001-T
Antenna
DEA202450BT-1294C Multilayer Chip Band Pass Filter For 2.4GHz W-
1
1
1
1
1
4
1
1
1
FL1
1.02 dB TDK
1-H
LAN/Bluetooth, SMD
Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17
ohm, SMD
L1
3.3 nH
2.2 µH
10 µH
10 k
MuRata
LQG15HS3N3S02D
Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm,
SMD
L2
MuRata
LQM2HPN2R2MG0L
CBC2518T100M
Inductor, Wirewound, Ceramic, 10 µH, 0.48 A, 0.36
ohm, SMD
L3(1)
Taiyo Yuden
Vishay-Dale
Vishay-Dale
Vishay-Dale
Vishay-Dale
CRCW040210K0JNE Resistor, 10 k, 5%, 0.063 W, 0402
D
R1
CRCW0402100KJNE Resistor, 100 k, 5%, 0.063 W, 0402
D
R2, R3, R4, R6
100 k
2.7 k
CRCW04022K70JNE Resistor, 2.7 k, 5%, 0.063 W, 0402
D
R5
R7
U2
CRCW0402270RJNE Resistor, 270, 5%, 0.063 W, 0402
D
270
Texas
Instruments
SimpleLink™ Wi-Fi® and internet-of-things solution,
a Single-Chip Wireless MCU, RGK0064B
CC3220
CC3220SF12RGK
Abracon
Corporation
ABS07-32.768KHZ-9- Crystal, 32.768 kHZ, 9PF, SMD
T
1
1
Y1
Y2
Crystal
Crystal
Epson
Q24FA20H0039600
Crystal, 40 MHz, 8pF, SMD
(1) For CC3220SF device, L3 is populated. For CC3220R and CC3220S devices, L3 is not populated and Pin 47 can be used as
GPIO_31.
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10.2 PCB Layout Guidelines
This section details the PCB guidelines to speed up the PCB design using the CC3220x VQFN device. Follow
these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC,
ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout
Guidelines.
10.2.1 General PCB Guidelines
Use the following PCB guidelines:
•
Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for
signals and ground.
•
•
Ensure that the PCB footprint of the VQFN follows the information in .
Ensure that the GND and solder paste of the VQFN PCB follow the recommendations provided in CC3120
and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
Decoupling capacitors must be as close as possible to the VQFN device.
•
10.2.2 Power Layout and Routing
Three critical DC/DC converters must be considered for the CC3220x device.
•
•
•
Analog DC/DC converter
PA DC/DC converter
Digital DC/DC converter
Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are
formed when laying out the power components.
10.2.2.1 Design Considerations
The following design guidelines must be followed when laying out the CC3220x device:
•
Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate
the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask
specifications.
•
Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power
amplifier supply lines (pins 33, 40, 41, and 42), and all input supply pins (pins 37, 39, and 44).
Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
Place all decoupling capacitors as close to the respective pins as possible.
Power budget: The CC3220x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700 mA for
1.85 V, for 24 ms during the calibration cycle.
•
•
•
•
•
Ensure the power supply is designed to source this current without any issues. The complete calibration (TX
and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
The CC3220x device contains many high-current input pins. Ensure the trace feeding these pins is capable of
handling the following currents:
– VIN_DCDC_PA input (pin 39) maximum is 1 A
– VIN_DCDC_ANA input (pin 37) maximum is 600 mA
– VIN_DCDC_DIG input (pin 44) maximum is 500 mA
– DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum is 1 A
– DCDC_PA_OUT output node (pin 42) maximum 1 A
– DCDC_ANA_SW switching node (pin 38) maximum is 600 mA
– DCDC_DIG_SW switching node (pin 43) maximum is 500 mA
– VDD_PA_IN supply (pin 33) maximum is 500 mA
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图 10-3 shows the ground routing for the input decoupling capacitors.
图 10-3. Ground Routing for the Input Decoupling Capacitors
The ground return for the input capacitors are routed on L2 to reduce the EMI and improve the spectral mask.
This routing must be strictly followed because it is critical for the overall performance of the device.
10.2.3 Clock Interfaces
The following guidelines are for the slow clock.
•
•
The 32.768-kHz crystal must be placed close to the VQFN package.
Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance is
within ±150 ppm.
•
The ground plane on layer two is solid below the trace lanes and there is ground around these traces on the
top layer.
The following guidelines are for the fast clock.
•
•
The 40-MHz crystal must be placed close to the VQFN package.
Ensure that he load capacitance is tuned according to the board parasitics to the frequency tolerance is
within ±100 ppm at room temperature. The total frequency across parts, temperature, and with aging, must
be ±25 ppm to meet the WLAN specification.
•
•
•
•
Ensure that no high-frequency lines are routed close to the crystal routing to avoid noise degradation.
Ensure that crystal tuning capacitors are close to the crystal pads.
Make both traces (XTAL_N and XTAL_P) as close to parallel as possible and approximately the same length.
The ground plane on layer two is solid below the trace lines and that there is ground around these traces on
the top layer.
•
See CC31xx & CC32xx Frequency Tuning for frequency tuning.
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10.2.4 Digital Input and Output
The following guidelines are for the digital I/O.
•
•
•
Route SPI and UART lines away from any RF traces.
Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects. This is required
if the traces cannot be kept short. Place the resistor at the source end, closer to the device that is driving the
signal.
•
Add a series-terminating resistor for each high-speed line (such as SPI_CLK or SPI_DATA) to match the
driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line
impedance.
•
•
•
Route high-speed lines with a ground reference plane continuously below it to offer good impedance
throughout. This routing also helps shield the trace against EMI.
Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations,
use a separate line driver for each line.
If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each
high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to
36 Ω for a 50-Ω line impedance.
10.2.5 RF Interface
The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna
design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT
Solution Layout Guidelines for general antenna guidelines.
•
•
Ensure that the antenna is matched for 50-Ω. TI recommends using a Pi-matching network.
Ensure that the area underneath the BPF pads is grounded on layer one and layer two, and ensure that the
minimum filter requirements are met.
•
•
•
•
•
Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
The RF trace bends must be made with gradual curves. Avoid using 90-degree bends.
The RF traces must not have sharp corners.
Do not place traces or ground under the antenna section.
The RF traces must have via stitching on the ground plane beside the RF trace on both sides.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed in this section.
11.1 Development Tools and Software
For the most up-to-date list of development tools and software, see the CC3220 Tools & Software product page.
Users can also click the "Alert Me" button on the top right corner of the CC3220 Tools & Software page to stay
informed about updates related to the CC3220MOD device.
Development Tools
Pin Mux Tool
The supported devices are: CC3200 and CC3220x.
The Pin Mux Tool is a software tool that provides a graphical user interface (GUI)
for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell
characteristics for MPUs from TI. Results are output as C header/code files that can be
imported into software development kits (SDKs) or used to configure customers' custom
software. Version 3 of the Pin Mux Tool adds the capability of automatically selecting a
mux configuration that satisfies the entered requirements.
SimpleLink™ Wi-Fi®
Starter Pro
The supported devices are: CC3100, CC3200, CC3120R, and CC3220x.
The SimpleLink™ Wi-Fi® Starter Pro mobile App is a new mobile application for
SimpleLink provisioning. The app goes along with the embedded provisioning library
and example that runs on the device side (see SimpleLink™ Wi-Fi® CC3120
SDK plugin and TI SimpleLink™ Wi-Fi® CC3220 Software Development Kit (SDK)).
The new provisioning release is a TI recommendation for Wi-Fi provisioning using
SimpleLink Wi-Fi products. The provisioning release implements advanced AP mode
and SmartConfig™ technology provisioning with feedback and fallback options to ensure
successful process has been accomplished. Customers can use both embedded library
and the mobile library for integration to their end products.
SimpleLink™ Wi-Fi®
Radio Testing Tool
The supported devices are: CC3100, CC3200, and CC3220x.
The SimpleLink™ Wi-Fi® Radio Testing Tool is a Windows-based software tool for
RF evaluation and testing of SimpleLink Wi-Fi CC3120 and CC3220 designs during
development and certification. The tool enables low-level radio testing capabilities by
manually setting the radio into transmit or receive modes. Using the tool requires
familiarity and knowledge of radio circuit theory and radio test methods.
Created for the Internet of Things (IoT), the SimpleLink Wi-Fi CC31xx and CC32xx
family of devices include on-chip Wi-Fi, Internet, and robust security protocols with no
prior Wi-Fi experience needed for faster development. For more information on these
devices, visit SimpleLink™ Wi-Fi® family, Internet-on-a chip™ solutions.
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CC3220 Software
Development Kit
(SDK)
The CC3220x device is supported.
The CC3220 SDK contains drivers, many sample applications for Wi-Fi features and
Internet, as well as documentation needed to use the CC3220 Internet-on-a-chip
solution. This SDK can be used with TI’s MSP432P401R LaunchPad™ development
kit, or with the SimpleLink Studio, a PC tool that allows MCU development with CC3220.
You can also use the SDK as example code for any platform. All sample applications
in the SDK are supported on TI’s MSP432P401R ultra-low-power MCUs with Code
Composer Studio™ IDE and TI-RTOS. In addition, many of the applications support IAR.
Uniflash Standalone
Flash Tool for
TI Microcontrollers
(MCU), Sitara
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs
and on-board flash memory for Sitara processors. Uniflash has a GUI, command line,
and scripting interface. CCS Uniflash is available free of charge.
Processors &
SimpleLink Devices
TI Designs and Reference Designs
The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI Designs
include schematic or block diagrams, BOMs, and design files to speed your time to market.
11.2 Firmware Updates
TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,
TI recommends that the user has the latest service pack in their module for production.
To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit SimpleLink™
Wi-Fi® CC3120 SDK plugin.
11.3 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the
CC3220x device and support tools (see 图 11-1).
CC
3220
x
xx
x
xxx
x
PREFIX
X = preproduction device
no prefix = production device
PACKAGING
R = tape/reel
T = small reel
DEVICE FAMILY
PACKAGE
RGK = 9-mm × 9-mm VQFN
CC = wireless connectivity
SERIES NUMBER
3 = Wi-Fi Centric
REVISION
A = Revision A
MEMORY
R = ROM
S = Secured
SF = Secured flash
MEMORY SIZE
M2 = 256KB RAM
12 = 1MB flash and 256KB RAM
图 11-1. CC3220x Device Nomenclature
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11.4 Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (CC3220). In the upper right corner, click the "Alert me" button. This registers you to receive a
weekly digest of product information that has changed (if any). For change details, check the revision history of
any revised document. The current documentation that describes the processor, related peripherals, and other
technical collateral follows.
The following documents provide support for the CC3220 device.
Errata
CC3220R, CC3220S This document describes the known exceptions to the functional specifications for
Silicon Errata
the CC3220R and the CC3220S SimpleLink™ Wi-Fi® Wireless and Internet-of-Things
Solution, a Single-Chip Wireless MCU.
CC3220SF
Errata
Silicon This document describes the known exception to the functional specifications for the
CC3220SF SimpleLink™ Wi-Fi® Wireless and Internet-of-Things Solution, a Single-
Chip Wireless MCU.
Application Reports
CC3120 and CC3220 SimpleLink™ CC3120 and CC3220 SimpleLink™ Wi-Fi® Embedded Programming
Wi-Fi® Embedded Programming
SimpleLink™ CC3120, CC3220 Wi- This application report describes the best practices for power
Fi® Internet-on-a chip™ Networking management and extended battery life for embedded low-power Wi-Fi
Sub-System Power Management
devices such as the SimpleLink™ Wi-Fi® Internet-on-a chip™ solution
from Texas Instruments™.
SimpleLink™ CC3120, CC3220 Wi- The SimpleLink™ Wi-Fi® CC3120 and CC3220 Internet-on-a chip™ family
Fi® Internet-on-a chip™ Solution of devices from Texas Instruments™ offer a wide range of built-in security
Built-In Security Features
features to help developers address a variety of security needs, which
is achieved without any processing burden on the main microcontroller
(MCU). This document describes these security-related features and
provides recommendations for leveraging each in the context of practical
system implementation.
SimpleLink™ CC3120, CC3220 Wi- This document describes the OTA library for the SimpleLink™ Wi-Fi®
Fi® and Internet of Things Over-the- CC3x20 family of devices from Texas Instruments™ and explains how to
Air Update
prepare a new cloud-ready update to be downloaded by the OTA library.
SimpleLink™ CC3120, CC3220 Wi- This guide describes the provisioning process, which provides the
Fi® Internet-on-a chip™ Solution SimpleLink™ Wi-Fi® device with the information (network name,
Device Provisioning
password, and so forth) needed to connect to a wireless network.
Transfer of TI's Wi-Fi® Alliance This document explains how to employ the Wi-Fi® Alliance (WFA)
Certifications to Products Based on derivative certification transfer policy to transfer a WFA certification,
SimpleLink™
already obtained by Texas Instruments, to a system you have developed.
Using Serial Flash on SimpleLink™ This application note is divided into two parts. The first part provides
CC3120 and CC3220 Wi-Fi® and important guidelines and best- practice design techniques to consider
Internet-of-Things Devices
when choosing and embedding a serial Flash paired with the CC3120 and
CC3220 (CC3x20) devices. The second part describes the file system,
along with guidelines and considerations for system designers working
with the CC3x20 devices.
Copyright © 2021 Texas Instruments Incorporated
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CC3220R, CC3220S, CC3220SF
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User's Guides
SimpleLink™
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
Wi-Fi®
and This document provides software (SW) programmers with all of the required
Internet of Things CC3120 and knowledge for working with the networking subsystem of the SimpleLink™ Wi-
CC3220 Network Processor
Fi® devices. This guide provides basic guidelines for writing robust, optimized
networking host applications, and describes the capabilities of the networking
subsystem. The guide contains some example code snapshots, to give users
an idea of how to work with the host driver. More comprehensive code
examples can be found in the formal software development kit (SDK). This
guide does not provide a detailed description of the host driver APIs.
SimpleLink™ Wi-Fi® CC3120 This document provides the design guidelines of the 4-layer PCB used for
and CC3220 and IoT Solution the CC3120 and CC3220 SimpleLink™ Wi-Fi® family of devices from Texas
Layout Guidelines
Instruments™. The CC3120 and CC3220 devices are easy to lay out and are
available in quad flat no-leads (QFNS) packages. When designing the board,
follow the suggestions in this document to optimize performance of the board.
SimpleLink™
Wi-Fi®
and This guide is intended to assist users in the initial setup and demonstration
Internet of Things Solution of running their first sample application for the CC3220, CC3220S, CC3220SF
CC3220,
Wireless MCU
a
Single-Chip SimpleLink™ Wi-Fi® and Internet of Things Solution, a Single-Chip Wireless
MCU from Texas Instruments™. The guide explains how to install the software
development kit (SDK) and various other tools required to get started with the
first application.
SimpleLink™ CC3220 Wi-Fi® The CC3220 SimpleLink LaunchPad™ Development Kit (CC3220-LAUNCHXL)
LaunchPad™ Development Kit is a low-cost evaluation platform for Arm® Cortex®-M4-based MCUs. The
Hardware
LaunchPad design highlights the CC3220 Internet-on-a chip™ solution and
Wi-Fi capabilities. The CC3220 LaunchPad also features temperature and
accelerometer sensors, programmable user buttons, three LEDs for custom
applications, and onboard emulation for debugging. The stackable headers of
the CC3220 LaunchPad XL interface demonstrate how easy it is to expand
the functionality of the LaunchPad when interfacing with other peripherals on
many existing BoosterPack™ Plug-in Module add-on boards, such as graphical
displays, audio codecs, antenna selection, environmental sensing, and more.
SimpleLink™
Internet of Things CC3220
Wi-Fi®
and This document introduces the user to the environment setup for the CC3220x
device, along with some reference examples from the software development kit
(SDK). This document explains both the platform and the framework available
to enable further application development.
SimpleLink™ Wi-Fi® CC3220 This guide demonstrates the out-of-box experience for the CC3220
Out-of-Box Application
LaunchPad™ Development Kit, highlighting the easy connection to the CC3220
LaunchPad using the SimpleLink™ Wi-Fi® Starter Pro application, and the over-
the-air update.
SimpleLink™
Wi-Fi®
and The Radio Tool serves as a control panel for direct access to the radio, and
Internet-on-a-chip™ CC3120 can be used for both the radio frequency (RF) evaluation and for certification
and CC3220 Solution Radio purposes. This guide describes how to have the tool work seamlessly on
Tool
Texas Instruments™ evaluation platforms such as the BoosterPack™ plus
FTDI emulation board for CC3120 devices, and the LaunchPad™ for CC3220
devices.
SimpleLink™ Wi-Fi® CC3120 This guide describes TI’s SimpleLink™ Wi-Fi® provisioning solution for mobile
and CC3220 Provisioning for applications, specifically on the usage of the Android™ and iOS® building
Mobile Applications
blocks for UI requirements, networking, and provisioning APIs required for
building the mobile application.
SimpleLink™ Wi-Fi® CC3220 This guide details the out-of-box (OOB) experience with the CC3220
Out-of-Box Application LaunchPad™ Development Kit from Texas Instruments™.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: CC3220R CC3220S CC3220SF
CC3220R, CC3220S, CC3220SF
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
www.ti.com.cn
UniFlash
CC3220 SimpleLink™ Wi-Fi® SimpleLink ImageCreator tool as part of the UniFlash.
and Internet-on-a chip™
CC3120
and This document describes the installation, operation, and usage of the
Solution ImageCreator and
Programming Tool
More Literature
CC3220,
CC3220S,
CC3220SF This technical reference manual details the modules and
SimpleLink™ Wi-Fi® and Internet of Things peripherals of the SimpleLink™ CC32xx wireless MCU. Each
description presents the module or peripheral in a general sense.
Not all features and functions of all modules or peripherals may be
present on all devices. Pin functions, internal signal connections,
and operational parameters differ from device to device. The user
should consult the device-specific data sheet for these details.
RemoTI Manifest
CC3120, CC3220 SimpleLink™ Wi-Fi® and
Internet of Things Design Checklist
CC3220 SimpleLink™ Wi-Fi® and Internet CC3220 hardware design files.
of Things
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅 TI
的《使用条款》。
11.6 Trademarks
Wi-Fi CERTIFIED™, WPA™, WPA2™, WPA3™, and are trademarks of Wi-Fi Alliance.
SmartConfig™ is a trademark of TI.
SimpleLink™, LaunchPad™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
Macrocell™ is a trademark of Kappa Global Inc.
WiMAX™ are trademarks of WiMAX Forum.
Wi-Fi Alliance® and Wi-Fi Direct® are registered trademarks of Wi-Fi Alliance.
Arm®, Cortex®, and Thumb® are registered trademarks of Arm Limited.
Zigbee® are registered trademarks of Zigbee Alliance.
所有商标均为其各自所有者的财产。
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
Copyright © 2021 Texas Instruments Incorporated
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CC3220R, CC3220S, CC3220SF
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
www.ti.com.cn
11.9 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
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CC3220R, CC3220S, CC3220SF
ZHCSJ35C – SEPTEMBER 2016 – REVISED MAY 2021
www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: CC3220R CC3220S CC3220SF
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com/legal/termsofsale.html) 或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器 (TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CC3220RM2ARGKR
CC3220RM2ARGKT
CC3220SF12ARGKR
CC3220SF12ARGKT
CC3220SM2ARGKR
CC3220SM2ARGKT
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGK
64
64
64
64
64
64
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
CC3220R
M2A
Samples
Samples
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RGK
CC3220R
M2A
RGK
CC3220SF
12A
RGK
CC3220SF
12A
RGK
CC3220S
M2A
RGK
CC3220S
M2A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC3220RM2ARGKR
CC3220RM2ARGKT
CC3220SF12ARGKR
CC3220SM2ARGKR
CC3220SM2ARGKT
VQFN
VQFN
VQFN
VQFN
VQFN
RGK
RGK
RGK
RGK
RGK
64
64
64
64
64
2500
250
330.0
180.0
330.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
2500
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC3220RM2ARGKR
CC3220RM2ARGKT
CC3220SF12ARGKR
CC3220SM2ARGKR
CC3220SM2ARGKT
VQFN
VQFN
VQFN
VQFN
VQFN
RGK
RGK
RGK
RGK
RGK
64
64
64
64
64
2500
250
367.0
210.0
367.0
367.0
210.0
367.0
185.0
367.0
367.0
185.0
38.0
35.0
38.0
38.0
35.0
2500
2500
250
Pack Materials-Page 2
PACKAGE OUTLINE
RGK0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
PIN 1 INDEX AREA
9.1
8.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
6.3 0.1
SYMM
(0.2) TYP
17
32
16
33
EXPOSED
THERMAL PAD
SYMM
65
2X 7.5
0.30
64X
1
48
60X 0.5
PIN 1 ID
0.18
64
49
0.1
C A B
0.5
0.3
0.05
64X
4222201/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGK0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
6.3)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
8X (1.1)
(R0.05) TYP
18X (1.2)
(0.6) TYP
SYMM
65
(8.8)
(
0.2) TYP
VIA
16
33
17
32
(0.6) TYP
18X (1.2)
8X
(1.1)
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222201/B 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGK0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
25X ( 1)
64
(1.2) TYP
49
64X (0.6)
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.2) TYP
65
SYMM
(8.8)
16
33
METAL
TYP
17
32
SYMM
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4222201/B 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SI9130DB
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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