CC3235SM2RGKR [TI]

具有 256kB RAM 的 SimpleLink™ 32 位 Arm Cortex-M4 双频带 Wi-Fi® 无线 MCU | RGK | 64 | -40 to 85;


型号：	CC3235SM2RGKR
厂家：	TEXAS INSTRUMENTS
描述：	具有 256kB RAM 的 SimpleLink™ 32 位 Arm Cortex-M4 双频带 Wi-Fi® 无线 MCU \| RGK \| 64 \| -40 to 85 无线
文件：	总106页 (文件大小：3709K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC3235S, CC3235SF

ZHCSJC1D –APRIL 2019 –REVISED MAY 2021

CC3235S 和CC3235SF SimpleLink™ Wi-Fi^®双频带单芯片解决方案

• 多层安全特性：

– 独立执行环境

1 特性

• 多核心架构，片上系统(SoC)

• 802.11 a/b/g/n：2.4GHz 和5GHz

• FIPS 140-2 1 级认证

• 多层安全特性可帮助开发人员保护身份信息、数据

和软件IP

– 网络安全

– 设备身份和密钥

– 硬件加速器加密引擎（AES、DES、SHA/MD5

和CRC）

– 应用级安全（加密、身份验证、访问控制）

– 初始安全编程

– 软件篡改检测

• 低功耗模式，适用于电池供电应用

• 与2.4GHz 无线电共存

– 安全引导

• 工业温度：–40°C 至+85°C

• 获得Wi-Fi Alliance^®的Wi-Fi CERTIFIED^®

• 应用微控制器子系统：

– 证书注册请求(CSR)

– 每个设备具有唯一密钥对

• 应用吞吐量：

– UDP：16Mbps，TCP：13Mbps

– 峰值：72Mbps

• 电源管理子系统：

– ^®运行频率为80MHz 的Arm^®Cortex^®-M4 内核

– 用户专用存储器

• 256KB RAM

• 可选的1MB 可执行闪存

– 多种外设和计时器

– 集成式直流/直流转换器支持宽电源电压范围：

• VBAT 宽电压模式：2.1 V 至3.6 V

• VIO 始终与VBAT 关联

– 27 个带灵活多路复用选项的I/O 引脚

• UART、I2S、I2C、SPI、SD、ADC，

8 位并行接口

– 高级低功耗模式：

• 关断：1µA，休眠：4.5µA

• 计时器和PWM

• Wi-Fi 网络处理器子系统：

– Wi-Fi^®内核：

• 低功耗深度睡眠(LPDS)：120µA

• 空闲连接（MCU 处于LPDS 状态）：710µA

• RX 流量（MCU 处于活动模式）：59 mA

• TX 流量（MCU 处于活动模式）：223 mA

• Wi-Fi TX 功率：

• 802.11 a/b/g/n 2.4GHz 和5GHz

• 模式：

– 接入点(AP)

– 2.4 GHz：1 DSSS 时为18.0dBm

– 5 GHz：6 OFDM 时为18.1dBm

• Wi-Fi RX 灵敏度：

– 2.4 GHz：1 DSSS 时为-96dBm

– 5 GHz：6 OFDM 时为-92dBm

• 时钟源：

– 基站(STA)

– Wi-Fi Direct^®（仅在2.4GHz 受支持）

• 安全性：

– WEP

– WPA^™/ WPA2^™PSK

– WPA2 企业

– WPA3^™个人版

– WPA3^™企业版

– 互联网和应用协议：

– 具有内部振荡器的40.0MHz 晶体

– 32.768kHz 晶体或外部RTC

• RGK 封装

– 64 引脚9mm × 9mm 极薄四方扁平无引线

(VQFN) 封装，0.5mm 间距

• 器件支持SimpleLink™ MCU 平台开发人员生态系

统

• HTTP 服务器、mDNS、DNS-SD 和DHCP

• IPv4 和IPv6 TCP/IP 堆栈

• 16 BSD 套接字（完全安全的TLS v1.2 和

SSL 3.0）

– 内置的电源管理子系统：

• 可配置的低功耗配置（始终、间歇性、标

签）

• 高级低功耗模式

• 集成式直流/直流稳压器

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SWRS215

CC3235S, CC3235SF

ZHCSJC1D –APRIL 2019 –REVISED MAY 2021

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– 电器

2 应用

– 资产跟踪

– 工厂自动化

– 医疗和保健

– 电网基础设施

• 对于物联网应用，例如：

– 楼宇和住宅自动化：

• HVAC 系统和恒温器

• 视频监控、可视门铃和低功耗摄像头

• 楼宇安全系统和电子锁

3 说明

双频带无线MCU CC3235x 器件有两种型号：CC3235S 和C3235SF。

• CC3235S 包括256KB RAM、IoT 网络安全性、器件身份和密钥以及MCU 级安全特性，例如文件系统加密、

用户IP（MCU 图像）加密、安全启动和调试安全性。

• CC3235SF 基于CC3235S 而构建，除了256KB RAM 以外，还集成了一个用户专用的1MB 可执行闪存。

使用 Wi-Fi CERTIFIED™ 无线微控制器 (MCU) 简化您的 IoT 设计。SimpleLink^™Wi-Fi^®CC3235x 器件系列是一

种双频带片上系统(SoC) 解决方案，将两个处理器集成在一个芯片上，包括：

• 应用处理器：Arm^®Cortex^®-M4 MCU，具有用户专用的256KB RAM 和可选的1MB 可执行闪存

• 用以运行所有Wi-Fi 和互联网逻辑层的网络处理器此基于ROM 的子系统完全减轻了主机MCU 的负载，包括

一个802.11 a/b/g/n 双频带2.4GHz 和5GHz 无线电、基带和带有强大硬件加密引擎的MAC

这些器件引入了可进一步简化物联网连接的新功能。主要新特性包括：

• 802.11a (5GHz) 支持

• 与BLE/2.4GHz 无线电共存

• 天线选择

• 经过FIPS 140-2 1 级认证和其他认证，安全性更强¹

• 可同时打开多达16 个安全套接字

• 证书注册请求(CSR)

• 在线证书状态协议(OCSP)

• 经过Wi-Fi^®Alliance 认证的IoT 省电特性（例如DMS、代理ARP 等）

• 降低模板包传输负载的无主机模式

• 改善了快速扫描

CC3235x 器件系列是 SimpleLink™ MCU 平台的一部分，该平台是一个常见、易用的开发环境，基于一个单核软

件开发套件 (SDK)，具有丰富的工具集和参考设计。E2E™ 社区支持 Wi-Fi^®、低功耗 Bluetooth^®、Sub-1GHz 器

件和主机MCU。关于更多信息，请访问www.ti.com.cn/simplelink 或www.ti.com.cn/simplelinkwifi。

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

CC3235SM2RGKR

封装

VQFN (64)

9.00mm x 9.00mm

CC3235SF12RGKR

(1) 有关所有可选封装，请参阅节12。

关于特定器件型号的具体FIPS 认证状态，请参考https://csrc.nist.gov/publications/fips。

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4 功能方框图

图4-1 显示了CC3235x SimpleLink™ Wi-Fi^®解决方案的功能方框图。

SPI

Flash

SPI

Peripheral

I2C

Peripheral

Dual band Ant.

SSPI

I2C

GSPI

V_CCWide voltage

(2.1 to 3.6V)

A_TX

A_RX

Wi-Fi RF

Switch

5 GHz

BPF

SOP0

SOP1

Diplexer /

SPDT RF

Switch

32.768 kHz

XTAL

RF_BG

CC3235x

Wi-Fi / BLE

RF Switch

2.4 GHz

BPF

BLE

DEVICE

40 MHz

XTAL

COEX_IO

Dual band Ant.

Output GPIOs

GPIO/

PWM

Parallel

Port

I2S

Miscellaneous

Peripherals

Camera

sensor

Audio

codec

注意：双信器用于信号天线解决方案。使用天线选择功能（双天线）时，需要在双信器后应用1 个SPDT 开关和2 条GPIO 线路。

图4-1. 功能方框图

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图4-2 为CC3235x 器件的硬件概览。

CC32xx Single-Chip Wireless MCU

1MB Flash (Optional)

Arm^®Cortex^®- M4

Processor

80 MHz

256KB RAM

ROM

1× SPI

2× UART

1× I2C

DMA

1× I2S/PCM

1× SD/MMC

Timers

GPIOs

COEX I/Os

8-Bit Camera

4× ADC

Antenna Selection

Network Processor

Power

Management

Application

Protocols

Wi-Fi^®Driver

TCP/IP Stack

Oscillators

DC/DC

RTC

(Arm^®Cortex^®

Processor)

RAM

ROM

Synthesizer

图4-2. CC3235x 硬件概览

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图4-3 为CC3235x 器件中的嵌入式软件概览。

Customer Application

NetApp

BSD Socket

Wi-Fi^®

SimpleLink™ MCU Driver APIs

Host Interface

Network Apps

WLAN Security

and Management

TCP/IP Stack

WLAN MAC and PHY

图4-3. CC3235x 嵌入式软件概览

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Table of Contents

8.16 Thermal Resistance Characteristics for RGK

1 特性................................................................................... 1

2 应用................................................................................... 2

3 说明................................................................................... 2

4 功能方框图.........................................................................3

5 Revision History.............................................................. 6

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 8

7 Terminal Configuration and Functions..........................9

7.1 Pin Diagram................................................................ 9

7.2 Pin Attributes.............................................................10

7.3 Signal Descriptions................................................... 18

7.4 Pin Multiplexing.........................................................26

7.5 Drive Strength and Reset States for Analog and

Package...................................................................... 43

8.17 Timing and Switching Characteristics..................... 43

9 Detailed Description......................................................61

9.1 Overview...................................................................61

9.2 Arm^®Cortex^®-M4 Processor Core Subsystem.........61

9.3 Wi-Fi^®Network Processor Subsystem..................... 61

9.4 Security.....................................................................64

9.5 FIPS 140-2 Level 1 Certification............................... 66

9.6 Power-Management Subsystem...............................66

9.7 Low-Power Operating Mode..................................... 66

9.8 Memory.....................................................................68

9.9 Restoring Factory Default Configuration...................71

9.10 Boot Modes.............................................................71

9.11 Hostless Mode........................................................ 72

10 Applications, Implementation, and Layout............... 74

10.1 Application Information........................................... 74

10.2 PCB Layout Guidelines...........................................86

11 Device and Documentation Support..........................90

11.1 第三方产品免责声明................................................90

11.2 Tools and Software..................................................90

11.3 Firmware Updates...................................................91

11.4 Device Nomenclature..............................................91

11.5 Documentation Support.......................................... 92

11.6 Related Links.......................................................... 94

11.7 支持资源..................................................................94

11.8 Trademarks............................................................. 94

11.9 静电放电警告...........................................................94

11.10 Export Control Notice............................................94

11.11 术语表....................................................................94

12 Mechanical, Packaging, and Orderable

Digital Multiplexed Pins............................................... 28

7.6 Pad State After Application of Power to Device,

Before Reset Release................................................. 28

7.7 Connections for Unused Pins................................... 29

8 Specifications................................................................ 30

8.1 Absolute Maximum Ratings...................................... 30

8.2 ESD Ratings............................................................. 30

8.3 Power-On Hours (POH)............................................30

8.4 Recommended Operating Conditions.......................30

8.5 Current Consumption Summary (CC3235S)............ 31

8.6 Current Consumption Summary (CC3235SF).......... 33

8.7 TX Power Control for 2.4 GHz Band.........................34

8.8 TX Power Control for 5 GHz..................................... 36

8.9 Brownout and Blackout Conditions...........................37

8.10 Electrical Characteristics for GPIO Pins................. 38

8.11 Electrical Characteristics for Pin Internal Pullup

and Pulldown...............................................................40

8.12 WLAN Receiver Characteristics..............................40

8.13 WLAN Transmitter Characteristics..........................41

8.14 WLAN Transmitter Out-of-Band Emissions.............42

8.15 BLE/2.4 GHz Radio Coexistence and WLAN

Information.................................................................... 95

12.1 Packaging Information............................................ 95

Coexistence Requirements......................................... 43

5 Revision History

Changes from May 5, 2020 to May 13, 2021 (from Revision C (May 2020) to Revision D (May

2021))

Page

• 在节1 中新增了“WPA3 企业版”.................................................................................................................... 1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Added "WPA3 personal and enterprise" to 节9.3 ............................................................................................61

• Changed footnote in 节9.3 ..............................................................................................................................61

• Added WPA3 Enterprise to 节9.3.1 .................................................................................................................62

• Added WPA3 enterprise to Wi-Fi security Feature in 表9-1 ............................................................................62

• Changed tablenote for 表9-1 .......................................................................................................................... 62

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6 Device Comparison

表6-1 lists the features supported across different CC3x35 devices.

表6-1. Comparison of Device Features

DEVICE

FEATURE

CC3135

Network processor

CC3235S

Wireless microcontroller

802.11a/b/g/n

CC3235SF

Wireless microcontroller

802.11a/b/g/n

Classification

Standard

802.11a/b/g/n

IPv4, IPv6

TCP/IP stack

Sockets

IPv4, IPv6

Package

9-mm × 9-mm VQFN

ON-CHIP APPLICATION MEMORY

Flash

1MB

—

RAM

256KB

RF FEATURES

Frequency

2.4 GHz, 5 GHz

Yes

2.4 GHz, 5 GHz

Yes

2.4 GHz, 5 GHz

Yes

Coexistence with BLE Radio

SECURITY FEATURES

Unique device identity

Trusted root-certificate catalog

TI Root-of-trust public key

Online certificate status protocol

(OCSP)

Trusted root-certificate catalog

TI Root-of-trust public key

Online certificate status protocol

(OCSP)

Trusted root-certificate catalog

TI Root-of-trust public key

Online certificate status protocol

(OCSP)

Additional networking security

Certificate signing request (CSR)

Unique per-device key pair

Certificate signing request (CSR)

Unique per-device key pair

Certificate signing request (CSR)

Unique per-device key pair

Hardware acceleration

Secure boot

Hardware crypto engines

Yes

Hardware crypto engines

Yes

—

File system security

Secure key storage

Enhanced application level security

FIPS 140-2 Level 1 Certification⁽¹⁾

Software tamper detection

Cloning protection

Initial secure programming

Software tamper detection

Cloning protection

Initial secure programming

—

Yes

(1) For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.

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6.1 Related Products

For information about other devices in this family of products or related products, see the links that follow.

The SimpleLink™ MCU This portfolio offers a single development environment that delivers flexible hardware,

Portfolio

software, and tool options for customers developing wired and wireless applications.

With 100 percent code reuse across host MCUs, Wi-Fi^®, Bluetooth^®low energy, Sub-1

GHz devices and more, choose the MCU or connectivity standard that fits your design.

A one-time investment with the SimpleLink™ software development kit (SDK) allows

you to reuse often, opening the door to create unlimited applications.

SimpleLink™ Wi-Fi^®

Family

This device platform offers several Internet-on-a chip^™solutions, which address the

need of battery-operated, security-enabled products. Texas Instruments offers a single-

chip wireless microcontroller and a wireless network processor that can be paired with

any MCU, allowing developers to design new Wi-Fi^®products or upgrade existing

products with Wi-Fi^®capabilities.

BoosterPack™ Plug-in Extend the functionality of the TI LaunchPad^™Development Kit with the BoosterPack^™

Module

Plug-in Module. The application-specific BoosterPack Plug-in Module allows you to

explore a broad range of applications, including capacitive touch, wireless sensing,

LED Lighting control, and more. Stack multiple BoosterPack Plug-in Modules onto a

single LaunchPad Development Kit to further enhance the functionality of your design.

Reference Designs for The TI Designs Reference Design Library is a robust reference design library spanning

CC3200, CC3220 and analog, embedded processor and connectivity. Created by TI experts to help you jump

CC3235 Devices

start your system design, all TI Designs include schematic or block diagrams, BOMs

and design files to speed your time to market.

The SimpleLink™ Wi- The SDK contains drivers for the CC3235 programmable MCU, sample applications,

Fi^®SDK

and documentation required to start development with CC3235x solutions.

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7 Terminal Configuration and Functions

7.1 Pin Diagram

图7-1 shows pin assignments for the 64-pin VQFN package.

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

nRESET

RF_BG

GND

VDD_RAM

GPIO0

RTC_XTAL_P

GND

A_TX

A_RX

RTC_XTAL_N

GPIO30

VIN_IO2

GPIO1

LDO_IN2

VDD_DIG2

GPIO2

GPIO3

VDD_PLL

WLAN_XTAL_P

WLAN_XTAL_N

SOP2

GPIO4

GPIO5

TMS

GPIO6

GPIO7

GPIO8

GPIO9

TCK

GPIO28

TDO

10 11 12 13 14 15 16

NC = No internal connection

图7-1. Top View Pin Assignment for 64-Pin VQFN

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7.2 Pin Attributes

The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in

the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of

hardware configuration (at device reset) and register control.

Note

TI highly recommends using the Pin Mux Tool to obtain the desired pinout. In addition refer to the user

guide within the SimpleLink™ CC32XX Software Development Kit (SDK)

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does

not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used.

表 7-1 and 表 7-2 list the pin descriptions and attributes. 表 7-3 lists the signal descriptions. 表 7-4 presents an

overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers.

The following special considerations apply:

• All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.

• All I/Os support 10-µA pullup and pulldown resistors.

• The V_IOand V_BATsupply must be tied together at all times.

• By default, all I/Os float in the Hibernate state. However, the default state can be changed by software.

• All digital I/Os are nonfail-safe.

Note

If an external device drives a positive voltage to the signal pads and the CC3235x device is not

powered, DC is drawn from the other device. If the drive strength of the external device is adequate,

an unintentional wakeup and boot of the CC3235x device can occur. To prevent current draw, TI

recommends any one of the following conditions:

• All devices interfaced to the CC3235x device must be powered from the same power rail as the

chip.

• Use level shifters between the device and any external devices fed from other independent rails.

• The nRESET pin of the CC3235x device must be held low until the V_BATsupply to the device is

driven and stable.

• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the

TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state.

The ADC inputs are tolerant up to 1.8 V (see 表 8-30 for more details about the usable range of the

ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent

accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital

I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter

disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For

more information, see 节7.5.

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表7-1. Pin Descriptions

PINS

NAME

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

GPIO10

GPIO11

I/O

General-purpose input or output

Internal digital core voltage

Yes

N/A

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

I/O

Yes

I/O

Yes

N/A

VDD_DIG1

Power

I/O power supply (same as

battery voltage)

VIN_IO1

Power

N/A

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

GPIO22

Serial flash interface: SPI clock

Serial flash interface: SPI data

out

Serial flash interface: SPI data in

Serial flash interface: SPI chip

select

I/O

General-purpose input or output

JTAG interface: data input

Muxed with

JTAG TDI

TDI

Muxed with

JTAG TDO

TDO

I/O

JTAG interface: data output

Yes

GPIO28

General-purpose input or output

Muxed with

JTAG/

SWD-TCK

TCK

TMS

I/O

JTAG / SWD interface: clock

Muxed with

JTAG/

SWD-TMSC

JTAG / SWD interface: mode

select or SWDIO

21⁽¹⁾

SOP2

Configuration sense-on-power

40-MHz XTAL

WLAN_XTAL_N

Analog

N/A

40-MHz XTAL or TCXO clock

input

WLAN_XTAL_P

VDD_PLL

Analog

Power

N/A

Internal analog voltage

Analog RF supply from analog

DCDC output

LDO_IN2

No Connect

N/A

—

A_RX

A_TX

GND

RF_BG

RF A band: 5 GHz A_RX

RF A band: 5 GHz A_TX

Ground

GND

Ground

RF BG band: 2.4 GHz TX, RX

Master chip reset input. Active

low input.

nRESET

VDD_PA_IN

SOP1

N/A

RF power amplifier (PA) input

from PA DC-DC output

Power

Configuration sense-on-power

and 5 GHz switch control

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表7-1. Pin Descriptions (continued)

PINS

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

NAME

Configuration sense-on-power

and 5 GHz switch control

SOP0

N/A

Analog RF supply from analog

DCDC output

LDO_IN1

Power

Analog DC-DC supply input

(same as battery voltage)

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

DCDC_PA_SW_P

Analog DC/DC converter

switching node

PA DC/DC converter input supply

(same as battery voltage)

PA DC/DC converter +ve

switching node

PA DC/DC converter –ve

switching node

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

Power

N/A

PA DC/DC converter output.

Digital DC/DC converter switching

node

Digital DC/DC converter supply

input (same as battery voltage)

VIN_DCDC_DIG

Power

I/O

N/A

Analog2 DCDC converter +ve

switching node

User configuration

not required ⁽²⁾

DCDC_ANA2_SW_P

Analog2 DC-DC converter -ve

switching node

DCDC_ANA2_SW_N

VDD_ANA2

VDD_ANA1

VDD_RAM

Power

Analog

I/O

N/A

Analog2 DC-DC output

Analog1 power supply fed by

ANA2 DC-DC output

SRAM LDO output

User configuration

not required ⁽²⁾

GPIO0

General-purpose input or output

32.768-kHz XTAL_P or external

CMOS level clock input

RTC_XTAL_P

RTC_XTAL_N

GPIO30

Analog

I/O

N/A

User configuration

not required ^{(2) (3)}

32.768-kHz XTAL_N

User configuration

not required ⁽²⁾

General-purpose input or output

VIN_IO2

GPIO1

Analog

I/O

Chip supply voltage (VBAT)

General-purpose input or output

Internal digital core voltage

N/A

VDD_DIG2

Analog

N/A

Analog input (1.5V max) or

general-purpose input or output

GPIO2

GPIO3

GPIO4

GPIO5

I/O

Wake-up source

See ⁽⁴⁾

Analog input (1.5V max) or

general-purpose input or output

Wake-up source

Analog input (1.5V max) or

general-purpose input or output

Analog input (1.5V max) or

general-purpose input or output

GPIO6

GPIO7

GPIO8

GPIO9

I/O

General-purpose input or output

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表7-1. Pin Descriptions (continued)

PINS

NAME

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

TYPE

DESCRIPTION

NO.

Thermal pad and electrical

ground

GND_TAB

N/A

—

(1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(2) Device firmware automatically enables the digital path during ROM boot.

(3) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩresistor.

(4) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always

connected and must be made Hi-Z before enabling the ADC switch.

表7-2. Pin Attributes

PAD STATES

Hib⁽⁴⁾

NO.

SIGNAL

TYPE⁽²⁾

PIN MUX

ENCODING

SIGNAL

DIRECTION

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hi-Z, Pull, Drive

nRESET = 0

GPIO10 (PN)

I2C_SCL

I/O

I/O (open drain)

GT_PWM06

UART1_TX

SDCARD_CLK

GT_CCP01

GPIO11 (PN)

I2C_SDA

Hi-Z, Pull,

Drive

I/O

Hi-Z

Hi-Z, Pull, Drive

I/O

I/O (open drain)

GT_PWM07

pXCLK(XVCLK)

SDCARD_CMD

UART1_RX

GT_CCP02

MCAFSX

Hi-Z, Pull,

Drive

Hi-Z

I/O (open drain)

Hi-Z, Pull, Drive

GPIO12 (PN)

McACLK

I/O

pVS(VSYNC)

I2C_SCL

Hi-Z, Pull,

Drive

Hi-Z

I/O (open drain)

UART0_TX

GT_CCP03

GPIO13 (PN)

I2C_SDA

Hi-Z, Pull, Drive

I/O

I/O (open drain)

Hi-Z, Pull,

Drive

pHS(HSYNC)

UART0_RX

GT_CCP04

GPIO14 (PN)

I2C_SCL

I/O

Hi-Z, Pull, Drive

Hi-Z

I/O

I/O (open drain)

Hi-Z, Pull,

Drive

GSPI_CLK

I/O

pDATA8(CAM_D4)

GT_CCP05

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nRESET = 0

表7-2. Pin Attributes (continued)

PAD STATES

Hib⁽⁴⁾

NO.

SIGNAL

PIN MUX

SIGNAL

SIGNAL NAME⁽¹⁾

TYPE⁽²⁾

ENCODING

DIRECTION

LPDS⁽³⁾

GPIO15 (PN)

I2C_SDA

I/O

I/O (open drain)

GSPI_MISO

I/O

Hi-Z, Pull,

Drive

I/O

Hi-Z, Pull, Drive

Hi-Z

pDATA9(CAM_D5)

GT_CCP06

SDCARD_ DATA0

GPIO16 (PN)

GSPI_MOSI

I/O

Hi-Z, Pull, Drive

pDATA10(CAM_D6)

UART1_TX

Hi-Z, Pull,

Drive

I/O

Hi-Z

GT_CCP07

Hi-Z, Pull, Drive

SDCARD_CLK

GPIO17 (PN)

UART1_RX

I/O

Hi-Z, Pull,

Drive

GSPI_CS

I/O

Hi-Z, Pull, Drive

pDATA11 (CAM_D7)

SDCARD_ CMD

VDD_DIG1 (PN)

VIN_IO1

I/O

N/A

—

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z, Pull,

Drive

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

N/A

Hi-Z

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z, Pull,

Drive

Hi-Z, Pull,

Drive⁽⁵⁾

Hi-Z

Hi-Z, Pull,

Drive

GPIO22 (PN)

McAFSX

I/O

Hi-Z, Pull,

Drive

I/O

Hi-Z, Pull, Drive

Hi-Z

GT_CCP04

TDI (PN)

Hi-Z, Pull, Drive

GPIO23

I/O

Hi-Z, Pull,

Drive

UART1_TX

I2C_SCL

TDO (PN)

GPIO24

I/O (open drain)

Hi-Z, Pull, Drive

I/O

Driven high

in SWD;

driven low in

4-wire JTAG

PWM0

UART1_RX

I2C_SDA

GT_CCP06

McAFSX

I/O

Hi-Z, Pull, Drive

Hi-Z

I/O (open drain)

Hi-Z, Pull,

Drive

GPIO28 (PN)

I/O

Hi-Z, Pull, Drive

Hi-Z

TCK (PN)

Hi-Z, Pull,

Drive

GT_PWM03

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表7-2. Pin Attributes (continued)

PAD STATES

SIGNAL

TYPE⁽²⁾

PIN MUX

SIGNAL

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hib⁽⁴⁾

nRESET = 0

NO.

ENCODING

DIRECTION

TMS (PN)

GPIO29

I/O

Hi-Z, Pull,

Drive

I/O

Hi-Z, Pull, Drive

Hi-Z

GPIO25

Hi-Z, Pull, Drive

GT_PWM02

Hi-Z, Pull, Drive

21⁽⁶⁾McAFSX

Hi-Z, Pull, Drive

Driven low

Hi-Z

TCXO_EN

N/A

See ⁽⁷⁾

N/A

Hi-Z, Pull, Drive

N/A

SOP2 (PN)

WLAN_XTAL_N

N/A

I/O

N/A

—

WLAN_XTAL_P

VDD_PLL

N/A

LDO_IN2

N/A

A_RX

N/A

A_TX

N/A

GND

N/A

GND

N/A

RF_BG

N/A

nRESET

N/A

VDD_PA_IN

SOP1 (PN)

A_SC1

N/A

34⁽⁸⁾

35⁽⁸⁾

I/O

N/A

SOP0 (PN)

A_SC2

N/A

LDO_IN1

N/A

—

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

DCDC_PA_SW_P

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

VIN_DCDC_DIG

GPIO31

N/A

UART0_RX

McAFSX

I/O

Hi-Z

UART1_RX

McAXR0

45⁽⁹⁾

I/O

GSPI_CLK

DCDC_ANA2_SW_P

(PN)

See ⁽¹⁰⁾

N/A

—

DCDC_ANA2_SW_N

VDD_ANA2

N/A

—

VDD_ANA1

VDD_RAM

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nRESET = 0

表7-2. Pin Attributes (continued)

PAD STATES

Hib⁽⁴⁾

NO.

SIGNAL

PIN MUX

SIGNAL

SIGNAL NAME⁽¹⁾

TYPE⁽²⁾

ENCODING

DIRECTION

LPDS⁽³⁾

Hi-Z, Pull, Drive

GPIO0 (PN)

UART0_CTS

McAXR1

I/O

GT_CCP00

GSPI_CS

Hi-Z, Pull,

Drive

I/O

Hi-Z

I/O

N/A

I/O

UART1_RTS

UART0_RTS

McAXR0

Hi-Z, Pull, Drive

N/A

RTC_XTAL_P

RTC_XTAL_N (PN)

GPIO32

N/A

—

N/A

McACLK

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

52⁽¹¹⁾

Hi-Z

McAXR0

UART0_RTS

GSPI_MOSI

GPIO30 (PN)

UART0_TX

McACLK

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

I/O

Hi-Z

McAFSX

Hi-Z, Pull, Drive

GT_CCP05

GSPI_MISO

VIN_IO2

I/O

N/A

I/O

N/A

Hi-Z

N/A

Hi-Z

—

GPIO1 (PN)

UART0_TX

pCLK (PIXCLK)

UART1_TX

GT_CCP01

VDD_DIG2

ADC_CH0

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

I/O

Hi-Z, Pull, Drive

N/A

—

See ⁽¹⁰⁾

GPIO2 (PN)

I/O

Analog input

(up to 1.5 V)

or digital I/O

Hi-Z, Pull,

Drive

57⁽¹²⁾UART0_RX

Hi-Z, Pull, Drive

UART1_RX

GT_CCP02

ADC_CH1

See ⁽¹⁰⁾

Hi-Z, Pull, Drive

Analog input

(up to 1.5 V)

or digital I/O

GPIO3 (PN)

58⁽¹²⁾

I/O

Hi-Z, Pull,

Drive

Hi-Z

UART1_TX

pDATA7 (CAM_D3)

Hi-Z, Pull, Drive

ADC_CH2

See ⁽¹⁰⁾

Analog input

(up to 1.5 V)

or digital I/O

GPIO4 (PN)

I/O

Hi-Z, Pull,

Drive

59⁽¹²⁾

Hi-Z, Pull, Drive

UART1_RX

pDATA6 (CAM_D2)

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表7-2. Pin Attributes (continued)

PAD STATES

SIGNAL

TYPE⁽²⁾

PIN MUX

SIGNAL

SIGNAL NAME⁽¹⁾

LPDS⁽³⁾

Hib⁽⁴⁾

nRESET = 0

NO.

ENCODING

DIRECTION

ADC_CH3

See ⁽¹⁰⁾

I/O

GPIO5 (PN)

Analog input

(up to 1.5 V)

or digital I/O

Hi-Z, Pull,

Drive

60⁽¹²⁾pDATA5 (CAM_D1)

Hi-Z, Pull, Drive

Hi-Z

McAXR1

I/O

GT_CCP05

GPIO6 (PN)

I/O

Hi-Z, Pull, Drive

UART0_RTS

pDATA4 (CAM_D0)

Hi-Z, Pull,

Drive

I/O

Hi-Z

UART1_CTS

Hi-Z, Pull, Drive

UART0_CTS

GT_CCP06

GPIO7 (PN)

McACLKX

I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

UART1_RTS

UART0_RTS

UART0_TX

GPIO8 (PN)

SDCARD_IRQ

McAFSX

I/O

Hi-Z

Hi-Z, Pull,

Drive

Hi-Z, Pull, Drive

GT_CCP06

GPIO9 (PN)

GT_PWM05

SDCARD_DATA0

McAXR0

I/O

Hi-Z, Pull,

Drive

I/O

Hi-Z, Pull, Drive

N/A

Hi-Z

N/A

GT_CCP00

N/A

GND_TAB

N/A

—

(1) Signals names with (PN) denote the default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin

configuration), according to the need.

(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin

configuration), according to the need.

(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak

pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.

(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(7) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode.

For this reason, the pin must be output only when used for digital functions.

(8) This pin has dual functions: as a SOP (device operation mode) input pin during boot up, and as the 5 GHz switch control (output) pin

on power up

(9) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on

pin 47.

(10) For details on proper use, see 节7.5.

(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level

configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some

applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,

the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to

automatically detect this configuration, a 100-kΩpullup resistor must be connected between pin 52 and the supply line. To prevent

false detection, TI recommends using pin 52 for output-only functions.

(12) This pin is shared by the ADC inputs and digital I/O pad cells.

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7.3 Signal Descriptions

表7-3. Signal Descriptions

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

ADC_CH0

DESCRIPTION

I/O

ADC channel 0 input (maximum of 1.5 V)

ADC channel 1 input (maximum of 1.5 V)

ADC channel 2 input (maximum of 1.5 V)

ADC channel 3 input (maximum of 1.5 V)

ADC_CH1

ADC_CH2

ADC_CH3

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO28

GPIO25

GPIO31

GPIO0

ADC

I/O

18⁽¹⁾

45^{(1) (2)}

52⁽¹⁾

53⁽¹⁾

Antenna

selection

Antenna selection control

I/O

GPIO32

GPIO30

GPIO3

GPIO4

GPIO5

GPIO6

GPIO8

GPIO9

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FUNCTION

表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

GPIO10

DESCRIPTION

I/O

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO28

GPIO25

GPIO31

GPIO0

I/O

18⁽¹⁾

45^{(1) (2)}

52⁽¹⁾

53⁽¹⁾

I/O

BLE/2.4 GHz

radio

coexistence

Coexistence inputs and outputs

I/O

—

I/O

GPIO32

GPIO30

GPIO3

GPIO4

GPIO5

I/O

—

GPIO6

GPIO8

GPIO9

WLAN_XTAL_N

WLAN_XTAL_P

40-MHz crystal; pull down if external TCXO is used

40-MHz crystal or TCXO clock input

—

Connect 32.768-kHz crystal or force external CMOS

level clock

Clock

RTC_XTAL_P

RTC_XTAL_N

—

Connect 32.768-kHz crystal or connect 100-kΩresistor

to supply voltage

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表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

HM_IO

DESCRIPTION

I/O

18⁽¹⁾

45^{(1) (2)}

52⁽¹⁾

53⁽¹⁾

I/O

Hostless mode

Hostless mode inputs and outputs

I/O

TDI

JTAG TDI. Reset default pinout.

TDO

TCK

TMS

JTAG TDO. Reset default pinout.

JTAG/SWD TCK. Reset default pinout.

JTAG/SWD TMS. Reset default pinout.

JTAG / SWD

I/O

I2C_SCL

I2C_SDA

I/O

I/O (open drain) I²C clock data

I²C

I/O (open drain) I²C data

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FUNCTION

表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

GT_PWM06

DESCRIPTION

I/O

Pulse-width modulated O/P

GT_CCP01

GT_PWM07

GT_CCP02

GT_CCP03

Timer capture port

Pulse-width modulated O/P

GT_CCP04

GT_CCP05

Timer capture ports

GT_CCP06

Timers

GT_CCP07

PWM0

GT_PWM03

GT_PWM02

Pulse-width modulated outputs

Timer capture ports

I/O

GT_CCP00

GT_CCP05

GT_CCP01

GT_CCP02

GT_CCP05

GT_PWM05

Timer capture port Input

I/O

Pulse-width modulated output

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表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

GPIO10

DESCRIPTION

I/O

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

GPIO23

GPIO24

GPIO28

GPIO29

GPIO25

GPIO31

GPIO0

45⁽²⁾

GPIO

General-purpose inputs or outputs

I/O

GPIO32

GPIO30

GPIO1

I/O

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

45⁽²⁾

MCAFSX

I/O

I²S audio port frame sync

I/O

McASP

McACLK

McAXR1

45⁽²⁾

I²S audio port clock outputs

I²S or PCM

I/O

I²S audio port data 1 (RX/TX)

I²S audio port data 1 (RX and TX)

I/O

I²S audio port data 0 (RX and TX)

I²S audio port data (only output mode is supported on

pin 52)

McAXR0

I/O

I²S audio port data (RX and TX)

I²S audio port clock

McACLKX

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FUNCTION

表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

DESCRIPTION

SDCARD_CLK

I/O

SD card clock data

I/O

I/O (open drain)

I/O

SDCARD_CMD

SD card command line

SD card data

Multimedia card

(MMC or SD)

SDCARD_DATA0

I/O

SDCARD_IRQ

pXCLK (XVCLK)

pVS (VSYNC)

pHS (HSYNC)

pDATA8 (CAM_D4)

pDATA9 (CAM_D5)

pDATA10 (CAM_D6)

pDATA11 (CAM_D7)

pCLK (PIXCLK)

pDATA7 (CAM_D3)

pDATA6 (CAM_D2)

pDATA5 (CAM_D1)

pDATA4 (CAM_D0)

VDD_DIG1

I/O

Interrupt from SD card⁽³⁾

Free clock to parallel camera

Parallel camera vertical sync

Parallel camera horizontal sync

Parallel camera data bit 4

Parallel camera data bit 5

Parallel camera data bit 6

Parallel camera data bit 7

Pixel clock from parallel camera sensor

Parallel camera data bit 3

Parallel camera data bit 2

Parallel camera data bit 1

Parallel camera data bit 0

Internal digital core voltage

Parallel interface

(8-bit π)

I/O

—

VIN_IO1

Device supply voltage (V_BAT

Internal analog voltage

)

—

VDD_PLL

—

LDO_IN2

Internal analog RF supply from analog DC/DC output

Internal PA supply voltage from PA DC/DC output

Internal analog RF supply from analog DC/DC output

—

VDD_PA_IN

—

LDO_IN1

—

Analog DC/DC input (connected to device input supply

[V_BAT])

VIN_DCDC_ANA

DCDC_ANA_SW

VIN_DCDC_PA

—

Internal analog DC/DC switching node

PA DC/DC input (connected to device input supply

[V_BAT])

DCDC_PA_SW_P

DCDC_PA_SW_N

DCDC_PA_OUT

DCDC_DIG_SW

Internal PA DC/DC switching node

Internal PA buck converter output

Internal digital DC/DC switching node

—

Power

Digital DC/DC input (connected to device input supply

[V_BAT])

VIN_DCDC_DIG

—

DCDC_ANA2_SW_P

DCDC_ANA2_SW_N

VDD_ANA2

45⁽²⁾

Analog to DC/DC converter +ve switching node

Internal analog to DC/DC converter –ve switching node

Internal analog to DC/DC output

—

VDD_ANA1

Internal analog supply fed by ANA2 DC/DC output

Internal SRAM LDO output

VDD_RAM

VIN_IO2

Device supply voltage (V_BAT

Internal digital core voltage

)

VDD_DIG2

Reset

nRESET

Global master device reset (active low)

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表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

FUNCTION

SIGNAL NAME

A_RX

DESCRIPTION

WLAN analog A-band receive

I/O

A_TX

WLAN analog A-band transmit

RF_BG

I/O

WLAN analog RF 802.11 b/g bands

GSPI_CLK

GSPI_MISO

GSPI_CS

General SPI clock

45⁽²⁾

General SPI MISO

General SPI device select

General SPI MOSI

SPI

GSPI_MOSI

FLASH_SPI_CLK

FLASH_SPI_DOUT

FLASH_SPI_DIN

FLASH_SPI_CS

Clock to SPI serial flash (fixed default)

Data to SPI serial flash (fixed default)

Data from SPI serial flash (fixed default)

FLASH SPI

Device select to SPI serial flash (fixed default)

I/O

UART TX data

UART1_TX

UART1 TX data

UART RX data

45⁽²⁾

UART1_RX

UART1 RX data

UART1_RTS

UART1_CTS

UART1 request-to-send (active low)

UART1 clear-to-send (active low)

UART

UART0_TX

UART0 TX data

UART0 RX data

UART0_RX

45⁽²⁾

UART0 RX data

UART0_CTS

I/O

UART0 clear-to-send input (active low)

I/O

UART0_RTS

UART0 request-to-send (active low)

I/O

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FUNCTION

表7-3. Signal Descriptions (continued)

NO.

TYPE

SIGNAL

DIRECTION

SIGNAL NAME

SOP2

DESCRIPTION

21⁽⁴⁾

Sense-on-power 2

Sense-On-Power SOP1

SOP0

Configuration sense-on-power 1

Configuration sense-on-power 0

(1) LPDS retention unavailable.

(2) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on

pin 47.

(3) Future support.

(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

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7.4 Pin Multiplexing

表7-4. Pin Multiplexing

ANALOG OR SPECIAL FUNCTION

Digital Function (XXX Field Encoding)⁽¹⁾

Address

Name

BLE COEX

Hostless

Mode

JTAG

CC_COEX CC_COEX

_SW_OUT _BLE_IN

0x4402

E0C8

GPIO_PAD_

CONFIG_10

I2C_

SCL

GT_

PWM06

SDCARD_ UART1_

CLK TX

GT_

CCP01

Y⁽²⁾

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO22

—

0x4402

E0CC

GPIO_PAD_

CONFIG_11

I2C_

SDA

GT_

PWM07

pXCLK

(XVCLK)

SDCARD_ UART1_

GT_

CCP02

MCAFSX

—

CMD

0x4402

E0D0

GPIO_PAD_

CONFIG_12

pVS

(VSYNC)

I2C_

SCL

UART0_

GT_

CCP03

McACLK

—

0x4402

E0D4

GPIO_PAD_

CONFIG_13

pHS

(HSYNC)

I2C_

SDA

UART0_

GT_

CCP04

—

0x4402

E0D8

GPIO_PAD_

CONFIG_14

pDATA8

(CAM_D4)

I2C_

SCL

GSPI_

CLK

GT_

CCP05

0x4402

E0DC

GPIO_PAD_

CONFIG_15

pDATA9

(CAM_D5)

I2C_

SDA

GSPI_

MISO

SDCARD_

DATA0

GT_

CCP06

—

0x4402

E0E0

GPIO_PAD_

CONFIG_16

pDATA10 UART1_

(CAM_D6)

GSPI_

MOSI

SDCARD_

CLK

GT_

CCP07

0x4402

E0E4

GPIO_PAD_

CONFIG_17

pDATA11

(CAM_D7)

UART1_

GSPI_

SDCARD_

CMD

Y⁽²⁾

—

0x4402

E0F8

GPIO_PAD_

CONFIG_22

GT_

CCP04

McAFSX

—

Muxed

with

JTAG

0x4402

E0FC

GPIO_PAD_

CONFIG_23

UART1_

I2C_

SCL

GPIO23

TDI

—

Muxed

with

JTAG

TDO

0x4402

E100

GPIO_PAD_

CONFIG_24

UART1_

GT_

CCP06

I2C_

SDA

GPIO24

GPIO28

TDO

PWM0

McAFSX

—

0x4402

E140

GPIO_PAD_

CONFIG_40

Y⁽³⁾

—

Muxed

with

JTAG

SWD

and

TCK

0x4402

E110

GPIO_PAD_

CONFIG_28

GT_

PWM03

TCK

TMS

—

Muxed

with

JTAG

SWD

and

TMSC

0x4402

E114

GPIO_PAD_

CONFIG_29

GPIO29

—

0x4402

E104

GPIO_PAD_

CONFIG_25

GT_

PWM02

21⁽⁴⁾

Y⁽²⁾

GPIO25

GPIO31

McAFSX

—

0x4402

E11C

GPIO_PAD_

CONFIG_31

45⁽³⁾

UART1_

GSPI_

CLK

UART0_

McAXR0

McAFSX

(5)

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表7-4. Pin Multiplexing (continued)

ANALOG OR SPECIAL FUNCTION

Digital Function (XXX Field Encoding)⁽¹⁾

Address

Name

BLE COEX

Hostless

Mode

JTAG

CC_COEX CC_COEX

_SW_OUT _BLE_IN

0x4402

E0A0

GPIO_PAD_

CONFIG_0

UART0_

RTS

GT_

CCP00

GSPI_

UART1_

RTS

UART0_

CTS

GPIO0

GPIO32

GPIO30

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

McAXR0

McAXR1

—

-—

—

-—

—

0x4402

E120

GPIO_PAD_

CONFIG_32

UART0_

RTS

GSPI_

MOSI

Y⁽³⁾

McACLK

—

0x4402

E118

GPIO_PAD_

CONFIG_30

GT_

CCP05

GSPI_

MISO

UART0_

McACLK McAFSX

UART0_

—

0x4402

E0A4

GPIO_PAD_

CONFIG_1

pCLK

(PIXCLK)

UART1_

GT_

CCP01

—

0x4402

E0A8

GPIO_PAD_

CONFIG_2

UART0_

UART1_

GT_

CCP02

—

0x4402

E0AC

GPIO_PAD_

CONFIG_3

pDATA7

(CAM_D3)

UART1_

Y⁽²⁾

—

0x4402

E0B0

GPIO_PAD_

CONFIG_4

pDATA6

(CAM_D2)

UART1_

—

0x4402

E0B4

GPIO_PAD_

CONFIG_5

pDATA5

(CAM_D1)

GT_

CCP05

McAXR1

0x4402

E0B8

GPIO_PAD_

CONFIG_6

UART1_

CTS

pDATA4

(CAM_D0)

UART0_

RTS

UART0_

CTS

GT_

CCP06

—

0x4402

E0BC

GPIO_PAD_

CONFIG_7

UART1_

RTS

UART0_ UART0_

RTS

McACLKX

—

0x4402

E0C0

GPIO_PAD_

CONFIG_8

SDCARD_

IRQ

GT_

CCP06

McAFSX

McAXR0

—

0x4402

E0C4

GPIO_PAD_

CONFIG_9

GT_

PWM05

SDCARD_

DATA0

GT_

CCP00

—

(1) Pin mux encodings with (RD) denote the default encoding after reset release.

(2) Output Only

(3) LPDS retention unavailable.

(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During

hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(5) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

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7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins

表 7-5 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time

power up and reset (nRESET pulled low).

表7-5. Drive Strength and Reset States for Analog and Digital Multiplexed Pins

State After Configuration of Analog

Switches (ACTIVE, LPDS, and HIB Effective Drive

Maximum

Board-Level Configuration and

Use

Default State at First Power Up

or Forced Reset

Power Modes)

Strength (mA)

VDD_ANA2 (pin 47) must be

shorted to the input supply rail.

Otherwise, the pin is driven by the is also isolated.

ANA2 DC/DC.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

other digital I/Os.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Generic I/O

The pin must have an external

pullup of 100 kΩto the supply rail

and must be used in output signals

only.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Analog is isolated. The digital I/O cell Determined by the I/O state, as are

is also isolated. other digital I/Os.

Generic I/O

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

Analog signal (1.8-V absolute,

1.46-V full scale)

ADC is isolated. The digital I/O cell is Determined by the I/O state, as are

also isolated. other digital I/Os.

7.6 Pad State After Application of Power to Device, Before Reset Release

When a stable power is applied to the CC3235x device for the first time or when supply voltage is restored to the

proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined in

the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than

approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set

of pins is required to have a definite value during this pre-reset period, an appropriate pullup or pulldown resistor

must be used at the board level. The recommended value of this external pull is 2.7 kΩ.

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7.7 Connections for Unused Pins

All unused pin should be configured as stated in 表7-6.

表7-6. Connections for Unused Pins

NUMBER

FUNCTION

SIGNAL DESCRIPTION

ACCEPTABLE PRACTICE

PREFERRED PRACTICE

Wake up I/O source should not be

floating during hibernate.

All the I/O pins will float while in

Hibernate and Reset states. Ensure

pullup and pulldown resistors are

available on board to maintain the

state of the I/O.

General-purpose input or

output

GPIO

Leave unused GPIOs as NC

No Connect

SOP

Unused pin, leave as NC.

Unused pin, leave as NC

69.8K Pull down resistor

on SOP0 and SOP1 used

as switch control pins,

Configuration sense-on-

power

Ensure pulldown resistors are

available on unused SOP pins

100K pull down on SOP2

Reset

RESET input for the device

RTC_XTAL_N

Never leave the reset pin floating

When using an external oscillator,

add a 100-kΩpullup resistor to VIO

Clock

JTAG

When using an external oscillator,

connect to ground if unused

WLAN_XTAL_N

JTAG interface

Leave as NC if unused

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8 Specifications

All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over

process and voltage, unless otherwise indicated.

8.1 Absolute Maximum Ratings

All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process and

overvoltage unless otherwise indicated.

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX UNIT

V_BATand V_IO

Pins: 37, 39, 44

Pins: 10, 54

3.8

–0.5

Supply voltage

V_BATand V_IOshould be tied

together

V_IO–V_BAT(differential)

Digital inputs

RF pins

V_IO+ 0.5

–0.5

–40

–55

2.1

Analog pins, Crystal

Pins: 22, 23, 51, 52

Operating temperature, T_A

Storage temperature, T_stg

°C

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

8.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_ESD

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Power-On Hours (POH)

This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's

standard terms and conditions for TI semiconductor products.

POWER-ON HOURS [POH]

OPERATING CONDITION

(hours)

T_Aup to 85°C⁽¹⁾

87,600

(1) The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device

can be in any other state.

8.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

2.1⁽⁴⁾

–20

TYP

MAX

UNIT

V_BAT, V_IO

(shorted to V_BAT

Direct battery

connection⁽³⁾

Supply voltage

Pins: 10, 37, 39, 44, 54

3.3

3.6

)

Ambient thermal slew

20 °C/minute

(1) Operating temperature is limited by crystal frequency variation.

(2) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect

feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the

transmission.

(3) To ensure WLAN performance, ripple on the supply must be less than ±300 mV.

(4) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also

2.1 V, and care must be taken when operating at the minimum specified voltage.

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8.5 Current Consumption Summary (CC3235S)

表8-1. Current Consumption Summary (CC3235S) 2.4 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (2)}

TX power level = 0

MIN

TYP⁽³⁾

272

190

248

182

223

160

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

NWP ACTIVE

MCU ACTIVE

1 DSSS

54 OFDM

NWP idle connected⁽⁴⁾

15.3

269

187

245

179

220

157

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU SLEEP

1 DSSS

54 OFDM

NWP idle connected⁽⁴⁾

12.2

266

184

242

176

217

154

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU LPDS

1 DSSS

54 OFDM

120 µA at 64KB

135 µA at 256KB

NWP LPDS⁽⁵⁾

135

µA

NWP idle connected⁽⁴⁾

MCU SHUTDOWN MCU shutdown

MCU HIBERNATE MCU hibernate

710

µA

4.5

420

450

670

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.1 V

Peak calibration current⁽⁶⁾

(1) TX power level = 0 implies maximum power (see 图8-1, 图8-2, and 图8-3). TX power level = 4 implies output power backed off

approximately 4 dB.

(2) The CC3235x system is a constant power-source system. The active current numbers scale based on the V_BATvoltage supplied.

(3) Typical numbers assume a VSWR of 1.5:1.

(4) DTIM = 1

(5) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3235x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

(6) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is

performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.

There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further

details, see CC31xx, CC32xx SimpleLink™ Wi-Fi^®and IoT Network Processor Programmer's Guide.

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表8-2. Current Consumption Summary (CC3235S) 5 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (2)}

6 OFDM

MIN

TYP⁽³⁾

318

293

MAX UNIT

NWP ACTIVE

54 OFDM

MCU ACTIVE

54 OFDM

NWP idle connected⁽⁴⁾

15.3

315

290

6 OFDM

54 OFDM

NWP ACTIVE

MCU SLEEP

MCU LPDS

NWP idle connected⁽⁴⁾

12.2

312

287

6 OFDM

54 OFDM

NWP ACTIVE

NWP LPDS⁽⁵⁾

µA

120 µA at 64KB

135 µA at 256KB

135

NWP idle connected⁽⁴⁾

710

MCU SHUTDOWN MCU shutdown

MCU HIBERNATE MCU hibernate

µA

4.5

290

310

400

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.7 V

V_BAT= 2.1 V

Peak calibration current⁽⁶⁾

(1) Measurements taken at maximum TX power

(2) The CC3235x system is a constant power-source system. The active current numbers scale based on the V_BATvoltage supplied.

(3) Typical numbers assume a VSWR of 1.5:1.

(4) DTIM = 1

(5) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3235x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

(6) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is

performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C.

There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further

details, see CC31xx, CC32xx SimpleLink™ Wi-Fi^®and IoT Network Processor Programmer's Guide.

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8.6 Current Consumption Summary (CC3235SF)

表8-3. Current Consumption Summary (CC3235SF) 2.4 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (2)}

TX power level = 0

MIN

TYP⁽³⁾

286

202

255

192

232

174

MAX UNIT

1 DSSS

6 OFDM

54 OFDM

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

NWP ACTIVE

MCU ACTIVE

1 DSSS

54 OFDM

NWP idle connected⁽⁴⁾

25.2

282

198

251

188

228

170

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP ACTIVE

MCU SLEEP

1 DSSS

54 OFDM

NWP idle connected⁽⁴⁾

21.2

266

184

242

176

217

154

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

TX power level = 0

TX power level = 4

1 DSSS

6 OFDM

54 OFDM

NWP active

MCU LPDS

1 DSSS

54 OFDM

120 µA at 64KB

135 µA at 256KB

NWP LPDS⁽⁵⁾

135

710

µA

NWP idle connected⁽⁴⁾

MCU shutdown

MCU

SHUTDOWN

µA

MCU

HIBERNATE

MCU hibernate

4.5

V_BAT= 3.6 V

V_BAT= 3.3 V

V_BAT= 2.1 V

420

450

670

Peak calibration current⁽⁶⁾

(1) TX power level = 0 implies maximum power (see 图8-1, 图8-2, and 图8-3). TX power level = 4 implies output power backed off

approximately 4 dB.

(2) The CC3235x system is a constant power-source system. The active current numbers scale based on the V_BATvoltage supplied.

(3) Typical numbers assume a VSWR of 1.5:1.

(4) DTIM = 1

(5) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3235x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

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(6) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,

typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be

controlled by a configuration file in the serial flash.

表8-4. Current Consumption Summary (CC3235SF) 5 GHz RF Band

T_A= 25°C, V_BAT= 3.6 V

PARAMETER

TEST CONDITIONS^{(1) (2)}

6 OFDM

MIN TYP⁽³⁾MAX UNIT

329

NWP ACTIVE

54 OFDM

306

MCU ACTIVE

MCU SLEEP

NWP idle connected⁽⁴⁾

25.2

325

6 OFDM

54 OFDM

NWP ACTIVE

302

NWP idle connected⁽⁴⁾

21.2

312

6 OFDM

54 OFDM

NWP active

289

µA

MCU LPDS

120 µA at 64KB

135 µA at 256KB

NWP LPDS⁽⁵⁾

135

710

NWP idle connected⁽⁴⁾

MCU shutdown

MCU

SHUTDOWN

µA

MCU

HIBERNATE

MCU hibernate

4.5

V_BAT= 3.6 V

290

310

400

V_BAT= 3.3 V

V_BAT= 2.7 V

V_BAT= 2.1 V

Peak calibration current⁽⁶⁾

(1) Measurements taken at maximum TX power

(2) The CC3235x system is a constant power-source system. The active current numbers scale based on the V_BATvoltage supplied.

(3) Typical numbers assume a VSWR of 1.5:1.

(4) DTIM = 1

(5) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The

CC3235x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU

retained SRAM increases LPDS current by 4 µA.

(6) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly,

typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be

controlled by a configuration file in the serial flash.

8.7 TX Power Control for 2.4 GHz Band

The CC3235x has several options for modifying the output power of the device when required. For the 2.4 GHz

band it is possible to lower the overall output power at a global level using the global TX power level setting. In

addition, the 2.4 GHz band allows the user to enter additional back-offs , per channel, region and modulation

rates ⁴, via Image creator (see the Uniflash with Image Creator User Guide for more details).

图 8-1, 图 8-2, and 图 8-3 show TX power and IBAT versus TX power level settings for the CC3235S device at

modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3235SF device, the IBAT current has

The back-off range is between -6 dB to +6 dB in 0.25dB increments.

FCC/ISED, ETSI (Europe), and Japan are supported.

Back-off rates are grouped into 11b rates, high modulation rates (MCS7, 54 OFDM and 48 OFDM), and lower modulation rates (all

other rates).

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an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX power level will remain

the same.

In 图 8-1, the area enclosed in the circle represents a significant reduction in current during transition from TX

power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using

TX power level 4 to reduce the current.

1 DSSS

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS)

6 OFDM

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)

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54 OFDM

19.00

17.00

280.00

264.40

249.00

233.30

218.00

202.00

186.70

171.00

Color by

TX Power (dBm)

15.00

13.00

IBAT (VBAT @ 3.6 V)

11.00

9.00

7.00

5.00

3.00

1.00

155.60

140.00

TX power level setting

图8-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)

8.8 TX Power Control for 5 GHz

5 GHz power control is done via Image Creator where the maximum transmit power is provided ⁵. Within Image

Creator power control is possible per channel, region ⁶, and modulation rates ⁷. In addition, it is possible to enter

an additional back-off ⁸factor per channel and modulation rate for further margin to regulatory requirements.

Finally, it is also possible to set the TX and RX trace losses to the antenna per band . The peak antenna

gain ¹⁰can also be provided, thus allowing further control. For a full description of options and capabilities see

Uniflash with Image Creator User Guide.

The maximum transmit power range is 18dBm to 0.125dBm in 0.125dBm decrements.

FCC/ISED, ETSI (Europe), and Japan are supported.

Rates are grouped into high modulation rates (MCS7, 54 OFDM and 48 OFDM) and lower modulation rates (all other rates).

The back-off range is 0 dBm to 18 dBm in 0.125 dBm increments, with the maximum back-off not exceed that of the maximum transmit

power.

The range of losses if from 0 dBm to 7.75 dBm in 0.125 dBm increments.

The antenna gain has a range of -2 dBi to 5.75 dBi in 0.125 dBi increments.

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8.9 Brownout and Blackout Conditions

The device enters a brownout condition when the input voltage drops below V_brownout(see 图 8-4 and 图 8-5).

This condition must be considered during design of the power supply routing, especially when operating from a

battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to

networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The resistance

includes the internal resistance of the battery, the contact resistance of the battery holder (four contacts for 2×

AA batteries), and the wiring and PCB routing resistance.

Note

When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during

HIBERNATE state.

图8-4. Brownout and Blackout Levels (1 of 2)

图8-5. Brownout and Blackout Levels (2 of 2)

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In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the

Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout

condition is equivalent to a hardware reset event in which all states within the device are lost.

表8-5 lists the brownout and blackout voltage levels.

表8-5. Brownout and Blackout Voltage Levels

CONDITION

VOLTAGE LEVEL

UNIT

V_brownout

V_blackout

2.1

1.67

8.10 Electrical Characteristics for GPIO Pins

表8-6. Electrical Characteristics: GPIO Pins Except 50, 52, and 53

T_A= 25°C, V_BAT= 2.1 V to 3.3 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

C_IN

V_IH

V_IL

I_IH

Pin capacitance

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

V_DD+ 0.5 V

0.35 × V_DD

–0.5

I_IL

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OH

High-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.1 V ≤V_DD< 2.4 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O drive

strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OL

Low-level output voltage

IL = 6 mA; configured I/O drive

strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O drive

strength = 2 mA;

2.1 V ≤V_DD< 2.4 V

2-mA drive

High-level

I_OH

source

current

4-mA drive

6-mA drive

2-mA drive

4-mA drive

6-mA drive

Low-level

I_OL

sink current

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

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表8-7. Electrical Characteristics: GPIO Pins 50, 52, and 53

T_A= 25°C, V_BAT= 2.1 V to 3.6 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_IN

V_IH

V_IL

I_IH

Pin capacitance

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

0.65 × V_DD

V_DD+ 0.5 V

0.35 × V_DD

–0.5

I_IL

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.8

V_DD× 0.7

V_DD× 0.75

IL = 4 mA; configured I/O

drive strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OH

High-level output voltage

IL = 6 mA; configured I/O

drive strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.1 V ≤V_DD< 2.4 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.4 V ≤V_DD< 3.6 V

V_DD× 0.2

V_DD× 0.25

IL = 4 mA; configured I/O

drive strength = 4 mA;

2.4 V ≤V_DD< 3.6 V

V_OL

Low-level output voltage

IL = 6 mA; configured I/O

drive strength = 6 mA;

2.4 V ≤V_DD< 3.6 V

IL = 2 mA; configured I/O

drive strength = 2 mA;

2.1 V ≤V_DD< 2.4 V

2-mA

drive

1.5

2.5

3.5

1.5

2.5

3.5

High-level

4-mA

I_OH

source current,

drive

V_OH= 2.4

6-mA

drive

2-mA

drive

Low-level sink

current

4-mA

drive

I_OL

6-mA

drive

V_IL

nRESET

0.6

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk

of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength

setting is 6 mA.

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8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown

T_A= 25°C, V_BAT= 3.0 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OH

I_OL

Pullup current, V_OH= 2.4 (V_DD= 3.0 V)

µA

Pulldown current, V_OL= 0.4 (V_DD= 3.0

µA

8.12 WLAN Receiver Characteristics

表8-8. WLAN Receiver Characteristics: 2.4 GHz Band

T_A= 25°C, V_BAT= 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz).

PARAMETER

TEST CONDITIONS (Mbps)

MIN

TYP

–96.0

–94.0

–88.0

–90.5

–90.0

–86.5

–80.5

–74.5

–71.5

–4.0

MAX

UNIT

1 DSSS

2 DSSS

11 CCK

6 OFDM

Sensitivity

(8% PER for 11b rates, 10% PER for 11g/11n

9 OFDM

dBm

rates)⁽¹⁾

18 OFDM

36 OFDM

54 OFDM

MCS7 (GF)⁽²⁾

802.11b

Maximum input level

(10% PER)

dBm

802.11g

–10.0

(1) Sensitivity is 1-dB worse on channel 13 (2472 MHz).

(2) Sensitivity for mixed mode is 1-dB worse.

表8-9. WLAN Receiver Characteristics: 5 GHz Band

T_A= 25°C, V_BAT= 2.1 V to 3.6 V. Parameters measured at SoC pin are the average of channels 40, 56, 120, and 157.

PARAMETER

TEST CONDITIONS (Mbps)

MIN

TYP

-92.0

-91.0

-88.0

-81.5

-75.0

-71.0

-20

MAX

UNIT

dBm

6 OFDM

9 OFDM

18 OFDM

Sensitivity

(10% PER for 11g/11n rates)

36 OFDM

54 OFDM

MCS7 (GF)⁽¹⁾

Maximum input level

802.11a

(1) Sensitivity for mixed mode is 1-dB worse.

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8.13 WLAN Transmitter Characteristics

表8-10. WLAN Transmitter Characteristics: 2.4 GHz Band

T_A= 25°C, V_BAT= 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).^{(1) (2)}

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating frequency range^{(3) (4)}

2412

2472

MHz

1 DSSS

2 DSSS

11 CCK

18.0

18.3

17.3

17.0

16.0

14.5

13.0

6 OFDM

9 OFDM

18 OFDM

36 OFDM

54 OFDM

MCS7

Maximum RMS output power measured at 1

dB from IEEE spectral mask or EVM

dBm

ppm

Transmit center frequency accuracy

–25

(1) The OFDM and MCS7 edge channels (2412 and 2462 MHz) have reduced TX power to meet FCC emission limits.

(2) Power of 802.11b rates are reduced to meet ETSI requirements in Europe.

(3) Channels 1 (2142 MHz) through 11 (2462 MHz) are supported for FCC.

(4) Channels 1 (2142 MHz) through 13 (2472MHz) are supported for Europe and Japan. Note that channel 14 is not supported for Japan.

表8-11. WLAN Transmitter Characteristics: 5 GHz Band

T_A= 25°C, V_BAT= 2.1 V to 3.6 V.⁽¹⁾Parameters measured at SoC pin are the average of channels 40, 56, 120, and 157.⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating frequency range^{(3) (4) (5)}

5180

5825

MHz

6 OFDM

9 OFDM

18 OFDM

36 OFDM

54 OFDM

MCS7

18.1

16.6

15.0

14.0

Maximum RMS output power measured at 1

dB from IEEE spectral mask or EVM

dBm

Transmit center frequency accuracy

-20

ppm

(1) Transmit power will be reduced by 1.5dB for V_BAT< 2.8V

(2) FCC, Europe, and Japan channel power limits per modulation rates can be found in the Uniflash with Image Creator User Guide.

(3) FCC band covers U-NII-1, U-NII-2A, U-NII-2C, and U-NII-3 20-MHz BW modulations.

(4) Europe bands 1, 2 and 3, 20-MHz BW modulations are supported.

(5) For Japan, W52, W53 and W56, 20-MHz BW modulations are supported.

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8.14 WLAN Transmitter Out-of-Band Emissions

Both the 2.4 GHz and the 5 GHz RF paths require an external band-pass filter to meet the various emission

standards, including FCC. 表 8-12 and 表 8-13 presents the minimum attenuation requirements for the 2.4 GHz

and 5 GHz band-pass filter, respectively. TI recommends using the same filter, switch, diplexer, and so on, used

in the reference design to ease the process of certification.

表8-12. WLAN 2.4 GHz Filter Requirements

PARAMETER

FREQUENCY (MHz)

2412 to 2484

804 to 828

MIN

TYP

MAX

UNIT

Return loss

Insertion loss⁽¹⁾

1.5

1608 to 1656

3216 to 3312

4020 to 4140

4824 to 4968

5628 to 5796

6432 to 6624

7200 to 7500

7500 to 10000

2412 to 2484

Bandpass

Attenuation

Reference impendence

Filter type

(1) Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation

requirements.

表8-13. WLAN 5 GHz Filter Requirements

PARAMETER

FREQUENCY (MHz)

5150 to 5925

600 to 2700

MIN

TYP

MAX

UNIT

Return loss

Insertion loss⁽¹⁾

2950 to 3850

4400 to 4600

6600 to 6900

7000 to 7775

10300 to 11850

5150 to 5925

Bandpass

Attenuation

Reference impendence

Filter type

(1) Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation

requirements.

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8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements

For proper BLE/2.4 GHz radio coexistence, the following requirements needs to met:

表8-14. COEX Isolation Requirement

PARAMETER

Band

MIN

20⁽¹⁾

20⁽²⁾

TYP

MAX

UNIT

Single antenna

Port-to-port isolation

Dual antenna Configuration

(1) WLAN/BLE switch used must provide a minimum of 20 dB isolation between ports.

(2) For dual antenna configuration antenna placement must be such that isolation between the BLE and WLAN ports is at least 20 dB.

8.16 Thermal Resistance Characteristics for RGK Package

THERMAL METRICS⁽¹⁾

°C/W^{(2) (3)}

6.3

AIR FLOW (m/s)⁽⁴⁾

0.0051

0.765

Junction-to-case

RΘ_JC

RΘ_JB

RΘ_JA

Junction-to-board

Junction-to-free air

2.4

14.6

12.4

10.8

0.2

Junction-to-moving air

1.275

RΘ_JMA

2.55

0.0051

0.765

0.2

Psi_JT

Junction-to-package top

0.3

1.275

0.1

2.55

2.3

0.0051

0.765

2.3

Psi_JB

Junction-to-board

2.2

1.275

2.4

2.55

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) °C/W = degrees Celsius per watt.

(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

Power dissipation of 2 W and an ambient temperature of 70°C is assumed.

(4) m/s = meters per second.

8.17 Timing and Switching Characteristics

8.17.1 Power Supply Sequencing

For proper operation of the CC3235x device, perform the recommended power-up sequencing as follows:

1. Tie the following pins together on the board:

• V_BAT(pins 37, 39, and 44)

• V_IO(pins 54 and 10)

2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100 K

||, 0.01 µF, RC = 1 ms).

3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high).

For timing diagrams, see 节8.17.3.

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8.17.2 Device Reset

When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow

one of the following alternatives to ensure the reset is properly applied:

• A negative reset pulse (on pin 32) of at least 200-ms duration

• If the 200-ms pulse duration cannot be ensured, a pulldown resistor of 2 MΩmust be connected to pin 52

(RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used.

To ensure a proper reset sequence, the user must call the sl_stop function prior to toggling the reset. When a

reset is required, it is preferable to use the software reset instead of an external trigger.

8.17.3 Reset Timing

8.17.3.1 nRESET (32-kHz Crystal)

图8-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal.

VBAT

VIO

nRESET

APP CODE

LOAD

APP CODE

EXECUTION

POWER

OFF

RESET

HW INIT

FW INIT

STATE

32-kHz

RTC CLK

图8-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal)

表8-15 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset removal.

表8-15. First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal)

ITEM

NAME

DESCRIPTION

MIN

NOM

MAX

UNIT

nReset timing after VBAT and VIO

supply are stable

nReset timing

Hardware wake-up time

Time taken by ROM

firmware to initialize

hardware

Includes 32.768-kHz XOSC settling

time

1.1

App code load time for

CC3235S

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

App code integrity check

time for CC3235SF

CC3235SF

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8.17.3.2 nRESET (External 32-kHz Clock)

图8-7 shows the reset timing diagram for the external 32-kHz clock first-time power-up and reset removal.

VBAT

VIO

nRESET

STATE

APP CODE

EXECUTION

POWER

OFF

APP CODE

LOAD

RESET

HW INIT

FW INIT

32-kHz

RTC CLK

图8-7. First-Time Power-Up and Reset Removal Timing Diagram (External 32-kHz Clock)

表8-16 describes the timing requirements for the external 32-kHz clock first-time power-up and reset removal.

表8-16. First-Time Power-Up and Reset Removal Timing Requirements (External 32-kHz Clock)

ITEM

NAME

DESCRIPTION

MIN

NOM

MAX

UNIT

nReset timing after VBAT and VIO

supply are stable

nReset time

Hardware wake-up time

Time taken by ROM

firmware to initialize

hardware

CC3235S

10.3

CC3235SF

17.3

App code load time for

CC3235R and CC3235S

CC3235S

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

App code integrity check

time for CC3235SF

CC3235SF

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8.17.4 Wakeup From HIBERNATE Mode

Note

The 32.768-kHz crystal is enabled by default when the chip goes into HIBERNATE mode.

表8-17 lists the software hibernate timing requirements.

表8-17. Software Hibernate Timing Requirements

ITEM

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

T_{HIB_MIN}

Minimum hibernate time

Hardware wakeup time plus

firmware initialization time

(1)

T_{wake_from_hib}

50⁽²⁾

App code load time for

CC3235S

Image size (KB) × 1.7 ms

Image size (KB) × 0.06 ms

T_APP_CODE_LOAD

App code load time for

CC3235SF

(1) T_{wake_from_hib}can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting

Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.

(2) Wake-up time can extend to 75 ms if a patch is downloaded from the serial Flash.

图8-8 shows the timing diagram for wakeup from HIBERNATE mode.

Application software requests

entry to hibernate moade

T_{wake_from_hib}

T_{APP_CODE_LOAD}

T_{HIB_MIN}

VBAT

nRESET

STATE

APP CODE

LOAD

ACTIVE

Hibernate

HW WAKEUP

FW INIT

EXECUTION

32-kHz

RTC CLK

图8-8. Wakeup From HIBERNATE Timing Diagram

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8.17.5 Clock Specifications

The CC3235x device requires two separate clocks for operation:

• A slow clock running at 32.768 kHz is used for the RTC.

• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated

TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system

and to reduce overall cost.

8.17.5.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock

frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P

(pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.

图8-9 shows the crystal connections for the slow clock.

RTC_XTAL_P

10 pF

GND

32.768 kHz

RTC_XTAL_N

10 pF

GND

图8-9. RTC Crystal Connections

表8-18 lists the RTC crystal requirements.

表8-18. RTC Crystal Requirements

CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

ppm

kΩ

Frequency

32.768

Frequency accuracy

Crystal ESR

Initial plus temperature plus aging

32.768 kHz

±150

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8.17.5.2 Slow Clock Using an External Clock

When an RTC oscillator is present in the system, the CC3235x device can accept this clock directly as an input.

The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to V_IO. The clock must be a CMOS-

level clock compatible with V_IOfed to the device.

图8-10 shows the external RTC input connection.

32.768 kHz

RTC_XTAL_P

Host system

VIO

100 kΩ

RTC_XTAL_N

图8-10. External RTC Input

表8-19 lists the external RTC digital clock requirements.

表8-19. External RTC Digital Clock Requirements

CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Frequency

32768

Frequency accuracy

(Initial plus temperature plus aging)

±150

50%

ppm

t_r, t_f

Input transition time t_r, t_f(10% to 90%)

Frequency input duty cycle

100

80%

20%

V_ih

V_il

0.65 × V_IO

V_IO

Slow clock input voltage limits

Input impedance

Square wave, DC coupled

0.35 × V_IO

V_peak

MΩ

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8.17.5.3 Fast Clock (F_ref) Using an External Crystal

The CC3235x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The

crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading

capacitors.

图8-11 shows the crystal connections for the fast clock.

WLAN_XTAL_P

6.2 pF

GND

40 MHz

WLAN_XTAL_N

6.2 pF

GND

SWAS031-030

A. The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for

information on frequency tuning.

图8-11. Fast Clock Crystal Connections

表8-20 lists the WLAN fast-clock crystal requirements.

表8-20. WLAN Fast-Clock Crystal Requirements

CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

ppm

Frequency

Frequency accuracy

Crystal ESR

Initial plus temperature plus aging

40 MHz

±20

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8.17.5.4 Fast Clock (F_ref) Using an External Oscillator

The CC3235x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the

clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external

TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the

system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the

LDO improves noise on the TCXO power supply.

图8-12 shows the connection.

V_CC

XO (40 MHz)

CC3235x

TCXO_EN

82 pF

WLAN_XTAL_P

WLAN_XTAL_N

OUT

图8-12. External TCXO Input

表8-21 lists the external F_refclock requirements.

表8-21. External F_refClock Requirements (–40°C to +85°C)

CHARACTERISTICS

TEST CONDITIONS

MIN

TYP

MAX UNIT

Frequency

40.00

MHz

Frequency accuracy (initial plus temperature

plus aging)

±20 ppm

55%

Frequency input duty cycle

Clock voltage limits

45%

0.7

50%

V_pp

Sine or clipped sine wave, AC coupled

1.2

–125

V_pp

at 1 kHz

Phase noise at 40 MHz

at 10 kHz

at 100 kHz

dBc/Hz

–138.5

–143

Resistance

Input impedance

kΩ

Capacitance

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8.17.6 Peripherals Timing

This section describes the peripherals that are supported by the CC3235x device:

• SPI

• I²S

• GPIOs

• I²C

• IEEE 1149.1 JTAG

• ADC

• Camera Parallel Port

• UART

• SD Host

• Timers

8.17.6.1 SPI

8.17.6.1.1 SPI Master

The CC3235x microcontroller includes one SPI module that can be configured as a master or slave device. The

SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing control

between chip select and external clock generation; and a programmable delay before the first SPI word is

transmitted. Slave mode does not include a dead cycle between two successive words.

图8-13 shows the timing diagram for the SPI master.

CLK

MISO

MOSI

图8-13. SPI Master Timing Diagram

表8-22 lists the timing parameters for the SPI master.

表8-22. SPI Master Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

F⁽¹⁾

T_clk

D⁽¹⁾

Clock frequency

Clock period

MHz

(1)

33.3

45%

Duty cycle

55%

(1)

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

(1)

t_IH

(1)

t_OD

t_OH

8.5

(1) Timing parameter assumes a maximum load of 20 pF.

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8.17.6.1.2 SPI Slave

图8-14 shows the timing diagram for the SPI slave.

CLK

MISO

MOSI

图8-14. SPI Slave Timing Diagram

表8-23 lists the timing parameters for the SPI slave.

表8-23. SPI Slave Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

Clock frequency at V_BAT= 3.3 V

F⁽¹⁾

MHz

Clock frequency at V_BAT≤2.1 V

Clock period

(1)

T_clk

D⁽¹⁾

45%

Duty cycle

55%

(1)

t_IS

RX data setup time

RX data hold time

TX data output delay

TX data hold time

(1)

t_IH

(1)

t_OD

t_OH

(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.

8.17.6.2 I²S

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio

applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit

and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A

fractional divider is available for bit-clock generation.

8.17.6.2.1 I²S Transmit Mode

图8-15 shows the timing diagram for the I²S transmit mode.

McACLKX

McAFSX

McAXR0/1

图8-15. I²S Transmit Mode Timing Diagram

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表8-24 lists the timing parameters for the I²S transmit mode.

表8-24. I²S Transmit Mode Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

(1)

f_clk

Clock frequency

Clock low period

Clock high period

TX data hold time

9.216

1/2 fclk

MHz

t^{LP (1)}

(1)

t_HT

(1)

t_OH

(1) Timing parameter assumes a maximum load of 20 pF.

8.17.6.2.2 I²S Receive Mode

图8-16 shows the timing diagram for the I²S receive mode.

McACLKX

McAFSX

McAXR0/1

图8-16. I²S Receive Mode Timing Diagram

表8-25 lists the timing parameters for the I²S receive mode.

表8-25. I²S Receive Mode Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

(1)

f_clk

Clock frequency

Clock low period

Clock high period

RX data hold time

RX data setup time

9.216

1/2 f_clk

MHz

t^{LP (1)}

(1)

t_HT

(1)

t_OH

(1)

t_OS

(1) Timing parameter assumes a maximum load of 20 pF.

8.17.6.3 GPIOs

All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module

consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24

programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown

strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.

Note

Unless otherwise stated, GPIO specifications also applies to pins configured as COEX IOs and

network scripter interface

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图8-17 shows the GPIO timing diagram.

V_DD

80%

20%

t_GPIOF

t_GPIOR

SWAS031-067

图8-17. GPIO Timing Diagram

8.17.6.3.1 GPIO Output Transition Time Parameters (V_supply= 3.3 V)

表8-26 lists the GPIO output transition times for V_supply= 3.3 V.

表8-26. GPIO Output Transition Times (V_supply= 3.3 V)^{(1) (2)}

t_r

t_f

DRIVE

STRENGTH (mA)

DRIVE STRENGTH

CONTROL BITS

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

2MA_EN=1

4MA_EN=0

2MA_EN=0

4MA_EN=1

2MA_EN=1

4MA_EN=1

2⁽³⁾

4⁽³⁾

8.0

9.3

10.7

8.2

9.5

11.0

5.8

6.6

3.2

7.1

3.5

7.6

3.7

4.7

2.3

5.2

2.6

2.9

(1) V_supply= 3.3 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.

(3) The 2-mA and 4-mA drive strength does not apply to the COEX I/O pins. Pins configured as COEX lines are invariably driven at 6 mA.

8.17.6.3.2 GPIO Input Transition Time Parameters

表8-27 lists the input transition time parameters.

表8-27. GPIO Input Transition Time Parameters

MIN

MAX

UNIT

t_r

t_f

Input transition time (t_r, t_f), 10% to 90%

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8.17.6.4 I²C

The CC3235x microcontroller includes one I²C module operating with standard (100 kbps) or fast

(400 kbps) transmission speeds.

图8-18 shows the I²C timing diagram.

I2CSCL

I2CSDA

图8-18. I²C Timing Diagram

表8-28 lists the I²C timing parameters.

表8-28. I²C Timing Parameters⁽¹⁾

PARAMETER

NUMBER

MIN

MAX

UNIT

t_LP

Clock low period

See ⁽²⁾

System clock

t_SRT

t_DH

t_SFT

t_HT

SCL/SDA rise time

Data hold time

See ⁽³⁾

N/A

SCL/SDA fall time

Clock high time

See ⁽²⁾

tLP/2

System clock

t_DS

Data setup time

t_SCSR

t_SCS

Start condition setup time

Stop condition setup time

(1) All timing is with 6-mA drive and 20-pF load.

(2) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal

value programmed in this register.

(3) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of an external pullup resistor. Rise time

depends on the value of the external signal capacitance and external pullup register.

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8.17.6.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary

scan architecture for digital integrated circuits and provides a standardized serial interface to control the

associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the

IEEE Standard 1149.1,Test Access Port and Boundary-Scan Architecture.

图8-19 shows the JTAG timing diagram.

TCK

TMS

TDI

TMS Input Valid

T9 T10

TDI Input Valid

TMS Input Valid

T10

TDI Input Valid

T11

TDO Output Valid

TDO

TDO Output Valid

图8-19. JTAG Timing Diagram

表8-29 lists the JTAG timing parameters.

表8-29. JTAG Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

T10

T11

f_TCK

Clock frequency

1 / f_TCK

t_TCK/ 2

MHz

t_TCK

Clock period

t_CL

Clock low period

Clock high period

TMS setup time

TMS hold time

TDI setup time

TDI hold time

t_CH

t_{TMS_SU}

t_{TMS_HO}

t_{TDI_SU}

t_{TDI_HO}

t_{TDO_HO}

TDO hold time

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8.17.6.6 ADC

图8-20 shows the ADC clock timing diagram.

Repeats Every 16 µs

Internal Ch

2 µs

ADC CLOCK

= 10 MHz

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

Sampling

4 cycles

SAR Conversion

16 cycles

EXT CHANNEL 0

EXT CHANNEL 1

INTERNAL CHANNEL

图8-20. ADC Clock Timing Diagram

表 8-30 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the

ADC and for application-specific examples.

表8-30. ADC Electrical Specifications

TEST CONDITIONS and

PARAMETER

Nbits

DESCRIPTION

Number of bits

MIN

TYP

MAX

UNIT

ASSUMPTIONS

Bits

Worst-case deviation from

histogram method over full scale

(not including first and last three

LSB levels)

INL

Integral nonlinearity

2.5

LSB

–2.5

Worst-case deviation of any step

from ideal

DNL

Differential nonlinearity

1.4

LSB

–1

Input range

Driving source

impedance

100

Successive approximation input

clock rate

FCLK

Clock rate

MHz

Input capacitance

2.15

0.7

ADC Pin 57

ADC Pin 58

ADC Pin 59

ADC Pin 60

Input impedance

kΩ

2.12

1.17

Number of channels

F_sample

Sampling rate of each pin

62.5

KSPS

kHz

F_input_max

Maximum input signal frequency

Input frequency DC to 300 Hz

and 1.4 V_ppsine wave input

SINAD

Signal-to-noise and distortion

Active supply current

Average for analog-to-digital

during conversion without

reference current

I_active

1.5

Total for analog-to-digital when

not active (this must be the SoC

level test)

Power-down supply current for

core supply

I_PD

µA

Absolute offset error

Gain error

FCLK = 10 MHz

±2

±2%

V_ref

ADC reference voltage

1.467

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8.17.6.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a

FIFO, and generates DMA requests. The camera parallel port supports 8 bits.

图8-21 shows the timing diagram for the camera parallel port.

pCLK

pVS, pHS

pDATA

图8-21. Camera Parallel Port Timing Diagram

表8-31 lists the timing parameters for the camera parallel port.

表8-31. Camera Parallel Port Timing Parameters

PARAMETER

NUMBER

MIN

MAX

UNIT

pCLK

T_clk

t_LP

Clock frequency

Clock period

1/pCLK

T_clk/2

MHz

Clock low period

Clock high period

RX data setup time

RX data hold time

Duty cycle

t_HT

t_IS

t_IH

45%

55%

8.17.6.8 UART

The CC3235x device includes two UARTs with the following features:

• Programmable baud-rate generator allows speeds up to 3 Mbps

• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading

• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered

interface

• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

• Standard asynchronous communication bits for start, stop, and parity

• Generation and detection of line-breaks

• Fully programmable serial interface characteristics:

– 5, 6, 7, or 8 data bits

– Generation and detection of even, odd, stick, or no-parity bits

– Generation of 1 or 2 stop-bits

• RTS and CTS hardware flow support

• Standard FIFO-level and End-of-Transmission interrupts

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• Efficient transfers using µDMA:

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO

level

– Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed

FIFO level

• System clock is used to generate the baud clock.

8.17.6.9 SD Host

The CC3235x device provides an interface between a local host (LH), such as an MCU and an SD memory card,

and handles SD transactions with minimal LH intervention.

The SD host does the following:

• Provides SD card access in 1-bit mode

• Deals with SD protocol at the transmission level

• Handles data packing

• Adds cyclic redundancy checks (CRC)

• Start and end bit

• Checks for syntactical correctness

The application interface sends every SD command and either polls for the status of the adapter or waits for an

interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-

of-operation. The controller can be configured to generate DMA requests and work with minimum CPU

intervention. Given the nature of integration of this peripheral on the CC3235x platform, TI recommends that

developers use peripheral library APIs to control and operate the block. This section emphasizes understanding

the SD host APIs provided in the peripheral library of the CC3235x Software Development Kit (SDK).

The SD Host features are as follows:

• Full compliance with SD command and response sets, as defined in the SD memory card

– Specifications, v2.0

– Includes high-capacity (size >2 GB) HC and SD cards

• Flexible architecture allows support for new command structure

• 1-bit transfer mode specifications for SD cards

• Built-in 1024-byte buffer for read or write

– 512-byte buffer for both transmit and receive

– Each buffer is 32-bits wide by 128-words deep

• 32-bit-wide access bus to maximize bus throughput

• Single interrupt line for multiple interrupt source events

• Two slave DMA channels (1 for TX, 1 for RX)

• Programmable clock generation

• Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver

• Supports configurable busy and response timeout

• Support for a wide range of card clock frequency with odd and even clock ratio

• Maximum frequency supported is 24 MHz

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8.17.6.10 Timers

Programmable timers can be used to count or time external events that drive the timer input pins. The CC3235x

general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block

provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate

independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers

can also be used to trigger µDMA transfers.

The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:

• Operating modes:

– 16- or 32-bit programmable one-shot timer

– 16- or 32-bit programmable periodic timer

– 16-bit general-purpose timer with an 8-bit prescaler

– 16-bit input-edge count or time-capture modes with an 8-bit prescaler

– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal

• Counts up or counts down

• Sixteen 16- or 32-bit capture compare pins (CCP)

• User-enabled stalling when the microcontroller asserts CPU Halt flag during debug

• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt

service routine

• Efficient transfers using micro direct memory access controller (µDMA):

– Dedicated channel for each timer

– Burst request generated on timer interrupt

• Runs from system clock (80 MHz)

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9 Detailed Description

9.1 Overview

The CC3235x wireless MCU family has a rich set of peripherals for diverse application requirements. This

section briefly highlights the internal details of the CC3235x devices and offers suggestions for application

configurations.

9.2 Arm^®Cortex^®-M4 Processor Core Subsystem

The high-performance Arm^®Cortex^®-M4 processor provides a cost-conscious platform that meets the needs of

minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding

computational performance and exceptional system response to interrupts.

• The Arm Cortex-M4 core has low-latency interrupt processing with the following features:

– A 32-bit Arm^®Thumb^®instruction set optimized for embedded applications

– Handler and thread modes

– Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit

– Support for Armv6 unaligned accesses

• Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency

interrupt processing. The NVIC includes the following features:

– Bits of priority configurable from 3 to 8

– Dynamic reprioritization of interrupts

– Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels

– Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing

without the overhead of state saving and restoration between interrupts

– Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction

overhead

– Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support

• Bus interfaces:

– Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces

– Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations

• Cost-conscious debug solution featuring:

– Debug access to all memory and registers in the system, including access to memory-mapped devices,

access to internal core registers when the core is halted, and access to debug control registers even while

SYSRESETn is asserted

– Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access

– Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches

9.3 Wi-Fi^®Network Processor Subsystem

The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU

along with an 802.11a/b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN

and Internet connections with 256-bit encryption. The CC3235x devices support station, AP, and Wi-Fi Direct

modes. The device also supports WPA2 personal and enterprise security, WPS 2.0, and WPA3 personal and

enterprise¹¹. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack, TLS stack and

network applications such as HTTPS server.

See CC3235 SDK v3.40 or later for details. Limited to STA mode only.

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9.3.1 WLAN

The WLAN features are as follows:

• 802.11a/b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP,

Wi-Fi Direct client, and group owner with CCK and OFDM rates in the 2.4 GHz band (channels 1 through 13),

and the 5 GHz 20-MHz BW U-NII bands (U-NII-1, U-NII-2A, U-NII-2C, and U-NII-3).

Note

802.11n is supported only in Wi-Fi station and Wi-Fi direct

• The automatically calibrated radio with a single-ended 50-Ωinterface enables easy connection to the

antenna without requiring expertise in radio circuit design.

• Advanced connection manager with multiple user-configurable profiles stored in serial flash allows automatic

fast connection to an access point without user or host intervention.

• Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security

accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x), WPA3 Personal, and WPA3

Enterprise.

• Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end

solution. With elaborate events notification to the host, enabling the application to control the provisioning

decision flow. The wide variety of Wi-Fi provisioning methods include:

– Access Point with HTTP server

– WPS - Wi-Fi Protected Setup, supporting both push button and pin code options.

– SmartConfig^™Technology: TI proprietary, easy to use, one-step, one-time process used to connect a

CC3235x-enabled device to the home wireless network.

• 802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket The 802.11

transceiver mode provides the option to select the working channel, rate, and transmitted power. The receiver

mode works with the filtering options.

• Antenna selection for best connection

• BLE/2.4 GHz radio coexistence mechanism to avoid interference

9.3.2 Network Stack

The Network Stack features are as follows:

• Integrated IPv4, IPv6 TCP/IP stack with BSD socket APIs for simple Internet connectivity with any MCU,

microprocessor, or ASIC

Note

Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.

• Support of 16 simultaneous TCP, UDP, RAW, SSL\TLS sockets

• Built-in network protocols:

– Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration

– ARP, ICMPv4, IGMP, ICMPv6, MLD, ND

– DNS client for easy connection to the local network and the Internet

• Built-in network applications and utilities:

– HTTP/HTTPS

• Web page content stored on serial flash

• RESTful APIs for setting and configuring application content

• Dynamic user callbacks

– Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized

server. After connecting to the access point, the CC3235x device provides critical information, such as

device name, IP, vendor, and port number.

– DHCP server

– Ping

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表9-1 describes the NWP features.

表9-1. NWP Features

Feature

Description

802.11a/b/g/n station

802.11a/b/g AP supporting up to four stations

Wi-Fi standards

Wi-Fi Direct client and group owner

2.4 GHz ISM and 5 GHz U-NII Channels

20 MHz

Wi-Fi channels

Channel Bandwidth

Wi-Fi security

Wi-Fi provisioning

IP protocols

WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x), WPA3 personal and enterprise ⁽¹⁾

SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server

IPv4/IPv6

IP addressing

Cross layer

Static IP, LLA, DHCPv4, DHCPv6 with DAD

ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP

UDP, TCP

Transport

SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2

RAW

Ping

HTTP/HTTPS web server

Network applications and

utilities

mDNS

DNS-SD

DHCP server

Host interface

UART/SPI

Device identity

Trusted root-certificate catalog

TI root-of-trust public key

The CC3235S and CC3235SF variants also support:

•

Secure key storage

Online certificate status protocol (OCSP)

Certificate signing request (CSR)

Unique per device Key-Pair

File system security

Security

Software tamper detection

Cloning protection

Secure boot

Validate the integrity and authenticity of the run-time binary during boot

Initial secure programming

Debug security

JTAG and debug

Power management

Other

Enhanced power policy management uses 802.11 power save and deep-sleep power modes

Transceiver

Programmable RX filters with event-trigger mechanism

Rx Metrics for tracking the surrounding RF environment

(1) See CC3235 SDK v3.40 or newer for details. Limited to STA mode only.

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9.4 Security

The SimpleLink™ Wi-Fi^®CC3235x Internet-on-a chip device enhances the security capabilities available for

development of IoT devices, while completely offloading these activities from the MCU to the networking

subsystem. The security capabilities include the following key features:

Wi-Fi and Internet Security:

• Personal and enterprise Wi-Fi security

– Personal standards

• AES (WPA2-PSK)

• TKIP (WPA-PSK)

• WEP

– Enterprise standards

• EAP Fast

• EAP PEAPv0/1

• EAP PEAPv0 TLS

• EAP PEAPv1 TLS EAP LS

• EAP TLS

• EAP TTLS TLS

• EAP TTLS MSCHAPv2

• Secure sockets

– Protocol versions: OCSP, SSL v3, TLS 1.0, TLS 1.1, TLS 1.2

– Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS

and SSL connections

– Ciphers suites

• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA

• SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA

• SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA

• SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384

• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256

• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256

• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256

– Server authentication

– Client authentication

– Domain name verification

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– Runtime socket upgrade to secure socket –STARTTLS

• Secure HTTP server (HTTPS)

• Trusted root-certificate catalog –Verifies that the CA used by the application is trusted and known secure

content delivery

• TI root-of-trust public key –Hardware-based mechanism that allows authenticating TI as the genuine origin

of a given content using asymmetric keys

• Secure content delivery –Allows encrypted file transfer to the system using asymmetric keys created by the

device

Code and Data Security:

• Network passwords and certificates are encrypted and signed.

• Cloning protection –Application and data files are encrypted by a unique key per device.

• Access control –Access to application and data files only by using a token provided in file creation time. If

an unauthorized access is detected, a tamper protection lock down mechanism takes effect.

• Secured boot –Authentication of the application image on every boot

• Code and data encryption –User application and data files can be encrypted in the serial flash

• Code and data authentication –User Application and data files are authenticated with a public key certificate

• Offloaded crypto library for asymmetric keys, including the ability to create key-pair, sign and verify data

buffer

• Recovery mechanism

Device Security:

• Separate execution environments –Application processor and network processor run on separate Arm

cores

• Initial secure programming –Allows for keeping the content confidential on the production line

• Debug security

– JTAG lock

– Debug ports lock

• True random number generator

图9-1 shows the high-level structure of the CC3235S and CC3235SF devices. The application image, user data,

and network information files (passwords, certificates) are encrypted using a device-specific key.

CC3235S and CC3235SF

Network Processor + MCU

MCU

Network Processor

Peripherals

ARM^®Cortex^®-M4

Processor

SPI and I2C

GPIO

Internet

Wi-Fi^®

MAC

Internet

256KB RAM /

UART

HTTPS

TLS/SSL

TCP/IP

1MB Flash (CC3235SF)

PWM

ADC

Baseband

OEM

Application

Dual-Band Radio

•

Serial Flash

OEM

Application

Data Files

Network Information

图9-1. CC3235S and CC3235SF High-Level Structure

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9.5 FIPS 140-2 Level 1 Certification

The Federal Information Processing Standard (FIPS) Publication 140-2 is a U.S. government computer security

standard. It is commonly referred to as FIPS 140-2 and is used to accredit the design and implementation of

cryptographic modules. A cryptographic module within a security system is necessary to maintain the

confidentiality and integrity of the information protected by the device.

The security engines of the CC3235x device are FIPS validated for FIPS 140-2 level 1 certification ¹². This

certification involves testing the device for all areas related to the secure design and implementation of the

cryptographic modules and covers topics such as: cryptographic specifications, ports and interfaces, a finite

state model for the cryptographic module, the operational environment of the module, and how cryptographic

keys are managed.

9.6 Power-Management Subsystem

The CC3235x power-management subsystem contains DC/DC converters to accommodate the different voltage

or current requirements of the system.

• Digital DC/DC (Pin 44)

– Input: V_BATwide voltage (2.1 to 3.6 V)

• ANA1 DC/DC (Pin 37)

– Input: V_BATwide voltage (2.1 to 3.6 V)

• PA DC/DC (Pin 39)

– Input: V_BATwide voltage (2.1 to 3.6 V)

• ANA2 DC/DC (Pin 47, CC3235SF only)

– Input: V_BATwide voltage (2.1 to 3.6 V)

The CC3235x device is a single-chip WLAN radio solution used on an embedded system with a wide-voltage

supply range. The internal power management, including DC/DC converters and LDOs, generates all of the

voltages required for the device to operate from a wide variety of input sources.

9.7 Low-Power Operating Mode

From a power-management perspective, the CC3235x device comprises the following two independent

subsystems:

• Arm^®Cortex^®-M4 application processor subsystem

• Networking subsystem

Each subsystem operates in one of several power states.

The Arm^®Cortex^®-M4 application processor runs the user application loaded from an external serial flash, or

internal flash (in CC3235SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer

functions.

For exact status of FIPS certification for a specific part number, please refer to https://csrc.nist.gov/publications/fips.

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The user program controls the power state of the application processor subsystem. The application processor

can be in one of the five modes described in 表9-2.

表9-2. User Program Modes

APPLICATION PROCESSOR

DESCRIPTION

(MCU) MODE⁽¹⁾

MCU active mode

MCU executing code at a state rate of 80 MHz

The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode

offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity

from any GPIO line or peripheral.

MCU sleep mode

State information is lost and only certain MCU-specific register configurations are retained. The MCU

can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.)

Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory

retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU

can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the

wake-up source.

MCU LPDS mode

The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly

from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about

15 ms plus the time to load the application from serial flash, which varies according to code size. In this

mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO.

MCU hibernate mode

MCU shutdown mode

The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in

this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the

nRESET line is changed (low to shut down, high to turn on).

(1) Modes are listed in order of power consumption, with highest power modes listed first.

The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network

activity, the NWP sleeps most of the time and wakes up only for beacon reception (see

表9-3).

表9-3. Networking Subsystem Modes

NETWORK PROCESSOR

DESCRIPTION

MODE

Network active mode

Transmitting or receiving IP protocol packets

(processing layer 3, 2, and 1)

Network active mode

Transmitting or receiving MAC management frames; IP processing is not required

(processing layer 2 and 1)

Network active listen mode

Network connected Idle

Special power-optimized active mode for receiving beacon frames (no other frames are supported)

A composite mode that implements 802.11 infrastructure power-save operation. The CC3235x NWP

automatically enters LPDS mode between beacons and then wakes into active listen mode to receive a

beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and

the cycle repeats.

Advanced features of long sleep interval and IoT low power for extending LPDS time for up to 22

seconds while maintaining Wi-Fi connection is supported in this mode.

Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake

Network LPDS mode

Network disabled

The network is disabled

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The operation of the application and network processor ensures that the device remains in the lowest power

mode most of the time to preserve battery life.

The following examples show the use of the power modes in applications:

• A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but

sends and receives little data spends most of the time in connected idle, which is a composite of receiving a

beacon frame and waiting for the next beacon.

• A product that is not continuously connected to the network but instead wakes up periodically (for example,

every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to

transmit data.

9.8 Memory

9.8.1 External Memory Requirements

The CC3235x device maintains a proprietary file system on the serial flash. The CC3235x file system stores the

MCU binary, service pack file, system files, configuration files, certificate files, web page files, and user files. By

using a format command through the API, users can provide the total size allocated for the file system. The

starting address of the file system cannot be set and is always at the beginning of the serial flash. The

applications microcontroller must access the serial flash memory area allocated to the file system directly

through the CC3235x file system. The applications microcontroller must not access the serial flash memory area

directly.

The file system manages the allocation of serial flash blocks for stored files according to download order, which

means that the location of a specific file is not fixed in all systems. Files are stored on serial flash using human-

readable filenames rather than file IDs. The file system API works using plain text, and file encryption and

decryption is invisible to the user. Encrypted files can be accessed only through the file system.

All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB blocks and

thus use a minimum of 4KB of flash space. Fail-safe files require twice the original size and use a minimum of

8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size is 1MB.

表9-4 lists the minimum required memory consumption under the following assumptions:

• System files in use consume 64 blocks (256KB).

• Vendor files are not taken into account.

• MCU code is taken as the maximal possible size for the CC3235 with fail-safe enabled to account for future

updates, such as through OTA.

• Gang image:

– Storage for the gang image is rounded up to 32 blocks (meaning 128-KB resolution).

– Gang image size depends on the actual content size of all components. Additionally, the image should be

128KB aligned so unaligned memory is considered lost. Service pack, system files, and the 128KB

aligned memory are assumed to occupy 256KB.

• All calculations consider that the restore-to-default is enabled.

表9-4. Recommended Flash Size

ITEM

File system allocation table

System and configuration files⁽¹⁾

Service pack⁽¹⁾

CC3235S (KB)

CC3235SF (KB)

256

264

MCU Code⁽¹⁾

512

2048

Gang image size

256 + MCU

1308 + MCU

16 MBit

256 + MCU

2844 + MCU

32 MBit

Total

Minimal flash size⁽²⁾

Recommended flash size⁽²⁾

(1) Including fail-safe.

(2) For maximum MCU size.

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Note

The maximum supported serial flash size is 32MB (256Mb) (see Using Serial Flash on CC3135/

CC3235 SimpleLink™ Wi-Fi® and Internet-of-Things Devices).

9.8.2 Internal Memory

The CC3235x device includes on-chip SRAM to which application programs are downloaded and executed. The

application developer must share the SRAM for code and data. The micro direct memory access (μDMA)

controller can transfer data to and from SRAM and various peripherals. The CC3235x ROM holds the rich set of

peripheral drivers, which saves SRAM space. For more information on drivers, see the CC3235x API list.

9.8.2.1 SRAM

The CC3235x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention during

LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map.

Use the µDMA controller to transfer data to and from the SRAM.

When the device enters low-power mode, the application developer can choose to retain a section of memory

based on need. Retaining the memory during low-power mode provides a faster wakeup. The application

developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API

guide.

9.8.2.2 ROM

The internal zero-wait-state ROM of the CC3235x device is at address 0x0000 0000 of the device memory and

is programmed with the following components:

• Bootloader

• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces

The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3235x

DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs

peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The

DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free the flash

memory for other purposes.

9.8.2.3 Flash Memory

The CC3235SF device comes with an on-chip flash memory of 1MB that allows application code to execute in

place while freeing SRAM exclusively for read-write data. The flash memory is used for code and constant data

sections and is directly attached to the icode/dcode bus of the Arm Cortex-M4 core. A 128-bit-wide instruction

prefetch buffer allows maintenance of maximum performance for linear code or loops that fit inside the buffer.

The flash memory is organized as 2KB sectors that can be independently erased. Reads and writes can be

performed at word (32-bit) level.

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9.8.2.4 Memory Map

表 9-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more

information on peripherals, see the API document.

表9-5. Memory Map

START ADDRESS

0x0000 0000

0x0100 0000

0x2000 0000

0x2200 0000

0x4000 0000

0x4000 4000

0x4000 5000

0x4000 6000

0x4000 7000

0x4000 C000

0x4000 D000

0x4002 0000

0x4002 0800

0x4002 4000

0x4003 0000

0x4003 1000

0x4003 2000

0x4003 3000

0x400F 7000

0x400F E000

0x400F F000

0x4200 0000

0x4401 0000

0x4401 8000

0x4401 C000

0x4402 0000

0x4402 1000

0x4402 5000

0x4402 6000

0x4402 D000

0x4402 E000

0x4402 F000

END ADDRESS

0x0007 FFFF

0x010F FFFF

0x2003 FFFF

0x23FF FFFF

0x4000 0FFF

0x4000 4FFF

0x4000 5FFF

0x4000 6FFF

0x4000 7FFF

0x4000 CFFF

0x4000 DFFF

0x4000 07FF

0x4002 0FFF

0x4002 4FFF

0x4003 0FFF

0x4003 1FFF

0x4003 2FFF

0x4003 3FFF

0x400F 7FFF

0x400F EFFF

0x400F FFFF

0x43FF FFFF

0x4401 0FFF

0x4401 8FFF

0x4401 DFFF

0x4402 1FFF

0x4402 2FFF

0x4402 5FFF

0x4402 6FFF

0x4402 DFFF

0x4402 EFFF

0x4402 FFFF

DESCRIPTION

On-chip ROM (bootloader + DriverLib)

On-chip flash (for user application code)

Bit-banded on-chip SRAM

Bit-band alias of 0x2000 0000 to 0x200F FFFF

Watchdog timer A0

COMMENT

CC3235SF device only

GPIO port A0

GPIO port A1

GPIO port A2

GPIO port A3

UART A0

UART A1

I²C A0 (master)

I²C A0 (slave)

GPIO group 4

General-purpose timer A0

General-purpose timer A1

General-purpose timer A2

General-purpose timer A3

Configuration registers

System control

µDMA

Bit band alias of 0x4000 0000 to 0x400F FFFF

SDIO master

Camera Interface

McASP

SSPI

Used for external serial flash

Used by application processor

GSPI

MCU reset clock manager

MCU configuration space

Global power, reset, and clock manager (GPRCM)

MCU shared configuration

Hibernate configuration

Crypto range (includes apertures for all crypto-related

blocks as follows)

0x4403 0000

0x4403 FFFF

0x4403 0000

0x4403 5000

0x4403 7000

0x4403 9000

0xE000 0000

0xE000 1000

0xE000 2000

0xE000 E000

0x4403 0FFF

0x4403 5FFF

0x4403 7FFF

0x4403 9FFF

0xE000 0FFF

0xE000 1FFF

0xE000 2FFF

0xE000 EFFF

DTHE registers and TCP checksum

MD5/SHA

AES

DES

Instrumentation trace Macrocell^™

Data watchpoint and trace (DWT)

Flash patch and breakpoint (FPB)

NVIC

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表9-5. Memory Map (continued)

DESCRIPTION

START ADDRESS

0xE004 0000

END ADDRESS

0xE004 0FFF

0xE004 1FFF

0xE00F FFFF

COMMENT

Trace port interface unit (TPIU)

0xE004 1000

Reserved for embedded trace macrocell (ETM)

Reserved

0xE004 2000

9.9 Restoring Factory Default Configuration

The device has an internal recovery mechanism that allows rolling back the file system to its predefined factory

image or restoring the factory default parameters of the device. The factory image is kept in a separate sector on

the serial flash in a secure manner and cannot be accessed from the host processor. The following restore

modes are supported:

• None –no factory restore settings

• Enable restore of factory default parameters

• Enable restore of factory image and factory default parameters

The restore process is performed by calling software APIs, or by pulling or forcing SOP[2:0] = 110 pins and

toggling the nRESET pin from low to high.

The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The

restore process typically takes about 8 seconds, depending on the attributes of the serial flash vendor.

9.10 Boot Modes

9.10.1 Boot Mode List

The CC3235x device implements a sense-on-power (SOP) scheme to determine the device operation mode.

SOP values are sensed from the device pin during power up. This encoding determines the boot flow. Before the

device is taken out of reset, the SOP values are copied to a register and used to determine the device operation

mode while powering up. These values determine the boot flow as well as the default mapping (to JTAG, SWD,

UART0) for some of the pins. 表9-6 lists the pull configurations.

表9-6. CC3235x Functional Configurations

BOOT MODE NAME

SOP[2]

SOP[1]

SOP[0]

SOP MODE

COMMENT

Factory, lab flash, and SRAM loads

through the UART. The device waits

indefinitely for the UART to load code.

The SOP bits then must be toggled to

configure the device in functional mode.

Also puts JTAG in 4-wire mode.

UARTLOAD

Pullup

Pulldown

Pulldown LDfrUART

Functional development mode. In this

mode, 2-pin SWD is available to the

developer. TMS and TCK are available

for debugger connection.

FUNCTIONAL_2WJ

FUNCTIONAL_4WJ

Pulldown Pulldown

Pullup

Fn2WJ

Functional development mode. In this

mode, 4-pin JTAG is available to the

developer. TDI, TMS, TCK, and TDO are

available for debugger connection.

Pulldown Fn4WJ

Supports flash and SRAM load through

UART and functional mode. The MCU

bootloader tries to detect a UART break

on UART receive line. If the break signal

UARTLOAD_FUNCTIONAL_4WJ

Pulldown Pullup

Pulldown LDfrUART_Fn4WJ is present, the device enters the

UARTLOAD mode, otherwise, the device

enters the functional mode. TDI, TMS,

TCK, and TDO are available for debugger

connection.

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表9-6. CC3235x Functional Configurations (continued)

BOOT MODE NAME

SOP[2]

SOP[1]

SOP[0]

SOP MODE

COMMENT

When device reset is toggled, the MCU

bootloader kick-starts the procedure to

restore factory default images.

RET_FACTORY_IMAGE

Pulldown Pullup

Pullup

RetFactDef

The recommended values of pull down resistors are 69.8-kΩ for SOP0 and SOP1 and 100-kΩ for SOP2. The

application can use SOP2 for other functions after the device has powered up. To avoid spurious SOP values

from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The SOP0

and SOP1 pins are used as 5 GHz control switch and are not available for other functions. Ensure the SOP pins

are configured as shown in 图 10-7, this is the recommended configuration to ensure the RF Switch, SOP boot

modes, and Factory restore process operates optimally without conflict.

9.11 Hostless Mode

The SimpleLink Wi-Fi CC3235 device incorporates a scripting ability that enables offloading of simple tasks from

the host processor. Using simple and conditional scripts, repetitive tasks can be handled internally, which allows

the host processor to remain in a low-power state. In some cases where the scripter is being used to send

packets, it reduces code footprint and memory consumption. The if-this-then-that style conditioning can include

anything from GPIO toggling to transmitting packets.

The conditional scripting abilities can be divided into conditions and actions. The conditions define when to

trigger actions. Only one action can be defined per condition, but multiple instances of the same condition may

be used, so in effect multiple actions can be defined for a single condition. In total, 16 condition and action pairs

can be defined. The conditions can be simple, or complex using sub-conditions (using a combinatorial AND

condition between them). The actions are divided into two types, those that can occur during runtime and those

that can occur only during the initialization phase.

The following actions can only be performed when triggered by the pre-initialization condition:

• Set roles AP, station, P2P, and Tag modes

• Delete all stored profiles

• Set connection policy

• Hardware GPIO indication allows an I/O to be driven directly from the WLAN core hardware to indicate

internal signaling

The following actions may be activated during runtime:

• Send transceiver packet

• Send UDP packet

• Send TCP packet

• Increment counter increments one of the user counters by 1

• Set counter allows setting a specific value to a counter

• Timer control

• Set GPIO allows GPIO output from the device using the internal networking core

• Enter Hibernate state

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Note

Consider the following limitations:

• Timing cannot be ensured when using the network scripter because some variable latency will

apply depending on the utilization of the networking core.

• The scripter is limited to 16 pairs of conditions and reactions.

• Both timers and counters are limited to 8 instances each. Timers are limited to a resolution of 1

second. Counters are 32 bits wide.

• Packet length is limited to the size of one packet and the number of possible packet tokens is

limited to 8.

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10 Applications, Implementation, and Layout

Note

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

10.1 Application Information

10.1.1 BLE/2.4 GHz Radio Coexistence

The CC3235x device is designed to support BLE/2.4 GHz radio coexistence. Because WLAN is inherently more

tolerant to time-domain disturbances, the coexistence mechanism gives priority to the Bluetooth^®low energy

entity over the WLAN. Bluetooth^®low energy operates in the 2.4 GHz band, therefore the coexistence

mechanism does not affect the 5 GHz band. The CC3235x device can operate normally on the 5 GHz band,

while the Bluetooth^®low energy works on the 2.4 GHz band without mutual interference.

The following coexistence modes can be configured by the user:

• Off mode or intrinsic mode

– No BLE/2.4 GHz radio coexistence, or no synchronization between WLAN and Bluetooth^®low energy—in

case Bluetooth^®low energy exists in this mode, collisions can randomly occur.

• Time Division Multiplexing (TDM, Single Antenna)

– 2.4 GHz Wi-Fi band (see 图10-1)

In this mode, the two entities share the antenna through an RF switch using two GPIOs (one input and

one output from the WLAN perspective).

– 5 GHz Wi-Fi band (see 图10-2)

In this mode, the WLAN operates on the 5 GHz band and Bluetooth^®low energy operates on the 2.4 GHz

band. A 2.4- or 5 GHz diplexer is required for sharing the single antenna.

• Time Division Multiplexing (TDM, Dual Antenna)

– 2.4 GHz Wi-Fi Band (see 图10-3)

In this mode, the two entities have separate antennas. No RF switch is required and only a single GPIO

(one input from the WLAN perspective).

– 5 GHz Wi-Fi band (see 图10-4)

In this mode, the WLAN operates on the 5 GHz band and Bluetooth^®low energy operates on the 2.4 GHz

band. No diplexer is required for the dual-antenna solution.

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BLE / 2.4 GHz Ant.

SPDT RF SWITCH

RF_BG

WLAN

CC3235x

BLE

CCxxxx

CC_COEX_SW_OUT

CC_COEX_BLE_IN

Coex IO

图10-1. 2.4 GHz, Single-Antenna Coexistence Mode Block Diagram

图 10-2 shows the single antenna implementation of a complete Bluetooth^®low energy and WLAN coexistence

network with the WLAN operating on either a 2.4- or a 5 GHz band. The SOP lines control the 5 GHz switch. The

Coex switch is controlled by a GPIO signal from the BLE device and a GPIO signal from the CC3235x device.

A_TX

5 GHz SPDT RF

SWITCH

A_RX

Dual band Ant.

SOP0

SOP1

5 GHz

BPF

WLAN

CC3235x

RF_BG

2.4 / 5 GHz

Diplexer

CC_COEX_SW_OUT

Coex SPDT RF

SWITCH

2.4 GHz

BPF

BLE

CCxxxx

Coex

CC_COEX_BLE_IN

图10-2. Single Antenna Coexistence Solution with 5 GHz Wi-Fi

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图 10-3 shows the dual antenna implementation of a complete Bluetooth^®low energy and WLAN coexistence

network with the WLAN operating on either a 2.4- or a 5 GHz band. Note in this implementation no Coex switch

is required and only a single GPIO from the BLE device to the CC3235x device is required.

2.4 GHz Ant.

BLE Ant.

RF_BG

WLAN

CC3235x

BLE

CCxxxx

CC_COEX_BLE_IN

Coex IO

图10-3. Dual-Antenna Coexistence Mode Block Diagram

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图 10-4 shows the dual antenna implementation of a complete Bluetooth^®low energy and WLAN coexistence

network with the WLAN operating on either a 2.4- or a 5 GHz band. In this case the 2.4 GHz and 5 GHz Wi-Fi

share an antenna and the BLE has it's own dedicated antenna. The SOP lines control the 5 GHz switch. Note in

this implementation no Coex switch is required and only a single GPIO from the BLE device to the CC3235x

device is required.

A_TX

5 GHz SPDT RF

SWITCH

A_RX

Dual Band Ant.

SOP0

SOP1

5 GHz

BPF

WLAN

CC3235x

2.4 / 5 GHz

Diplexer

RF_BG

2.4 GHz

BPF

CC_COEX_SW_OUT

BLE

CCxxxx

CC_COEX_BLE_IN

Coex IO

BLE Ant.

图10-4. Dual Antenna Coexistence Solution with 5 GHz Wi-Fi

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10.1.2 Antenna Selection

The CC3235x device is designed to also support antenna selection and is controlled from Image Creator. When

enabled, there are 3 options possible options:

• ANT 1: When selected, the GPIOs that are defined for antenna selection with set the RF path for antenna 1.

• ANT 2: When selected, the GPIOs that are defined for antenna selection will set the RF path for antenna 2.

• Autoselect: When selected, during a scan and prior to connecting to an AP, CC3235x device will determine

the best RF path and select the appropriate antenna ^{13 14}. The result is the saved as port of the profile.

图10-5 shows the implementation of a complete Bluetooth^®low energy and WLAN coexistence network with the

WLAN operating on either a 2.4- or a 5 GHz band with antenna selection. The SOP lines control the 5 GHz

switch. The Coex switch is controlled by a GPIO signal from the BLE device and a GPIO signal from the

CC3235x device. The Antenna switch is controlled by 2 GPIO lines from the CC3235x device.

A_TX

5 GHz SPDT RF

SWITCH

A_RX

Dual Band Ant. 1

SOP0

SOP1

5 GHz

BPF

WLAN

CC3235x

RF_BG

2.4 / 5 GHz

Diplexer

Antenna Selection

SPDT RF Switch

CC_COEX_SW_OUT

Coex SPDT RF

SWITCH

2.4 GHz

BPF

BLE

CCxxxx

CC_COEX_BLE_IN

Coex IO

Dual Band Ant. 2

ANT_SEL_1

ANT_SEL_2

图10-5. Antenna Selection Solution with Coexistence Solution and 5 GHz Wi-Fi

When selecting Autoselect via the API, a reset is required in order for the CC3235x device to determine the best antenna for use.

Refer to the Uniflash with Image Creator User Guidefor more information.

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图10-6 shows the antenna selection implementation for Wi-Fi, with BLE operating on it's own antenna. The SOP

lines control the 5 GHz switch. Note in this implementation no Coex switch is required and only a single GPIO

from the BLE device to the CC3235x device is required. The Antenna switch is controlled by 2 GPIO lines from

the CC3235x device.

A_TX

5 GHz SPDT RF

SWITCH

Dual Band Ant. 2

A_RX

5 GHz

BPF

SOP0

SOP1

WLAN

CC3235x

2.4 / 5 GHz

Diplexer

Antenna Selection

SPDT RF Switch

RF_BG

2.4 GHz

BPF

CC_COEX_SW_OUT

Dual Band Ant. 2

BLE

CCxxxx

CC_COEX_BLE_IN

Coex IO

ANT_SEL_1

ANT_SEL_2

BLE Ant.

图10-6. Coexistence Solution with Wi-Fi Antenna Selection and dedicated BLE antenna

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10.1.3 Typical Application

图 10-7 shows the schematic of the engine area for the CC3235x device in the wide-voltage mode of operation, with the corresponding bill of materials

show in 表 10-1. 图 10-8 provides the schematic for the RF implementation with and without BLE/2.4 GHz coexistence, with the corresponding bill of

materials shown in 表10-2. For a full operation reference design, see the CC3235x SimpleLink™ and Internet of Things Hardware Design Files.

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VBAT_CC

Optional:

Consider adding extra decoupling

capacitors if the battery cannot source

the peak currents.

VBAT_CC

100k

VBAT_CC

CC_nRESET

100µF

RF_BG

4.7uF

0.6pF

4.7uF

0.5pF

0.1µF

C10

0.01µF

See Figure 7.8 For

RF Conﬁguration Options

GND

A_TX

A_RX

GND

VBAT_CC

VIN_IO1

VIN_IO2

VCC

RESET

RF_BG

SCLK

100k

2.2uH

C11

0.1µF

SI/SIO0

SO/SIO1

VDD_ANA

VIN_DCDC_DIG

VIN_DCDC_PA

VIN_DCDC_ANA

DCDC_ANA_SW

VDD_ANA1

A_TX

A_RX

WP/SIO2

RESET/SIO3

GND

SFL_CS

MX25R3235FM1IL0

FLASH_SPI_CS

FLASH_SPI_DIN

FLASH_SPI_DOUT

FLASH_SPI_CLK

SFL_DIN

SFL_DOUT

SFL_CLK

C12

10uF

C13

0.1µF

C14

0.2pF

C15

0.1uF

C16

0.6pF

GND

R3 R4

100k 100k

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

P50_GPIO_00

P55_GPIO_01

P57_GPIO_02

P58_GPIO_03

P59_GPIO_04

P60_GPIO_05

P61_GPIO_06

P62_GPIO_07

LDO_IN1

LDO_IN2

1uH

DCDC_PA_SW_P

DCDC_PA_SW_N

DCDC_PA_OUT

VDD_PA_IN

VDD_PA

GND GND

GPIO8

GPIO9

P63_GPIO_08

P64_GPIO_09

P01_GPIO_10

P02_GPIO_11

P03_GPIO_12

P04_GPIO_13

P05_GPIO_14

P06_GPIO_15

C17

22uF

C18

22uF

C19

1µF

TP1

TP2

TP3

TP4

TP5

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

CC_nReset

P55_GPIO_01

P57_GPIO_02

SOP0

FLASH PROGRAMMING

INTERFACE

DCDC_DIG_SW

2.2uH

VDD_DIG

GND

VDD_DIG1

VDD_DIG2

Add provision on the board to isolate

GPIO_01 and GPIO_02 while programming

DCDC_ANA2_SW_P

DCDC_ANA2_SW_N

VDD_ANA2

GPIO16

GPIO17

GPIO22

GPIO28

GPIO30

P07_GPIO_16

P08_GPIO_17

P15_GPIO_22

P18_GPIO_28

P53_GPIO_30

C20

10uF

C21

0.1µF

C22

0.1µF

VBAT_CC

SOP2

Pins 45, 46 and 47:

Refer to BOM Table for notes on

device-dependent conﬁgurations.

GND

10uH

VDD_RAM

RTC_XTAL_P

RTC_XTAL_N

VDD_PLL

C23

10uF

WLAN_XTAL_P

WLAN_XTAL_N

C24

0.1µF

C25

0.1uF

32.768kHz

SOP0

SOP1

SOP2

C26

10pF

C27

10pF

GND

C28

6.2pF

TCK

TMS

TDI

C29

0.6pF

C30

6.2pF

GND

TDO

GND_TAB

40MHz

GND

VBAT_CC

CC3235SF12RGKR

GND

270

69.8k

SOP0

SOP1

SOP2

GND

P17_JTAG_TDO

P16_JTAG_TDI

P20_JTAG_TMS

P19_JTAG_TCK

JTAG

100k

R10

69.8k

R11

69.8k

GND

图10-7. CC3235x Engine Area

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表10-1. Bill of Materials for CC3235x Engine Area

Quantity

Designator

Value

Manufacturer

Part Number

Description

CAP, CERM, 100 µF, 10 V,

+/- 20%, X5R, AEC-Q200 Grade 3, 1210

C1, C2

100 µF

4.7 µF

0.6 pF

0.5 pF

0.1 µF

0.01 µF

10 µF

0.2 pF

0.1 µF

22 µF

1 µF

Taiyo Yuden

LMK325ABJ107MMHT

CAP, CERM, 4.7 uF, 6.3 V,

+/- 20%, X6S, 0402

C3, C4, C6

C5, C16, C29

Taiyo Yuden

MuRata

JMK105BC6475MV-F

GJM0335C1ER60BB01D

GJM0335C1ER50BB01D

CL05B104KO5NNNC

0402B103K500CT

CAP, CERM, 0.6pF, 25 V,

+/- 16%, C0G/NP0, 0201

CAP, CERM, 0.5 pF, 25 V,

+/- 20%, C0G/NP0, 0201

Murata

C8, C9, C11, C13, C21,

C22, C24

CAP, CERM, 0.1 µF, 16 V,

+/- 10%, X7R, 0402

Walsin

CAP, CERM, 0.01 µF, 50 V,

+/- 10%, X7R, 0402

C10

Walsin

CAP, CERM, 10 uF, 10 V,

+/- 20%, X6S, 0603

C12, C20, C23

C14

Taiyo Yuden

MuRata

LMK107BC6106MA-T

GJM0335C1ER20BB01D

CL03A104KP3NNNC

GRM188C80G226ME15J

CL05A105MP5NNNC

0402N100J500CT

CAP, CERM, 0.2pF, 25 V,

+/- 50%, C0G/NP0, 0201

CAP, CERM, 0.1 uF, 10 V,

+/- 10%, X5R, 0201

C15, C25

C17, C18

C19

Samsung Electro-Mechanics

MuRata

CAP, CERM, 22 uF, 4 V,

+/- 20%, X6S, 0603

CAP, CERM, 1 µF, 10 V,

+/- 20%, X5R, 0402

Walsin

CAP, CERM, 10 pF, 50 V,

+/- 5%, C0G/NP0, 0402

C26, C27

10 pF

6.2 pF

Walsin

CAP, CERM, 6.2 pF, 50 V,

+/- 4%, C0G/NP0, 0402

C28, C30

J1, J2, J3

L1, L3

Walsin

0402N6R2C500CT

61300311121

Wurth Elektronik

MuRata

Header, 2.54 mm, 3x1, Gold, TH

Inductor, Multilayer, Ferrite,

2.2 uH, 1.2 A, 0.11 ohm, SMD

2.2 µH

1 µH

LQM2MPN2R2NG0

Inductor, Multilayer, Ferrite,

1 uH, 1.6 A, 0.055 ohm, SMD

MuRata

TDK

LQM2HPN1R0MG0L

MLP2520S100MT0S1

Inductor, Multilayer, Ferrite,

10 uH, 0.7 A, 0.364 ohm, SMD

L4⁽¹⁾

10 µH

RES, 100 k, 5%, 0.063 W,

AEC-Q200 Grade 0, 0402

R1, R2, R3, R4, R9

100k

Vishay-Dale

Panasonic

CRCW0402100KJNED

ERJ-2GE0R00X

R5⁽²⁾

RES, 0, 5%, 0.063 W, 0402

RES, 270, 5%, 0.063 W,

AEC-Q200 Grade 0, 0402

270

Vishay-Dale

CRCW0402270RJNED

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表10-1. Bill of Materials for CC3235x Engine Area (continued)

Quantity

Designator

Value

Manufacturer

Part Number

Description

RES, 69.8 k, 1%, 0.063 W,

AEC-Q200 Grade 0, 0402

R7, R8, R10, R11

69.8k

Vishay-Dale

CRCW040269K8FKED

Ultra low power, 32M-bit

Macronix International Co., LTD MX25R3235FM1IL0

[x 1/x 2/x 4] CMOS MXSMIO(serial multi I/O)

Flash memory, SOP-8

SimpleLink Wi-Fi and Internet-of-Things

Solution, a Single-Chip Wireless MCU,

RGK0064B (VQFN-64)

Texas Instruments

CC3235SF12RGKR

Abracon Corporation

TXC Corporation

ABS07-32.768KHZ-9-T

8Y40072002

Crystal, 32.768KHz, 9PF, SMD

Crystal, 40 MHz, 8 pF, SMD

(1) For the CC3235SF device, L4 is populated. For the CC3235S device, L4 is not populated.

(2) For the CC3220SF device, R5 is not populated. For the CC3235S device if R5 is populated, Pin 45 can be used as GPIO_31.

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Fine tuning of DC blocking capacitor

values for C31, C32, and C33 may be

required for optimal performance.

C31

RF1

VC1

VC2

RFC

RF_BLE

C32

68pF

RF2

C33

68pF

GND

R12

100k

C34

100pF

R13

100k

C35

100pF

68pF

RTC6608OSP

Circuit configuration for BLE/2.4-GHz

COEX only. If feature is not being used

GND these components are not required.

GND

A DC blocking capacitor is required. If

the antenna match contains a series

capacitor, this is suﬃcient to meet the

requirement and thus C36 is not

required.

FL1

Antenna match. Pi

network might be

required depending on

type of antenna.

OUT

RF_BG

GND

C36

C37

LBP

DEA202450BT-1294C1-H

8.2pF

2.2pF

HBP

GND

3.9nH

GND

DPX165950DT-8148A1

FL2

C38

C39

GND

RF2

RF1

RFC

VC2

VC1

OUT

GND

C40

1.6pF

1.9pF

A_RX

A_TX

GND

C41

4.7pF

2.7nH

DEA165538BT-2236B1-H

4.7pF

GND

RTC6608OSP

GND

SOP0

SOP1

C42

100pF

C43

100pF

GND

图10-8. CC3235x RF Schematic Implementation with and without Coexistence

Note

The Following guidelines are recommended for implementation of the RF design:

• Ensure an RF path is designed with an impedance of 50 Ω

• Tuning of the antenna impedance πmatching network is recommended after manufacturing of the PCB to account for PCB parasitics

• πor L matching and tuning may be required between cascaded passive components on the RF path

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表10-2. Bill of Materials For CC3235x RF Section

Quantity

Designator

Value

Manufacturer

Part Number

Description

CAP, CERM, 68 pF, 50 V,

+/- 5%, C0G/NP0, 0201

C31⁽¹⁾, C32⁽¹⁾, C33⁽¹⁾

68 pF

Murata

Yageo

GRM0335C1H680JA1D

CAP, CERM, 100 pF, 25 V,

+/- 5%, C0G/NP0, 0201

C34⁽¹⁾, C35⁽¹⁾, C42, C43

100 pF

8.2 pF

2.2 pF

1.6 pF

1.9 pF

4.7 pF

CC0201JRNPO8BN101

0402N8R2C500CT

CAP, CERM, 8.2 pF, 50 V,

+/- 3%, C0G/NP0, 0402

C36

C37

C38

C39

Walsin

CAP, CERM, 2.2 pF, 50 V,

+/- 4.5%, C0G/NP0, 0402

MuRata

GJM1555C1H2R2BB01D

GRM0335C1H1R6BA01D

GJM1555C1H1R9WB01D

CAP, CERM, 1.6 pF, 50 V,

+/- 7%, C0G/NP0, 0201

CAP, CERM, 1.9 pF, 50 V,

+/- 2.6%, C0G/NP0, 0402

CAP, CERM, 4.7 pF, 50 V,

+/- 3%, C0G/NP0, 0201

C40, C41

GRM0335C1H4R7BA01D

M830520

Ethertronics

TDK

WLAN Antenna 802.11, SMD

Multilayer Chip Band Pass Filter For 2.4 GHz

W-LAN/Bluetooth, SMD

FL1

DEA202450BT-1294C1-H

Multilayer Band Pass Filter For

5 GHz W-LAN/LTE-U

FL2

TDK

DEA165538BT-2236B1-H

LQG15HS3N9S02D

Inductor, Multilayer, Air Core,

3.9 nH, 0.75 A, 0.14 ohm, SMD

3.9 nH

2.7 nH

100k

MuRata

Inductor, Multilayer, Air Core,

2.7 nH, 0.9 A, 0.07 ohm,

AEC-Q200 Grade 1, SMD

MuRata

LQG15WH2N7C02D

RES, 100 k, 5%, 0.063 W,

AEC-Q200 Grade 0, 0402

R12⁽¹⁾, R13⁽¹⁾

U3⁽¹⁾, U5

Vishay-Dale

Richwave

CRCW0402100KJNED

RTC6608OSP

0.03 GHz-6 GHz SPDT Switch

Multilayer Diplexer for 2.4 GHz W-LAN &

Bluetooth / 5 GHz

TDK

DPX165950DT-8148A1

W-LAN

(1) If the BLE/2.4 GHz Coexistence features is not used, these components are not required.

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10.2 PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC3235x VQFN device. Follow

these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC, ETSI,

and CE. For more information, see CC3135 and CC3235 SimpleLink™ Wi-Fi^®and IoT Solution Layout

Guidelines.

10.2.1 General PCB Guidelines

Use the following PCB guidelines:

• Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for

signals and ground.

• Ensure that the VQFN PCB footprint follows the information in 节12.

• Ensure that the VQFN PCB GND and solder paste follow the recommendations provided in CC3135 and

CC3235 SimpleLink™ Wi-Fi^®and IoT Solution Layout Guidelines.

• Decoupling capacitors must be as close as possible to the VQFN device.

10.2.2 Power Layout and Routing

Three critical DC/DC converters must be considered for the CC3235x device.

• Analog DC/DC converter

• PA DC/DC converter

• Digital DC/DC converter

Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are

formed when laying out the power components.

10.2.2.1 Design Considerations

The following design guidelines must be followed when laying out the CC3235x device:

• Ground returns of the input decoupling capacitors (C13, C15, and C22) should be routed on Layer 2 using

thick traces to isolate the RF ground from the noisy supply ground. This step is also required to meet the

IEEE spectral mask specifications.

• Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power

amplifier supply lines (pin 33, 40, 41, and 42), and all input supply pins (pin 37, 39, and 44).

• Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).

• Place all decoupling capacitors as close to the respective pins as possible.

• Power budget—the CC3235x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, for

24 ms during the calibration cycle.

• Ensure the power supply is designed to source this current without any issues. The complete calibration (TX

and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.

• The CC3235x device contains many high-current input pins. Ensure the trace feeding these pins can handle

the following currents:

– VIN_DCDC_PA input (pin 39) maximum 1 A

– VIN_DCDC_ANA input (pin 37) maximum 600 mA

– VIN_DCDC_DIG input (pin 44) maximum 500 mA

– DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum 1 A

– DCDC_PA_OUT output node (pin 42) maximum 1 A

– DCDC_ANA_SW switching node (pin 38) maximum 600 mA

– DCDC_DIG_SW switching node (pin 43) maximum 500 mA

– VDD_PA_IN supply (pin 33) maximum 500 mA

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图10-9 shows the ground routing for the input decoupling capacitors.

C7: 0.5 pF

C5: 0.6 pF

C16: 0.6 pF

C14: 0.2 pF

C29: 0.6 pF

图10-9. Ground Routing for Input Decoupling Capacitors

Note

The ground returns for the input capacitors are routed on layer two to reduce the EMI and improve the

spectral mask. This routing must be strictly followed because it is critical for the overall performance of

the device.

Pin 37

Ground

Traces

Pin 37

图10-10. Ground Returns for Input Capacitors

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10.2.3 Clock Interface Guidelines

The following guidelines are for the slow clock:

• The 32.768-kHz crystal must be placed close to the VQFN package.

• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within

±150 ppm.

• The ground plane on layer two is solid below the trace lanes, and there is ground around these traces on the

top layer.

The following guidelines are for the fast clock:

• The 40-MHz crystal must be placed close to the VQFN package.

• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance within

±10 ppm at room temperature. The total frequency across parts, temperature, and with aging must be ±20

ppm to meet the WLAN specification.

• To avoid noise degradation, ensure that no high-frequency lines are routed close to the routing of the crystal

pins.

• Ensure that crystal tuning capacitors are close to the crystal pads.

• Both traces (XTAL_N and XTAL_P) should be as close as possible to parallel and approximately the same

length.

• The ground plane on layer two is solid below the trace lines, and there should be ground around these traces

on the top layer.

• For frequency tuning, see CC31xx & CC32xx Frequency Tuning.

10.2.4 Digital Input and Output Guidelines

The following guidelines are for the digital I/Os:

• Route SPI and UART lines away from any RF traces.

• Keep the length of the high-speed lines as short as possible to avoid transmission line effects.

• Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects (required if the

traces cannot be kept short). Place the resistor at the source end closer to the device that is driving the

signal.

• Add a series-terminating resistor for each high-speed line (for example, SPI_CLK or SPI_DATA) to match the

driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ωfor a 50-Ωline

impedance.

• Route high-speed lines with a continuous ground reference plane below it to offer good impedance

throughout. This routing also helps shield the trace against EMI.

• Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations,

use a separate line driver for each line.

• If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each

high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to

36 Ωfor a 50-Ωline impedance.

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10.2.5 RF Interface Guidelines

The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna

design guides (including placement of the antenna). Also see CC3135 and CC3235 SimpleLink™ Wi-Fi^®and IoT

Solution Layout Guidelines for general antenna guidelines.

• Ensure that the antenna is matched for 50-Ω. A π-matching network is recommended. Ensure that the π

pad is available for tuning the matching network after PCB manufacture.

• A DC blocking capacitor is required before the antenna. If the antenna matching network contains a series

capacitor, this is sufficient to meet the requirement.

• Ensure that the area underneath the BPFs pads have a solid plane on layer 2 and that the minimum filter

requirements are met.

• Ensure that the area underneath the RF switch pads have a solid plane on layer 2 and that the minimum

switch isolation requirements are met.

• Ensure that the area underneath the diplexer pads have a solid plane on layer 2 and that the minimum

diplexer requirements are met.

• Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.

• The RF trace bends must be made with gradual curves. Avoid 90-degree bends.

• The RF traces must not have sharp corners.

• There must be no traces or ground under the antenna section.

• The RF traces must have via stitching on the ground plane beside the RF trace on both sides.

• For optimal antenna performance, ensure adequate ground plane around the antenna on all layers.

• Ensure RF connectors for conducted testing are isolated from the top layer ground using vias.

• Maintain a controlled pad to trace shapes using filleted edges if necessary to avoid mismatch.

• Diplexers, switches, BPF, and other elements on the RF route should be isolated from the top layer ground

using vias.

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11 Device and Documentation Support

11.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 Tools and Software

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed in this section.

For the most up-to-date list of development tools and software, see the CC3235 Tools & Software product page.

Users can also click the "Alert Me" button on the top right corner of the CC3235 Tools & Software page to stay

informed about updates related to the CC3235x device.

Development Tools

Pin Mux Tool

The supported devices are: CC3200, CC3220x, and CC3235x.

The Pin Mux Tool is a software tool that provides a graphical user interface (GUI) for

configuring pin multiplexing settings, resolving conflicts and specifying I/O cell

characteristics for MPUs from TI. Results are output as C header/code files that can

be imported into software development kits (SDKs) or used to configure customers'

custom software. Version 3 of the Pin Mux Tool adds the capability of automatically

selecting a mux configuration that satisfies the entered requirements.

SimpleLink™ Wi-Fi^®

Starter Pro

The supported devices are: CC3100, CC3200, CC3120R, CC3220x, CC3135 and

CC3235x.

The SimpleLink™ Wi-Fi^®Starter Pro mobile App is a new mobile application for

SimpleLink™ provisioning. The app goes along with the embedded provisioning

library and example that runs on the device side (see SimpleLink™ Wi-Fi^®SDK plugin

and TI SimpleLink ™ CC32XX Software Development Kit (SDK)). The new

provisioning release is a TI recommendation for Wi-Fi^®provisioning using SimpleLink

™ Wi-Fi^®products. The provisioning release implements advanced AP mode and

SmartConfig™ technology provisioning with feedback and fallback options to ensure

successful process has been accomplished. Customers can use both embedded

library and the mobile library for integration to their end products.

SimpleLink™ CC32XX

The CC3235x devices are supported.

Software Development

Kit (SDK)

The SimpleLink™ CC32XX SDK contains drivers for the CC3235 programmable

MCU, more than 30 sample applications, and documentation needed to use the

solution. It also contains the flash programmer, a command line tool for flashing

software, configuring network and software parameters (SSID, access point channel,

network profile, BS NIEW), system files, and user files (certificates, web pages, and

more). This SDK can be used with TI’s SimpleLink™ Wi-Fi^®CC3235 LaunchPad™

development kits.

Uniflash Standalone

Flash Tool for TI

The supported devices are: CC3120R, CC3220x, CC3135 and CC3235x.

Microcontrollers (MCU), CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs

Sitara Processors &

SimpleLink Devices

and on-board flash memory for Sitara™ processors. Uniflash has a GUI, command

line, and scripting interface. CCS Uniflash is available free of charge.

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SimpleLink™ Wi-Fi^®

Radio Testing Tool

The supported devices are: CC3100, CC3200, CC3120R, CC3220, CC3135 and

CC3235x.

The SimpleLink™ Wi-Fi^®Radio Testing Tool is a Windows-based software tool for RF

evaluation and testing of SimpleLink™ Wi-Fi^®CC3x20 and CC3x35 designs during

development and certification. The tool enables low-level radio testing capabilities by

manually setting the radio into transmit or receive modes. Using the tool requires

familiarity and knowledge of radio circuit theory and radio test methods.

Created for the internet-of-things (IoT), the SimpleLink™ Wi-Fi^®CC31xx and CC32xx

family of devices include on-chip Wi-Fi^®, Internet, and robust security protocols with

no prior Wi-Fi^®experience needed for faster development. For more information on

these devices, visit SimpleLink™ Wi-Fi^®family, Internet-on-a chip™ solutions.

UniFlash Standalone

Flash Tool for TI

Microcontrollers (MCU),

Sitara™ Processors and

SimpleLink™ Devices

CCS UniFlash is a standalone tool used to program on-chip flash memory on TI

MCUs and on-board flash memory for Sitara^™processors. UniFlash has a GUI,

command line, and scripting interface. CCS UniFlash is available free of charge.

TI Designs and Reference Designs

The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded

processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI Designs

include schematic or block diagrams, BOMs, and design files to speed your time to market.

11.3 Firmware Updates

TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes,

TI recommends that the user has the latest service pack in their module for production.

To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit SimpleLink

™ CC32XX SDK.

11.4 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the

CC3235x device and support tools (see 图11-1).

xxx

PREFIX

X = Preproduction device

Null = Production device

PACKAGING

R = large reel

DEVICE FAMILY

CC = Wireless Connectivity

PACKAGE

RGK = 9-mm × 9-mm VQFN

SERIES NUMBER

3 = Wi-Fi Centric

MEMORY SIZE

M2 = 256KB RAM

12 = 1MB Flash and 256KB RAM

MCU / HOST

1 = No MCU

2 = MCU

DEVICE VARIANTS

S = Secured

SF = Secured Flash

DEVICE GENERATION

0 = Gen 1

2 = Gen 2

DUAL BAND

0 = 2.4-GHz only

5 = 2.4-GHz and 5-GHz supported

3 = Gen 3

图11-1. CC3235x Device Nomenclature

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11.5 Documentation Support

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (CC3235). In the upper right corner, click the "Alert me" button. This registers you to receive a

weekly digest of product information that has changed (if any). For change details, check the revision history of

any revised document. The current documentation that describes the processor, related peripherals, and other

technical collateral follows.

The following documents provide support for the CC3235 device.

Application Reports

CC3135 and CC3235 SimpleLink ™ CC3135 and CC3235 SimpleLink Wi-Fi Embedded Programming User

Wi-Fi^®Embedded Programming User Guide

Guide

SimpleLink™ CC3135, CC3235 Wi-Fi^®This application report describes the best practices for power

Internet-on-a chip™ Networking Sub- management and extended battery life for embedded low-power Wi-Fi

System Power Management

devices such as the SimpleLink Wi-Fi Internet-on-a chip solution from

Texas Instruments.

SimpleLink™ CC31xx, CC32xx Wi-Fi^®The SimpleLink Wi-Fi CC31xx and CC32xx Internet-on-a chip family of

Internet-on-a chip™ Solution Built-In devices from Texas Instruments offer a wide range of built-in security

Security Features

features to help developers address a variety of security needs, which

is achieved without any processing burden on the main microcontroller

(MCU). This document describes these security-related features and

provides recommendations for leveraging each in the context of

practical system implementation.

SimpleLink™ CC3135, CC3235 Wi-Fi^®This document describes the OTA library for the SimpleLink Wi-Fi

and Internet-of-Things Over-the-Air CC3x35 family of devices from Texas Instruments and explains how to

Update

prepare a new cloud-ready update to be downloaded by the OTA

library.

SimpleLink™ CC3135, CC3235 Wi-Fi^®This guide describes the provisioning process, which provides the

Internet-on-a chip™ Solution Device SimpleLink Wi-Fi device with the information (network name, password,

Provisioning

and so forth) needed to connect to a wireless network.

Transfer of TI's Wi-Fi^®Alliance This document explains how to employ the Wi-Fi® Alliance (WFA)

Certifications to Products Based on derivative certification transfer policy to transfer a WFA certification,

SimpleLink™

already obtained by Texas Instruments, to a system you have

developed.

Using Serial Flash on SimpleLink™ This application note is divided into two parts. The first part provides

CC3135 and CC3235 Wi-Fi^®and important guidelines and best- practice design techniques to consider

Internet-of-Things Devices

when choosing and embedding a serial Flash paired with the CC3135

and CC3235 (CC3x35) devices. The second part describes the file

system, along with guidelines and considerations for system designers

working with the CC3x35 devices.

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User's Guides

SimpleLink ™ Wi-Fi^®and This document provides software (SW) programmers with all of the required

Internet-of-Things CC31xx knowledge for working with the networking subsystem of the SimpleLink Wi-Fi

and

Processor

CC32xx

Network devices. This guide provides basic guidelines for writing robust, optimized

networking host applications, and describes the capabilities of the networking

subsystem. The guide contains some example code snapshots, to give users an

idea of how to work with the host driver. More comprehensive code examples can

be found in the formal software development kit (SDK). This guide does not

provide a detailed description of the host driver APIs.

SimpleLink ™

Wi-Fi^®This document provides the design guidelines of the 4-layer PCB used for the

CC3135 and CC3235 and CC3135 and CC3235 SimpleLink Wi-Fi family of devices from Texas Instruments.

IoT

Guidelines

Solution

Layout The CC3135 and CC3235 devices are easy to lay out and are available in quad

flat no-leads (QFNS) packages. When designing the board, follow the suggestions

in this document to optimize performance of the board.

SimpleLink™ CC3235 Wi- The CC3235 SimpleLink LaunchPad Development Kit (LAUNCHXL-CC3235) is a

Fi^®

LaunchPad ™ cost-conscious evaluation platform for Arm Cortex-M4-based MCUs. The

Development Kit Hardware LaunchPad design highlights the CC3235 Internet-on-a chip solution and Wi-Fi

capabilities. The CC3235 LaunchPad also features temperature and

accelerometer sensors, programmable user buttons, three LEDs for custom

applications, and onboard emulation for debugging. The stackable headers of the

CC3235 LaunchPad XL interface demonstrate how easy it is to expand the

functionality of the LaunchPad when interfacing with other peripherals on many

existing BoosterPack^™Plug-in Module add-on boards, such as graphical displays,

audio codecs, antenna selection, environmental sensing, and more.

SimpleLink ™ Wi-Fi^®and The Radio Tool serves as a control panel for direct access to the radio, and can be

Internet-on-a

chip ™ used for both the radio frequency (RF) evaluation and for certification purposes.

CC3235 This guide describes how to have the tool work seamlessly on Texas Instruments

evaluation platforms such as the BoosterPack™ plus FTDI emulation board for

CC3235 devices, and the LaunchPad™ for CC3235 devices.

CC3135

and

Solution Radio Tool

SimpleLink ™

Wi-Fi^®

CC3235

This guide describes TI’s SimpleLink Wi-Fi provisioning solution for mobile

applications, specifically on the usage of the Android^™and IOS^®building blocks

for UI requirements, networking, and provisioning APIs required for building the

mobile application.

CC3135

and

Provisioning for Mobile

Applications

More Literature

CC3235 SimpleLink™ Wi-Fi^®and Internet This technical reference manual details the modules and

of Things Technical Reference Manual

peripherals of the CC3235 SimpleLink ™ Wi-Fi^®MCU. Each

description presents the module or peripheral in a general sense.

Not all features and functions of all modules or peripherals may be

present on all devices. Pin functions, internal signal connections,

and operational parameters differ from device to device. The user

should consult the device-specific data sheet for these details.

CC3x35 SimpleLink™ Wi-Fi^®Hardware

Design Checklist

CC3235S/CC3235SF SimpleLink™ Wi-Fi^®

LaunchPad™ Design Files

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11.6 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

表11-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

CC3235S

Click here

CC3235SF

11.7 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.8 Trademarks

WPA^™, WPA2^™, WPA3^™, and are trademarks of Wi-Fi Alliance.

SimpleLink^™, Internet-on-a chip^™, LaunchPad^™, BoosterPack^™, SmartConfig^™, Sitara^™, TI E2E^™are

trademarks of Texas Instruments.

Macrocell^™is a trademark of Kappa Global Inc.

Android^™is a trademark of Google LLC.

Wi-Fi Alliance^®, Wi-Fi CERTIFIED^®, Wi-Fi^®, and Wi-Fi Direct^®are registered trademarks of Wi-Fi Alliance.

^®, Arm^®, Cortex^®, and Thumb^®are registered trademarks of Arm Limited.

Bluetooth^®is a registered trademark of Bluetooth SIG Inc.

IOS^®is a registered trademark of Cisco.

所有商标均为其各自所有者的财产。

11.9 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.10 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

11.11 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

12.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1.1 Package Option Addendum

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12.1.1.1 Packaging Information

Package

Type

Package

Drawing

Package

Qty

Lead/Ball

Finish⁽³⁾

Orderable Device

CC3235SM2RGKR

CC3235SF12RGKR

Status ⁽¹⁾

ACTIVE

Pins

Eco Plan ⁽²⁾

MSL Peak Temp ⁽⁴⁾

Level-3-260C-168 HR

Op Temp (°C)

–40 to 85

Device Marking^{(5) (6)}

CC3235SM2

Green (RoHS &

no Sb/Br)

CU NIPDAU | CU

NIPDAUAG

VQFN

RGK

2500

Green (RoHS &

no Sb/Br)

CU NIPDAU | CU

NIPDAUAG

CC3235SF12

–40 to 85

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PRE_PROD: Unannounced device, not in production, not available for mass market, nor on the web, samples not available.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

space

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest

availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the

requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified

lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used

between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1%

by weight in homogeneous material).

space

(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the

finish value exceeds the maximum column width.

space

(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

space

(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

space

(6) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by

third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable

steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain

information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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12.1.1.2 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

CC3235SM2RGKR

CC3235SF12RGKR

VQFN

RGK

2500

330.0

16.4

9.3

1.1

12.0

16.0

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TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing

Pins

SPQ

2500

Length (mm)

367.0

Width (mm)

367.0

Height (mm)

38.0

CC3235SM2RGKR

CC3235SF12RGKR

VQFN

RGK

367.0

38.0

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重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

23-Aug-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

CC3235SF12RGKR

CC3235SM2RGKR

ACTIVE

VQFN

RGK

2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR

-40 to 85

CC3235SF

ACTIVE

RGK

2500 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR

CC3235S

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Aug-2021

Addendum-Page 2

PACKAGE OUTLINE

RGK0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9.1

8.9

PIN 1 INDEX AREA

9.1

8.9

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2X 7.5

6.3 0.1

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

SYMM

2X 7.5

0.30

64X

60X 0.5

PIN 1 ID

0.18

0.1

C A B

0.5

0.3

0.05

64X

4222201/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGK0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

6.3)

SEE SOLDER MASK

DETAIL

SYMM

64X (0.6)

64X (0.24)

60X (0.5)

8X (1.1)

(R0.05) TYP

18X (1.2)

(0.6) TYP

SYMM

(8.8)

(

0.2) TYP

VIA

(0.6) TYP

18X (1.2)

(1.1)

(8.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222201/B 03/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGK0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

25X ( 1)

(1.2) TYP

64X (0.6)

64X (0.24)

60X (0.5)

(R0.05) TYP

(1.2) TYP

SYMM

(8.8)

METAL

TYP

SYMM

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4222201/B 03/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CC3235SM2RGKR [TI]

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