CD4066B-MIL [TI]
CMOS 四路双向开关;
| 型号： | CD4066B-MIL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CMOS 四路双向开关 开关 信号电路 复用器 复用器或开关 |
| 文件： | 总20页 (文件大小：545K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
15-V Digital or 7.5-V Peak-to-Peak
Switching
Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients
125-Ω Typical On-State Resistance for 15-V
Operation
Frequency Response, Switch On = 40 MHz
Typical
Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
100% Tested for Quiescent Current at 20 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications
for Description of “B” Series CMOS
Devices
High On/Off Output-Voltage Ratio: 80 dB
Typical at f = 10 kHz, R = 1 kΩ
is
L
High Degree of Linearity: <0.5% Distortion
Typical at f = 1 kHz, V = 5 V p-p,
Applications:
is
is
V
– V ≥ 10 V, R = 10 kΩ
– Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
DD
SS
L
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
– Digital Signal Switching/Multiplexing
– Transmission-Gate Logic Implementation
– Analog-to-Digital and Digital-to-Analog
Conversion
– Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
Typical at V
– V = 10 V, T = 25°C
DD
SS A
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
12
Circuit): 10 Ω Typical
Low Crosstalk Between Switches: –50 dB
Typical at f = 8 MHz, R = 1 kΩ
is
L
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
V
DD
CONTROL A
CONTROL D
SIG D IN/OUT
10 SIG D OUT/IN
9
8
SIG C OUT/IN
SIG C IN/OUT
V
SS
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to V (when the switch
SS
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
CD4066BF3A
CD4066BE
CDIP – F
PDIP – E
Tube of 25
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
CD4066BF3A
CD4066BE
CD4066BM
SOIC – M
CD4066BM96
CD4066BMT
CD4066BNSR
CD4066BPW
CD4066BPWR
CD4066BM
–55°C to 125°C
SOP – NS
CD4066B
CM066B
TSSOP – PW
†
Packagedrawings, standardpackingquantities, thermaldata, symbolization, andPCBdesign
guidelines are available at www.ti.com/sc/package.
Switch
Control
In
V
is
p
n
p
n
Out
V
os
n
Control
†
V
C
V
SS
V
DD
V
SS
†
All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to V
.
DD
B. Normal operation control-line biasing: switch on (logic 1), V = V ; switch off (logic 0), V = V
SS
C
DD
C
C. Signal-level range: V
≤ V ≤ V
92CS-29113
SS
is DD
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
DC supply-voltage range, V
(voltages referenced to V terminal) . . . . . . . . . . . . . . . . . . . . –0.5 V to 20 V
DD
SS
Input voltage range, V (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
DD
is
DC input current, I (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
IN
Package thermal impedance, θ (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Lead temperature (during soldering):
At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
3
MAX
18
UNIT
V
V
DD
Supply voltage
T
A
Operating free-air temperature
–55
125
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER
TEST CONDITIONS
25°C
UNIT
V
(V)
V
DD
IN
125°C
–55°C –40°C
85°C
(V)
TYP
0.01
0.01
0.01
0.02
MAX
0.25
0.5
1
0, 5
5
0.25
0.5
1
0.25
0.5
1
7.5
15
7.5
15
0, 10
0, 15
0, 20
10
15
20
Quiescent device
current
I
µA
DD
30
30
5
5
150
150
5
Signal Inputs (V ) and Outputs (V
)
os
is
V
R
= V
,
DD
C
L
5
800
310
200
850
330
210
1200
500
1300
550
470 1050
= 10 kΩ returned
VDD VSS
On-state resistance
(max)
10
15
180
125
400
240
r
Ω
on
to
V
,
2
= V
to V
DD
300
320
is
SS
5
15
10
5
On-state resistance
difference between
any two switches
∆r
R
= 10 kΩ, V = V
DD
10
15
Ω
on
L
C
V
V
R
= V
= 5 V, V = –5 V,
SS
C
DD
= 5 V (sine wave centered on 0 V),
Total harmonic
distortion
THD
0.4
40
%
is(p-p)
= 10 kΩ, f = 1-kHz sine wave
is
L
–3-dB cutoff
frequency
(switch on)
V
C
= V
= 5 V, V
DD SS
= –5 V, V = 5 V
is(p-p)
MHz
MHz
µA
(sine wave centered on 0 V), R = 1 kΩ
L
–50-dB feedthrough
V
C
= V
= –5 V, V = 5 V
is(p-p)
SS
1
frequency (switch off) (sine wave centered on 0 V), R = 1 kΩ
L
Input/output leakage
current (switch off)
(max)
V
and
= 0 V, V = 18 V, V = 0 V;
is os
C
–5
10
I
is
18
0.1
0.1
1
1
0.1
V
C
= 0 V, V = 0 V, V = 18 V
is
os
V (A) = V
= 5 V,
= –5 V,
C
DD
SS
–50-dB crosstalk
frequency
V (B) = V
C
8
MHz
ns
V (A) = 5 V , 50-Ω source,
is
L
p-p
R
= 1 kΩ
R
= 200 kΩ, V = V
,
5
20
10
7
40
20
15
L
C
DD
Propagation delay
(signal input to
signal output)
V
V
= GND, C = 50 pF,
SS
is
L
= 10 V
10
15
t
pd
(square wave centered on 5 V),
t , t = 20 ns
r f
C
C
C
Input capacitance
Output capacitance
Feedthrough
V
DD
V
DD
V
DD
= 5 V, V = V
= –5 V
= –5 V
= –5 V
8
8
pF
pF
pF
is
C
SS
SS
SS
= 5 V, V = V
C
os
ios
= 5 V, V = V
C
0.5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC
TEST CONDITIONS
25°C
UNIT
V
DD
(V)
125°C
–55°C –40°C
85°C
TYP
MAX
Control (V )
C
5
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
|I | < 10 A,
is
Control input,
low voltage (max)
V
10
15
5
V
V
V
is
V
is
= V , V
= V , and
ILC
SS OS DD
= V , V
= V
DD OS
SS
3.5 (MIN)
Control input,
high voltage
V
IHC
See Figure 6
10
15
7 (MIN)
11 (MIN)
V
V
≤ V , V
DD DD
– V
SS
= 18 V,
is
SS
–5
10
I
IN
Input current (max)
18
10
0.1
0.1
1
1
0.1
µA
≤ V – V
CC
DD
Crosstalk (control input
to signal output)
V
C
= 10 V (square wave),
50
mV
t , t = 20 ns, R = 10 kΩ
r f
L
5
10
15
35
20
15
70
40
30
Turn-on and turn-off
propagation delay
V
C
= V , t , t = 20 ns,
DD r f
IN
= 50 pF, R = 1 kΩ
ns
L
L
V
R
= V , V
DD SS
= GND,
5
10
15
6
9
is
L
= 1 kΩ to GND, C = 50 pF,
L
Maximum control input
repetition rate
V
C
= 10 V (square wave
MHz
pF
centered on 5 V), t , t = 20 ns,
r f
9.5
5
V
os
= 1/2 V at 1 kHz
os
C
Input capacitance
7.5
I
switching characteristics
SWITCH
OUTPUT, V
SWITCH INPUT
V
(V)
os
DD
I
(mA)
(V)
V
(V)
is
25°C
0.51
is
–55°C
0.64
–40°C
0.61
85°C
125°C
MIN
MAX
0.4
5
5
0
5
0
0.42
–0.42
1.1
0.36
–0.36
0.9
–0.64
1.6
–0.61
1.5
–0.51
1.3
4.6
9.5
0.5
1.5
10
10
15
15
10
0
–1.6
4.2
–1.5
4
–1.3
3.4
–1.1
2.8
–0.9
2.4
15
–4.2
–4
–3.4
–2.8
–2.4
13.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (V
DD
– V ) = 5 V
SS
300 Supply Voltage (V
– V ) = 10 V
SS
600
500
400
300
200
DD
T
A
= 125°C
250
T
A
= 125°C
200
150
+25°C
–55°C
+25°C
–55°C
100
50
0
100
0
–4
–3
–2
–1
0
1
2
3
4
–10 –7.5 –5 –2.5
0
2.5
5
7.5
10
V
is
– Input Signal Voltage – V
V
is
– Input Signal Voltage – V
92CS-27327RI
92CS-27326RI
Figure 2
Figure 3
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
Supply Voltage (V
– V ) = 15 V
SS
T
A
= 125°C
DD
600
500
300
250
200
150
100
Supply Voltage (V
– V ) = 5 V
SS
DD
400
300
200
T
A
= 125°C
+25°C
–55°C
10 V
–15 V
100
0
50
0
–10 –7.5 –5 –2.5
0
2.5
5
7.5
10
–10 –7.5 –5
–2.5
0
2.5
5
7.5
10
V
is
– Input Signal Voltage – V
V
is
– Input Signal Voltage – V
92CS-27329RI
92CS-27330RI
Figure 4
Figure 5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
I
is
CD4066B
1 of 4 Switches
V
is
V
os
|V – V
|
is os
r
=
on
|I
is
|
92CS-30966
Figure 6. Determination of r as a Test Condition for Control-Input High-Voltage (V
on
) Specification
IHC
Keithley
V
DD
160 Digital
Multimeter
TG
On
10 kΩ
1-kΩ
Range
Y
X
H. P.
Moseley
7030A
X-Y
Plotter
V
SS
92CS-22716
Figure 7. Channel On-State Resistance Measurement Circuit
POWER DISSIPATION PER PACKAGE
vs
TYPICAL ON CHARACTERISTICS
FOR 1 OF 4 CHANNELS
SWITCHING FREQUENCY
4
10
10
10
10
6
4
T
A
= 25°C
3
2
1
2
3
Supply Voltage
6
4
(V ) = 15 V
DD
2
10 V
2
V
0
6
4
DD
5 V
14
V
V
= V
DD
DD
C
5
6
V
os
2
CD4066B
1 of 4
Switches
–1
V
is
CD4066B
1
12
13
R
L
6
4
V
SS
–2
–3
7
All unused terminals are
2
V
6
SS
connected to V
SS
10
2
4
6
2
4
2
10
3
10
10
–3
–2
–1
0
1
2
3
4
V – Input Voltage – V
I
f – Switching Frequency – kHz
92CS-30919
92C-30920
Figure 8
Figure 9
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
C
ios
V
DD
= 5 V
V
C
= –5 V
CD4066B
1 of 4
Switches
V
DD
V
= V
C
SS
V
os
CD4066B
1 of 4
Switches
V
is
= V
DD
C
is
C
os
V
I
SS = –5 V
V
SS
92CS-30921
92CS-30922
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
All unused terminals are connected to V
.
SS
Figure 11. Off-Switch Input or Output Leakage
Figure 10. Typical On Characteristics
for One of Four Channels
V
DD
V
C
= V
DD
+10 V
V
V
V
DD
C
V
os
CD4066B
1 of 4
Switches
V
is
V
os
t = t = 20 ns
is
r
f
CD4066B
1 of 4
Switches
200 kΩ
50 pF
V
10 kΩ
SS
1 kΩ
V
SS
V
DD
t = t = 20 ns
r
f
92CS-30924
92CS-30923
All unused terminals are connected to V
.
SS
All unused terminals are connected to V
.
SS
Figure 12. Propagation Delay Time Signal Input
(V ) to Signal Output (V
Figure 13. Crosstalk-Control Input
to Signal Output
)
os
is
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
V
DD
V
DD
V
C
= V
V
DD
t = t = 20 ns
r
f
V
os
CD4066B
1 of 4
DD
Switches
1 kΩ
50 pF
V
SS
92CS-30925
NOTES: A. All unused terminals are connected to V
.
SS
B. Delay is measured at V level of +10% from ground (turn-on) or on-state output level (turn-off).
os
Figure 14. Propagation Delay, t
, t
Control-Signal Output
PLH PHL
t
t
r
f
10 V
0 V
V
C
90%
50%
10%
Repetition
Rate
t = t = 20 ns
r
f
VOS at 1 kHz
V
os
VOS
2
V
DD
= 10 V
V
VOS at 1 kHz
C
VOS
2
CD4066B
1 of 4
V
is
= 10 V
Switches
1 kΩ
50 pF
V
SS
All unused terminals are connected to V
.
92CS-30925
SS
Figure 15. Maximum Allowable Control-Input Repetition Rate
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
V
DD
Inputs
V
DD
I
V
SS
92CS-27555
V
SS
Measure inputs sequentially to both V
and V . Connect all unused inputs to either V
SS DD
or V . Measure control inputs only.
SS
DD
Figure 16. Input Leakage-Current Test Circuit
10
2
3
7
9
12
10
2
3
7
9
12
Clock
14
15
Clock
Reset
P
J
J
J
J
J
5
E
1
2
3
4
14
15
1
P
J
J
J
J
J
5
E
1
2
3
4
External
Reset
CD4018B
CD4018B
13
Q
1
Q
2
1
Q
5
Q
4
1
2
5
4
1
1/4 CD4066B
2
13
12
9
8
6
5
2
1
1
3
4
7
6
2
1/3 CD4049B
3
5
6
2
4
CD4001B
9
10
1/3 CD4049B
3
10
4
11
5
8
9
10
Signal
Outputs
12
6
5
11
2
5
13
6
12
13
11
12
Channel 1
Channel 2
Channel 3
Channel 4
LPF
11
12
Signal
Inputs
10 kΩ
Channel 1
Channel 2
Channel 3
Channel 4
1/6 CD4049B
5
2
3
1
4
1
4
CD4066B
3
9
LPF
8
9
10 kΩ
CD4066B
1/4 CD4066B
4
3
8
10
11
11
LPF
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
10 kΩ
10 kΩ
LPF
V
10
DD
Clock
Maximum
Allowable
10 kΩ
30% (V
– V
)
SS
DD
V
SS
Signal Level
Chan 1 Chan 2 Chan 3 Chan 4
92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
5 V
Analog Inputs ( 5 V)
0
–5 V
V
DD
= 5 V
V
DD
= 5 V
CD4066B
A
5 V
0
SW
SW
B
IN
CD4054B
SW
C
SW
D
Digital
Control
Inputs
V
SS
= 0 V
V
SS
= –5 V
V
EE
= –5 V
Analog Outputs ( 5 V)
92CS-30927
Figure 18. Bidirectional Signal Transmission Via Digital Control Logic
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD4066B
CMOS QUAD BILATERAL SWITCH
SCHS051D – NOVEMBER 1998 – REVISED SEPTEMBER 2003
APPLICATION INFORMATION
In applications that employ separate power sources to drive V
and the signal inputs, the V
current capability
DD
DD
should exceed V /R (R = effective external load of the four CD4066B bilateral switches). This provision avoids
DD
L
L
any permanent current flow or clamp action on the V supply when power is applied or removed from the CD4066B.
DD
In certain applications, the external load-resistor current can include both V
and signal-line components. To avoid
DD
drawing V
current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional
DD
switch must not exceed 0.8 V (calculated from r values shown).
on
No V
current will flow through R if the switch current flows into terminals 2, 3, 9, or 10.
L
DD
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
CD4066BE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD4066BEE4
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD4066BF
CD4066BF3A
CD4066BM
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
SOIC
J
J
14
14
14
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4066BM96
CD4066BM96E4
CD4066BME4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4066BMT
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4066BMTE4
CD4066BNSR
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
PW
PW
J
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4066BNSRE4
CD4066BPW
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
CDIP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD4066BPWG4
CD4066BPWR
CD4066BPWRG4
JM38510/05852BCA
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1
TBD
Call TI
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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