CD4066B_14 [TI]

CMOS QUAD BILATERAL SWITCH;


型号：	CD4066B_14
厂家：	TEXAS INSTRUMENTS
描述：	CMOS QUAD BILATERAL SWITCH
文件：	总25页 (文件大小：1147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

15-V Digital or 7.5-V Peak-to-Peak

Switching

Matched Control-Input to Signal-Output

Capacitance: Reduces Output Signal

Transients

125-Ω Typical On-State Resistance for 15-V

Operation

Frequency Response, Switch On = 40 MHz

Typical

Switch On-State Resistance Matched to

Within 5 Ω Over 15-V Signal-Input Range

On-State Resistance Flat Over Full

Peak-to-Peak Signal Range

100% Tested for Quiescent Current at 20 V

5-V, 10-V, and 15-V Parametric Ratings

Meets All Requirements of JEDEC Tentative

Standard No. 13-B, Standard Specifications

for Description of “B” Series CMOS

Devices

High On/Off Output-Voltage Ratio: 80 dB

Typical at f = 10 kHz, R = 1 kΩ

High Degree of Linearity: <0.5% Distortion

Typical at f = 1 kHz, V = 5 V p-p,

Applications:

− V ≥ 10 V, R = 10 kΩ

− Analog Signal Switching/Multiplexing:

Signal Gating, Modulator, Squelch

Control, Demodulator, Chopper,

Commutating Switch

Extremely Low Off-State Switch Leakage,

Resulting in Very Low Offset Current and

High Effective Off-State Resistance: 10 pA

− Digital Signal Switching/Multiplexing

− Transmission-Gate Logic Implementation

− Analog-to-Digital and Digital-to-Analog

Conversion

− Digital Control of Frequency, Impedance,

Phase, and Analog-Signal Gain

Typical at V

− V = 10 V, T = 25°C

SS A

Extremely High Control Input Impedance

(Control Circuit Isolated From Signal

Circuit): 10 Ω Typical

Low Crosstalk Between Switches: −50 dB

Typical at f = 8 MHz, R = 1 kΩ

E, F, M, NS, OR PW PACKAGE

(TOP VIEW)

SIG A IN/OUT

SIG A OUT/IN

SIG B OUT/IN

SIG B IN/OUT

CONTROL B

CONTROL C

CONTROL A

CONTROL D

SIG D IN/OUT

10 SIG D OUT/IN

SIG C OUT/IN

SIG C IN/OUT

description/ordering information

The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.

It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the

on-state resistance is relatively constant over the full signal-input range.

The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices

in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the

n-channel device on each switch is tied to either the input (when the switch is on) or to V (when the switch

is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,

thus, keeps the on-state resistance low over the full operating-signal range.

The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply

voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold

applications, the CD4016B is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

description/ordering information (continued)

ORDERING INFORMATION

ORDERABLE

TOP-SIDE

MARKING

†

PACKAGE

PART NUMBER

CD4066BF3A

CD4066BE

CDIP − F

PDIP − E

Tube of 25

Tube of 50

Reel of 2500

Reel of 250

Reel of 2000

Tube of 90

Reel of 2000

CD4066BF3A

CD4066BE

CD4066BM

CD4066BM96

CD4066BMT

CD4066BNSR

CD4066BPW

CD4066BPWR

SOIC − M

CD4066BM

−55°C to 125°C

SOP − NS

CD4066B

CM066B

TSSOP − PW

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Switch

Control

Out

Control

†

All control inputs are protected by the CMOS protection network.

NOTES: A. All p substrates are connected to V

B. Normal operation control-line biasing: switch on (logic 1), V = V ; switch off (logic 0), V = V

DD SS

C. Signal-level range: V

≤ V ≤ V

is DD

92CS-29113

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply-voltage range, V

(voltages referenced to V terminal) . . . . . . . . . . . . . . . . . . . . −0.5 V to 20 V

Input voltage range, V (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

DC input current, I (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Package thermal impedance, θ (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

Lead temperature (during soldering):

At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN

MAX

UNIT

Supply voltage

Operating free-air temperature

−55

125

°C

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

electrical characteristics

LIMITS AT INDICATED TEMPERATURES

PARAMETER

TEST CONDITIONS

25°C

UNIT

(V)

125°C

−55°C −40°C

85°C

(V)

TYP

0.01

0.02

MAX

0.25

0.5

0, 5

0.25

0.5

0.25

0.5

7.5

0, 10

0, 15

0, 20

Quiescent device

current

µA

150

Signal Inputs (V ) and Outputs (V

)

= V

= 10 kΩ returned

800

310

200

850

330

210

1200

500

1300

550

470 1050

On-state resistance

(max)

V_DD* V_SS

180

125

400

240

Ω

= V

to V

300

320

On-state resistance

difference between

any two switches

∆r

= 10 kΩ, V = V

Ω

= V

= 5 V, V

= −5 V,

= 5 V (sine wave centered on 0 V),

Total harmonic

distortion

THD

0.4

is(p-p)

= 10 kΩ, f = 1-kHz sine wave

−3-dB cutoff

frequency

(switch on)

= V

= 5 V, V

= −5 V, V = 5 V

is(p-p)

MHz

µA

(sine wave centered on 0 V), R = 1 kΩ

−50-dB feedthrough

= V

= −5 V, V = 5 V

is(p-p)

frequency (switch off) (sine wave centered on 0 V), R = 1 kΩ

Input/output leakage

current (switch off)

(max)

and

= 0 V, V = 18 V, V = 0 V;

is os

−5

0.1

= 0 V, V = 0 V, V = 18 V

V (A) = V

= 5 V,

= −5 V,

−50-dB crosstalk

frequency

V (B) = V

MHz

V (A) = 5 V , 50-Ω source,

p-p

= 1 kΩ

= 200 kΩ, V = V ,

= GND, C = 50 pF,

Propagation delay

(signal input to

signal output)

= 10 V

(square wave centered on 5 V),

t , t = 20 ns

r f

Input capacitance

Output capacitance

Feedthrough

= 5 V, V = V

= −5 V

= 5 V, V = V

ios

= 5 V, V = V

0.5

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

electrical characteristics (continued)

LIMITS AT INDICATED TEMPERATURES

CHARACTERISTIC

TEST CONDITIONS

25°C

UNIT

(V)

125°C

−55°C −40°C

85°C

TYP

MAX

Control (V )

|I | < 10 µA,

Control input,

low voltage (max)

= V , V

= V , and

SS OS DD

ILC

= V , V

= V

DD OS

3.5 (MIN)

Control input,

high voltage

7 (MIN)

IHC

See Figure 6

11 (MIN)

≤ V , V

DD DD

− V

= 18 V,

−5

Input current (max)

0.1

µA

≤ V − V

Crosstalk (control input

to signal output)

= 10 V (square wave),

t , t = 20 ns, R = 10 kΩ

r f

Turn-on and turn-off

propagation delay

= V , t , t = 20 ns,

DD r f

= 50 pF, R = 1 kΩ

= V , V

DD SS

= GND,

= 1 kΩ to GND, C = 50 pF,

Maximum control input

repetition rate

= 10 V (square wave

MHz

centered on 5 V), t , t = 20 ns,

r f

9.5

= 1/2 V at 1 kHz

Input capacitance

7.5

switching characteristics

SWITCH

OUTPUT, V

SWITCH INPUT

(V)

(mA)

(V)

25°C

0.51

−55°C

0.64

−40°C

0.61

85°C

125°C

MIN

MAX

0.4

0.42

−0.42

1.1

0.36

−0.36

0.9

−0.64

1.6

−0.61

1.5

−0.51

1.3

4.6

9.5

0.5

1.5

−1.6

4.2

−1.5

−1.3

3.4

−1.1

2.8

−0.9

2.4

−4.2

−4

−3.4

−2.8

−2.4

13.5

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE

INPUT SIGNAL VOLTAGE (ALL TYPES)

TYPICAL ON-STATE RESISTANCE

INPUT SIGNAL VOLTAGE (ALL TYPES)

300

250

Supply Voltage (V

− V ) = 5 V

Supply Voltage (V

− V ) = 10 V

600

500

400

300

200

= 125°C

200

150

+25°C

−55°C

+25°C

−55°C

100

−4

−3

−2

−1

−10 −7.5 −5 −2.5

2.5

7.5

− Input Signal Voltage − V

92CS-27327RI

92CS-27326RI

Figure 2

Figure 3

TYPICAL ON-STATE RESISTANCE

INPUT SIGNAL VOLTAGE (ALL TYPES)

TYPICAL ON-STATE RESISTANCE

INPUT SIGNAL VOLTAGE (ALL TYPES)

= 125°C

Supply Voltage (V

− V ) = 15 V

600

500

300

250

200

150

100

Supply Voltage (V

− V ) = 5 V

400

300

200

= 125°C

+25°C

−55°C

10 V

−15 V

100

−10 −7.5 −5 −2.5

2.5

7.5

−10 −7.5 −5 −2.5

2.5

7.5

− Input Signal Voltage − V

92CS-27329RI

92CS-27330RI

Figure 5

Figure 4

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

CD4066B

1 of 4 Switches

|V − V

is os

92CS-30966

Figure 6. Determination of r as a Test Condition for Control-Input High-Voltage (V

) Specification

IHC

Keithley

160 Digital

Multimeter

10 kΩ

1-kΩ

Range

H. P.

Moseley

7030A

X-Y

Plotter

92CS-22716

Figure 7. Channel On-State Resistance Measurement Circuit

POWER DISSIPATION PER PACKAGE

TYPICAL ON CHARACTERISTICS

FOR 1 OF 4 CHANNELS

SWITCHING FREQUENCY

= 25°C

Supply Voltage

(V ) = 15 V

10 V

5 V

= V

CD4066B

1 of 4

Switches

−1

CD4066B

−2

−3

All unused terminals are

connected to V

−3

−2

−1

V − Input Voltage − V

f − Switching Frequency − kHz

92CS-30919

92C-30920

Figure 9

Figure 8

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

ios

= 5 V

= −5 V

CD4066B

1 of 4

Switches

= V

CD4066B

1 of 4

Switches

= V

SS = −5 V

92CS-30921

92CS-30922

Measured on Boonton capacitance bridge, model 75a (1 MHz);

test-fixture capacitance nulled out.

All unused terminals are connected to V

Figure 10. Typical On Characteristics

for One of Four Channels

Figure 11. Off-Switch Input or Output Leakage

= V

+10 V

CD4066B

1 of 4

Switches

t = t = 20 ns

CD4066B

1 of 4

Switches

200 kΩ

50 pF

10 kΩ

1 kΩ

t = t = 20 ns

92CS-30924

92CS-30923

All unused terminals are connected to V

Figure 12. Propagation Delay Time Signal Input

(V ) to Signal Output (V

Figure 13. Crosstalk-Control Input

to Signal Output

)

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

= V

t = t = 20 ns

CD4066B

1 of 4

Switches

1 kΩ

50 pF

92CS-30925

NOTES: A. All unused terminals are connected to V

B. Delay is measured at V level of +10% from ground (turn-on) or on-state output level (turn-off).

Figure 14. Propagation Delay, t

, t

Control-Signal Output

PLH PHL

10 V

0 V

90%

50%

10%

Repetition

Rate

t = t = 20 ns

_OSat 1 kHz

V_OS

= 10 V

_OSat 1 kHz

V_OS

CD4066B

1 of 4

= 10 V

Switches

1 kΩ

50 pF

All unused terminals are connected to V

92CS-30925

Figure 15. Maximum Allowable Control-Input Repetition Rate

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

Inputs

92CS-27555

Measure inputs sequentially to both V

and V . Connect all unused inputs to either V

SS DD

or V . Measure control inputs only.

Figure 16. Input Leakage-Current Test Circuit

Clock

Reset

External

Reset

CD4018B

1/4 CD4066B

1/3 CD4049B

CD4001B

1/3 CD4049B

Signal

Outputs

Channel 1

Channel 2

Channel 3

Channel 4

LPF

Signal

Inputs

10 kΩ

Channel 1

Channel 2

Channel 3

Channel 4

1/6 CD4049B

CD4066B

LPF

10 kΩ

CD4066B

1/4 CD4066B

LPF

Package Count

2 - CD4001B

1 - CD4049B

3 - CD4066B

2 - CD4018B

10 kΩ

LPF

Clock

Maximum

Allowable

10 kΩ

30% (V

− V )

Signal Level

Chan 1 Chan 2 Chan 3 Chan 4

92CM-30928

Figure 17. Four-Channel PAM Multiplex System Diagram

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

TYPICAL CHARACTERISTICS

5 V

Analog Inputs ( 5 V)

−5 V

= 5 V

CD4066B

5 V

CD4054B

Digital

Control

Inputs

= 0 V

= −5 V

Analog Outputs ( 5 V)

92CS-30927

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

APPLICATION INFORMATION

In applications that employ separate power sources to drive V

and the signal inputs, the V

current capability

should exceed V /R (R = effective external load of the four CD4066B bilateral switches). This provision avoids

any permanent current flow or clamp action on the V

supply when power is applied or removed from the CD4066B.

In certain applications, the external load-resistor current can include both V

and signal-line components. To avoid

drawing V

current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional

switch must not exceed 0.8 V (calculated from r values shown).

No V

current will flow through R if the switch current flows into terminals 2, 3, 9, or 10.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

PACKAGING INFORMATION

Orderable Device

CD4066BE

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

CD4066BE

CD4066BEE4

ACTIVE

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

-55 to 125

CD4066BE

CD4066BF

ACTIVE

CDIP

TBD

A42

N / A for Pkg Type

-55 to 125

CD4066BF

CD4066BF3A

TBD

CD4066BF3A

CD4066BF3AS2283

CD4066BF3AS2534

CD4066BM

OBSOLETE

ACTIVE

CDIP

SOIC

TBD

Call TI

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-55 to 125

CD4066BM

CD4066B

CD4066BM96

CD4066BM96E4

CD4066BM96G4

CD4066BME4

CD4066BMG4

CD4066BMT

ACTIVE

SOIC

2500

Green (RoHS CU NIPDAU | CU SN

& no Sb/Br)

Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

CD4066BMTE4

CD4066BMTG4

CD4066BNSR

CD4066BNSRE4

CD4066BNSRG4

250

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CD4066B

Green (RoHS

& no Sb/Br)

CD4066B

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

CD4066BPW

CD4066BPWE4

CD4066BPWG4

CD4066BPWR

ACTIVE

TSSOP

CDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

A42

Level-1-260C-UNLIM

N / A for Pkg Type

CM066B

ACTIVE

Green (RoHS

& no Sb/Br)

CM066B

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

CD4066BPWRE4

CD4066BPWRG4

JM38510/05852BCA

M38510/05852BCA

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TBD

JM38510/

05852BCA

CDIP

TBD

A42

N / A for Pkg Type

JM38510/

05852BCA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2013

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :

Catalog: CD4066B

•

Automotive: CD4066B-Q1, CD4066B-Q1

•

Military: CD4066B-MIL

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CD4066BM96

CD4066BM96G4

CD4066BMT

SOIC

2500

250

330.0

16.4

12.4

6.5

8.2

6.9

9.0

10.5

5.6

2.1

2.5

1.6

8.0

12.0

8.0

16.0

12.0

CD4066BNSR

CD4066BPWR

2000

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CD4066BM96

CD4066BM96G4

CD4066BMT

SOIC

2500

250

367.0

333.2

367.0

333.2

367.0

345.9

367.0

345.9

367.0

38.0

28.6

38.0

28.6

38.0

35.0

CD4066BNSR

CD4066BPWR

2000

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CD4066B_14 [TI]

相关型号：

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