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CD4070BMJ-MIL [TI]

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CD4070BMJ-MIL
型号： CD4070BMJ-MIL
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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CD4070B,  
CD4077B  
Data sheet acquired from Harris Semiconductor  
SCHS055  
CMOS Quad Exclusive-OR  
and Exclusive-NOR Gate  
January 1998  
Features  
Description  
• High-Voltage Types (20V Rating)  
• CD4070B - Quad Exclusive-OR Gate  
• CD4077B - Quad Exclusive-NOR Gate  
• Medium Speed Operation  
The Harris CD4070B contains four independent Exclusive-  
OR gates. The Harris CD4077B contains four independent  
Exclusive-NOR gates.  
[ /Title  
(CD40  
70B,  
CD407  
7B)  
/Sub-  
ject  
(CMO  
SQuad  
Exclu-  
sive-  
The CD4070B and CD4077B provide the system designer  
with a means for direct implementation of the Exclusive-OR  
and Exclusive-NOR functions, respectively.  
- t  
, t  
PHL PLH  
= 65ns (Typ) at V = 10V, C = 50pF  
DD L  
• 100% Tested for Quiescent Current at 20V  
• Standardized Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
Ordering Information  
TEMP.  
PKG.  
NO.  
o
PART NUMBER RANGE ( C)  
PACKAGE  
-55 to 125 14 Ld PDIP  
-55 to 125 14 Ld PDIP  
• Maximum Input Current of 1µA at 18V Over Full  
Package Temperature Range  
CD4070BE  
CD4077BE  
CD4070BF  
CD4077BF  
CD4070BM  
CD4077BM  
E14.3  
o
- 100nA at 18V and 25 C  
E14.3  
• Noise Margin (Over Full Package Temperature Range)  
OR  
and  
- 1V at V  
DD  
= 5V, 2V at V  
= 10V, 2.5V at V  
= 15V  
DD  
DD  
-55 to 125 14 Ld CERDIP  
-55 to 125 14 Ld CERDIP  
-55 to 125 14 Ld SOIC  
-55 to 125 14 Ld SOIC  
F14.3  
• Meets All Requirements of JEDEC Standard No. 13B,  
“Standard Specifications for Description of ‘B’ Series  
CMOS Devices  
F14.3  
Exclu-  
sive-  
NOR  
Gate)  
/Autho  
r ()  
M14.15  
M14.15  
Applications  
• Logical Comparators  
• Adders/Subtractors  
/Key-  
words  
(Har-  
ris  
Semi-  
con-  
• Parity Generators and Checkers  
Pinouts  
CD4070B  
(PDIP, CERDIP, SOIC)  
TOP VIEW  
CD4077B  
(PDIP, CERDIP, SOIC)  
TOP VIEW  
ductor,  
CD400  
0,  
metal  
gate,  
CMOS  
, pdip,  
cerdip,  
mil,  
A
B
B
D
C
D
1
2
3
4
5
6
7
14  
13  
12  
V
A
B
B
D
C
D
1
2
3
4
5
6
7
14  
13  
12  
V
DD  
DD  
H
G
H
G
J = A  
K = C  
J = A  
K = C  
11 M = G  
10 L = E  
H
11 M = G  
10 L = E  
H
F
F
9
8
F
E
9
8
F
E
V
V
SS  
SS  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 910.1  
Copyright © Harris Corporation 1998  
1
CD4070B, CD4077B  
Functional Diagrams  
CD4070B  
CD4077B  
1
2
1
A
B
A
B
3
3
4
J
J
2
J = A  
B
D
J = A  
B
D
C
5
6
5
6
K =  
C
D
4
C
D
K = C  
K
L
K
L
M = G  
L = E  
H
F
8
9
8
9
E
F
E
F
10  
11  
M = G  
L = E  
H
F
10  
11  
V
V
= 7  
= 14  
SS  
DD  
12  
13  
12  
13  
G
H
G
H
M
M
V
DD  
V
DD  
V
DD  
p
n
V
DD  
p
B †  
p
n
B †  
n
2(5,9,12)  
p
n
V
n
2(5,9,12)  
p
SS  
DD  
p
p
V
V
SS  
DD  
J
V
p
p
J
p
n
3(4,10,11)  
n
A †  
3(4,10,11)  
p
n
n
A †  
1(6,8,13)  
n
n
1(6,8,13)  
V
SS  
V
SS  
V
V
DD  
DD  
V
V
SS  
SS  
† INPUTS PROTECTED  
† INPUTS PROTECTED  
BY CMOS PROTECTION  
NETWORK  
BY CMOS PROTECTION  
NETWORK  
V
V
SS  
SS  
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B  
(1 OF 4 IDENTICAL GATES)  
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B  
(1 OF 4 IDENTICAL GATES)  
CD4070B TRUTH TABLE (1 OF 4 GATES)  
CD4077B TRUTH TABLE (1 OF 4 GATES)  
A
0
1
0
1
B
0
0
1
1
J
0
1
1
0
A
B
0
0
1
1
J
1
0
0
1
0
1
0
1
NOTE:  
NOTE:  
1 = High Level  
0 = Low Level  
1 = High Level  
0 = Low Level  
J = A  
B
J = A  
B
2
CD4070B, CD4077B  
Absolute Maximum Ratings  
Thermal Information  
o
o
DC Supply Voltage Range (V ) . . . . . . . . . . . . . . . . . -0.5V to 20V Thermal Resistance (Typical, Note 1)  
DD  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to V  
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA  
0.5V  
PDIP Package . . . . . . . . . . . . . . . . . . .  
CERDIP Package . . . . . . . . . . . . . . . .  
SOIC Package. . . . . . . . . . . . . . . . . . .  
Maximum Junction Temperature (Hermetic Package or Die)175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
90  
95  
175  
N/A  
38  
DD  
N/A  
o
Operating Conditions  
o
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
DC Electrical Specifications  
o
LIMITS AT INDICATED TEMPERATURES ( C)  
CONDITIONS  
25  
V
V
V
DD  
O
IN  
PARAMETER  
(V)  
(V)  
0, 5  
0, 10  
0, 15  
0, 20  
0, 5  
0, 10  
0, 15  
0, 5  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
-
(V)  
-55  
0.25  
0.5  
1
-40  
0.25  
0.5  
1
85  
7.5  
15  
125  
7.5  
MIN  
TYP  
0.01  
0.01  
0.01  
0.02  
1
MAX  
UNITS  
µA  
µA  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
Quiescent Device Current  
-
5
-
0.25  
I
Max  
DD  
-
10  
15  
20  
5
15  
-
0.5  
-
30  
30  
-
-
1
-
5
5
150  
0.42  
1.1  
2.8  
-0.42  
-1.3  
-1.1  
-2.8  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
150  
0.36  
0.9  
5
Output Low (Sink) Current  
Min  
0.4  
0.64  
1.6  
4.2  
-0.64  
-2  
0.61  
1.5  
4
0.51  
1.3  
3.4  
-0.51  
-1.6  
-1.3  
-3.4  
-
-
I
OL  
0.5  
10  
15  
5
2.6  
6.8  
-1  
-
1.5  
2.4  
-
Output High (Source) Current  
Min  
4.6  
-0.61  
-1.8  
-1.5  
-4  
-0.36  
-1.15  
-0.9  
-2.4  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
-
I
OH  
2.5  
5
-3.2  
-2.6  
-6.8  
0
-
9.5  
10  
15  
5
-1.6  
-4.2  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
-
13.5  
-
Output Voltage: Low Level,  
Max  
-
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
3
0.05  
V
OL  
-
10  
15  
5
-
0
0.05  
V
-
-
0
0.05  
V
Output Voltage: High Level,  
Min  
-
4.95  
9.95  
14.95  
-
5
-
V
V
OH  
-
-
10  
15  
5
10  
15  
-
-
V
-
V
Input Low Voltage,  
Max  
0.5, 4.5  
1, 9  
1.5  
V
V
IL  
-
10  
15  
5
3
-
-
3
V
1.5, 13.5  
0.5, 4.5  
1, 9  
-
4
4
4
4
-
-
4
V
Input High Voltage,  
Min  
-
3.5  
7
3.5  
7
3.5  
7
3.5  
3.5  
7
-
-
V
V
IH  
-
10  
15  
18  
7
-
-
-
V
1.5, 13.5  
-
-
11  
11  
11  
11  
11  
-
-
V
-5  
±10  
Input Current, I Max  
IN  
0, 18  
±0.1  
±0.1  
±1  
±1  
±0.1  
µA  
3
CD4070B, CD4077B  
o
AC Electrical Specifications  
T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ  
A
r
f
L
L
TEST CONDITIONS  
LIMITS ON ALL TYPES  
PARAMETER  
SYMBOL  
V
(V)  
TYP  
140  
65  
MAX  
280  
130  
100  
200  
100  
80  
UNITS  
ns  
DD  
Propagation Delay Time  
t
, t  
5
PHL PLH  
10  
15  
5
ns  
50  
ns  
Transition Time  
t
, t  
THL TLH  
100  
50  
ns  
10  
15  
ns  
40  
ns  
Input Capacitance  
C
Any Input  
5
7.5  
pF  
IN  
Typical Performance Curves  
o
o
T
= 25 C  
T = 25 C  
A
A
30  
25  
20  
15  
10  
5
GATE TO SOURCE VOLTAGE (V ) = 15V  
GS  
15  
12.5  
10  
GATE TO SOURCE VOLTAGE (V ) = 15V  
GS  
10V  
10V  
7.5  
5
5V  
5V  
2.5  
0
0
0
0
5
10  
15  
5
10  
15  
V
, DRAIN TO SOURCE VOLTAGE (V)  
V , DRAIN TO SOURCE VOLTAGE (V)  
DS  
DS  
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT  
CHARACTERISTICS  
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT  
CHARACTERISTICS  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
-15  
-10  
-5  
0
-15  
-10  
-5  
0
0
0
o
o
T
= 25 C  
A
T
= 25 C  
A
-5  
GATE TO SOURCE VOLTAGE (V ) = -5V  
GS  
GATE TO SOURCE VOLTAGE (V ) = -5V  
GS  
-10  
-15  
-20  
-25  
-30  
-5  
-10V  
-10V  
-10  
-15  
-15V  
-15V  
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT  
CHARACTERISTICS  
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT  
CHARACTERISTICS  
4
CD4070B, CD4077B  
Typical Performance Curves (Continued)  
o
T
= 25 C  
A
o
T
= 25 C  
A
300  
200  
100  
0
200  
150  
100  
50  
SUPPLY VOLTAGE (V ) = 5V  
DD  
SUPPLY VOLTAGE (V ) = 5V  
DD  
10V  
10V  
15V  
15V  
0
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
110  
C , LOAD CAPACITANCE (pF)  
C , LOAD CAPACITANCE (pF)  
L
L
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF  
LOAD CAPACITANCE  
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A  
FUNCTION OF LOAD CAPACITANCE  
5
10  
o
o
T
= 25 C  
T
= 25 C  
A
A
LOAD CAPACITANCE C = 50pF  
L
4
3
2
10  
10  
10  
300  
200  
100  
0
10V  
C
= 50pF  
L
10V  
= 15pF  
C
L
10  
1
5V  
-1  
10  
-1  
2
3
4
0
5
10  
15  
20  
10  
1
10  
10  
10  
10  
V
, SUPPLY VOLTAGE (V)  
f , INPUT FREQUENCY (kHz)  
DD  
I
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A  
FUNCTION OF SUPPLY VOLTAGE  
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A  
FUNCTION OF INPUT FREQUENCY  
5
CD4070B, CD4077B  
Dual-In-Line Plastic Packages (PDIP)  
E14.3 (JEDEC MS-001-AA ISSUE D)  
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE  
E1  
INDEX  
AREA  
INCHES  
MILLIMETERS  
1 2  
3
N/2  
SYMBOL  
MIN  
MAX  
0.210  
-
MIN  
-
MAX  
5.33  
-
NOTES  
-B-  
A
A1  
A2  
B
-
4
-A-  
0.015  
0.115  
0.014  
0.045  
0.008  
0.735  
0.005  
0.300  
0.240  
0.39  
2.93  
0.356  
1.15  
0.204  
18.66  
0.13  
7.62  
6.10  
4
D
E
BASE  
PLANE  
0.195  
0.022  
0.070  
0.014  
0.775  
-
4.95  
0.558  
1.77  
0.355  
19.68  
-
-
A2  
A
-C-  
-
SEATING  
PLANE  
L
C
L
B1  
C
8
D1  
B1  
-
eA  
A1  
A
D1  
e
D
5
C
eC  
B
eB  
D1  
E
5
0.010 (0.25)  
C
B
S
M
0.325  
0.280  
8.25  
7.11  
6
NOTES:  
E1  
e
5
1. Controlling Dimensions: INCH. In case of conflict between English  
and Metric dimensions, the inch dimensions control.  
0.100 BSC  
0.300 BSC  
2.54 BSC  
7.62 BSC  
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication No. 95.  
e
-
0.430  
0.150  
-
10.92  
3.81  
7
B
L
0.115  
2.93  
4
9
4. Dimensions A, A1 and L are measured with the package seated in  
N
14  
14  
JEDEC seating plane gauge GS-3.  
Rev. 0 12/93  
5. D, D1, and E1 dimensions do not include mold flash or protrusions.  
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).  
e
6. E and  
dicular to datum  
7. e and e are measured at the lead tips with the leads uncon-  
are measured with the leads constrained to be perpen-  
A
-C-  
.
B
C
strained. e must be zero or greater.  
C
8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar  
protrusions shall not exceed 0.010 inch (0.25mm).  
9. N is the maximum number of terminal positions.  
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,  
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -  
1.14mm).  
6
CD4070B, CD4077B  
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)  
c1 LEAD FINISH  
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)  
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE  
-D-  
E
-A-  
INCHES MILLIMETERS  
MIN  
BASE  
(c)  
METAL  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.785  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
19.94  
7.87  
NOTES  
b1  
A
b
-
-
M
M
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
(b)  
b1  
b2  
b3  
c
3
SECTION A-A  
S
S
S
D
bbb  
C A - B  
D
-
4
BASE  
PLANE  
Q
2
A
-C-  
SEATING  
PLANE  
c1  
D
3
L
α
5
S1  
b2  
eA  
A A  
e
E
0.220  
5.59  
5
b
C A - B  
eA/2  
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
M
S
S
M
S
S
D
ccc  
D
aaa  
C A - B  
-
NOTES:  
0.125  
0.200  
0.060  
-
3.18  
5.08  
1.52  
-
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.38  
0.13  
6
S1  
7
o
o
o
o
90  
105  
90  
105  
-
α
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
aaa  
bbb  
ccc  
M
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
2, 3  
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
N
14  
14  
Rev. 0 4/94  
5. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
6. Dimension Q shall be measured from the seating plane to the  
base plane.  
7. Measure dimension S1 at all four corners.  
8. N is the maximum number of terminal positions.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
7
IMPORTANT NOTICE  
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
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Copyright 1999, Texas Instruments Incorporated  

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