CD4541B_16 [TI]

CMOS Programmable Timer;
CD4541B_16
型号: CD4541B_16
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

CMOS Programmable Timer

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CD4541B  
CMOS Programmable Timer  
High Voltage Types (20V Rating)  
Data sheet acquired from Harris Semiconductor  
SCHS085E – Revised September 2003  
The output from this timer is the Q or Q output from the 8th,  
10th, 13th, or 16th counter stage. The desired stage is chosen  
using time-select inputs A and B (see Frequency Select Table).  
Features  
• Low Symmetrical Output Resistance, Typically 100Ω  
at V  
= 15V  
DD  
The output is available in either of two modes selectable via the  
MODE input, pin 10 (see Truth Table). When this MODE input is  
a logic “1”, the output will be a continuous square wave having  
[ /Title  
(CD45  
41B)  
/Sub-  
ject  
(CMO  
S Pro-  
gram-  
mable  
Timer  
High  
Volt-  
age  
Types  
(20V  
Rat-  
ing))  
/Autho  
r ()  
/Key-  
words  
(Har-  
ris  
Semi-  
con-  
ductor,  
CD400  
0,  
metal  
gate,  
• Built-In Low-Power RC Oscillator  
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz  
N
a frequency equal to the oscillator frequency divided by 2 .  
• External Clock (Applied to Pin 3) can be Used Instead  
of Oscillator  
With the MODE input set to logic “0” and after a MASTER  
N
RESET is initiated, the output (assuming Q output has been  
• Operates as 2 Frequency Divider or as a Single-  
N-1  
selected) changes from a low to a high state after 2  
counts  
Transition Timer  
and remains in that state until another MASTER RESET pulse  
is applied or the MODE input is set to a logic “1”.  
• Q/Q Select Provides Output Logic Level Flexibility  
• AUTO or MASTER RESET Disables Oscillator During  
Reset to Reduce Power Dissipation  
Timing is initialized by setting the AUTO RESET input (pin 5) to  
logic “0” and turning power on. If pin 5 is set to logic “1”, the  
AUTO RESET circuit is disabled and counting will not start until  
after a positive MASTER RESET pulse is applied and returns  
to a low level. The AUTO RESET consumes an appreciable  
amount of power and should not be used if low-power operation  
• Operates With Very Slow Clock Rise and Fall Times  
• Capable of Driving Six Low Power TTL Loads, Three  
Low-Power Schottky Loads, or Six HTL Loads Over  
the Rated Temperature Range  
is desired. For reliable automatic power-on reset, V  
be greater than 5V.  
should  
DD  
• Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V, and 15V Parametric Ratings  
The RC oscillator, shown in Figure 2, oscillates with a  
frequency determined by the RC network and is calculated  
using:  
• Meets All Requirements of JEDEC Standard No. 13B,  
“Standard Specications for Description of ‘B’ Series  
CMOS Devices”  
Where f is between 1kHz  
and 100kHz  
1
----------------------------------  
f =  
2.3 R  
C
TC TC  
and R 10kΩ and 2R  
S
TC  
Description  
CD4541B programmable timer consists of a 16-stage binary  
counter, an oscillator that is controlled by external R-C compo-  
nents (2 resistors and a capacitor), an automatic power-on  
reset circuit, and output control logic. The counter increments  
on positive-edge clock transitions and can also be reset via the  
MASTER RESET input.  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD4541BF3A  
CD4541BE  
( C)  
PACKAGE  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
CD4541BM  
CD4541BMT  
CD4541BM96  
CD4541BNSR  
CD4541BPW  
CD4541BPWR  
Pinout  
CD4541B  
(CERDIP, PDIP, SOIC, SOP, TSSOP)  
14 Ld TSSOP  
14 Ld TSSOP  
TOP VIEW  
CMOS  
, pdip,  
cerdip,  
mil,  
mili-  
tary,  
R
C
1
2
3
4
5
6
7
14  
13  
12  
V
DD  
TC  
NOTE: When ordering, use the entire part number. The sufxes 96  
and R denote tape and reel. The sufx T denotes a small-quantity  
reel of 250.  
B
A
TC  
R
S
NC  
AUTO RESET  
11 NC  
10 MODE  
mil  
MASTER RESET  
9
8
Q/Q SELECT  
OUTPUT  
V
SS  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD4541B  
Functional Diagram  
12  
13  
1
A
B
R
C
TC  
2
3
5
6
10  
TC  
8
R
Q
S
AR  
MR  
MODE  
Q/Q  
SELECT  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
9
12 13  
A B  
R
N
P
8
Q
1 OF 3  
MUX  
9
N
P
16  
Q/Q SELECT  
2
OR  
3
10  
13  
8
2
2
2
R  
S
V
2
1
DD  
8-STAGE  
COUNTER  
8-STAGE  
COUNTER  
OSC  
R
C  
TC  
R  
TC  
R
R
10  
MODE  
5
PWR ON  
RESET  
V
SS  
V
V
= 14  
= 7  
DD  
SS  
All inputs are protected by CMOS Protection Network.  
NC = 4, 11  
6
MANUAL RESET†  
FIGURE 1.  
FREQUENCY SELECTION TABLE  
NO. OF  
N
A
0
0
1
1
B
0
1
0
1
STAGES N  
COUNT 2  
8192  
13  
10  
8
3
TO CLOCK  
CKT  
1024  
R
256  
S
INTERNAL  
RESET  
16  
65536  
C
2
1
TC  
TRUTH TABLE  
STATE  
PIN  
5
0
Auto Reset On  
Master Reset Off  
1
R
TC  
Auto Reset Disable  
Master Reset On  
6
FIGURE 2. RC OSCILLATOR CIRCUIT  
9
Output Initially Low After  
Reset (Q)  
Output Initially High After  
Reset (Q)  
10  
Single Transition Mode  
Recycle Mode  
2
CD4541B  
Absolute Maximum Ratings  
Thermal Information  
DC Supply - Voltage Range, V  
Package Thermal Impedance, θ (see Note 1)  
JA  
PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 C/W  
SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 C/W  
SOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 C/W  
TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 C/W  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
DD  
o
o
o
o
Voltages Referenced to V Terminal . . . . . . . . . . -0.5V to +20V  
SS  
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V  
+0.5V  
DD  
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . 10mA  
Device Dissipation Per Output Transistor  
For T = Full Package Temperature Range  
A
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW  
o
o
o
Maximum Storage Temperature Range (T  
) . . . -65 C to 150 C  
STG  
Maximum Lead Temperature (Soldering 10s)  
At Distance 1/16in 1/32in (1.59mm 0.79mm)  
from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265 C  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
o
Temperature Range T . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range  
For T = Full Package Temperature Range . . . . .3V (Min), 18V (Typ)  
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
Electrical Specications  
o
CONDITIONS  
LIMITS AT INDICATED TEMPERATURES ( C)  
25  
V
(V)  
V
V
DD  
O
IN  
PARAMETER  
(V)  
0, 5  
0, 10  
0, 15  
0, 20  
0, 5  
0, 10  
0, 15  
0, 5  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
0, 5  
0, 10  
0, 15  
-
(V)  
-55  
-40  
5
85  
150  
300  
600  
3000  
1.26  
3.3  
125  
150  
300  
600  
3000  
1.08  
2.8  
MIN  
TYP  
0.04  
0.04  
0.04  
0.08  
3.1  
8
MAX  
UNITS  
μA  
μA  
μA  
μA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
V
Quiescent Device  
Current,  
-
5
5
-
5
-
10  
15  
20  
5
10  
10  
-
10  
(Note 2) I  
(Max)  
DD  
-
20  
20  
-
20  
-
100  
100  
1.85  
4.8  
12  
-
100  
Output Low (Sink)  
0.4  
1.9  
1.55  
-
Current l (Min)  
OL  
0.5  
10  
15  
5
5
4
-
1.5  
12.6  
8.4  
7.2  
10  
20  
-3.1  
-10  
-8  
-
Output High (Source)  
4.6  
-1.9  
-1.85  
-6  
-1.26  
-4.1  
-3.3  
-8.4  
0.05  
0.05  
0.05  
4.95  
9.95  
14.95  
1.5  
-1.08  
-3  
-1.55  
-
Current, I  
(Min)  
OH  
2.5  
5
-6.2  
-5  
-
9.5  
10  
15  
5
-5  
-4.8  
-12  
-2.8  
-7.2  
-4  
-
13.5  
-12.6  
-10  
-20  
0
-
0.05  
0.05  
0.05  
-
Output Voltage:  
-
-
-
-
-
-
-
-
-
-
-
Low-Level, V (Max)  
OL  
-
10  
15  
5
-
0
V
-
-
0
V
Output Voltage:  
-
4.95  
5
V
High-Level, V  
(Min)  
OH  
-
-
10  
15  
5
9.95  
10  
15  
-
-
V
14.95  
-
V
Input Low Voltage,  
(Max)  
0.5, 4.5  
1, 9  
-
-
-
1.5  
3
V
V
IL  
-
10  
15  
3
-
V
1.5, 13.5  
-
4
-
4
V
3
CD4541B  
Electrical Specications (Continued)  
o
CONDITIONS  
LIMITS AT INDICATED TEMPERATURES ( C)  
25  
V
V
(V)  
V
DD  
O
IN  
PARAMETER  
(V)  
0.5, 4.5  
1, 9  
(V)  
-55  
-40  
85  
3.5  
7
125  
MIN  
3.5  
7
TYP  
MAX  
UNITS  
Input High Voltage,  
-
5
-
-
-
-
-
V
V
V
(Min)  
IH  
-
-
10  
15  
18  
-
-
1.5, 13.5  
-
-
11  
1
11  
-
-
V
-5  
Input Current, l (Max)  
IN  
0, 18  
0.1  
0.1  
1
10  
0.1  
μA  
NOTE:  
o
2. With AUTO RESET enabled, additional current drain at 25 C is:  
7μA (Typ), 200μA (Max) at 5V;  
30μA (Typ), 350μA (Max) at 10V;  
80μA (Typ), 500μA (Max) at 15V  
o
Dynamic Electrical Specications T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ  
A
r
f
L
L
PARAMETER  
SYMBOL  
V
(V)  
MIN  
TYP  
3.5  
MAX  
10.5  
3.8  
2.9  
18  
10  
7.5  
200  
100  
80  
360  
180  
130  
-
UNITS  
DD  
8
Propagation Delay Times  
Clock to Q  
(2 ) t  
, t  
5
-
μs  
μs  
PHL PLH  
10  
15  
5
-
1.25  
0.9  
-
μs  
16  
(2 ) t  
, t  
PHL PLH  
-
6.0  
μs  
10  
15  
5
-
3.5  
μs  
-
2.5  
μs  
Transition Time  
t
-
100  
50  
ns  
THL  
10  
15  
5
-
ns  
-
40  
ns  
t
-
180  
90  
ns  
THL  
10  
15  
5
-
ns  
-
900  
300  
225  
-
65  
ns  
MASTER RESET, CLOCK  
Pulse Width  
300  
100  
85  
ns  
10  
15  
5
-
ns  
-
ns  
Maximum Clock Pulse Input  
Frequency  
f
1.5  
-
MHz  
MHz  
MHz  
μs  
CL  
10  
15  
-
4
-
-
6
-
Maximum Clock Pulse Input  
Rise or Fall time  
t , t  
5, 10, 15  
Unlimited  
r
f
4
CD4541B  
Digital Timer Application  
A positive pulse on MASTER RESET resets the counters  
and latch. The output goes high and remains high until the  
number of pulses, selected by A and B, are counted. This  
circuit is retriggerable and is as accurate as the input fre-  
quency. If additional accuracy is desired, an external clock  
can be used on pin 3. A setup time equal to the width of the  
one-shot output is required immediately following initial  
power up, during which time the output will be high.  
V
DD  
R
C
TC  
1
14  
2
3
4
5
13  
12  
11  
10  
B
A
TC  
R
AR  
MR  
S
6
7
9
8
OUTPUT  
INPUT  
t
FIGURE 3. DIGITAL TIMER APPLICATION CIRCUIT  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
PACKAGING INFORMATION  
Orderable Device  
CD4541BE  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
PDIP  
N
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4541BEE4  
PDIP  
N
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD4541BF  
CD4541BF3A  
CD4541BM  
ACTIVE  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
SOIC  
J
J
14  
14  
14  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4541BM96  
CD4541BM96E4  
CD4541BM96G4  
CD4541BME4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4541BMG4  
CD4541BMT  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4541BMTE4  
CD4541BMTG4  
CD4541BNSR  
CD4541BNSRE4  
CD4541BNSRG4  
CD4541BPW  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD4541BPWE4  
CD4541BPWG4  
CD4541BPWR  
CD4541BPWRE4  
CD4541BPWRG4  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
30-Jul-2010  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CD4541BM96  
CD4541BNSR  
CD4541BPWR  
SOIC  
SO  
D
14  
14  
14  
2500  
2000  
2000  
330.0  
330.0  
330.0  
16.4  
16.4  
12.4  
6.5  
8.2  
6.9  
9.0  
10.5  
5.6  
2.1  
2.5  
1.6  
8.0  
12.0  
8.0  
16.0  
16.0  
12.0  
Q1  
Q1  
Q1  
NS  
PW  
TSSOP  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
30-Jul-2010  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD4541BM96  
CD4541BNSR  
CD4541BPWR  
SOIC  
SO  
D
14  
14  
14  
2500  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
33.0  
29.0  
NS  
PW  
TSSOP  
Pack Materials-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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