CD4541G-P14-R [UTC]

PROGRAMMABLE TIMER; 可编程定时器


型号：	CD4541G-P14-R
厂家：	Unisonic Technologies
描述：	PROGRAMMABLE TIMER 可编程定时器
文件：	总7页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO., LTD

CD4541

CMOS IC

PROGRAMMABLE TIMER

SOP-14

DIP-14

DESCRIPTION

The CD4541 programmable timer comprise a 16-stage

binary counter, an integrated oscillator for use with an external

capacitor and two resistors, output control logic, and a special

power-on reset circuit. The counter divides the oscillator

frequency by any of 4 digitally controlled division ratios.

FEATURES

* Operates at 2ⁿfrequency divider or as single transition timer

* Increments on positive edge clock transitions

* Wide supply voltage range: 3.0V ~ 15V

* Built-in low power RC oscillator

TSSOP-14

* Oscillator frequency range ~ DC to 100 kHz

* External clock applied to Pin 3 can be used instead of

* oscillator

* Available division ratios 2⁸, 2¹⁰, 2¹³, or 2¹⁶

* High noise immunity: 0.45 V_DD(typ)

* Master reset totally independent of automatic reset operation

* Automatic reset initializes all counters when power turns on

* Q/Q select provides output logic level flexibility

* High output drive min. one TTL load

* Maximum input leakage 1μA at 15V over full temperature

* range

ORDERING INFORMATION

Ordering Number

Package

Packing

Lead Free

Halogen Free

CD4541L-D14-T

CD4541L-S14-R

CD4541L-S14-T

CD4541L-P14-R

CD4541L-P14-T

CD4541G-D14-T

CD4541G-S14-R

CD4541G-S14-T

CD4541G-P14-R

CD4541G-P14-T

DIP-14

SOP-14

Tube

Tape Reel

Tube

SOP-14

TSSOP-14

Tape Reel

Tube

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CD4541

CMOS IC

PIN CONFIGURATION

R_TC

C_TC

V_DD

R_S

N.C.

MODE

N.C.

V_SS

Q/Q SELECT

TRUTH TABLE

STATE

Auto Reset Operating

Timer Operational

Auto Reset Disabled

Master Reset On

Output Initially Low after Reset

Single Cycle Mode

Output Initially High after Reset

Recycle Mode

DIVISION RATIO TABLE

Number of Counter Stages

Count

2ⁿ

8192

1024

256

65536

BLOCK DIAGRAM

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CD4541

CMOS IC

ABSOLUTE MAXIMUM RATING

PARAMETER

SYMBOL

V_DD

RATINGS

-0.5 ~ +18

-0.5 ~ V_DD+0.5

700

UNIT

Supply Voltage

Input Voltage

V_IN

DIP-14

Power Dissipation

P_D

SOP-14/ TSSOP-14

500

℃

Junction Temperature

Operating Temperature

Storage Temperature

T_J

125

T_OPR

T_STG

-20 ~ +85

-40 ~ +150

Notes: Absolute maximum ratings are those values beyond which the device could be permanently damaged.

Absolute maximum ratings are stress ratings only and functional device operation is not implied.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

V_DD

RATINGS

3 ~ 15

UNIT

Supply Voltage

Input Voltage

V_IN

0 ~ V_DD

℃

Operating Temperature

T_OPR

-40 ~ +85

DC ELECTRICAL CHARACTERISTICS (T_A=25℃, unless otherwise specified.)

PARAMETER

SYMBOL

TEST CONDITIONS

V_DD= 5V, V_IN=V_DDor V_SS

V_DD=10V, V_IN=V_DDor V_SS

V_DD=15V, V_IN=V_DDor V_SS

V_DD=5V

MIN

TYP

0.005

0.010

0.015

MAX

UNIT

Quiescent Device Current

Low Level Output Voltage

High Level Output Voltage

Low Level Input Voltage

I_DD

μA

0.05

V_OL

V_OH

V_IL

V_DD=10V, I I_OI<1μA

V_DD=15V

V_DD=5V

4.95

9.95

V_DD=10V, I I_OI<1μA

V_DD=15V

14.95

V_DD=5V, V_O=0.5V or 4.5V

1.5

3.0

4.0

V_DD=10V, V_O=1.0V or 9.0V

V_DD=15V, V_O=1.5V or 13.5V

V_DD=5V, V_O=0.5V or 4.5V

V_DD=10V, V_O=1.0V or 9.0V

V_DD=15V, V_O=1.5V or 13.5V

V_DD=5V, V_O=0.4V

3.5

7.0

High Level Input Voltage

Low Level Output Current (Note 1)

V_IH

11.0

1.96

2.66

10.4

4.27

2.25

8.8

3.6

9.0

34.0

130

8.0

30.0

-10^-5

10^-5

I_OL

V_DD=10V, V_O=0.5V

V_DD=15V, V_O=1.5V

V_DD=5V, V_O=2.5V

High Level Output Current (Note 1)

Input Current

I_OH

V_DD=10V, V_O=9.5V

V_DD=15V, V_O=13.5V

V_DD=15V, V_IN=0V

-0.3

0.3

I_IN

μA

V_DD=15V, V_IN=15V

Notes: 1. I_OHand I_OLare tested one output at a time.

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CD4541

CMOS IC

AC ELECTRICAL CHARACTERISTICS (Note 1, T_A=25℃, C_L=50pF (refer to test circuits))

PARAMETER

SYMBOL

TEST CONDITIONS

V_DD=5V

MIN

TYP

MAX

UNIT

200

100

Output Rise Time

Output Fall Time

t_TLH

V_DD=10V

V_DD=15V

V_DD=5V

200

100

t_THL

V_DD=10V

V_DD=15V

V_DD=5V

1.8

0.6

0.4

3.2

1.5

1.0

200

100

4.0

1.5

1.0

8.0

3.0

2.0

Turn-Off, Turn-On Propagation

Delay, Clock to Q (2⁸Output)

_PLH, t_PHL

_PHL, t_PLH

t_WH(CL)

f_CL

V_DD=10V

V_DD=15V

V_DD=5V

μs

Turn-On, Turn-Off Propagation

Delay, Clock to Q (2¹⁶Output)

V_DD=10V

V_DD=15V

V_DD=5V

μs

400

200

150

Clock Pulse Width

Clock Pulse Frequency

MR Pulse Width

V_DD=10V

V_DD=15V

V_DD=5V

2.5

6.0

8.5

170

1.0

3.0

4.0

V_DD=10V

V_DD=15V

V_DD=5V

MHz

400

200

150

t_WH(R)

V_DD=10V

V_DD=15V

Any Input

(Note 2)

Average Input Capacitance

C_I

5.0

100

7.5

Power Dissipation Capacitance

C_PD

Notes: 1. AC Parameters are guaranteed by DC correlated testing.

2. C_PDdetermines the no load AC power consumption of any CMOS device.

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CD4541

CMOS IC

OPERATING CHARACTERISTICS

With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the

counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously

resetting all counter stages independent of counter state.

The RC oscillator frequency is determined by the external RC network, i.e.:

and RS ~ 2 R_TCwhere RS≧10 kΩ

The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (2⁸, 2¹⁰, 2¹³,

and 2¹⁶). The 2ⁿcounts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter.

When A is “1”, 2¹⁶is selected for both states of B.

However, when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from

the oscillator (i.e., effectively outputting 2⁸).

The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition

and Q/Q select pin is set to a “0” the Q output is a “0”. Correspondingly, when Q/Q select pin is set to a “1” the Q

output is a “1”.

When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with

mode pin “0” and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after

2^n-1counts the RS flip-flop sets which causes the output to change state. Hence, after another 2^n-1counts the output

will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset

the single cycle operation.

Oscillator Circuit Using RC Configuration

TO CLOCK

CIRCUIT

INTERNAL

RESET

C_TC

R_TC

R^S

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CD4541

CMOS IC

TEST CIRCUIT AND WAVEFORMS

Switching Time Test Circuit and Waveforms

V_DD

PULSE

GENERATOR

Q/Q SELECT

MODE

C_L

V_SS

t_WH(C_L)

20 ns

90%

50%

10%

50%

t_PLH

t_PHL

50%

t_THL

90%

50%

10%

t_TLH

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CD4541

CMOS IC

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or

other parameters) listed in products specifications of any and all UTC products described or contained

herein. UTC products are not designed for use in life support appliances, devices or systems where

malfunction of these products can be reasonably expected to result in personal injury. Reproduction in

whole or in part is prohibited without the prior written consent of the copyright owner. The information

presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice.

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