CD54AC112_14 [TI]
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS;
| 型号： | CD54AC112_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| 文件： | 总10页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
CD54AC112 . . . F PACKAGE
CD74AC112 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
1CLK
1K
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
1CLR
2CLR
2CLK
2K
1J
Balanced Propagation Delays
1PRE
1Q
±24-mA Output Drive Current
– Fanout to 15 F Devices
1Q
11 2J
SCR-Latchup-Resistant CMOS Process and
Circuit Design
10
9
2Q
2PRE
2Q
GND
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
SOIC – M
CDIP – F
Tube
Tube
CD74AC112E
CD74AC112M
CD74AC112E
–55°C to 125°C
AC112M
Tape and reel CD74AC112M96
Tube CD54AC112F3A
CD54AC112F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
†
L
L
X
H
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle
H
H
H
Q
Q
0
0
†
Output states are unpredictable if PRE and CLR go high
simultaneously after both being low at the same time.
logic diagram (positive logic)
Q
Q
PRE
CLR
K
J
CLK
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 V or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 V or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V > 0 V or V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
O
O
CC
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
recommended operating conditions (see Note 3)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
UNIT
MIN
1.5
MAX
MIN
1.5
MAX
MIN
1.5
MAX
V
V
Supply voltage
5.5
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.5 V
= 3 V
1.2
1.2
1.2
High-level input voltage
2.1
2.1
2.1
V
V
IH
= 5.5 V
= 1.5 V
= 3 V
3.85
3.85
3.85
0.3
0.9
0.3
0.9
0.3
0.9
V
IL
Low-level input voltage
= 5.5 V
1.65
1.65
1.65
V
V
Input voltage
0
0
V
V
0
0
V
0
0
V
V
V
I
CC
CC
CC
Output voltage
V
CC
V
CC
O
CC
I
I
High-level output current
Low-level output current
V
CC
V
CC
V
CC
V
CC
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
= 1.5 V to 3 V
–24
24
–24
24
–24
24
mA
mA
OH
OL
50
50
50
∆t/∆v
Input transition rise or fall rate
ns/V
= 3.6 V to 5.5 V
20
20
20
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.4
MAX
MIN
1.4
MAX
MIN
1.4
MAX
1.5 V
3 V
I
= –50 µA
2.9
2.9
2.9
OH
4.5 V
3 V
4.4
4.4
4.4
V
OH
V = V or V
I IH
I
I
I
I
= –4 mA
2.58
3.94
2.4
2.48
3.8
V
IL
OH
OH
OH
OH
= –24 mA
= –50 mA
= –75 mA
4.5 V
5.5 V
5.5 V
1.5 V
3 V
3.7
†
†
3.85
3.85
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
4.5 V
3 V
0.1
0.1
0.1
V
OL
V = V or V
I
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.5
0.44
0.44
V
I
IH
IL
OL
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
0.5
†
= 50 mA
= 75 mA
1.65
†
1.65
±1
I
I
V = V
or GND
or GND,
±0.1
4
±1
80
10
µA
µA
pF
I
I
CC
CC
V = V
I
O
= 0
40
CC
I
C
10
10
i
†
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
timing requirements over recommended operating free-air temperature range, V = 1.5 V (unless
CC
otherwise noted)
–55°C to
125°C
–40°C to
85°C
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
8
9
MHz
ns
clock
CLK high or low
CLR or PRE low
J or K
63
56
50
0
55
49
44
0
w
t
t
t
Setup time, before CLK↓
Hold time, after CLK↓
ns
ns
ns
su
J or K
h
Recovery time, before CLK↓
CLR↑ or PRE↑
31
27
rec
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted)
= 3.3 V ± 0.3 V
CC
–55°C to
125°C
–40°C to
85°C
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
71
81
MHz
ns
clock
CLK high or low
CLR or PRE low
J or K
7
6.3
5.6
0
6
5.5
4.9
0
w
t
t
t
Setup time, before CLK↓
Hold time, after CLK↓
ns
ns
ns
su
J or K
h
Recovery time, before CLK↓
CLR↑ or PRE↑
3.5
3..1
rec
timing requirements over recommended operating free-air temperature0 range, V
(unless otherwise noted)
= 5 V ± 0.5 V
CC
–55°C to
125°C
–40°C to
85°C
UNIT
MIN
MAX
100
MIN
MAX
114
f
t
Clock frequency
Pulse duration
MHz
ns
clock
CLK high or low
CLR or PRE low
J or K
5
4.5
4
4.4
3.9
3.5
0
w
t
t
t
Setup time, before CLK↓
Hold time, after CLK↓
ns
ns
ns
su
J or K
0
h
Recovery time, before CLK↓
CLR↑ or PRE↑
2.5
2.2
rec
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 1.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
f
t
8
9
MHz
ns
max
CLK
129
153
129
153
117
139
117
139
Q or Q
Q or Q
PLH
CLR or PRE
CLK
t
ns
PHL
CLR or PRE
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
71
MAX
MIN
81
3.7
MAX
f
t
MHz
ns
max
CLK
3.6
4.3
3.6
4.3
14.4
17.1
14.4
17.1
13.1
15.5
13.1
15.5
Q or Q
Q or Q
PLH
CLR or PRE
CLK
4.4
3.7
4.4
t
ns
PHL
CLR or PRE
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
100
2.6
MAX
MIN
114
2.7
MAX
f
t
MHz
ns
max
CLK
10.3
12.2
10.3
12.2
9.4
11.1
9.4
Q or Q
Q or Q
PLH
CLR or PRE
CLK
3.1
3.2
2.7
3.2
2.6
t
ns
PHL
CLR or PRE
3.1
11.1
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
56
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
TEST
S1
CC
Open
GND
S1
†
R1 = 500 Ω
t
/t
Open
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
†
L
R2 = 500 Ω
(see Note A)
t
w
V
CC
†
When V
= 1.5 V, R1 = R2 = 1 kΩ
CC
Input
50% V
50% V
CC
CC
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Reference
Input
V
CC
50% V
CC
CLR
Input
50% V
CC
0 V
0 V
t
t
h
su
t
rec
V
CC
CC
0 V
Data
Input
90%
90%
V
CC
50%
10%
50% V
10%
50% V
CC
CLK
t
t
f
0 V
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
50% V
CC
CC
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
Output
Waveform 1
90%
≈V
CC
50%
10%
50% V
10%
CC
V
50% V
20% V
CC
CC
S1 at 2 × V
(see Note B)
OL
CC
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PHZ
PZH
V
V
OH
Output
Waveform 2
S1 at GND
90%
Out-of-Phase
Output
50% V
10%
50%
10%
V
OH
CC
80% V
50% V
CC
OL
CC
t
f
t
≈0 V
r
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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