CD54AC138_14 [TI]
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CD54/74AC138, CD54/74ACT138,
CD74AC238, CD74ACT238
Data sheet acquired from Harris Semiconductor
SCHS234A
3-to-8-Line Decoders/Demultiplexers
September 1998 - Revised May 2000
Features
Description
• ’AC138, ’ACT138. . . . . . . . . . . . . . . . . . . . . . . . Inverting The ’AC138, ’ACT138, CD74AC238, and CD74ACT238 are
3-to-8-line decoders/demultiplexers that utilize Advanced
CMOS Logic technology. Both circuits have three binary
• CD74AC238, CD74ACT238 . . . . . . . . . . . Non-Inverting
select inputs (A0, A1, and A2). If the device is enabled, these
inputs determine which one of the eight normally HIGH out-
puts of the AC/ACT138 will go LOW or which on of the nor-
mally LOW outputs of the AC/ACT238 will go HIGH. Two
active LOW and one active HIGH enables (E1, E2 and E3)
are provided to simplify the cascading of these devices.
• Buffered Inputs
• Typical Propagation Delay
o
- 5ns at V
CC
= 5V, T = 25 C, C = 50pF
A L
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
[ /Title
(CD74
AC138
,
CD74
ACT13
8,
CD74
AC238
,
CD74
ACT23
8)
/Sub-
ject (3-
to-8-
Line
Decod-
ers/De
multi-
plex-
ers)
/Autho
r ()
/Key-
words
(Har-
ris
Ordering Information
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
PART
NUMBER
TEMP.
RANGE ( C)
o
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PACKAGE
CD54AC138F3A
CD74AC138E
-55 to 125
o
16 Ld CERDIP
• Balanced Propagation Delays
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
o
CD74AC138M
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
CD54ACT138F3A
CD74ACT138E
-55 to 125
o
16 Ld CERDIP
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
- Drives 50Ω Transmission Lines
o
CD74ACT138M
CD74AC238E
CD74AC238M
CD74ACT238E
CD74ACT238M
NOTES:
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
Pinout
o
0 to 70 C, -40 to 85, 16 Ld PDIP
CD54AC138, CD54ACT138
-55 to 125
(CERDIP)
CD74AC138, CD74ACT138, CD74AC238, CD74ACT238
(PDIP, SOIC)
o
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
o
TOP VIEW
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
o
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
V
A0
A1
A2
E1
E2
E3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Y0 AC/ACT138
Y0 AC/ACT238
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
Y1 AC/ACT138
Y1 AC/ACT238
Y2 AC/ACT138
Y2 AC/ACT238
Y3 AC/ACT138
Y3 AC/ACT238
Y4 AC/ACT138
Y4 AC/ACT238
Y5 AC/ACT138
Y5 AC/ACT238
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
AC/ACT138 Y7
AC/ACT238 Y7
Y6 AC/ACT138
Y6 AC/ACT238
GND
Semi-
con-
ductor,
Advan
ced
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated.
CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238
Functional Diagram
AC/ACT AC/ACT
238
138
1
2
3
15
14
13
12
11
10
9
A0
A1
A2
Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4
5
6
E1
E2
E3
7
CD74AC/ACT138 TRUTH TABLE
INPUTS
ENABLE
(NOTE 4)
ADDRESS
OUTPUTS
Y3
E
E0
H
X
L
A
A
A
0
Y0
H
H
L
Y1
H
H
H
L
Y2
H
H
H
H
L
Y4
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
L
3
2
1
X
X
X
X
H
H
H
H
H
L
L
X
L
X
L
X
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
H
L
H
H
L
H
H
L
H
H
CD74AC/ACT238 TRUTH TABLE
INPUTS
ENABLE
ADDRESS
OUTPUTS
(NOTE 4)
E
E0
A
A
A
0
Y0
L
Y1
L
Y2
L
Y3
L
Y4
L
Y5
L
Y6
L
Y7
L
3
2
1
X
H
X
L
L
L
L
L
L
L
L
X
X
X
X
L
L
X
L
X
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
H
L
L
H
L
L
L
L
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
H
NOTES:
3. H = High Level, L = Low Level, X = Don’t Care
4. E0 = E1 + E2
2
CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 7)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 5) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 6)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
5. For up to 4 outputs per device, add ±25mA for each additional output.
6. Unless otherwise specified, all voltages are referenced to ground.
7. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 8, 9)
-50
5.5
-
-
-
-
3.85
-
V
(Note 8, 9)
3
CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 8, 9)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 8, 9)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 8, 9)
3.85
-50
(Note 8, 9)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 8, 9)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 8, 9)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
8. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
9. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
A0-A2
E1, E2
E3
UNIT LOAD
0.83
1
0.42
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
An to Output
(CD54/74AC/ACT138)
t
, t
1.5
3.3
-
-
-
125
14
-
-
-
138
ns
ns
PLH PHL
4
3.9
15.4
(Note 11)
5
2.8
-
10
2.8
-
11
ns
(Note 12)
Propagation Delay,
E1, E2 to Output
(CD54/74AC/ACT138)
t
t
t
t
t
, t
1.5
3.3
5
-
3.6
2.6
-
-
114
12.7
9.1
-
3.5
2.5
-
-
125
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
-
-
-
-
10
Propagation Delay,
E3 to Output
(CD54/74AC/ACT138)
, t
PLH PHL
1.5
3.3
5
-
125
14
-
138
15.4
11
4
-
3.9
2.8
-
-
2.8
-
-
10
-
Propagation Delay,
An to Output
(CD74AC/ACT238)
, t
PLH PHL
1.5
3.3
5
-
170
19.1
13.6
135
15.2
10.7
189
21.1
15.1
10
-
187
21
5.4
3.9
-
-
5.3
3.8
-
-
-
-
15
Propagation Delay,
E1, E2 to Output
(CD74AC/ACT238)
, t
PLH PHL
1.5
3.3
5
-
-
149
16.7
11.9
208
23.2
16.6
10
4.3
3.1
-
-
4.2
3
-
-
-
Propagation Delay,
E3 to Output
(CD74AC/ACT238)
, t
PLH PHL
1.5
3.3
5
-
-
-
6
-
5.8
4.2
-
-
4.3
-
-
-
-
-
Input Capacitance
C
-
I
Power Dissipation Capacitance
C
-
-
110
-
-
110
-
PD
(Note 13)
ACT TYPES
Propagation Delay,
An to Output
(CD54/74AC/ACT138)
t
t
t
t
t
, t
5
3.1
2.7
2.8
4
-
-
-
-
-
10.9
9.5
3
-
-
-
-
-
12
ns
ns
ns
ns
ns
PLH PHL
(Note 12)
Propagation Delay,
E1, E2 to Output
(CD54/74AC/ACT138)
, t
PLH PHL
5
5
5
5
2.6
2.8
3.9
3.6
10.5
11
Propagation Delay,
E3 to Output
(CD54/74AC/ACT138)
, t
PLH PHL
10
Propagation Delay,
An to Output
(CD74AC/ACT238)
, t
PLH PHL
14.2
12.9
15.6
14.2
Propagation Delay,
E1, E2 to Output
, t
PLH PHL
3.7
(CD74AC/ACT238)
5
CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Propagation Delay,
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
CC
t
, t
5
3.5
-
12.4
3.4
-
13.6
ns
PLH PHL
E3 to Output
(CD74AC/ACT238)
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
110
110
PD
(Note 13)
NOTES:
10. Limits tested at 100%.
11. 3.3V Min at 3.6V, Max at 3V.
12. 5V Min at 5.5V, Max at 4.5V.
13. C
is used to determine the dynamic power consumption per package.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
+ C ) + V
∆I
where f = input frequency, C = output load capacitance, V
= supply voltage.
D
CC
i
PD
L
CC CC
i
L
CC
t = 3ns
f
t = 3ns
r
t = 3ns
r
t = 3ns
f
90%
V
S
INPUT
E1, E2
E3
90%
10%
V
INPUT
S
GND
GND
138 OUTPUT
138 OUTPUT
V
S
V
S
t
t
PHL
PLH
t
t
PLH
PHL
V
S
V
S
238 OUTPUT
238 OUTPUT
t
PLH
t
PHL
t
t
PLH
PHL
FIGURE 1. PROPAGATION DELAY TIMES
FIGURE 2. PROPAGATION DELAY TIMES
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 3. PROPAGATION DELAY TIMES
6
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Customers are responsible for their applications using TI components.
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