CD54ACT112_08 [TI]

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET; 双JK负边沿触发触发器具有清零和预设
CD54ACT112_08
型号: CD54ACT112_08
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
双JK负边沿触发触发器具有清零和预设

触发器
文件: 总13页 (文件大小:546K)
中文:  中文翻译
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CD54ACT112, CD74ACT112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS323 – JANUARY 2003  
CD54ACT112 . . . F PACKAGE  
CD74ACT112 . . . M PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
Balanced Propagation Delays  
1CLR  
2CLR  
2CLK  
2K  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
1J  
1PRE  
1Q  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
1Q  
11 2J  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
10  
9
2Q  
2PRE  
2Q  
GND  
description/ordering information  
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset  
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE  
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to  
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and  
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs  
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle  
flip-flops by tying J and K high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
Tube  
CD74ACT112M  
SOIC – M  
CDIP – F  
ACT112M  
CD54ACT112F3A  
–55°C to 125°C  
Tape and reel CD74ACT112M96  
Tube CD54ACT112F3A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
L
L
X
H
H
H
H
Q
Q
0
0
H
H
H
L
L
H
L
H
H
H
H
X
L
H
H
H
H
X
Toggle  
H
H
H
Q
Q
0
0
Output states are unpredictable if PRE and CLR go high  
simultaneously after both being low at the same time.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CD54ACT112, CD74ACT112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS323 JANUARY 2003  
logic diagram (positive logic)  
Q
Q
PRE  
CLR  
K
J
CLK  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V  
CC  
I
Input clamp current, I (V < 0 V or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
IK  
I
CC  
Output clamp current, I  
(V < 0 V or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
OK  
O O CC  
Continuous output current, I (V > 0 V or V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
Continuous current through V  
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W  
Storage temperature range, T  
O
O
CC  
O
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA  
JA  
stg  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 3)  
55°C to  
125°C  
40°C to  
85°C  
T
A
= 25°C  
UNIT  
MIN  
4.5  
2
MAX  
MIN  
4.5  
2
MAX  
MIN  
MAX  
V
V
V
V
V
Supply voltage  
5.5  
5.5  
4.5  
2
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
0.8  
0.8  
V
0
0
V
V
0
0
V
V
0
0
V
V
V
I
CC  
CC  
CC  
Output voltage  
V
O
CC  
CC  
CC  
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
24  
24  
24  
24  
24  
24  
mA  
mA  
ns/V  
OH  
OL  
I
t/v  
10  
10  
10  
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CD54ACT112, CD74ACT112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS323 JANUARY 2003  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
55°C to  
125°C  
40°C to  
85°C  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
CC  
UNIT  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
I
I
I
I
I
I
I
I
= 50 µA  
= 24 mA  
= 50 mA  
= 75 mA  
= 50 µA  
4.5 V  
4.5 V  
5.5 V  
5.5 V  
4.5 V  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
3.94  
3.7  
3.8  
V
V
V = V or V  
IH  
V
OH  
I
IL  
3.85  
3.85  
0.1  
0.1  
0.5  
0.1  
= 24 mA  
0.36  
0.44  
V = V or V  
V
OL  
I
IH  
IL  
= 50 mA  
= 75 mA  
1.65  
1.65  
±1  
I
I
V = V  
or GND  
or GND,  
±0.1  
±1  
µA  
µA  
I
I
CC  
CC  
V = V  
I
I
O
= 0  
4
80  
40  
CC  
4.5 V to  
5.5 V  
V = V  
I
2.1 V  
2.4  
3
2.8  
mA  
I
CC  
CC  
C
10  
10  
10  
pF  
i
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize  
power dissipation. Test verifies a minimum 50-transmission-line drive capability at 85°C and 75-transmission-line drive capability at 125°C.  
ACT INPUT LOAD TABLE  
INPUT  
J or CLK  
K
UNIT LOAD  
1
0.53  
CLR or PRE  
0.58  
Unit Load is I  
electrical characteristics table  
limit specified in  
CC  
(e.g., 2.4 mA at 25°C).  
timing requirements over recommended operating conditions (unless otherwise noted)  
55°C to  
125°C  
40°C to  
85°C  
UNIT  
MIN  
MAX  
100  
MIN  
MAX  
114  
f
t
Clock frequency  
Pulse duration  
MHz  
ns  
clock  
CLK high or low  
CLR or PRE low  
J or K  
5
5.5  
4
4.4  
4.8  
3.5  
1
w
t
t
t
Setup time, before CLK↓  
Hold time, after CLK↓  
ns  
ns  
ns  
su  
J or K  
1
h
Recovery time, before CLK↓  
CLRor PRE↑  
2.5  
2.2  
rec  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CD54ACT112, CD74ACT112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS323 JANUARY 2003  
switching characteristics over recommended operating free-air temperature range,  
V
= 5 V ± 0.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)  
CC  
L
55°C to  
125°C  
40°C to  
85°C  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
100  
2.6  
MAX  
MIN  
114  
2.7  
MAX  
f
t
MHz  
ns  
max  
CLK  
10.3  
12.2  
10.3  
12.2  
9.4  
11.1  
9.4  
Q or Q  
Q or Q  
PLH  
CLR or PRE  
CLK  
3.1  
3.2  
2.6  
2.7  
t
ns  
PHL  
CLR or PRE  
3.1  
3.2  
11.1  
operating characteristics, V  
= 5 V, T = 25°C  
CC  
A
PARAMETER  
TYP  
UNIT  
C
Power dissipation capacitance  
56  
pF  
pd  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
CD54ACT112, CD74ACT112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCHS323 JANUARY 2003  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
Open  
GND  
TEST  
S1  
S1  
t
t
/t  
Open  
R1 = 500 Ω  
R2 = 500 Ω  
PLH PHL  
From Output  
Under Test  
t
/t  
2 × V  
CC  
GND  
PLZ PZL  
/t  
PHZ PZH  
C
= 50 pF  
L
(see Note A)  
t
w
3 V  
0 V  
1.5 V  
1.5 V  
Input  
LOAD CIRCUIT  
VOLTAGE WAVEFORMS  
PULSE DURATION  
3 V  
Reference  
Input  
3 V  
0 V  
1.5 V  
CLR  
Input  
1.5 V  
0 V  
t
t
h
su  
t
rec  
3 V  
0 V  
Data  
Input  
90%  
t
90%  
3 V  
0 V  
1.5 V  
10%  
1.5 V  
10%  
1.5 V  
CLK  
t
r
f
VOLTAGE WAVEFORMS  
RECOVERY TIME  
VOLTAGE WAVEFORMS  
SETUP AND HOLD AND INPUT RISE AND FALL TIMES  
3 V  
0 V  
3 V  
Input  
1.5 V  
1.5 V  
Output  
Control  
1.5 V  
1.5 V  
0 V  
t
t
PLH  
PHL  
90%  
t
t
PLZ  
PZL  
V
OH  
Output  
Waveform 1  
In-Phase  
Output  
90%  
t
V  
CC  
50%  
10%  
50% V  
10%  
CC  
V
20% V  
20% V  
CC  
S1 at 2 × V  
(see Note B)  
CC  
OL  
CC  
t
f
r
V
OL  
t
t
PLH  
PHL  
90%  
t
t
PHZ  
PZH  
V
V
OH  
90%  
Output  
Waveform 2  
S1 at GND  
Out-of-Phase  
Output  
50% V  
10%  
50%  
10%  
CC  
V
OH  
80% V  
80% V  
CC  
CC  
OL  
t
t
r
f
0 V  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES  
VOLTAGE WAVEFORMS  
OUTPUT ENABLE AND DISABLE TIMES  
NOTES: A.  
C includes probe and test-fixture capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t = 3 ns, t = 3 ns.  
O
r
f
Phase relationships between waveforms are arbitrary.  
D. For clock inputs, f is measured with the input duty cycle at 50%.  
max  
E. The outputs are measured one at a time with one input transition per measurement.  
F.  
G.  
H.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
pd  
PLH  
PZL  
PLZ  
PHL  
PZH  
PHZ  
are the same as t  
are the same as t  
.
en  
dis  
.
I. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
SOIC  
Drawing  
CD54ACT112F3A  
CD74ACT112M  
ACTIVE  
ACTIVE  
J
16  
16  
1
TBD  
A42 SNPB  
N / A for Pkg Type  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74ACT112M96  
CD74ACT112M96E4  
CD74ACT112M96G4  
CD74ACT112ME4  
CD74ACT112MG4  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
D
D
D
D
D
16  
16  
16  
16  
16  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
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for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Mar-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
CD74ACT112M96  
SOIC  
D
16  
2500  
330.0  
16.4  
6.5  
10.3  
2.1  
8.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-Mar-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
333.2 345.9 28.6  
CD74ACT112M96  
D
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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