CD54ACT191 [TI]
Presettable Synchronous 4-Bit Binary Up/Down Counter; 可预置同步4位二进制加/减计数器
| 型号： | CD54ACT191 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Presettable Synchronous 4-Bit Binary Up/Down Counter |
| 文件： | 总11页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54AC191,
CD54ACT191
Data sheet acquired from Harris Semiconductor
SCHS243A
Presettable Synchronous 4-Bit Binary
Up/Down Counter
October 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The CD54AC191 and CD54ACT191 are asynchronously
presettable binary up/down synchronous counters that utilize
Advanced CMOS Logic technology. Presetting the counter to
the number on preset data inputs (P0-P3) is accomplished
by setting LOW the asynchronous parallel load input (PL).
Counting occurs when PL is HIGH, Count Enable (CE) is
LOW, and the Up/Down (U/D) input is either LOW for up-
counting or HIGH for down-counting. The counter is incre-
mented or decremented synchronously with the LOW-to-
HIGH transition of the clock.
• Typical Propagation Delay
o
- 12.8ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
When an overflow or underflow of the counter occurs, the
Terminal Count (TC) output, which is LOW during counting,
goes HIGH and remains HIGH for one clock cycle. This out-
put can be used for look-ahead carry in high-speed cascad-
ing (see Figure 12). The TC output also initiates the Ripple
Clock (RC) output which, normally HIGH, goes LOW and
remains LOW for the low-level cascaded using the Ripple
Count output.
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Ordering Information
Pinout
PART
NUMBER
TEMP.
CD54AC191, CD54ACT191
(CERDIP)
o
RANGE ( C)
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
TOP VIEW
CD54AC191F3A
CD54ACT191F3A
NOTES:
P1
Q1
1
2
3
4
5
6
7
8
16 V
CC
15 P0
14 CP
13 RC
12 TC
11 PL
10 P2
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
Q0
CE
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
U/D
Q2
Q3
9
P3
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD54AC191, CD54ACT191
Functional Diagram
BINARY
PRESET
P0 P1 P2 P3
15
1
10
9
ASYN. PARALLEL
LOAD ENABLE
11
14
5
3
2
6
7
Q0
Q1
BINARY
OUTPUTS
CLOCK
Q2
Q3
UP/DOWN
12 TERMINAL
COUNT
4
13
COUNT
ENABLE
RIPPLE CLOCK
TRUTH TABLE
INPUTS
U/D
PL
H
CE
L
CP
↑
FUNCTION
Count Up
L
H
L
H
X
X
↑
Count Down
L
X
X
Asynchronous Preset
No Change
H
H
X
U/D or CE should be changed only when clock is high.
X = Don’t Care
↑ = Low-to-High clock transition.
2
CD54AC191, CD54ACT191
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
___
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD54AC191, CD54ACT191
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
UNIT LOAD
0.75
P0-P3, PL
CL, U/D, CE
0.85
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD54AC191, CD54ACT191
Prerequisite For Switching Function
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
UNITS
CC
AC TYPES
Max. Frequency
f
1.5
3.3
5.5
49
-
-
4.8
43
-
-
MHz
MHz
MAX
(Note 10)
(Note 8)
5
68
-
60
-
MHz
(Note 9)
CP Pulse Width
t
t
1.5
3.3
5
91
10.5
7.3
66
7.4
5.3
71
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
104
11.6
8.3
75
8.4
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
PL Pulse Width
1.5
3.3
5
W
Recovery Time
t
1.5
3.3
5
81
9.1
6.5
50
5.6
4
REC
5.7
44
4.9
3.5
115
12.9
9.2
132
14.7
10.5
22
2.5
2
Set-Up Time, Pn to PL
Set-Up Time, CE to CP
Set-Up Time, U/D to CP
Hold Time, Pn to PL
Hold Time, CE to CP
Hold Time, U/D to CP
t
t
t
1.5
3.3
5
SU
SU
SU
1.5
3.3
5
131
14.7
10.5
150
16.8
12
25
2.8
2
1.5
3.3
5
t
t
t
1.5
3.3
5
H
H
H
1.5
3.3
5
0
0
0
0
0
0
1.5
3.3
5
0
0
0
0
0
0
ACT TYPES
Max. Frequency
f
5
68
-
60
-
MHz
MAX
(Note 10)
(Note 9)
CP Pulse Width
PL Pulse Width
t
t
5
5
5
5
7.3
5.3
5.7
3.5
-
-
-
-
8.3
6
-
-
-
-
ns
ns
ns
ns
W
W
Recovery Time
t
6.5
4
REC
Set-Up Time, Pn to PL
t
SU
5
CD54AC191, CD54ACT191
Prerequisite For Switching Function (Continued)
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Set-Up Time, CE to CP
SYMBOL
V
(V)
MIN
9.2
10.5
2
MAX
MIN
10.5
12
2
MAX
UNITS
ns
CC
t
t
5
-
-
-
-
-
-
-
-
-
-
SU
Set-Up Time, U/D to CP
Hold Time, Pn to PL
Hold Time, CE to CP
Hold Time, U/D to CP
5
5
5
5
ns
SU
t
t
t
ns
H
H
H
0
0
ns
0
0
ns
NOTES:
8. 3.3V Min is at 3V.
9. 5V Min is at 4.5V.
10. Applies to non-cascaded operation only. With cascaded counters clock-to-terminal count propagation delays, count enable (CE)-to-clock
o
set-up times, and count enable (CE)-to-clock hold times determine max clock frequency. For example, with these AC devices at 85 C
and V
= 5V:.
CC
1
1
------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------
≈ 36MHz
f
(CP)=
=
MAX
CP-to-TC prop. delay + CE-to-CP setup + CE-to-CP Hold 18.2 + 9.2 + 0
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay
PL to Qn
t
, t
1.5
3.3
-
-
-
171
-
-
-
188
21
ns
ns
PLH PHL
5.4
19.1
5.3
(Note 12)
5
3.9
-
13.6
3.8
-
15
ns
(Note 13)
Propagation Delay
Pn to Qn
t
t
t
t
t
t
, t
1.5
3.3
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
173
19.4
13.8
182
20.4
14.5
136
15.3
11
-
5.3
3.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
190
21.3
15.2
200
22.4
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
5.4
3.9
-
Propagation Delay
CP to Qn
, t
PLH PHL
1.5
3.3
5
5.8
4.1
-
5.6
4
Propagation Delay
CP to RC
, t
PLH PHL
1.5
3.3
5
-
150
16.8
12
4.3
3.1
-
4.2
3
Propagation Delay
CP to TC
, t
PLH PHL
1.5
3.3
5
227
25.5
18.2
246
27.6
19.7
160
17.9
12.8
-
250
28
7.2
5.2
-
7
5
20
Propagation Delay
U/D to RC
, t
PLH PHL
1.5
3.3
5
-
271
30.4
21.7
176
19.7
14.1
7.8
5.6
-
7.6
5.4
-
Propagation Delay
U/D to TC
, t
PLH PHL
1.5
3.3
5
5.1
3.6
4.9
3.5
6
CD54AC191, CD54ACT191
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Propagation Delay
SYMBOL
, t
V
(V)
MIN
TYP
MAX
137
15.4
11
MIN
TYP
MAX
UNITS
ns
CC
t
1.5
3.3
5
-
4.4
3.1
-
-
-
-
4.2
3
-
-
151
16.9
12.1
10
PLH PHL
CE to RC
ns
-
-
ns
Input Capacitance
C
-
-
10
-
-
pF
I
Power Dissipation Capacitance
C
-
-
96
-
-
96
-
pF
PD
(Note 14)
ACT TYPES
Propagation Delay
PL to Qn
t
t
t
t
t
t
t
t
, t
5
4.2
3.9
4.1
3.1
5.2
5.6
3.8
3.3
-
-
-
-
-
-
-
-
14.8
13.8
14.5
10.9
18.2
19.7
13.5
11.5
4.1
3.8
4
-
-
-
-
-
-
-
-
16.3
15.2
16
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
(Note 13)
Propagation Delay
Pn to Qn
, t
PLH PHL
5
Propagation Delay
CP to Qn
, t
PLH PHL
5
5
5
5
5
5
Propagation Delay
CP to RC
, t
PLH PHL
3
12
Propagation Delay
CP to TC
, t
PLH PHL
5
20
Propagation Delay
U/D to RC
, t
PLH PHL
5.4
3.7
3.2
21.7
14.9
12.7
Propagation Delay
U/D to TC
, t
PLH PHL
Propagation Delay
CE to RC
, t
PLH PHL
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
96
96
PD
(Note 14)
NOTES:
11. Limits tested 100%.
12. 3.3V Min is at 3.6V, Max is at 3V.
13. 5V Min is at 5.5V, Max is at 4.5V
14. C
P
is used to determine the dynamic power consumption per package.
PD
= C
2
V
f + (C + V 2 f ) where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage.
CC
D
PD CC
i
L
CC
o
i
o
L
1/f
MAX
INPUT LEVEL
INPUT LEVEL
t
CP OR CE
RC
W
V
V
S
S
t
CP
V
V
S
S
PLH
t
PHL
t
PLH
t
PHL
Qn OR TC
V
V
S
S
V
V
S
S
FIGURE 1.
FIGURE 2.
7
CD54AC191, CD54ACT191
INPUT LEVEL
Pn
INPUT LEVEL
t
Pn
Qn
W
V
S
t
V
S
INPUT LEVEL
V
t
V
S
PL
Qn
S
PHL
PLH
V
S
t
t
V
S
PLH
PHL
V
V
S
S
FIGURE 3.
FIGURE 4.
INPUT LEVEL
t (L)
V
Pn
PL
Qn
V
S
S
t (H)
H
H
t
(L)
t
(H)
INPUT LEVEL
INPUT LEVEL
SU
SU
INPUT LEVEL
PL
V
S
V
V
S
S
t
W
t
REC
CP
Qn
The shaded areas indicate when the input is permitted to change for
predictable output performance.
FIGURE 5.
FIGURE 6.
INPUT LEVEL
INPUT
U/D
V
V
S
S
V
V
V
S
CP
CE
S
S
LEVEL
t
t
(L)
t
PLH
t
(H)
SU
PHL
SU
t (L)
H
V
V
INPUT
LEVEL
TC
RC
CE MAY
CHANGE
CE MAY
CHANGE
S
S
V
S
t
t
PLH
PHL
(H-L)
ONLY
V
V
S
S
FIGURE 7.
FIGURE 8.
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 9. PROPAGATION DELAY TIMES
8
CD54AC191, CD54ACT191
LOAD
P0
P1
P2
P3
H
L
PRESET
INPUTS
H
H
CLOCK
L
L
DOWN/UP
ENABLE
H
L
Q0
H
Q1
Q2
H
L
Q3
TERMINAL COUNT
RIPPLE CLOCK
H
L
13 14 15
0
1 2
2
2
1
0
15 14 13
COUNT UP INHIBIT
COUNT DOWN
LOAD
Sequence:
1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen, zero, one, and two.
3. Inhibit.
4. Count down to one, zero, fifteen, fourteen, and thirteen.
FIGURE 10. CD54AC191 DECODE COUNTERS TYPICAL LOAD, COUNT, AND INHIBIT SEQUENCES
DIRECTION
CONTROL
ENABLE
U/D
CE
CP
U/D
CE
CP
U/D
CE
CP
TC
TC
TC
CLOCK
FIGURE 11. SYNCHRONOUS N-STAGE COUNTER WITH PARALLEL GATED TC/RC
DIRECTION
CONTROL
U/D
CE
CP
RC
U/D
CE
CP
U/D
CE
CP
RC
RC
ENABLE
CLOCK
FIGURE 12. SYNCHRONOUS N-STAGE COUNTER USING RIPPLE TC/RC
9
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