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CD54HC138F3A [TI]

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting; 高速CMOS逻辑3至8线路解码器/多路解复用器反相和同相
CD54HC138F3A
型号： CD54HC138F3A
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting
高速CMOS逻辑3至8线路解码器/多路解复用器反相和同相

解码器 驱动器 解复用器 逻辑集成电路 输入元件
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CD54/74HC138, CD54/74HCT138,  
CD54/74HC238, CD54/74HCT238  
Data sheet acquired from Harris Semiconductor  
SCHS147I  
High-Speed CMOS Logic 3- to 8-Line Decoder/  
Demultiplexer Inverting and Noninverting  
October 1997 - Revised August 2004  
Features  
Ordering Information  
• Select One Of Eight Data Outputs  
Active Low for 138, Active High for 238  
TEMP. RANGE  
o
PART NUMBER  
CD54HC138F3A  
CD54HC238F3A  
CD54HCT138F3A  
CD54HCT238F3A  
CD74HC138E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
[ /Title  
(CD74  
HC138  
,
CD74  
HCT13  
8,  
CD74  
HC238  
,
CD74  
HCT23  
8)  
• l/O Port or Memory Selector  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Three Enable Inputs to Simplify Cascading  
• Typical Propagation Delay of 13 ns at V  
CC  
= 5 V,  
o
C = 15 pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
CD74HC138M  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74HC138MT  
CD74HC138M96  
CD74HC238E  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
• HC Types  
CD74HC238M  
/Sub-  
ject  
(High  
Speed  
- 2 V to 6 V Operation  
CD74HC238MT  
CD74HC238M96  
CD74HC238NSR  
CD74HC238PW  
CD74HC238PWR  
CD74HC238PWT  
CD74HCT138E  
CD74HCT138M  
CD74HCT138MT  
CD74HCT138M96  
CD74HCT238E  
CD74HCT238M  
CD74HCT238M96  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5 V  
CC  
• HCT Types  
- 4.5-V to 5.5-V Operation  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8 V (Max), V = 2 V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Description  
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed  
silicon-gate CMOS decoders well suited to memory address  
decoding or data-routing applications. Both circuits feature  
low power consumption usually associated with CMOS  
circuitry, yet have speeds comparable to low-power Schottky  
TTL logic. Both circuits have three binary select inputs (A0,  
A1, and A2). If the device is enabled, these inputs determine  
which one of the eight normally high outputs of the  
HC/HCT138 series go low or which of the normally low  
outputs of the HC/HCT238 series go high.  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Two active low and one active high enables (E1, E2, and E3)  
are provided to ease the cascading of decoders. The  
decoder’s eight outputs can drive ten low-power Schottky  
TTL equivalent loads.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
1
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238  
Functional Diagram  
Pinout  
HC/HCT HC/HCT  
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238  
238  
138  
(CERDIP)  
CD74HC138, CD74HCT138, CD74HCT238  
(PDIP, SOIC)  
1
2
3
15  
14  
13  
12  
11  
10  
9
A0  
A1  
A2  
Y0  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
CD74HC238  
(PDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
A0  
A1  
1
2
3
4
5
6
7
8
16 V  
CC  
4
5
6
E1  
E2  
E3  
15 Y0 (Y0)  
14 Y1 (Y1)  
13 Y2 (Y2)  
12 Y3 (Y3)  
11 Y4 (Y4)  
10 Y5 (Y5)  
A2  
E1  
E2  
7
E3  
(Y7) Y7  
GND  
9
Y6 (Y6)  
Signal names in parentheses are for ’HC138 and ’HCT138.  
TRUTH TABLE ’HC138, ’HCT138  
INPUTS  
ENABLE  
ADDRESS  
OUTPUTS  
Y3 Y4  
E3  
X
E2  
X
X
H
L
E1  
A2  
X
X
X
L
A1  
X
X
X
L
A0  
X
X
X
L
Y0  
H
H
H
L
Y1  
H
H
H
H
L
Y2  
H
H
H
H
H
L
Y5  
H
H
H
H
H
H
H
H
L
Y6  
Y7  
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
X
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
TRUTH TABLE ’HC238, ’HCT238  
INPUTS  
ENABLE  
ADDRESS  
OUTPUTS  
Y3 Y4  
E3  
X
E2  
X
X
H
L
E1  
A2  
X
X
X
L
A1  
X
X
X
L
A0  
X
X
X
L
Y0  
L
Y1  
L
Y2  
L
Y5  
L
Y6  
L
Y7  
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
L
L
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
2
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
3
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HCT TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
-
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE:  
2. For dual-supply systems, theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
UNIT LOADS  
A0-A2  
E1, E2  
1.5  
1.25  
1
E3  
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
Switching Specifications Input t , t = 6ns  
r
f
o
-40 C TO  
85 C  
o
o
o
o
25 C  
-55 C TO 125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HC TYPES  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
Propagation Delay  
Address to Output  
t
t
C = 50pF  
2
-
-
-
150  
30  
-
-
-
-
-
190  
38  
-
-
-
-
-
225  
45  
-
ns  
ns  
ns  
ns  
PLH, PHL  
L
4.5  
5
-
-
-
C = 15pF  
13  
-
L
C = 50pF  
6
26  
33  
38  
L
4
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
-40 C TO  
85 C  
o
o
o
o
25 C  
-55 C TO 125 C  
TEST  
PARAMETER  
SYMBOL CONDITIONS  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
Enable to Output  
HC/HCT138  
t
t
C = 50pF  
2
-
-
-
150  
30  
26  
75  
15  
13  
-
-
-
-
-
-
-
-
190  
38  
33  
95  
19  
16  
-
-
-
-
-
-
-
-
265  
53  
45  
110  
22  
19  
-
ns  
ns  
ns  
ns  
ns  
ns  
pF  
PLH, PHL  
L
4.5  
6
-
-
-
-
-
-
-
Output Transition Time  
(Figure 1)  
t
, t  
TLH THL  
C = 50pF  
2
-
L
4.5  
6
-
-
Power Dissipation  
C
C = 15pF  
L
5
67  
PD  
Capacitance (Notes 3, 4)  
Input Capacitance  
C
-
-
-
-
10  
-
10  
-
10  
pF  
IN  
HCT TYPES  
Propagation Delay  
Address to Output  
t
, t  
PLH PHL  
C = 50pF  
4.5  
5
-
-
-
-
14  
-
35  
-
-
-
-
44  
-
-
-
-
53  
-
ns  
ns  
ns  
L
C = 15pF  
L
Enable to Output  
HC/HCT138  
t
, t  
PLH PHL  
C = 50pF  
4.5  
35  
44  
53  
L
Enable to Output  
HC/HCT238  
t
t
C = 15pF  
4.5  
4.5  
5
-
-
-
-
-
-
40  
15  
-
-
-
-
-
50  
19  
-
-
-
-
-
60  
22  
-
ns  
ns  
pF  
pF  
PLH, PHL  
L
Output Transition Time  
(Figure 2)  
t
, t C = 50pF  
TLH THL L  
Power Dissipation  
Capacitance (Notes 3, 4)  
C
C = 15pF  
L
67  
-
PD  
Input Capacitance  
NOTES:  
C
-
-
10  
10  
10  
IN  
3. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
t = 6ns  
f
r
t = 6ns  
f
t = 6ns  
r
V
CC  
3V  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
TLH  
THL  
t
t
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
t
t
PLH  
PLH  
PHL  
PHL  
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8688401EA  
CD54HC138F  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
J
J
J
J
J
N
16  
16  
16  
16  
16  
16  
16  
16  
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
CD54HC138F3A  
CD54HC238F3A  
CD54HCT138F  
CD54HCT138F3A  
CD54HCT238F3A  
CD74HC138E  
1
1
1
1
1
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC138EE4  
CD74HC138M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
N
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC138M96  
CD74HC138M96E4  
CD74HC138ME4  
CD74HC138MT  
CD74HC138MTE4  
CD74HC238E  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC238EE4  
CD74HC238M  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC238M96  
CD74HC238M96E4  
CD74HC238ME4  
CD74HC238MT  
CD74HC238MTE4  
CD74HC238NSR  
CD74HC238NSRE4  
CD74HC238PW  
CD74HC238PWE4  
CD74HC238PWR  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
no Sb/Br)  
CD74HC238PWRE4  
CD74HC238PWT  
CD74HC238PWTE4  
CD74HCT138E  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
PDIP  
PW  
PW  
PW  
N
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HCT138EE4  
CD74HCT138M  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT138M96  
CD74HCT138M96E4  
CD74HCT138ME4  
CD74HCT138MT  
CD74HCT138MTE4  
CD74HCT238E  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HCT238EE4  
CD74HCT238M  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HCT238M96  
CD74HCT238M96E4  
CD74HCT238ME4  
CD74HCT238PW  
CD74HCT238PWE4  
CD74HCT238PWR  
CD74HCT238PWRE4  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
PW  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 3  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  

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