CD54HC191H [TI]

HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE;


型号：	CD54HC191H
厂家：	TEXAS INSTRUMENTS
描述：	HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE
文件：	总32页 (文件大小：1019K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

CD54HC190, 191; CD54HCT191 . . . F PACKAGE

CD74HC190 . . . E, NS, OR PW PACKAGE

CD74HC191, CD74HCT191 . . . E OR M PACKAGE

(TOP VIEW)

2-V to 6-V V

Operation (’HC190, 191)

4.5-V to 5.5-V V

Operation (’HCT191)

Wide Operating Temperature Range of

−55°C to 125°C

Synchronous Counting and Asynchronous

CLK

RCO

MAX/MIN

LOAD

Two Outputs for n-Bit Cascading

CTEN

D/U

Look-Ahead Carry for High-Speed Counting

Balanced Propagation Delays and

Transition Times

GND

Standard Outputs Drive Up To 15 LS-TTL

Loads

Significant Power Reduction Compared to

LS-TTL Logic ICs

description/ordering information

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and

CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous

parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up

(D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented

synchronously with the low-to-high transition of the clock.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

CD74HC190E

CD74HC191E

CD74HCT191E

CD74HC191E

PDIP − E

SOIC − M

Tube of 25

CD74HCT191E

CD74HC191M

Tube of 40

Reel of 2500

Reel of 250

Tube of 40

Reel of 2000

Tube of 90

Reel of 2000

Reel of 250

CD74HC191M96

CD74HC191MT

CD74HCT191M

CD74HC190NSR

CD74HC190PW

CD74HC190PWR

CD74HC190PWT

CD54HC190F3A

CD54HC191F3A

HC191M

HCT191M

HC190M

−55°C to 125°C

SOP − NS

TSSOP − PW

HJ190

CD54HC190F3A

CD54HC191F3A

CD54HCT191F3A

CDIP − F

Tube of 25

CD54HCT191F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢏ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢖꢕ ꢗꢯ ꢑꢎ ꢰ ꢯꢱꢲꢂ ꢱꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ

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ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

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ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢏ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

description/ordering information (continued)

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes

high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading

(see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes

low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO

(see Figure 2).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to

the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

FUNCTION TABLE

INPUTS

FUNCTION

CTEN

D/U

CLK

LOAD

Count up

Count down

Asynchronous preset

No change

D/U or CTEN should be changed only when clock is high.

X = Don’t care

Low-to-high clock transition

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190 logic diagram

CLK

D/U

LOAD

DATA

LOAD

DATA

CLKQ

FF0

CLKQ

FF1

CTEN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190 logic diagram (continued)

RCO

MAX/MIN

LOAD

DATA

CLKQ

FF2

CLKQ

FF3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC191, ’HCT191 logic diagram

CLK

D/U

LOAD

DATA

LOAD

DATA

LOAD

DATA

CLKQ

CLK Q

FF0

CLKQ

FF1

FF2

CTEN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC191, ’HCT191 logic diagram (continued)

RCO

MAX/MIN

LOAD

DATA

CLK

FF3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190 and ’HC191/HCT191 flip-flop

DATA

LOAD

CLK

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

typical load, count, and inhibit sequence for ’HC190

The following sequence is illustrated below:

1. Load (preset) to BCD 7

2. Count up to 8, 9 (maximum), 0, 1, and 2

3. Inhibit

4. Count down to 1, 0 (minimum), 9, 8, and 7

Parallel Load

Preset

Input

Data

Clock

Down/Up

Clock Enable

Terminal Count

Ripple Clock

Count Up

Inhibit

Count Down

Load

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁꢂ ꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ ꢈ ꢀꢁꢉ ꢃꢄ ꢀꢊ ꢅꢆ

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SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

typical load, count, and inhibit sequence for ’HC191 and ’HCT191

The following sequence is illustrated below:

1. Load (preset) to binary 13

2. Count up to 14, 15 (maximum), 0, 1, and 2

3. Inhibit

4. Count down to 1, 0 (minimum), 15, 14, and 13

LOAD

Data

Inputs

CLK

D/U

CTEN

Data

Outputs

MAX/MIN

RCO

Count Up

Inhibit

Count Down

Load

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

Direction

Control

Enable

D/U

Clock

Figure 1. ’HC190 Synchronous n-Stage Counter With Parallel Gated Terminal Count

Direction

Control

D/U

Enable

Clock

Figure 2. ’HC191, ’HCT191 Synchronous n-Stage Counter With Parallel Gated Terminal Count

Count Down

Count Up

NOTE: Illegal states in BCD counters corrected in one count

NOTE: Illegal states in BCD counters corrected in one or two counts

Figure 3. ’HC190 State Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢈ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢀ

ꢊ

ꢅ

ꢆ

ꢅ

ꢈ

ꢀ

ꢁ

ꢉ

ꢃ

ꢄ

ꢀ

ꢊ

ꢅ

ꢆ

ꢋ

ꢌꢍ

ꢀ

ꢄ

ꢎ

ꢏ

ꢍ

ꢏ

ꢐ

ꢋ

ꢐꢑ

ꢒ

ꢁ

ꢏ

ꢓ

ꢍ

ꢀꢏ

ꢐ

ꢍ

ꢊ

ꢔ

ꢎ

ꢋ

ꢓ

ꢕ

ꢊ

ꢄ

ꢁ

ꢏ

ꢓ

ꢍ

ꢒ

ꢐ

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ꢖ

ꢏ

ꢁ

ꢔ

ꢀ

ꢏ

ꢍ

ꢊ

ꢎ

ꢏ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

O O CC

Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA

Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions for ’HC190 and ’HC191 (see Note 3)

= −55°C

T = −40°C

TO 85°C

= 25°C

TO 125°C

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Supply voltage

= 2 V

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

= 4.5 V

= 6 V

High-level input voltage

= 2 V

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

= 4.5 V

= 6 V

Low-level input voltage

Input voltage

Output voltage

= 2 V

1000

500

1000

500

1000

500

Input transition (rise and fall) time

= 4.5 V

= 6 V

400

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

recommended operating conditions for ’HCT191 (see Note 4)

= −55°C

T = −40°C

TO 85°C

= 25°C

TO 125°C

UNIT

MIN

4.5

MAX

MIN

4.5

MAX

MIN

4.5

MAX

Supply voltage

5.5

High-level input voltage

Low-level input voltage

Input voltage

0.8

Output voltage

Input transition (rise and fall) time

500

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190, ’HC191

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= −55°C

T = −40°C

TO 85°C

= 25°C

TO 125°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

1.9

MAX

MIN

1.9

4.4

5.9

3.7

5.2

MAX

MIN

1.9

MAX

2 V

4.5 V

6 V

4.4

= −20 µA

5.9

V = V or V

= −4 mA

4.5 V

6 V

3.98

5.48

3.84

5.34

= −5.2 mA

2 V

0.1

0.26

0.1

0.4

0.1

0.33

4.5 V

6 V

= 20 µA

V = V or V

= 4 mA

4.5 V

6 V

= 5.2 mA

V = V

or 0

6 V

µA

V = V

or 0,

= 0

6 V

160

’HCT191

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

= −55°C

T = −40°C

TO 85°C

= 25°C

TO 125°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

4.4

TYP

MAX

MIN

4.4

MAX

MIN

4.4

MAX

= −20 µA

= −4 mA

= 20 µA

= 4 mA

V = V or V

4.5 V

3.98

3.7

3.84

0.1

0.26

0.1

0.4

0.1

0.33

V = V or V

V = V

to GND

or 0,

5.5 V

µA

V = V

= 0

160

One input at V

Other inputs at 0 or V

− 2.1 V,

†

4.5 V to 5.5 V

100

360

490

450

µA

∆I

†

Additional quiescent supply current per input pin, TTL inputs high, 1 unit load

HCT INPUT LOADING TABLE

INPUTS

A-D

UNIT LOADS

0.4

1.5

1.2

1.5

CLK

LOAD

D/U

CTEN

Unit load is nI

limit specified in electrical

characteristics table, (e.g., 360 µA max at 25°C).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢉ

ꢃ

ꢄ

ꢀ

ꢅ

ꢆ

ꢇ

ꢅ

ꢗ

ꢀꢁꢂ ꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ ꢈ ꢀꢁꢉ ꢃꢄ ꢀꢊ ꢅꢆ

ꢋ

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ꢋ

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ꢁ

ꢏ

ꢓ

ꢍ

ꢀ

ꢏ

ꢐ

ꢍ

ꢊ

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ꢋ

ꢓ

ꢕ

ꢊ

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ꢁ

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ꢍ

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ꢖ

ꢏ

ꢁ

ꢔ

ꢀ

ꢏ

ꢍ

ꢊ

ꢎ

ꢏ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190, ’HC191 timing requirements over recommended operating free-air temperature range

(unless otherwise noted) (see Figure 4)

= −55°C

T = −40°C

TO 85°C

= 25°C

TO 125°C

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

2 V

4.5 V

6 V

†

Clock frequency

MHz

clock

2 V

100

120

150

135

100

125

115

4.5 V

6 V

LOAD low

Pulse duration

2 V

4.5 V

6 V

CLK high or low

Data before LOAD↑

CTEN before CLK↑

D/U before CLK↑

Data before LOAD↑

2 V

4.5 V

6 V

2 V

4.5 V

6 V

Setup time

2 V

4.5 V

6 V

2 V

4.5 V

6 V

2 V

Hold time

CTEN before CLK↑

4.5 V

6 V

2 V

D/U before CLK↑

4.5 V

6 V

2 V

4.5 V

6 V

Recovery time

LOAD inactive before CLK↑

rec

†

Applies to noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, CTEN-to-clock setup times, and

CTEN-to-clock hold times determine maximum clock frequency. For example, with these HC devices:

(

)

f_maxCLK +

[ 18 MHz

42 ) 12 ) 2

CLK-to-MAXńMIN propagation delay ) CTEN-to-CLK setup time ) CTEN-to-CLK hold time

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HC190, ’HC191

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 4)

= −55°C

T = −40°C

= 25°C

FROM

(INPUT)

LOAD

TO 125°C

TO 85°C

PARAMETER

UNIT

(OUTPUT) CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

2 V

4.5 V

6 V

MHz

max

2 V

195

295

245

4.5 V

6 V

= 50 pF

= 15 pF

LOAD

5 V

2 V

175

265

220

4.5 V

6 V

= 50 pF

= 15 pF

A, B, C,

or D

5 V

2 V

170

255

215

4.5 V

6 V

= 50 pF

= 15 pF

CLK

D/U

5 V

2 V

125

190

155

4.5 V

6 V

= 50 pF

= 15 pF

RCO

MAX/MIN

RCO

MAX/MIN

5 V

2 V

210

315

265

4.5 V

6 V

= 50 pF

= 15 pF

5 V

2 V

150

225

190

4.5 V

6 V

= 50 pF

= 15 pF

5 V

2 V

165

250

205

4.5 V

6 V

= 50 pF

= 15 pF

D/U

5 V

2 V

125

190

155

4.5 V

6 V

= 50 pF

= 15 pF

= 50 pF

CTEN

RCO

Any

5 V

2 V

110

4.5 V

6 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢈ

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ꢃ

ꢄ

ꢀ

ꢊ

ꢅ

ꢆ

ꢅ

ꢈ

ꢀ

ꢁ

ꢉ

ꢃ

ꢄ

ꢀ

ꢊ

ꢅ

ꢆ

ꢋ

ꢌꢍ

ꢀꢄ

ꢎ

ꢏꢍ

ꢏꢐ

ꢋ

ꢐꢑ

ꢒ

ꢁ

ꢏ

ꢓ

ꢍ

ꢀꢏ

ꢐꢍ

ꢊ

ꢔꢎ

ꢋ

ꢓ

ꢕꢊ

ꢄ

ꢁ

ꢏ

ꢓ

ꢍ

ꢒ

ꢐ

ꢑ

ꢖ

ꢏ

ꢁ

ꢔ

ꢀ

ꢏ

ꢍ

ꢊ

ꢎ

ꢏ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

’HCT191

timing requirements over recommended operating free-air temperature range V

otherwise noted) (see Figure 5)

= 4.5 V (unless

= −55°C

= −40°C

TO 85°C

= 25°C

TO 125°C

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Clock frequency

Pulse duration

MHz

clock

LOAD low

CLK high or low

Data before LOAD↑

CTEN before CLK↑

D/U before CLK↑

Data before LOAD↑

CTEN before CLK↑

D/U before CLK↑

Setup time

Hold time

Recovery time

LOAD inactive before CLK↑

rec

’HCT191

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 5)

= −55°C

T = −40°C

= 25°C

FROM

(INPUT)

LOAD

TO 125°C

TO 85°C

PARAMETER

UNIT

(OUTPUT) CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

4.5 V

5 V

MHz

max

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

= 15 pF

= 50 pF

LOAD

4.5 V

5 V

A, B, C,

or D

4.5 V

5 V

CLK

D/U

RCO

4.5 V

5 V

4.5 V

5 V

MAX/MIN

RCO

MAX/MIN

4.5 V

5 V

4.5 V

5 V

D/U

4.5 V

5 V

CTEN

RCO

Any

4.5 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

operating characteristics, V

= 5 V, T = 25°C

PARAMETER

TYP

UNIT

’HC190

’HC191

’HCT191

Power dissipation capacitance

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁꢂ ꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ ꢈ ꢀꢁꢉ ꢃꢄ ꢀꢊ ꢅꢆ

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ꢐ

ꢑ

ꢖ

ꢏ

ꢁ

ꢔ

ꢀ

ꢏ

ꢍ

ꢊ

ꢎ

ꢏ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION − ’HC190, ’HC191

PARAMETER

Open

Closed

Open

Closed

Open

PZH

Test

PZL

PHZ

PLZ

Point

= 1 kΩ

From Output

Under Test

Closed

dis

Closed

Open

(see Note A)

or t

LOAD CIRCUIT

Input

50% V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Reference

Input

50% V

LOAD

Input

50% V

0 V

rec

0 V

Data

Input

90%

50%

10%

50% V

10%

50% V

CLK

0 V

VOLTAGE WAVEFORMS

RECOVERY TIME

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

Input

50% V

Output

Control

50% V

0 V

PLH

PHL

90%

PLZ

PZL

In-Phase

Output

90%

≈V

Output

Waveform 1

(see Note B)

50%

10%

50% V

10%

50% V

10%

PHL

90%

PLH

PZH

PHZ

90%

Out-of-Phase

Output

50% V

10%

50%

10%

Output

Waveform 2

(see Note B)

90%

50% V

≈0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS

OUTPUT ENABLE AND DISABLE TIMES

NOTES: A. includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

D. For clock inputs, f

is measured with the input duty cycle at 50%.

E. The outputs are measured one at a time with one input transition per measurement.

max

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

are the same as t

are the same as t .

Figure 4. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢇ

ꢀ ꢁꢂꢃ ꢄꢀ ꢅ ꢆꢅ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅꢆ ꢅ ꢈ ꢀꢁ ꢂ ꢃꢄ ꢀꢊ ꢅꢆ ꢅ ꢈ ꢀꢁꢉ ꢃ ꢄꢀ ꢊꢅ ꢆ ꢅ

ꢋ ꢌꢍꢀ ꢄ ꢎ ꢏꢍꢏꢐ ꢋ ꢐꢑ ꢒ ꢁꢏ ꢓ ꢍ ꢀꢏ ꢐꢍ ꢊꢔ ꢎꢋ ꢓ ꢕꢊ ꢄ ꢁꢏ ꢓ ꢍꢒꢐ ꢑ ꢖ ꢏꢁ ꢔ ꢀꢏ ꢍꢊ ꢎꢏ ꢗ

SCHS275E − MARCH 2002 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION − ’HCT191

PARAMETER

Open

Closed

Open

Closed

Open

PZH

Test

Point

= 1 kΩ

PZL

PHZ

PLZ

From Output

Under Test

Closed

dis

Closed

Open

(see Note A)

or t

LOAD CIRCUIT

Input

50% V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Reference

Input

50% V

LOAD

Input

50% V

0 V

rec

0 V

Data

Input

90%

50%

10%

50% V

10%

50% V

CLK

0 V

VOLTAGE WAVEFORMS

RECOVERY TIME

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

Input

50% V

Output

Control

50% V

0 V

PLH

PHL

90%

PLZ

PZL

In-Phase

Output

90%

≈V

Output

Waveform 1

(see Note B)

50%

10%

50% V

10%

50% V

10%

PHL

90%

PLH

PZH

PHZ

90%

Out-of-Phase

Output

50% V

10%

50%

10%

Output

Waveform 2

(see Note B)

90%

50% V

≈0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS

OUTPUT ENABLE AND DISABLE TIMES

NOTES: A. includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

D. For clock inputs, f

is measured with the input duty cycle at 50%.

E. The outputs are measured one at a time with one input transition per measurement.

max

and t

are the same as t

PLZ

PZL

PLH

PHZ

PZH

PHL

dis

are the same as t

are the same as t .

Figure 5. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

PACKAGING INFORMATION

Orderable Device

5962-8867101EA

5962-8994601EA

CD54HC190F3A

CD54HC191F3A

CD54HCT191F3A

CD74HC190E

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

CDIP

TBD

A42

N / A for Pkg Type

Level-1-260C-UNLIM

5962-8867101EA

CD54HCT191F3A

ACTIVE

A42

5962-8994601EA

CD54HC190F3A

CDIP

A42

5962-8994601EA

CD54HC190F3A

CDIP

A42

5962-8689101EA

CD54HC191F3A

CDIP

A42

5962-8867101EA

CD54HCT191F3A

PDIP

Pb-Free

(RoHS)

CU NIPDAU

CD74HC190E

HC190M

HJ190

CD74HC190EE4

CD74HC190NSR

CD74HC190NSRE4

CD74HC190NSRG4

CD74HC190PW

PDIP

Pb-Free

(RoHS)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

CD74HC190PWE4

CD74HC190PWG4

CD74HC190PWR

CD74HC190PWRE4

CD74HC190PWRG4

CD74HC190PWT

Green (RoHS

& no Sb/Br)

HJ190

Green (RoHS

& no Sb/Br)

HJ190

2000

250

Green (RoHS

& no Sb/Br)

HJ190

Green (RoHS

& no Sb/Br)

HJ190

Green (RoHS

& no Sb/Br)

HJ190

Green (RoHS

& no Sb/Br)

HJ190

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

CD74HC190PWTE4

CD74HC190PWTG4

CD74HC191E

ACTIVE

TSSOP

PDIP

SOIC

PDIP

SOIC

250

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

HJ190

ACTIVE

250

Green (RoHS

& no Sb/Br)

HJ190

Pb-Free

(RoHS)

CD74HC191E

HC191M

CD74HC191EE4

CD74HC191M

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

CD74HC191M96

CD74HC191M96E4

CD74HC191M96G4

CD74HC191ME4

CD74HC191MG4

CD74HC191MT

2500

Green (RoHS

& no Sb/Br)

HC191M

Green (RoHS

& no Sb/Br)

HC191M

Green (RoHS

& no Sb/Br)

HC191M

Green (RoHS

& no Sb/Br)

HC191M

Green (RoHS

& no Sb/Br)

HC191M

250

Green (RoHS

& no Sb/Br)

HC191M

CD74HC191MTE4

CD74HC191MTG4

CD74HCT191E

Green (RoHS

& no Sb/Br)

HC191M

Green (RoHS

& no Sb/Br)

HC191M

Pb-Free

(RoHS)

CD74HCT191E

HCT191M

CD74HCT191EE4

CD74HCT191M

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

CD74HCT191ME4

CD74HCT191MG4

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC190, CD54HC191, CD54HCT191, CD74HC190, CD74HC191, CD74HCT191 :

Catalog: CD74HC190, CD74HC191, CD74HCT191

•

Military: CD54HC190, CD54HC191, CD54HCT191

•

NOTE: Qualified Version Definitions:

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CD74HC190NSR

CD74HC190PWR

CD74HC190PWT

CD74HC191M96

2000

250

330.0

16.4

12.4

16.4

8.2

6.9

6.5

10.5

5.6

2.5

1.6

2.1

12.0

8.0

16.0

12.0

16.0

TSSOP

SOIC

5.6

2500

10.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CD74HC190NSR

CD74HC190PWR

CD74HC190PWT

CD74HC191M96

2000

250

367.0

333.2

367.0

345.9

38.0

35.0

28.6

TSSOP

SOIC

2500

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

CD54HC191H [TI]

相关型号：

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CD54HC192F/3

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