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CD54HC237F3A [TI]

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches; 高速CMOS逻辑， 3-8线译码器/多路解复用器与地址锁存器
CD54HC237F3A
型号： CD54HC237F3A
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches
高速CMOS逻辑， 3-8线译码器/多路解复用器与地址锁存器

解码器 驱动器 解复用器 锁存器 逻辑集成电路 双倍数据速率
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中文：  中文翻译
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CD74HC137, CD74HCT137,  
CD54HC237, CD74HC237,  
Data sheet acquired from Harris Semiconductor  
SCHS146F  
CD74HCT237  
High-Speed CMOS Logic, 3- to 8-Line  
Decoder/Demultiplexer with Address Latches  
March 1998 - Revised October 2003  
Both circuits have three binary select inputs (A0, A1 and A2)  
that can be latched by an active High Latch Enable (LE)  
signal to isolate the outputs from select-input changes. A  
“Low” LE makes the output transparent to the input and the  
circuit functions as a one-of-eight decoder. Two Output  
Features  
• Select One of Eight Data Outputs  
- Active Low for CD74HC137 and CD74HCT137  
- Active High for ’HC237 and CD74HCT237  
[ /Title  
(CD74  
HC137  
,
CD74  
HCT13  
7,  
CD74  
HC237  
,
CD74  
HCT23  
7)  
Enable inputs (OE and OE ) are provided to simplify  
1
to  
0
• l/O Port or Memory Selector  
cascading  
and  
facilitate  
demultiplexing.  
The  
demultiplexing function is accomplished by using the A , A ,  
0
1
• Two Enable Inputs to Simplify Cascading  
A inputs to select the desired output and using one of the  
2
• Typical Propagation Delay of 13ns at V  
o
= 5V,  
other Output Enable inputs as the data input while holding  
the other Output Enable input in its active state. In the  
CD74HC137 and CD74HCT137 the selected output is a  
“Low”; in the ’HC237 and CD74HCT237 the selected output is  
a “High”.  
CC  
15pF, T = 25 C (CD74HC237)  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
Ordering Information  
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC237F3A  
CD74HC137E  
( C)  
PACKAGE  
16 Ld CERDIP  
16 Ld PDIP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOIC  
16 Ld SOP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
/Sub-  
ject  
(High  
Speed  
• HC Types  
- 2V to 6V Operation  
CD74HC137PW  
CD74HC137PWR  
CD74HC137PWT  
CD74HC237E  
- High Noise Immunity: N = 30%, N = 30%, of V  
IL IH  
CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
CD74HC237M  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
CD74HC237MT  
CD74HC237M96  
CD74HC237NSR  
CD74HC237PW  
CD74HC237PWR  
CD74HC237PWT  
CD74HCT137E  
CD74HCT137MT  
CD74HCT137M96  
CD74HCT237E  
Description  
The  
CD74HC137,  
CD74HCT137,  
’HC237,  
and  
CD74HCT237 are high speed silicon gate CMOS decoders  
well suited to memory address decoding or data routing  
applications. Both circuits feature low power consumption  
usually associated with CMOS circuitry, yet have speeds  
comparable to low power Schottky TTL logic.  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld TSSOP  
16 Ld PDIP  
16 Ld SOIC  
16 Ld SOIC  
16 Ld PDIP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Functional Diagram  
Pinout  
HC/HCT HC/HCT  
237 137  
CD54HC237 (CERDIP)  
CD74HC137 (PDIP, TSSOP)  
CD74HCT137 (PDIP, SOIC)  
CD74HC237 (PDIP, SOIC, SOP, TSSOP)  
CD74HCT237 (PDIP)  
1
2
3
15  
14  
13  
12  
11  
10  
9
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
3-BIT  
LATCH  
1 OF 8  
DECODER  
TOP VIEW  
A
A
A
1
2
3
4
5
6
7
8
16 V  
15 Y  
14 Y  
13 Y  
12 Y  
11 Y  
10 Y  
0
1
3
CC  
0
4
LE  
1
LE  
2
OE  
5
1
0
7
3
OE  
1
OE  
Y
4
6
7
OE  
0
5
GND = 8  
= 16  
9
Y
GND  
6
V
CC  
’HC137, ’HCT137 TRUTH TABLE  
INPUTS  
OUTPUTS  
LE  
X
X
L
OE  
X
OE  
H
X
L
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
7
0
1
2
1
0
0
1
2
3
4
5
6
X
X
X
H
H
H
H
H
H
H
H
L
X
L
X
L
X
L
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
X
H
H
L
L
H
X
H
H
L
Depends upon the address previously applied while LE was at a logic low.  
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
’HC237, ’HCT237 TRUTH TABLE  
INPUTS  
OUTPUTS  
LE  
X
X
L
OE  
X
OE  
H
X
L
A
A
A
Y
Y
Y
Y
Y
Y
Y
Y
7
0
1
2
1
0
0
1
2
3
4
5
6
X
X
X
L
L
L
L
L
L
L
L
L
X
L
X
L
X
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
H
L
L
L
H
H
H
H
X
L
L
L
H
L
L
L
H
H
X
L
L
H
X
H
L
Depends upon the address previously applied while LE was at a logic low.  
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
2
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Functional Block Diagram  
A
0
15  
14  
LE  
Y
Y
Y
Y
Y
0
1
2
3
4
5
6
7
1
A
p
n
0
A
0
LE  
LE  
p
n
13  
12  
LE  
A
1
2
A
A
A1 LATCH  
1
A
11  
0
10  
Y
A
A
2
3
A2 LATCH  
LE  
2
2
9
Y
Y
7
4
5
LE  
LE  
OE  
1
0
6
OE  
3
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
O
High Level Input  
Voltage  
V
-
-
-
2
4.5  
6
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
3.15  
-
-
3.15  
-
-
3.15  
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
4
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
DC Electrical Specifications  
(Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
(mA)  
O
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
8
-
80  
-
160  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
CMOS Loads  
V
V
V
or V  
-0.02  
4.5  
4.5  
4.5  
4.5  
4.4  
4.4  
4.4  
OH  
IH  
IH  
IL  
High Level Output  
Voltage  
TTL Loads  
-4  
3.98  
-
-
-
-
3.84  
-
3.7  
-
V
V
V
Low Level Output  
Voltage  
CMOS Loads  
V
or V  
0.02  
4
-
-
0.1  
0.26  
-
-
0.1  
0.33  
-
-
0.1  
0.4  
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
Input Leakage  
Current  
I
V
and  
0
0
-
5.5  
5.5  
-
-
-
-
-
±0.1  
8
-
-
-
±1  
80  
-
-
-
±1  
µA  
µA  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
or  
160  
490  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
CC  
-2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
All  
UNIT LOADS  
1.5  
NOTE: Unit Load is ∆I  
360µA max at 25 C.  
limit specified in DC Electrical Table, e.g.,  
CC  
o
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
HC TYPES  
A to LE Setup Time  
SYMBOL  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
t
2
4.5  
6
50  
10  
9
-
-
-
-
-
-
-
-
-
-
-
-
65  
13  
11  
40  
8
-
-
-
-
-
-
75  
15  
13  
45  
9
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
n
SU  
A
to LE Hold Time  
t
2
30  
6
n
H
4.5  
6
5
7
8
5
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
LE Pulse Width  
SYMBOL  
(V)  
MIN  
50  
10  
9
TYP  
MAX  
MIN  
65  
13  
1
MAX  
MIN  
75  
MAX  
UNITS  
ns  
t
2
-
-
-
-
-
-
-
-
-
-
-
-
W
4.5  
6
15  
ns  
13  
ns  
HCT TYPES  
An to LE Setup Time  
t
4.5  
10  
-
-
13  
-
15  
-
ns  
SU  
An to LE Hold Time  
CD74HCT137  
t
t
H
4.5  
4.5  
4.5  
7
5
-
-
-
-
-
-
9
5
-
-
-
11  
5
-
-
-
ns  
ns  
ns  
CD74HCT237  
H
LE Pulse Width  
t
10  
13  
15  
W
Switching Specifications Input t , t = 6ns  
r
f
o
-40 C TO  
85 C  
o
o
o
o
25 C  
-55 C TO 125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HC TYPES  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
Propagation Delay  
t
t
C = 50pF  
2
-
-
180  
-
225  
-
270  
ns  
PLH, PHL  
L
CD74HC137, CD74HCT137  
An to any Y  
4.5  
6
-
-
-
-
-
-
36  
31  
-
-
-
45  
38  
-
-
-
54  
46  
ns  
ns  
ns  
Propagation Delay  
t
t
C = 50pF  
2
160  
200  
240  
PLH, PHL  
L
’HC237, CD74HCT237  
An to any Y  
4.5  
6
-
-
-
-
32  
27  
-
-
40  
34  
-
-
48  
41  
ns  
ns  
Address to Output  
CD74HC137  
’HC237  
t
t
, t  
PLH PHL  
C
C
= 15pF  
= 15pF  
5
5
5
-
-
-
-
-
-
-
-
-
-
15  
13  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
L
, t  
PLH PHL  
-
-
-
L
OE to any Y or Y  
t
t
C = 50pF  
2
145  
29  
25  
145  
29  
25  
190  
38  
32  
180  
36  
31  
180  
36  
31  
240  
48  
41  
220  
44  
38  
220  
44  
38  
285  
57  
48  
0
PLH, PHL  
L
4.5  
6
-
-
OE to any Y or Y  
1
t
, t  
TLH THL  
C = 50pF  
2
-
L
4.5  
6
-
-
LE to any Y or Y  
t
, t  
TLH THL  
C
= 50pF  
2
-
L
4.5  
6
-
-
Power Dissipation  
Capacitance, (Notes 3, 4)  
CD74HC137  
’HC237  
C
C
C
C
= 15pF  
= 15pF  
5
5
-
-
-
-
-
-
19  
23  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF  
pF  
ns  
ns  
ns  
pF  
PD  
L
-
-
PD  
L
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
L
2
75  
15  
13  
10  
95  
19  
16  
10  
110  
22  
19  
10  
4.5  
6
-
-
Input Capacitance  
C
-
-
-
I
6
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
-40 C TO  
85 C  
o
o
o
o
25 C  
-55 C TO 125 C  
TEST  
SYMBOL CONDITIONS  
PARAMETER  
HCT TYPES  
V
(V) MIN  
TYP MAX  
MIN  
MAX  
MIN  
MAX UNITS  
CC  
Propagation Delay  
An to any Y or Y  
Address to Output  
t
t
t
t
, t  
C
C
C
C
= 50pF  
= 15pF  
= 50pF  
= 50pF  
4.5  
5
-
-
-
-
-
-
-
-
-
16  
-
38  
-
-
48  
-
-
-
-
-
-
-
-
57  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH PHL  
L
L
L
L
, t  
PLH PHL  
-
-
-
-
-
-
-
-
OE to any Y (HC137)  
, t  
PLH PHL  
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
35  
33  
37  
35  
44  
42  
44  
41  
46  
44  
55  
53  
53  
60  
56  
53  
66  
63  
0
OE to any Y (HC237)  
, t  
PLH PHL  
-
0
OE to any Y (HC137)  
t
t
, t  
TLH THL  
C = 50pF  
-
1
L
OE to any Y (HC237)  
1
, t  
TLH THL  
C = 50pF  
L
-
LE to any Y (HC137)  
LE to any Y (HC237)  
t
, t  
CL = 50pF  
-
TLH THL  
t
t
, t  
TLH THL  
C = 50pF  
-
L
Power Dissipation  
Capacitance, (Notes 3, 4)  
CD74HC137  
’HC237  
C
C
C
= 15pF  
5
5
-
-
19  
23  
-
-
-
-
-
-
-
pF  
pF  
ns  
pF  
PD  
L
C = 15pF  
-
-
-
PD  
L
Output Transition Time  
Input Capacitance  
NOTES:  
, t  
TLH THL  
C = 50pF  
L
4.5  
-
15  
10  
19  
10  
22  
10  
C
-
-
-
-
-
I
3. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
fC  
t C  
f
L
L
r
L
3V  
V
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
7
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237  
Test Circuits and Waveforms (Continued)  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
8
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8860601EA  
CD54HC237F  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
16  
16  
16  
16  
1
1
None  
None  
None  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
CD54HC237F3A  
CD74HC137E  
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
CD74HC137PW  
CD74HC137PWR  
CD74HC137PWT  
CD74HC237E  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
PDIP  
PW  
PW  
PW  
N
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
90  
2000  
250  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
CD74HC237M  
SOIC  
D
40  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
CD74HC237M96  
CD74HC237MT  
CD74HC237NSR  
CD74HC237PW  
CD74HC237PWR  
CD74HC237PWT  
CD74HCT137E  
CD74HCT137M96  
CD74HCT137MT  
CD74HCT237E  
SOIC  
D
2500  
250  
2000  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SO  
NS  
PW  
PW  
PW  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
TSSOP  
PDIP  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
2000  
250  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
SOIC  
D
2500  
250  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
PDIP  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  

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