CD54HC75F3A_技术文档

CD54HC75, CD74HC75,

CD54HCT75, CD74HCT75

Data sheet acquired from Harris Semiconductor

SCHS135F

Dual 2-Bit Bistable

Transparent Latch

March 1998 - Revised October 2003

Features

Description

• True and Complementary Outputs

• Buffered Inputs and Outputs

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent

latches. Each one of the 2-bit latches is controlled by

separate Enable inputs (1E and 2E) which are active LOW.

When the Enable input is HIGH data enters the latch and

appears at the Q output. When the Enable input (1E and 2E)

is LOW the output is not affected.

[ /Title

(CD74

HC75,

CD74

HCT75

)

/Sub-

ject

(Dual

2-Bit

Bistabl

e

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

o

PART NUMBER

CD54HC75F3A

CD54HCT75F3A

CD74HC75E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC75M

16 Ld SOIC

16 Ld SOP

at V

= 5V

CC

CD74HC75MT

CD74HC75M96

CD74HC75NSR

CD74HC75PW

CD74HC75PWR

CD74HCT75E

CD74HCT75M

CD74HCT75PWT

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

16 Ld TSSOP

16 Ld PDIP

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

l

16 Ld SOIC

16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Pinout

CD54HC75, CD54HCT75 (CERDIP)

CD74HC75 (PDIP, SOIC, SOP, TSSOP)

CD74HCT75 (PDIP, SOIC, TSSOP)

TOP VIEW

1Q0

1D0

1D1

2E

1

2

3

4

5

6

7

8

16 1Q0

15 1Q1

14 1Q1

13 1E

V

12 GND

11 2Q0

10 2Q0

CC

2D0

2D1

2Q1

9

2Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

1

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Functional Diagram

16 (10)

1 (11)

14 (8)

15 (9)

Q0

2 (6)

3 (7)

D0

D1

Q0

Q1

1 OF 2

LATCHES

13 (4)

E

TRUTH TABLE

INPUTS

OUTPUTS

D

L

E

Q

L

Q

H

L

H

X

H

L

Q0

H= High Level

L= Low Level

X= Don’t Care

Q0 = The level of Q before the transition of E.

Logic Diagram

LATCH 0

2 (6)

16 (10)

Q0

D0

D

Q

LE

1 (11)

Q0

13 (4)

E

LE

P

N

P

N

14 (8)

Q1

Q

LE

D

LE

Q

3 (7)

D1

LE

Q

LE

15 (9)

Q1

LATCH 1

5

V

CC

12

GND

FIGURE 1. LOGIC DIAGRAM

FIGURE 2. LATCH DETAIL

2

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

Package Thermal Impedance, θ (see Note 1)

JA

CC

DC Input Diode Current, I

For V < -0.5V or V > V

o

IK

E (PDIP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W

M (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W

NS (SOP) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W

PW (TSSOP) package. . . . . . . . . . . . . . . . . . . . . . . . . .108 C/W

o

+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

I

CC

o

DC Drain Current, per Output, I

O

o

For -0.5V < V < V

+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

O

CC

o

DC Output Diode Current, I

OK

For V < -0.5V or V > V

Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C

o

+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

O

CC

o

DC Output Source or Sink Current per Output Pin, I

O

o

For V > -0.5V or V < V

+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

O

CC

DC V

or Ground Current, I

. . . . . . . . . . . . . . . . . . . . . . . . .±50mA

CC

(SOIC - Lead Tips Only)

Operating Conditions

o

Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

A

Supply Voltage Range, V

CC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V

I

O

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

TEST

CONDITIONS

o

25 C

-40 C TO 85 C

-55 C TO 125 C

PARAMETER

HC TYPES

SYMBOL V (V)

I

(mA)

V

(V) MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

I

O

CC

High Level Input

Voltage

V

-

2

1.5

-

1.5

-

1.5

-

V

µA

IH

4.5

3.15

-

3.15

-

3.15

6

2

4.2

-

Low Level Input

Voltage

V

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

0.5

1.35

1.8

-

IL

4.5

6

-

High Level Output

Voltage

CMOS Loads

V

or

-0.02

2

1.9

OH

IH

V

IL

4.5

6

4.4

-

4.4

-

4.4

-

5.9

-

5.9

-

5.9

-

High Level Output

Voltage

TTL Loads

-

-4

4.5

6

3.98

-

3.84

-

3.7

-

-5.2

5.48

-

5.34

-

5.2

-

Low Level Output

Voltage

CMOS Loads

V

or

0.02

2

-

0.1

-

0.1

-

0.1

-

OL

IH

V

IL

4.5

6

Low Level Output

Voltage

TTL Loads

-

4

-

4.5

6

0.26

±0.1

0.33

±1

0.4

±1

5.2

-

Input Leakage

Current

I

V

or

6

I

CC

GND

3

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

o

25 C

-40 C TO 85 C

-55 C TO 125 C

PARAMETER

SYMBOL V (V)

I

(mA)

V

(V) MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

I

O

CC

Quiescent Device

Current

I

V

GND

or

0

6

-

4

-

40

-

80

µA

CC

HCT TYPES

High Level Input

Voltage

V

-

4.5 to

5.5

2

-

0.8

-

2

-

0.8

-

2

-

0.8

-

V

IH

Low Level Input

Voltage

V

4.5 to

5.5

IL

High Level Output

Voltage

CMOS Loads

V

or

IH

- 0.02

-4

4.5

4.4

OH

V

IL

High Level Output

Voltage

4.5

3.98

-

3.84

-

3.7

-

V

TTL Loads

Low Level Output

Voltage CMOS Loads

V

or

IH

0.02

4

4.5

-

0.1

-

0.1

-

0.1

0.4

V

OL

IL

Low Level Output

Voltage

0.26

0.33

TTL Loads

Input Leakage

Current

I

V

and

GND

-

5.5

-

±0.1

-

±1

-

±1

µA

I

CC

Quiescent Device

Current

I

V

or

0

-

4

-

40

-

80

µA

CC

GND

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆I

CC

(Note 2)

V

4.5 to

5.5

100

360

450

490

CC

- 2.1

NOTE:

2. For dual-supply systems theoretical worst case (V = 2.4V, V

I

= 5.5V) specification is 1.8mA.

CC

HCT Input Loading Table

INPUT

D0, D1

UNIT LOADS

0.8

1.2

1E, 2E

NOTE: Unit Load is ∆I

tions table, e.g., 360µA max at 25 C.

limit speciﬁed in DC Electrical Speciﬁca-

CC

o

Prerequisite For Switching Speciﬁcations

o

25 C

-40 C TO 85 C -55 C TO 125 C

TEST

V

CC

PARAMETER

HC TYPES

SYMBOL CONDITIONS (V)

MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

Pulse Width Enable Input

t

-

2

80

16

14

60

12

10

-

100

20

17

75

15

13

-

120

24

20

90

18

15

-

ns

W

4.5

6

Setup Time D to Enable

t

2

SU

4.5

6

4

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Prerequisite For Switching Speciﬁcations (Continued)

o

25 C

-40 C TO 85 C -55 C TO 125 C

TEST

V

CC

PARAMETER

SYMBOL CONDITIONS (V)

MIN TYP MAX

MIN

3

MAX

MIN

3

MAX

UNITS

ns

Hold Time Enable to D

t

-

2

4.5

6

3

-

H

3

ns

3

ns

HCT TYPES

Pulse Width Enable Input

t

-

4.5

16

12

3

-

20

15

3

-

24

18

3

-

ns

W

Setup Time D to Enable

Hold Time Enable to D

t

SU

t

H

Switching Speciﬁcations Input t , t = 6ns

r

f

o

25 C

MIN TYP MAX

-40 C TO 85 C -55 C TO 125 C

TEST

V

CC

PARAMETER

HC TYPES

SYMBOL CONDITIONS (V)

MIN

MAX

MIN

MAX

UNITS

Propagation Delay,

Data to Q

t

, t

C = 50pF

2

4.5

5

-

110

22

-

140

28

-

165

33

-

ns

pF

PLH PHL

L

C = 50pF

L

C = 15pF

9

-

L

C = 50pF

6

19

130

26

-

24

165

33

-

28

195

39

-

L

Propagation Delay,

Data to Q

, t

PLH PHL

C = 50pF

2

-

L

C = 50pF

4.5

5

-

L

C = 15pF

10

-

L

C = 50pF

6

22

130

26

-

28

165

33

-

33

195

39

-

L

Propagation Delay,

Enable to Q

, t

PLH PHL

C = 50pF

2

-

L

C = 50pF

4.5

5

-

L

C = 15pF

10

-

L

C = 50pF

6

22

130

26

-

28

165

33

-

33

195

39

-

L

Propagation Delay,

Enable to Q

, t

PLH PHL

C = 50pF

2

-

L

C = 50pF

4.5

5

-

L

C = 15pF

11

-

L

C = 50pF

6

22

75

15

13

10

-

28

95

19

16

10

-

33

110

22

19

10

-

L

Output Transition Time

Input Capacitance

t

, t

TLH THL

C = 50pF

2

-

L

C = 50pF

4.5

6

-

L

C = 50pF

L

-

C

-

I

Power Dissipation Capacitance

(Notes 3, 4)

C

5

46

PD

HCT TYPES

Propagation Delay,

Data to Q

t

, t

C = 50pF

4.5

5

-

11

-

28

-

35

-

42

-

ns

PLH PHL

L

C = 15pF

L

Propagation Delay,

Data to Q

, t

PLH PHL

C = 50pF

4.5

5

28

-

35

-

42

-

L

C = 15pF

11

-

L

Propagation Delay,

Enable to Q

, t

PLH PHL

C = 50pF

4.5

5

28

-

35

-

42

-

L

C = 15pF

11

L

5

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Switching Speciﬁcations Input t , t = 6ns (Continued)

r

f

o

25 C

-40 C TO 85 C -55 C TO 125 C

TEST

V

CC

PARAMETER

Propagation Delay,

SYMBOL CONDITIONS (V)

MIN TYP MAX

MIN

MAX

38

-

MIN

MAX

45

-

UNITS

ns

t

, t

C = 50pF

4.5

5

-

12

-

30

-

PLH PHL

L

Enable to Q

C = 15pF

ns

L

Output Transition Time

Input Capacitance

t

, t

TLH THL

C = 50pF

L

4.5

-

15

10

-

19

10

-

22

10

-

ns

C

-

pF

I

Power Dissipation Capacitance

(Notes 3, 4)

C

5

46

pF

PD

NOTES:

3. C

is used to determine the dynamic power consumption, per latch.

2

PD

4. P = V

f (C

PD

+ C ) where f = input frequency, C = output load capacitance, V

= supply voltage.

D

CC

i

L

i

L

CC

Test Circuits and Waveforms

I

t

+ t

WH

=

WL

I

t C = 6ns

fC

L

r

L

t

+ t

=

WL

WH

t C = 6ns

t C

f

L

f

t C

f

L

CL

r

L

3V

V

CC

90%

10%

2.7V

CLOCK

50%

10%

1.3V

0.3V

50%

t

50%

1.3V

t

1.3V

0.3V

GND

t

WH

WL

WH

WL

NOTE: Outputs should be switching from 10% V

to 90% V

in

NOTE: Outputs should be switching from 10% V

to 90% V

in

CC

accordance with device truth table. For f

, input duty cycle = 50%.

accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

t = 6ns

r

f

r

f

V

3V

CC

90%

50%

10%

2.7V

1.3V

0.3V

INPUT

GND

t

THL

TLH

THL

TLH

90%

1.3V

90%

50%

10%

INVERTING

OUTPUT

INVERTING

OUTPUT

10%

t

PLH

PHL

t

PLH

PHL

FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Test Circuits and Waveforms (Continued)

t C

r

L

f

L

f

L

r

L

V

3V

CC

90%

10%

2.7V

0.3V

CLOCK

INPUT

CLOCK

INPUT

50%

1.3V

GND

t

H(L)

H(H)

H(L)

V

3V

CC

DATA

INPUT

DATA

INPUT

50%

1.3V

t

SU(L)

1.3V

GND

t

SU(H)

SU(L)

t

90%

50%

t

THL

TLH

THL

TLH

90%

1.3V

90%

1.3V

OUTPUT

10%

t

PLH

t

PHL

PLH

t

REM

t

REM

V

3V

CC

SET, RESET

OR PRESET

SET, RESET

OR PRESET

50%

1.3V

GND

IC

C

L

50pF

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this

warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily

performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should

provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask

work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services

are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such

products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under

the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an

unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service

voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business

practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would

reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement

specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications

of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related

requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any

applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its

representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is

solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in

connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products

are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any

non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

microcontroller.ti.com

www.ti.com/lpw

Low Power

Wireless

Telephony

www.ti.com/telephony

Video & Imaging

Wireless

www.ti.com/video

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

PDIP

Drawing

5962-9075801MEA

8407001EA

ACTIVE

J

16

1

TBD

A42 SNPB

N / A for Pkg Type

CD54HC75F3A

CD54HCT75F3A

CD74HC75E

J

1

J

1

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

CD74HC75EE4

CD74HC75M

ACTIVE

PDIP

SOIC

SO

N

D

16

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75M96

CD74HC75M96E4

CD74HC75M96G4

CD74HC75ME4

CD74HC75MG4

CD74HC75MT

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75MTE4

CD74HC75MTG4

CD74HC75NSR

CD74HC75NSRE4

D

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75NSRG4

CD74HC75PW

ACTIVE

SO

NS

16

2000

TBD

Call TI

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75PWE4

CD74HC75PWG4

CD74HC75PWR

ACTIVE

TSSOP

PW

16

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75PWRE4

CD74HC75PWRG4

CD74HC75PWT

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC75PWTE4

CD74HC75PWTG4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2007

Orderable Device

CD74HCT75E

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

PDIP

N

16

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

CD74HCT75EE4

CD74HCT75M

PDIP

SOIC

N

D

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HCT75ME4

CD74HCT75MG4

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

0

(mm)

16

CD74HC75M96

CD74HC75NSR

CD74HC75PWR

D

16

FMX

MLA

6.5

8.2

7.0

10.3

10.5

5.6

12.1

2.5

2

12

8

16

12

Q1

NS

PW

330

16

12

1.6

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

CD74HC75M96

CD74HC75NSR

CD74HC75PWR

D

16

FMX

MLA

342.9

338.1

336.6

340.5

28.58

20.64

NS

PW

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Pack Materials-Page 3

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265