CD74AC163MG4 [TI]

Synchronous Presettable Binary Counters with Synchronous Reset 16-SOIC -55 to 125;


型号：	CD74AC163MG4
厂家：	TEXAS INSTRUMENTS
描述：	Synchronous Presettable Binary Counters with Synchronous Reset 16-SOIC -55 to 125 光电二极管输出元件逻辑集成电路触发器
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中文：	中文翻译
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CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

CD54AC163 . . . F PACKAGE

CD74AC163 . . . E OR M PACKAGE

(TOP VIEW)

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

CLR

CLK

RCO

Synchronously Programmable

description/ordering information

The ’AC163 devices are 4-bit binary counters.

These synchronous, presettable counters feature

an internal carry look-ahead for application in

high-speed counting designs. Synchronous

operation is provided by having all flip-flops

clocked simultaneously so that the outputs

ENP

GND

ENT

LOAD

change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.

This mode of operation eliminates the output counting spikes normally associated with synchronous

(ripple-clock)counters. Abufferedclock(CLK)inputtriggersthefourflip-flopsontherising(positive-going)edge

of the clock waveform.

The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.

Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes

the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low

after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear

allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The

active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000

(LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – E

Tube

CD74AC163E

CD74AC163M

CD74AC163M96

CD54AC163F3A

–55°C to 125°C

SOIC – M

AC163M

Tape and reel

Tube

CDIP – F

CD54AC163F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB

design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

FUNCTION TABLE

INPUTS

OUTPUTS

Q RCO

FUNCTION

Reset (clear)

Parallel load

CLR

CLK

ENP

ENT

LOAD

A,B,C,D

↑

Note 1

↑

Count

Note 1 Count

Note 1

Inhibit

H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK

low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the

state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high

transition.

NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count

(HHHH).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

logic diagram (positive logic)

LOAD

ENT

RCO

†

ENP

†

CLK

CLR

1, 2T/1C3

†

For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

logic symbol, each D/T flip-flop

LD (Load)

TE (Toggle Enable)

CK (Clock)

1, 2T/1C3

Q (Output)

D (Inverted Data)

R (Inverted Reset)

logic diagram, each D/T flip-flop (positive logic)

†

The origins of LD and CK are shown in the logic diagram of the overall device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:

1. Clear outputs to zero (synchronous)

2. Preset to binary 12

3. Count to 13, 14, 15, 0, 1, and 2

4. Inhibit

CLR

LOAD

Data

Inputs

CLK

ENP

ENT

Data

Outputs

RCO

Count

Inhibit

Sync Preset

Clear

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V

Input clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Output clamp current, I

(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Continuous current through V

Package thermal impedance, θ (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA

M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

–55°C to

125°C

–40°C to

85°C

= 25°C

UNIT

MIN

1.5

MAX

MIN

1.5

MAX

MIN

MAX

Supply voltage

5.5

1.5

1.2

5.5

= 1.5 V

= 3 V

1.2

High-level input voltage

2.1

= 5.5 V

= 1.5 V

= 3 V

3.85

0.3

0.9

0.3

0.9

0.3

0.9

Low-level input voltage

= 5.5 V

1.65

Input voltage

Output voltage

High-level output current

Low-level output current

–24

= 1.5 V to 3 V

∆t/∆v

Input transition rise or fall rate

= 3.6 V to 5.5 V

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

–55°C to

125°C

–40°C to

85°C

= 25°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

1.4

2.9

4.4

2.58

3.94

–

MAX

MIN

1.4

2.9

4.4

2.4

3.7

3.85

–

MAX

MIN

1.4

2.9

4.4

2.48

3.8

–

MAX

1.5 V

3 V

= –50 µA

4.5 V

3 V

V = V or V

= –4 mA

= –24 mA

= –50 mA

= –75 mA

4.5 V

5.5 V

1.5 V

3 V

†

–

3.85

0.1

0.36

–

0.1

0.5

1.65

–

0.1

0.44

–

= 50 µA

4.5 V

3 V

V = V or V

= 12 mA

= 24 mA

4.5 V

5.5 V

†

= 50 mA

= 75 mA

†

–

1.65

±1

V = V

or GND

or GND,

±0.1

±1

µA

V = V

= 0

160

†

Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize

power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

–55°C to

125°C

–40°C to

85°C

UNIT

MIN

MAX

MIN

MAX

1.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

Clock frequency

Pulse duration

MHz

clock

103

7.7

5.5

6.8

4.8

6.1

4.4

8.2

4.4

7.4

5.3

7.4

5.3

CLK high or low

A, B, C, or D

ENP or ENT

LOAD low

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

9.6

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

Setup time, before CLK↑

8.4

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

8.4

CLR inactive

A, B, C, or D

ENP or ENT

LOAD low

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

Hold time, after CLK↑

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

CLR inactive

3.3 V ± 0.3 V

5 V ± 0.5 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

(unless otherwise noted) (see Figure 1)

–55°C to

125°C

–40°C to

85°C

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1.5 V

max

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

–

103

–

MHz

209

23.4

16.7

207

190

RCO

Any Q

RCO

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

4.3

–

4.3

–

15.2

188

CLK

ENT

3.3 V ± 0.3 V

5 V ± 0.5 V

1.5 V

5.9

4.2

–

23.1

16.5

129

5.9

4.2

–

117

13.1

9.4

3.3 V ± 0.3 V

5 V ± 0.5 V

3.6

2.6

14.4

10.3

3.7

2.7

operating characteristics, T = 25°C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Power dissipation capacitance

No load

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54AC163, CD74AC163

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS299B – APRIL 2000 – REVISED MARCH 2003

PARAMETER MEASUREMENT INFORMATION

2 × V

Open

GND

TEST

R1 = 500 Ω

R2 = 500 Ω

Open

PLH PHL

From Output

Under Test

2 × V

GND

PLZ PZL

PHZ PZH

= 50 pF

(see Note A)

NOTE: When V

= 1.5 V, R1 and R2 = 1 kΩ.

Input

50% V

LOAD CIRCUIT

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Reference

Input

CLR

Input

50% V

0 V

rec

Data

Input

90%

50% V

50%

10%

50% V

10%

CLK

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

RECOVERY TIME

Input

50% V

PHL

90%

Output

Control

50% V

0 V

PLH

PLZ

PZL

In-Phase

Output

Waveform 1

90%

≈V

50%

10%

50% V

10%

50% V

+ 0.3 V

S1 at 2 × V

(see Note B)

PLH

PHL

90%

PZH

PHZ

Output

Waveform 2

S1 at Open

(see Note B)

90%

Out-of-Phase

Output

50% V

10%

50%

10%

– 0.3 V

50% V

≈0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS

OUTPUT ENABLE AND DISABLE TIMES

NOTES: A.

C includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.

Phase relationships between waveforms are arbitrary.

D. For clock inputs, f is measured with the input duty cycle at 50%.

max

E. The outputs are measured one at a time with one input transition per measurement.

and t

are the same as t

PLH

PZL

PLZ

PHL

PZH

PHZ

are the same as t

dis

I. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

CD54AC163F3A

CD74AC163E

ACTIVE

CDIP

PDIP

TBD

A42

N / A for Pkg Type

-55 to 125

CD54AC163F3A

ACTIVE

Pb-Free

(RoHS)

CU NIPDAU

CD74AC163E

AC163M

CD74AC163EE4

CD74AC163M

PDIP

SOIC

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

Level-1-260C-UNLIM

-55 to 125

Green (RoHS

& no Sb/Br)

CD74AC163M96

CD74AC163MG4

2500

Green (RoHS

& no Sb/Br)

AC163M

Green (RoHS

& no Sb/Br)

AC163M

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54AC163, CD74AC163 :

Catalog: CD74AC163

•

Military: CD54AC163

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

CD74AC163M96

SOIC

2500

330.0

16.4

6.5

10.3

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC 16

SPQ

Length (mm) Width (mm) Height (mm)

333.2 345.9 28.6

CD74AC163M96

2500

Pack Materials-Page 2

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CD74AC163MG4 [TI]

相关型号：

CD74AC163MX

CD74AC164

CD74AC164E

CD74AC164E

CD74AC164EE4

CD74AC164EN

CD74AC164EX

CD74AC164F

CD74AC164M

CD74AC164M

CD74AC164M96

CD74AC164M96E4